TWI428877B - Multimode source driver and display device having the same - Google Patents

Description

Multi-mode source driver and its suitable display device

The invention discloses a display device, in particular a multi-mode source driver and a display device using a multi-mode source driver.

Liquid crystal display devices have been widely used in portable electronic devices such as mobile phones or other portable devices. Drivers for liquid crystal displays typically include a source driver, a gate driver, and a clock controller. For all liquid crystal displays, it is best to have low performance and high image quality.

Conventionally, the liquid crystal display panel is driven by an inversion mode such as a picture inversion method, a line (or column) inversion method, or a dot inversion method to improve image quality and avoid damage to the liquid crystal material. Compared with other methods, driving the liquid crystal display panel by the dot inversion method can cause the flicker of the vertical and horizontal methods to cancel each other, so that the image quality can be better. However, by driving the liquid crystal panel by the dot inversion method, the required power is greatly increased because of a large change in the display signal applied to the source driver.

The recently released Z-reverse display panel has the same image quality as the dot-reversal method, and can greatly reduce the power of the source driver.

On the other hand, the performance of the source driver is very important for achieving low power and high speed liquid crystal display devices. In order to meet the large load of the display panel and to achieve low power performance, various source drivers have been developed to overcome, for example, design bottlenecks for driving capability and driving speed. However, in Xu In many cases, for example, the load on the display panel may be very high, it may be necessary to separate a set of source drivers on both sides of the display panel to alleviate the load on the display panel.

Therefore, it is preferable to have a source driver that can overcome the bottleneck of the above design at the same time, and can be widely applied to various display types, in particular, a Z-reverse display panel capable of reducing the power and a double that can alleviate the load. Source drive configuration.

The present invention discloses a multi-mode source driver for a display device that is operable in different modes to provide better drive speeds, and is applicable to a variety of display planes and configurations of dual source drivers. The present invention also discloses a display device having a multi-mode source driver and a driving method for driving the display device.

In one aspect, the multi-mode source driver is coupled to the first data bus and the second data bus to drive the display device. The multi-mode data driver includes a busbar switching circuit, and connects the first data busbar to one of the first internal busbar and the second internal busbar according to the switching control signal, and connects the second data busbar to the first The other of the internal bus and the second internal bus. The multi-mode data driver further includes a start pulse switching circuit that receives the first start pulse and the second start pulse according to the exchange control signal to provide the first exchange start pulse and the second exchange start pulse. The multi-mode data driver further includes a first shift register, which is triggered by the first exchange start pulse to generate a first sequence of latch signals, a second shift register, which is triggered by a second exchange start pulse. A second sequence of latch signals is generated. The multi-mode data driver further includes a shift multiplexer that receives the first sequence of latch signals and the second sequence of latch signals, and outputs the latch signals of the first sequence and the latch signals of the second sequence. The third sequence of latch signals. The multi-mode data driver further includes a plurality of latch multiplexers each coupled to the first internal bus and the second internal bus, and each configured to selectively select from the first internal bus or the second according to the mode control signal The internal bus transmits pixel data. The multi-mode data drive in turn includes a plurality of latch units that latch the pixel data with the self-latching multiplexer by a third sequence of latch signal control. The multi-mode data drive further includes an output unit configured to provide a plurality of drive voltages based on pixel data from the latch unit.

In another aspect, the invention also discloses a display device comprising a display plane, a first multi-mode source driver, a device on one side of the display panel to drive the display panel, and a second multi-mode source driver, the device being in the display panel The other side drives the display panel.

Other objects, features, and advantages of the present invention are as defined by the scope of the claims and are disclosed by the following non-limiting embodiments.

1 is a schematic illustration of a multi-mode source driver in accordance with an embodiment of the present invention. The multi-mode source driver 100 is connected to the first data bus "bus A" and the second data bus "bus B", which can be configured to process from the clock controller (not shown here) and Pixel data transmitted on the first data bus "bus A" and the second data bus "bus B", and respectively provide a plurality of driving voltages 'DO(1)'-'DO(m)' (wherem Right An integer of zero) to drive the corresponding pixel on the display device (not shown here).

The output channel 'CH(1)'-'CH(m)' can be grouped into channel groups 'G(1)'-'G(n)' (where n is a non-zero integer), and each channel group contains at least one Output channel. Preferably, as shown in the figure, each channel group contains three output channels that drive blue, green, and red pixels, respectively (i.e., m = 3n). Therefore, the channel groups 'G1', 'G2', ..., 'Gn' contain the output channels 'DO(1)'-'DO(3)', 'DO(4)'-'DO(6)',... , 'DO(m-2)'-'DO(m)'.

In addition, the clock controller can transmit pixel data according to the transmission mode via the first data bus "bus A" and the second data bus "bus B". In an embodiment, the transmission mode of the clock controller may include M ₁ M ₂ M ₃ M ₄ = AAAA, AABB, and ABAA modes. When the transmission mode is AAAA, the clock controller only transmits pixel data via the first data bus "bus A". When the transmission mode is AABB, the clock controller transmits the first pixel data and the second pixel data via the first data bus "bus A", and transmits the third pixel through the second data bus "bus B". The data and the fourth pixel data are then transmitted in the same order. When the transmission mode is ABAB, the clock controller transmits the first pixel data and the third pixel data via the first data bus "bus A", and transmits the second pixel via the second data bus "bus B". The data and the fourth pixel data are then transmitted in the same order.

The multi-mode source driver 100 can then instruct the clock controller to obtain the pixel data transmitted on the first data bus "bus A" and the second data bus "bus B", and according to the clock controller Transmission mode The output mode provides a drive voltage 'DO(1)'-'DO(m)'.

The multi-mode source driver 100 can then determine whether to provide the pixel data received from the first data bus "bus A" or the pixel data received from the second data bus "bus B" according to its output mode. Give each channel group 'Gi' (i is an integer from 1 to m). The driving voltage supplied to each channel group 'Gi' may be pixel data received from the first data bus "bus A" or pixel data received from the second data bus "bus B". Therefore, the multi-mode source driver 100 can reconfigure the order of the pixel data input by the clock controller in different manners, so that the driving voltage can be supplied according to different output modes.

In an embodiment where n=4, the input mode may include M ₁ M ₂ M ₃ M ₄ =AAAA, AABB, and BBAA modes. If Mi=A, the multi-mode source driver 100 will supply the pixel data received from the first data bus “bus A” to the channel group 'Gi', and if Mi=B, the multi-mode source driver 100 The pixel data received from the second data bus "bus B" will be supplied to the channel group 'Gi', where i=1~4.

As shown in FIG. 1 , the multi-mode source driver 100 can include a bus bar switching circuit 110 , a starting pulse switching circuit 120 , a first shift register 131 , a second shift register 132 , a shift multiplexer 140 , A plurality of latch multiplexers 150, a plurality of latch units 160, and an output unit 170. Preferably, multi-mode source driver 100 can include a latch unit 162 coupled between latch unit 160 and output unit 170. In addition, the multi-mode source driver 100 can be set to selectively operate in one of a plurality of output modes by the mode control signal "SC_M" and the exchange control signal "SC_W" received from the clock controller.

The busbar switching circuit 110 is coupled between the clock controller and the latch multiplexer 150, and is configured to be received on the first data bus "bus A" and the second data bus "bus B". The transmitted pixel data is provided to the latched multiplexer 150. In addition, the bus bar switching circuit 110 can further receive the exchange control signal 'SC_W' from the clock controller. The bus switch circuit 110 can connect the first data bus "bus A" to the first internal bus "internal bus 1" and the second internal bus "internal bus 2" according to the exchange control signal 'SC_W' One of them connects the second data bus "bus B" to the other of the first internal bus "internal bus 1" and the second internal bus "internal bus 2". The start pulse switching circuit 120 can be implemented using a multiplexer.

Wherein, if the exchange control signal 'SC_W' is in the first state (ie, in the low state or '0'), then the busbar switching circuit 110 connects the first data bus "bus A" to the first internal busbar. "Internal Bus 1" and connect the second data bus "B" to the second internal bus "Internal Bus 2". Otherwise, if the exchange control signal 'SC_W' is in the second state (ie, in the high state or '1'), then the bus switch circuit 110 connects the first data bus "bus A" to the second internal bus. "Internal Bus 2" and connect the second data bus "B" to the first internal bus "Internal Bus 1".

The start pulse switching circuit 120 is coupled between the clock controller and the first and second shift registers 131, 132. The start pulse switching circuit 120 can be configured to receive the first start pulse STH (A) and the second start pulse STH (B) from the clock controller according to the exchange control signal 'SC_W', and provide the first exchange start pulse The STH (1) and the second exchange start pulse STH (2) are supplied to the first and second shift registers 131, 132.

The start pulse switching circuit 120 is controlled by the exchange control signal 'SC_W', which may be required to operate for the corresponding bus switch circuit 110. For example, if the exchange control signal 'SC_W' is in the first state (ie, in the low state or '0'), the start pulse switching circuit 120 will not execute the first start pulse STH (A) and the second start pulse STH ( The exchange of B) is provided directly as the first exchange start pulse STH(1) and the second exchange start pulse STH(2), respectively. Otherwise, if the exchange control signal 'SC_W' is in the second state (ie, in the high state or '1'), the initial pulse switching circuit 120 will execute the first start pulse STH (A) and the second start pulse STH (B). The exchange, which will be provided directly as the second exchange start pulse STH(2) and the first exchange start pulse STH(1), respectively.

The first shift register 131 is coupled between the start pulse switching circuit 120 and the shift multiplexer 140, and can be sequentially generated by the first switching start pulse STH(1) according to the mode control signal SC_M. The first sequence of latch signals SR1(1)-SR1(n).

Similarly, the second displacement register 132 is coupled between the initial pulse switching circuit 120 and the displacement multiplexer 140, and can be triggered by the second switching start pulse STH(2) according to the mode control signal SC_M. The second sequence of latch signals SR2(1)-SR2(n) is generated in sequence. The first and second shift registers 131 and 132 may each include, for example, a group of flip-flops for performing a shift operation.

The displacement multiplexer 140 is coupled between the first and second displacement registers 131, 132 and the latch multiplexer 150. The shift multiplexer 140 is configured to receive the first sequence of latch signals SR1(1)-SR1(n) and the second sequence of latch signals SR2(1)-SR2(n), and outputs a third sequence of latch signals SR3(1)-SR3(n) by selecting a latch signal of the first sequence and a latch signal of the second sequence. The multiplexer array 143 may include, for example, a plurality of multiplexers as shown in FIG. 1. Each multiplexer can select a corresponding first latch signal SR1(i) and a corresponding second latch signal SR2(i) according to the mode control signal SC_M, wherein one of i=1~n is corresponding The third latch signal SR3(i).

For example, the mode control signal 'SC_M' is labeled (S1, S2, ..., Sn), which means that if Si=0, the i-th multiplexer will transmit the first sequence of latch signals in the shift multiplexer. The i-th 'SR1(i)' in the third sequence is the i-th 'SR3(i)' in the latch signal of the third sequence, and if Si=1, the multiplexer 14(i) will transmit the second latch The lock signal 'SR2(i)' is the i-th 'SR3(i)' in the latch signal of the third sequence.

Each of the plurality of latch multiplexers 150 is coupled to the first internal busbar "internal busbar 1" and the second internal busbar IBSU2. Each of the plurality of latch multiplexers 150 can be configured to selectively transmit pixel data from the first internal bus "internal bus 1" or the second internal bus "internal bus 2" according to the mode control signal SC_M. .

Additionally, the multiplexer 150 and the multiplexer within the shift multiplexer 140 may be required to perform corresponding operations such that they can transmit corresponding pixel data and a third sequence of latch signals to the latch unit 160. For example, the mode control signal 'SC_M' may be labeled as (S1, S2, ..., Sn), which means that if Si = 0, then the i-th multiplexer in the shift multiplexer 150 will take the first internal bus The pixel data of "Internal Bus 1" is transmitted to a corresponding one of the latch units 160. If Si=1, the i-th multiplexer in the shift multiplexer 150 will be taken from the second internal The pixel data of the bus bar "internal bus bar 2" is transmitted to a corresponding one of the latch units 160.

The plurality of latch units 160 are controlled by the third sequence of latch signals SR3(1)-SR3(n) to latch the pixel data from the latch multiplexer 140 to provide a plurality of pixel data D1 (1). )-D1(n). Each of the latch units 160 can be triggered by a corresponding latch signal SR3(1)-SR3(n) provided by the corresponding multiplexer in the multiplexer 140 to obtain more latches. A pixel data provided by a corresponding multiplexer in the workpiece 150, and then a corresponding one of the pixel data D1(1)-D1(n).

Preferably, the multi-mode source driver 100 can further include a latch unit 162 coupled to the latch unit 160. The latch unit 162 can be configured to reconfigure the pixels 'D1(1)'-'D1(n)' received by the latch unit 160 to have a plurality of pixel data 'D2(1)'-'D2(m) 'Provided to output unit 170.

The output unit 170 is configured to provide the pixel data 'D1(1)'-'D1(n)' received from the latch unit 160 through the output channel 'CH(1)'-'CH(m)', respectively. The driving voltage 'DO(1)'-'DO(m)', wherein the pixel data 'D1(1)'-'D1(n)' is preferably rearranged by the latch unit 162 into pixel data 'D2(1) ) '-'D2(m)'. For example, output unit 170 can include a digital to analog converter (DAC) to convert pixel data 'D2(1)'-'D2(m)' to an analog signal, and can include an output buffer to amplify and output the analog signal.

An important feature in this embodiment is that the bus bar switching circuit 110 and the start pulse switching circuit 120 controlled by the exchange control signal 'SC_W' can allow the start pulses 'STH(A)', 'STH(B)', and From data bus The pixel data inputs of "Bus A" and "Bus B" can be exchanged. Another important feature in this embodiment is that the shift multiplexer 140 and the latch multiplexer 150 controlled by the mode control signal 'SC_M' can be selectively transmitted in the internal bus bar "internal bus bar 1" and "internal". The pixel data on the bus bar 2" and the latch signals SR1, SR2 of the first and second sequences. In this embodiment, the multi-mode source driver 100 can rearrange the order of the input pixel data in different manners to provide a driving voltage according to different output modes specified by the mode control signal 'SC_M' and the switching control signal 'SC_W'.

In the example of n=4, if the mode control signal 'SC_M' (labeled as S1, S2, S3, S4) is set to '(0, 0, 1, 1)' and the exchange control signal 'SC_W' is '0 ', the multi-mode source driver 100 operates in the output mode 'AABB'. If the mode control signal 'SC_M' is held at '(0, 0, 1, 1)' and the exchange control signal 'SC_W' is '1', the multi-mode source driver 100 operates in the output mode 'BBAA'.

Since the source driver can simultaneously receive pixel data from the two data bus bars "bus bar A" and "bus bar B", the speed of the multi-mode source driver 100 driving the display panel can be increased. Moreover, since the multi-mode source driver 100 can operate in different output modes, the speed at which the display panel is driven can also be adjusted.

Additionally, because multi-mode source driver 100 has the ability to selectively operate in different modes, multi-mode source driver 100 can have diverse and immediate applications. For example, the multi-mode source driver 100 can be applied to various display panels, so that the advantages of these display panels can be utilized. For another example, if set in the appropriate output mode, two multi-mode source drivers can be used to cooperatively drive the same display surface. The board can alleviate the load from the display panel. Moreover, the multi-mode source driver can operate in a corresponding output mode to drive various display panels, so that a simple control mechanism can be provided. These advantages can be seen in the following examples.

First Embodiment: Dual Multimode Source Drivers Each Having a 12N Output Channel

In this embodiment, two multimode source drivers are used to drive the same display panel, which needs to be driven with 12N output channels (i.e., m = 12N, where N is a non-zero integer). Thus, each of the twelve output channels (ie, every four channel groups for m=3n) can be configured as one channel substrate. Since the multimode source driver has four output channels in each channel substrate, the output mode can thus include modes M ₁ M ₂ M ₃ M ₄ = AAAA, AABB, and ABAB. In addition, the display panel can be driven according to various known driving methods, such as a face inversion method, a line inversion method, a column inversion method, and a dot inversion method.

2A-2C depicts a display device employing two "12N" type multi-mode source drivers as shown in FIG. 1 and operating in different output modes, wherein N can be used, for example, in accordance with an embodiment of the present invention. Is 1. As shown in Figs. 2A-2C, the display device includes a display panel 20, and two multi-mode source drivers 200 and 200' respectively disposed on both sides of the display panel 20.

As shown in FIG. 2A, the multi-mode source driver 200 in the upper half of the display panel 20 and the multi-mode source driver 200' in the lower half of the display panel 20 operate in the output mode AAAA such that the display panel 20 Source lines L1-L3, L4-L6, L7-L9, and L10-L12 will receive the first capital in Figure 1. The pixel data transmitted on the bus "bus A".

As shown in FIG. 2B, the multi-mode source driver 200 in the upper half of the display panel 20 operates in the output mode AABB, and the multi-mode source driver 200' in the lower half of the display panel 20 operates in the output mode BBAA, and thus Each source line can be provided by the multi-mode source drivers 200 and 200' from the same data bus (ie, the first data bus "bus A" or the second data bus "bus B" in FIG. ) Pixel data.

As shown in FIG. 2C, the multi-mode source driver 200 in the upper half of the display panel 20 operates in the output mode ABAB, and the multi-mode source driver 200' in the lower half of the display panel 20 operates in the output mode BABA, and thus Each source line can be provided by the multi-mode source drivers 200 and 200' from the same data bus (ie, the first data bus "bus A" or the second data bus "bus B" in FIG. 1) The transmitted pixel data.

3A-3C are diagrams showing an example of the detailed operation of the two-mode source driver according to an embodiment of the present invention, wherein n=8 and m=n ^* 3=24, so m =6 ^* 4 (ie, N=4).

In the embodiment shown in Figures 3A-3C, the output units are not shown to more clearly describe these embodiments. In addition, the multiplexers in the shift multiplexer 340 are painted in gray or white to indicate their transmission latch signals SR1 and SR2, respectively. In addition, the latch multiplexer 350 is painted in gray or white to transmit data from the internal bus bars 'BUS1' and 'BUS2', respectively.

Table 1 is a list which summarizes the output modes of the multimode source drivers 300 and 300' in Figures 3A-3C and 4A-4C, and the states corresponding to the exchange control signals and mode control signals.

In the 3A, 4A, and Table 1, the two multimode source drivers 300 and 300' operate in the output mode AAAA and receive the exchange control signals 'SC_W' and 'SC'_W which are also '0'. ', and the mode control signals 'SC_M' and 'SC_M' which are also '(0,0,0,0)'.

Please refer to FIG. 4A, which illustrates the first and second sequence latch signals SR1(1)-SR1(8) and SR2(1)-SR2(8) and the third sequence latch provided to the multimode source driver 300. Signals of signals SR3(1)-SR3(8), and describe first and second sequence latch signals SR1'(1)-SR1'(8) and SR2' (1) provided to multimode source driver 300' )-SR2' (8) and the waveform of the third sequence latch signal SR'(1)-SR'(8).

As shown in FIG. 4A, the first sequence of latch signals SR1(1)-SR1(8) are sequentially turned on, and the second sequence of latch signals SR2(1)-SR2(8) are continuously maintained. Low state, and then selectively transmitted according to the mode control signal 'SC'_M'' (0, 0, 0, 0)' to provide a third sequence of latch signals SR3(1)-SR3(8), wherein The latch signal SR3(1)-SR3(8) of the third sequence is SR3(1)=SR1(1)→SR3(2)=SR1(2)→SR3(3)=SR1(3)→...→ The sequence of SR3(8)=SR1(8) is turned on. On the other hand, the first sequence of latch signals SR1(1)-SR1(8) and SR1'(1)-SR1'(8) have the reverse order, ie SR1'(i)=SR1(8-i+1), where the second sequence of latches The lock signals SR2(1)-SR2(8) and SR2'(1)-SR2'(8) have the reverse order, that is, SR2'(i)=SR2(8-i+1). Then, the latching signals SR3(1)-SR3(8) and SR'(1)-SR'(8) of the third sequence also have the reverse order, that is, SR'(i)=SR3(8-i+1 ), so that each source line of the display plane can be driven with the same timing.

In the 3B, 4B, and Table 1, the multi-mode source drivers 300 and 300' operate in the output modes AABB and BBAA, respectively, and receive the exchange control signals 'SC_W' and 'SC' which are both '0'. _W' and the mode control signals 'SC'_M' and 'SC'_M' for '(0,0,1,1)' and '(1,1,0,0)' respectively.

Referring again to FIG. 4B, the latch signals SR1(1)-SR1(8) and SR2(1)-SR2(8) of the first and second sequences are sequentially turned on in the following sequence: SR1(1) and SR2(3) Both are turned on → SR1 (2) and SR2 (4) are both turned on → SR1 (5) and SR2 (7) are both turned on → SR1 (6) and SR2 (8) are both turned on, and then selectively controlled according to the mode ' SC'_M''(0,0,1,1)' is transmitted to provide a third sequence of latch signals SR1(1)-SR1(8), which are turned on in the following sequence: SR3(1)=SR1(1 ) and SR3(3)=SR2(1) are both turned on→SR3(2)=SR1(2) and SR3(4)=SR2(4) are all turned on→SR3(5)=SR1(5) and SR3(7) =SR2(7) is on → R3(6)=SR1(6) and SR3(8)=SR2(8) are both on. On the other hand, SR1'(i)=SR1(8-i+1), SR2'(i)=SR2(8-i+1), SR'(i)=SR3(8-i+1), where So that each source line of the display plane can be driven simultaneously by the multi-mode source drivers 300 and 300'.

In the 3C, 4C, and Table 1, the multi-mode source driver 300 and 300' operates in the output modes ABAB and BABA, respectively, and receives the exchange control signals 'SC_W' and 'SC'_W', both of which are '0' and '(0,1,0,1)' and '( Mode control signals 'SC'_M' and 'SC'_M' for 1,0,1,0)'.

Referring again to FIG. 4C, the latch signals SR1(1)-SR1(8) and SR2(1)-SR2(8) of the first and second sequences are sequentially turned on in the following sequence: SR1(1) and SR2(2) ) are all turned on → SR1 (2), SR1 (3), SR2 (1), and SR2 (4) are all turned on → SR1 (4), SR1 (5), SR2 (3), and SR2 (6) are all turned on → SR1 ( 6), SR1 (7), SR2 (5) and SR2 (8) are both turned on → SR1 (8) and SR2 (7) are both turned on, and then selectively controlled according to the mode 'SC'_M'' (0, 1,0,1)'transmission to provide a third sequence of latch signals SR1(1)-SR1(8), which are turned on in the following sequence: SR3(1)=SR1(1) and SR3(2)=SR2 (2) Both open → SR3 (3) = SR1 (3) and SR3 (4) = SR2 (4) are both turned on → SR3 (5) = SR1 (5) and SR3 (6) = SR2 (6) are turned on → R3(7)=SR1(7) and SR3(8)=SR2(8) are both on. On the other hand, SR1'(i)=SR1(8-i+1), SR2'(i)=SR2(8-i+1), SR'(i)=SR3(8-i+1), where i=1~8, so that each source line of the display plane can be driven by the multi-mode source drivers 300 and 300' at the same time.

Second Embodiment: Z-reverse display plane driven by dual multi-mode source drivers each having a (12N+6) output channel

In this embodiment, two multi-mode source drivers are used to drive the Z-reverse display plane, thereby reducing power. In addition, the output mode in this embodiment can be the same as that described in the first embodiment. That is, every twelve output channels (ie, each The four channel groups can also be configured as a channel base and the output modes can also be AAAA, AABB and ABAB.

FIG. 5 is a schematic diagram showing an example of pixel connection relationships on an output channel and a Z-reverse display plane in accordance with an embodiment of the present invention. The Z reverse type display plane is preferably driven in accordance with a so-called column inversion mode to achieve image quality such as dot inversion, and thus can perform better than the first embodiment.

As shown in the figure, in the conventional Z reverse connection mode, the display panel 60 includes a plurality of pixels connected to the source lines L1-L (12N+1), where N is, for example, one. As shown, the pixels on the same column are each connected to one of two adjacent source lines. In addition, the source lines L1-L13 are respectively driven by the plurality of output channels 'CH1'-'CH13' of the multi-mode source driver 600, and also by the plurality of output channels CH'18 of the multi-mode source driver 600', respectively. Driven by '-'CH'6'. In addition, there are multiple output channels CH14-CH18 of the multi-mode source driver 600 and output channels CH'1-CH'5 of the multi-mode source driver 600', but these channels are not connected to any source lines, making Both the mode source driver 600 and the multi-mode source driver 600' are operable in output modes AAAA, AABB, and ABAB.

6A-6C are schematic diagrams showing a display device in accordance with an embodiment of the present invention, which employs two "12N+6" type multimode source drivers operating in different output modes as shown in FIG. 1, wherein N is, for example, 1. In FIGS. 6A-6C, the display device includes a Z-reverse display panel 70, and two multi-mode source drivers respectively disposed on both sides of the display panel 70.

As shown in Fig. 6A, the multi-mode source drivers 700, 700' operate in the output mode AAAA as in the case of '12N' shown in Fig. 2A.

As shown in FIG. 6B, the multi-mode source driver 700 operates in the output mode AABB, and the multi-mode source driver 700' operates in the output mode AABB instead of the output used in the case of '12N' shown in FIG. 2B. Mode BBAA, such that each source line can be transmitted from the same data bus by the multi-mode source drivers 700 and 700' (ie, the first data bus "bus A" or the second data bus in the first figure" Pixel data for bus B").

As shown in FIG. 6C, the multi-mode source driver 700 operates in the output mode ABAB, and the multi-mode source driver 700' operates in the output mode BABA as in the case of '12N' shown in FIG. 2C, and thus each source The pole lines may be provided by the multi-mode source drivers 700 and 700' from the same data bus (ie, the first data bus "bus A" or the second data bus "bus B" in Figure 1 data.

7A-7C are diagrams showing an example of two multi-mode source drivers corresponding to the 6A-6C diagram, wherein n=10 and m=n ^* 3=30, respectively, in accordance with an embodiment of the present invention. =6 ^* 4+6 (ie, N=4).

In the embodiment shown in Figures 7A-7C, the output units are not shown to more clearly describe these embodiments. In addition, the multiplexers in the shift multiplexer 840 are colored in gray or white to indicate their transmission latch signals SR1 and SR2, respectively. In addition, the latch multiplexer 850 is painted in gray or white to transmit data from the internal bus bars 'BUS1' and 'BUS2', respectively.

Figure 8 is a list of the output modes of the multimode source drivers in Figures 6A-6C and 7A-7C, and the states corresponding to the exchange control signals and mode control signals.

Table 2 is a list of the 7A-7C and 8A-8C The output mode of the multi-mode source driver and the state corresponding to the exchange control signal and the mode control signal.

In the 7A, 8A, and 2 tables, the two multimode source drivers 800 and 800' operate in the output mode AAAA and receive the exchange control signals 'SC_W' and 'SC'_W which are also '0'. ', and the mode control signals 'SC_M' and 'SC_M' which are also '(0,0,0,0)', as in the case of the '12N' type shown in Figures 2A and 3A.

As shown in FIG. 8A, the first sequence of latch signals SR1(1)-SR1(10) are sequentially turned on, and the second sequence of latch signals SR2(1)-SR2(10) are continuously maintained. Low state, and then selectively transmitted by the module control signal 'SC'_M''(0,0,0,0)' to provide a third sequence of latch signals SR3(1)-SR3(10), wherein The third sequence of latch signals SR3(1)-SR3(10) is SR3(1)=SR1(1)→SR3(2)=SR1(2)→SR3(3)=SR1(3)→...→ The sequence of SR3(10)=SR1(10) is turned on. On the other hand, SR1'(i)=SR1(10-i+1), SR2'(i)=SR2(10-i+1) and SR'(i)=SR3(10-i+1), Each source line of the display plane can be multimode at the same time The source drivers 800 and 800' are driven.

In FIGS. 7B, 8B, and 2, the multimode source drivers 800 and 800' operate in the output modes AABB and BBAA, respectively, and receive the exchange control signals 'SC_W' of '0' and '1', respectively. And 'SC'_W' and mode control signals 'SC'_M' and 'SC'_M' for '(0,0,1,1)' and '(1,1,0,0)' respectively.

In addition, the embodiment of the '12N+6' type has the same mode control signals 'SC'_M' and 'SC'_M' as compared with the embodiment of the '12N' type shown in FIGS. 2B and 3B. However, its exchange control signals 'SC_W' and ''SC'_W' are different. Comparing FIGS. 3B and 7B, the bus bar switching circuit and the start pulse switching circuit can exchange the pixel data and the start pulse input from the clock controller to allow the implementation of the '12N+6' type. The example control signals 'SC'_M' and 'SC'_M' are equal to the '12N' type of embodiment. Therefore, the multi-mode source driver can have a simple control mechanism.

Referring again to FIG. 8B, the latch signals SR1(1)-SR1(10) and SR2(1)-SR2(10) of the first and second sequences are sequentially turned on in the following sequence: SR1(1) and SR2(3) Both are turned on → SR1 (2) and SR2 (4) are both turned on → SR1 (5) and SR2 (7) are both turned on → SR1 (6) and SR2 (8) are both turned on → SR1 (9) is turned on → SR1 (10) Turning on, and then selectively transmitting according to the mode control signal 'SC'_M''(0,0,1,1)' to provide a third sequence of latch signals SR1(1)-SR1(8), which is The sequence described later is turned on: SR3(1)=SR1(1) and SR3(3)=SR2(1) are both turned on→SR3(2)=SR1(2) and SR3(4)=SR2(4) are both on→SR3( 5) = SR1 (5) and SR3 (7) = SR2 (7) are both turned on → R3 (6) = SR1 (6) and SR3 (8) = SR2 (8) are both turned on → SR3 (9) = SR1 (9 ) On → SR3 (10) = SR1 (10) is on.

On the other hand, the latch signals SR2'(1)-SR2'(10) and SR1(1)-SR1(10) have the reverse order, and the latch signals SR1'(1)-SR1'(10) and SR2 (1) -SR2(10) has the reverse order. Then, the latching signals SR3(1)-SR3(10) and SR3'(1)-SR3'(10) of the third sequence also have the reverse order, so that each source line of the display plane can use the same timing. drive.

In addition, the configuration shown in Fig. 6B can also be implemented in the embodiments shown in Figs. 9 and 10.

Figure 9 is a diagram showing an exemplary operation of the detailed operation of the two multi-mode source drivers corresponding to Figure 6B in accordance with another embodiment. Figure 10 is a diagram showing an exemplary clock diagram of the waveform of a typical latch signal in Figure 9 in accordance with an embodiment.

Compared with FIG. 7B and FIG. 8B, the multi-mode source drivers 800 and 800' in FIGS. 9 and 10 operate in the output modes AABB and BBAA, respectively, and respectively receive the exchange control signals 'SC_W which are both '0'. 'And' 'SC'_W' and the mode control signals 'SC'_M' and 'SC'_M' which are both '(0,0,1,1)'. Compared with the '12N' type of embodiment, the '12N+6' type embodiment has different mode control signals 'SC'_M' and 'SC'_M' and exchange control signals 'SC_W' and ''SC' _W'. Comparing Figure 7B with Figure 9, it can be seen that the implementation of the busbar switching circuit and the start-up pulse switching circuit allows the pixel data and the starting pulse input from the clock controller to be interchanged, allowing the configuration mode of Figure 6 to be allowed. The control signal and the exchange control signal are different. Therefore, the multi-mode source driver can have a flexible control mechanism.

Referring again to FIG. 10, the first and second sequences of latch signals SR1(1)-SR1(10) and SR2(1)-SR2(10) and the third sequence of latch signals SR1(1)-SR1 (8) is turned on in the order similar to that shown in Fig. 8B. on the other hand, SR1'(i)=SR1(10-i+1), SR2'(i)=SR2(10-i+1), and further SR'(i)=SR3(10-i+1), so that the plane is displayed Each source line can be driven simultaneously by multimode source drivers 800 and 800'.

In the 7C, 8C, and Table 2, the multi-mode source drivers 800 and 800' operate in the output modes ABAB and BABA, respectively, and receive the exchange control signals 'SC_W' and 'SC' which are both '0'. _W' and the mode control signals 'SC'_M' and 'SC'_M' for '(0,1,0,1)' and '(1,0,1,0)', respectively, like 2C and 3C An embodiment of the '12N' type shown.

Referring again to FIG. 8C, the latch signals SR1(1)-SR1(10) and SR2(1)-SR2(10) of the first and second sequences are sequentially turned on in the following sequence: SR1(1) and SR2(2) ) are all turned on → SR1 (2), SR1 (3), SR2 (1), and SR2 (4) are all turned on → SR1 (4), SR1 (5), SR2 (3), and SR2 (6) are all turned on → SR1 ( 6), SR1 (7), SR2 (5) and SR2 (8) are all turned on → SR1 (8), SR1 (9), SR2 (7) and SR2 (10) are both turned on → SR1 (10) and SR2 (9) Both are turned on, and then selectively transmitted according to the mode control signal 'SC'_M'' (0, 1, 0, 1)' to provide a third sequence of latch signals SR1(1)-SR1(8), which The sequence will be opened in the following sequence: SR3(1)=SR1(1) and SR3(2)=SR2(2) are all turned on→SR3(3)=SR1(3) and SR3(4)=SR2(4) are all turned on→ SR3(5)=SR1(5) and SR3(6)=SR2(6) are both on→R3(7)=SR1(7) and SR3(8)=SR2(8) are all on→SR3(9)=SR1 (9) and SR3(10)=SR2(10) are both on. On the other hand, SR1'(i)=SR1(10-i+1), SR2'(i)=SR2(10-i+1), and further SR'(i)=SR3(10-i+1), Each source line of the display plane can be driven simultaneously by multi-mode source drivers 800 and 800'.

Therefore, in the above embodiments, the multimode source driver can be used differently. The mode reconfigures the order of the pixel data input by the clock controller, so the driving voltage can be supplied according to different output modes. Multi-mode source drivers have been disclosed herein to be applicable to a variety of different display panels, regardless of whether the display panel has a special line connection or must be driven with a different number of output channels, so that the different types of display panels can be utilized advantage. Additionally, as in the embodiments of Figures 2A-2C and 6A-6C, the multi-mode source driver can have a different number of output channels to drive different kinds of display panels and can be driven using corresponding output modes (ie, Patterns 'AAAA', 'AABB', 'ABAB'). Among them, two multi-mode source drivers, which have (12N+6) output channels, can operate in a combination of appropriate output modes to cooperatively drive a Z-reverse display panel, thus having a lower power. Moreover, the implementation of the busbar switching circuit and the start-up pulse switching circuit enables the pixel data and the starting pulse input from the clock controller to be interchanged, so that the multi-mode source driver has a simple and flexible control mechanism, like the first Figures 3B, 7B and 9 are shown.

Finally, without departing from the spirit and scope of the present invention, as will be apparent to those skilled in the art, the concept and embodiments of the present disclosure may be readily applied to design or The architecture is used to achieve the same function as the purpose of the present invention.

100‧‧‧Multimode source driver

110‧‧‧ Busbar Switching Circuit

120‧‧‧Starting pulse exchange circuit

131‧‧‧First Displacement Register

132‧‧‧Second displacement register

140‧‧‧Displacement multiplexer

143‧‧‧Multiplexer array

150‧‧‧Latch multiplexer

160‧‧‧Latch unit

162‧‧‧Latch unit

170‧‧‧Output unit

20‧‧‧ display panel

200, 200’‧‧‧ multimode source driver

300, 300’‧‧‧ multimode source driver

310, 310'‧‧‧ Busbar Switching Circuit

320, 320'‧‧‧ starting pulse exchange circuit

331,331'‧‧‧First Displacement Register

332, 332'‧‧‧ second displacement register

340, 340'‧‧‧ Displacement multiplexer

350, 350'‧‧‧Latch multiplexer

360, 360’‧‧‧Latch unit

362, 362'‧‧‧Latch unit

800, 800'‧‧‧ multimode source driver

810, 810'‧‧‧ busbar switching circuit

820, 820'‧‧‧ starting pulse exchange circuit

831, 831'‧‧‧ first displacement register

832, 832'‧‧‧ second displacement register

840, 840'‧‧‧ Displacement multiplexer

850, 850'‧‧‧Latch multiplexer

860, 860'‧‧‧Latch unit

862, 862’‧‧‧Latch unit

1 is a schematic illustration of a multi-mode source driver in accordance with an embodiment of the present invention.

2A-2C is a description of a display according to an embodiment of the present invention The device employs two "12N" type multi-mode source drivers as shown in Figure 1 and operating in different output modes.

3A-3C are diagrams showing an example of the detailed operation of the two multimode source drivers, respectively, in accordance with an embodiment of the present invention, corresponding to FIG. 2A-2C.

4A-4C are diagrams depicting the waveform of a typical latch signal in Figures 3A-3C, respectively, in accordance with an embodiment of the present invention.

Fig. 5 is a schematic diagram showing an example of a Z-reverse display plane in accordance with an embodiment of the present invention.

6A-6C are schematic diagrams showing a display device employing two "12N+6" type multimode source drivers operating in different output modes as shown in FIG. 1 in accordance with an embodiment of the present invention.

7A-7C are diagrams showing an example of two multimode source drivers corresponding to FIGS. 6A-6C, respectively, in accordance with an embodiment of the present invention.

8A-8C are diagrams depicting the waveform of a typical latch signal in Figures 3A-3C, respectively, in accordance with an embodiment of the present invention.

Figure 9 is a diagram showing an exemplary operation of the detailed operation of the two multi-mode source drivers corresponding to Figure 6B in accordance with another embodiment.

Figure 10 is a diagram showing an exemplary clock diagram of the waveform of a typical latch signal in Figure 9 in accordance with an embodiment.

100‧‧‧Multimode source driver

110‧‧‧ Busbar Switching Circuit

120‧‧‧Starting pulse exchange circuit

131‧‧‧First Displacement Register

132‧‧‧Second displacement register

140‧‧‧Displacement multiplexer

143‧‧‧Multiplexer array

150‧‧‧Latch multiplexer

160‧‧‧Latch unit

162‧‧‧Latch unit

170‧‧‧Output unit

Claims (18)

A multi-mode source driver is coupled to the first and second data busses for driving a display device, comprising: a bus bar switching circuit for connecting the first data bus bar to a first internal confluence according to an exchange control signal Aligning one of the second internal bus bars and connecting the second data bus to the other of the first internal bus and the second internal bus; an initial pulse switching circuit according to the exchange The control signal receives a first start pulse and a second start pulse to provide a first exchange start pulse and a second exchange start pulse; a first shift register is triggered by the first exchange start pulse to generate a first sequence of latch signals; a second shift register triggered by the second swap enable pulse to generate a second sequence of latch signals; a shift multiplexer receiving the first sequence a latch signal and the latch signal of the second sequence, and outputting a third sequence of latch signals by selecting the latch signal of the first sequence and the latch signal of the second sequence; Locking multiplexers, each coupled to the first internal busbar and the second internal busbar, and each configured to selectively transmit from the first internal busbar or the second internal busbar according to a mode control signal Pixel data; a plurality of latch units controlled by the latch signal of the third sequence to latch the pixel data from the latch multiplexer; An output unit configured to provide a plurality of drive voltages based on the pixel data from the latch unit. The multi-mode source driver of claim 1, wherein the displacement multiplexer and the first and second displacement registers are controlled by the mode control signal. The multi-mode source driver of claim 1, wherein the multi-mode source driver is configured by the mode control signal and the exchange control signal to selectively select one of a plurality of output modes. operating. The multi-mode source driver of claim 3, wherein the multi-mode source driver selects pixel data received from the first data bus or from the second data bus according to the output mode. The received pixel data is provided to each of a plurality of channel groups. As described in the multi-mode source driver described in claim 4, the output mode includes M ₁ M ₂ M ₃ M ₄ = AAAA, AABB, and BBAA modes, and if Mi=A, the multi-mode source driver will The pixel data received by the first data bus is provided to the i-th group in the channel group. If Mi=B, the multi-mode source driver supplies the pixel data received from the second data bus to the The i-th group in the channel group, where i=1~4. The multimode source driver of claim 1, wherein the output unit has 12N output channels, wherein N is a non-zero integer. The multimode source driver of claim 1, wherein the output unit has (12N+6) output channels, where N is a non-zero integer. The multi-mode source driver of claim 1, wherein the multi-mode source driver is coupled to drive a Z-inverted display panel. A display device comprising: a display panel; the first multi-mode source driver according to claim 1, wherein the device is driven on the side of the display panel; and One of the second multi-mode source drivers, the device being on the other side of the display panel to drive the display panel. The display device of claim 9, wherein the displacement multiplexer and the first and second displacement registers are in the mode in each of the first and second multi-mode source drivers Control signal is controlled. The display device of claim 9, wherein each of the first and second multi-mode source drivers are selectively set by the respective mode control signals and the respective exchange control signals. plural One of the output modes operates. The display device of claim 11, wherein each of the first and second multi-mode source drivers converts pixel data received from the first data bus according to the output mode or from the second The pixel data received by the data bus is provided to each of the plurality of channel groups. The display device of claim 12, wherein the output mode of each of the first and second multi-mode source drivers comprises M ₁ M ₂ M ₃ M ₄ = AAAA, AABB, and BBAA modes, if Mi=A, the multi-mode source driver supplies the pixel data received from the first data bus to the i-th group in the channel group. If Mi=B, the multi-mode source driver will be from the first The pixel data received by the data bus is provided to the i-th group in the channel group, where i=1~4. The display device of claim 9, wherein the output unit of each of the first and second multi-mode source drivers has 12N output channels, wherein N is a non-zero integer. The display device of claim 9, wherein the output unit of each of the first and second multi-mode source drivers has (12N+6) output channels, wherein N is a non-zero integer. The display device of claim 14, wherein When the first multi-mode source driver operates in the AAAA, AABB, and ABAB modes, the second multi-mode source driver operates in the AAAA, BBAA, and BABA modes, respectively. The display device of claim 15, wherein when the first multi-mode source driver operates in the AAAA, AABB, and ABAB modes, the second multi-mode source driver operates in AAAA, AABB, and BABA mode. The display device of claim 17, wherein the display panel is a Z reverse display surface.