KR20050112263A - Driving circuit and system for liquid crystal display - Google Patents

Abstract

Disclosed are a circuit and a system for driving a liquid crystal display panel. According to an embodiment of the present invention, the output polarity of the source driver circuit for driving the source line of the liquid crystal display panel may be alternately changed, thereby extending the pixel life of the liquid crystal display and minimizing interference between pixels and improving image quality. Markedly improved. To this end, a polarity control unit and a dummy DAC circuit for selectively controlling a multiplexer inside the source driver are mounted in the source driver. According to another embodiment of the present invention, a polarity control unit may be separately provided from the source driver so that the polarity of the voltage applied to the panel may be alternately changed without difficulty even when the source driver driving the source line of the liquid crystal display panel is an odd number. Or a polarity control part in the source driver to form a liquid crystal display panel drive system. According to another exemplary embodiment of the present invention, one source driver may be determined based on a relative position of a load signal input to a source driver and a start pulse SP to determine where the source driver is mounted in the liquid crystal display panel. It is now possible to alter the polarity of the output voltage alternately between the outputs belonging to and the outputs belonging to adjacent source drivers.

Description

Liquid crystal display driving circuit and driving system {Driving circuit and System for Liquid Crystal Display}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving circuit. In particular, the structure of a digital-to-analog converter (DAC) inside an integrated circuit driving a source line of a liquid crystal display panel is adapted to the driving of a source line of a liquid crystal display. It relates to a technique for alternating polarity alternately.

A liquid crystal display (LCD) refers to a device in which image data is displayed by passing light through a liquid crystal using a feature in which arrangement states of liquid crystal molecules vary according to an applied voltage. Among these, the most actively used device is a thin film transistor (TFT) type liquid crystal display (LCD) made using a manufacturing technology of a silicon integrated circuit.

Since the liquid crystal molecules are arranged differently according to the polarity of the voltage applied to the liquid crystal display, if the voltage polarity in one direction is continuously applied, the characteristics of the liquid crystal molecules, such as the responsiveness and arrangement of the liquid crystal molecules, are reduced, thereby increasing the interference between pixels. But the picture quality is poor. Therefore, whenever the data of the horizontal line of each pixel array changes, it is common to change the polarity of the applied voltage applied to each pixel of the liquid crystal.

As shown in FIG. 1A, the inversion of the applied voltage of each pixel has a line inversion technique in the unit of a source line of the liquid crystal panel. As shown in FIG. There is a dot inversion technique that has been inverted. Recently, most companies use the dot inversion technique. The horizontal two-dot inversion technique that applies the dot inversion technique to invert every two adjacent dots as shown in FIG. 1C is also widely used in recent years. 1A to 1C, each symbol in the liquid crystal display panel 30 represents one pixel, and output terminals (out 1 to out n) of the source drivers 21 and 22 are each pixel of the liquid crystal display panel 30. A terminal for outputting a voltage for driving a column or a source line. 1A to 1C are extremely simplified diagrams for explaining only the voltage inversion phenomenon of a pixel.

On the other hand, a system for driving a general liquid crystal display panel, as shown in Figure 2 and the panel 30 consisting of a liquid crystal and a color filter, and the gate driver 40 consisting of gate drivers (41, 42, 43) and And a source driver 20 including source drivers 21, 22, and 23 driving the source lines of the liquid crystal, a timing for controlling the gate driver 40 and the source driver 20 and outputting pixel data. It is comprised by the control part 10.

Each pixel is composed of a switch transistor and a liquid crystal element, and the gate terminal of the switch transistor is driven by the gate drivers 41, 42, 43 .... A liquid crystal element is connected to one terminal of the switch transistor except for the gate terminal, and an output terminal of the source drivers 21, 22, 23 ... is connected to the other terminal of the switch transistor.

The timing controller 10 controls timing of the gate drivers 41, 42, 43 ... and the source drivers 21, 22, 23 ... as a part of the overall control of the liquid crystal display panel system. The video signals R, G, and B are transmitted to the source drivers 21, 22, 23, ....

Hereinafter, the overall operation of the liquid crystal display panel system will be described in more detail.

Among the source timing signals, the LOAD, SPi and POL signals are commonly supplied to all the source drivers 21, 22, 223 .... However, the SPi signal is only connected to the SPi terminal of the first source driver 21 from the timing controller 10, and the signal from the SPo terminal of the front end is connected to the SPi terminal of the remaining source drivers 22, 23 .... do. Note that the SPi signal and the SPi terminal must be distinguished from each other, and the SPo signal and the SPo terminal are the same. After the first source driver 21 recognizes the Spi signal, the first source driver 21 starts to accept the video signals into the chip. When the video signal input is completed, the first source driver 21 outputs the SPo signal to the second source driver 22. This SPo signal is input to the SPi terminal of the second source driver 22. The SPo signal input to the SPi terminal of the second source driver 22 functions like the SPi signal received by the first source driver 21 to cause the second source driver 22 to receive a video signal. In this way, all the source drivers are sequentially operated by the signal input to the SPi terminal, so that all the source drivers connected to the liquid crystal display panel 30 receive the video signals. Thereafter, the outputs of all the source drivers 21, 22, 23, ... are transferred to the liquid crystal display panel 30 at once by the LOAD signal, thereby finally displaying data of one horizontal line. At this time, the POL signal determines the polarity of the output voltage of the source driver delivered to the panel. For convenience, the time interval in which data of one horizontal line is displayed is defined as T _LOAD for convenience.

The above-described operation is repeated during the next T _LOAD period, but the phase of the signal POL, which determines the polarity, is inverted and supplied to each source driver 21, 22, 23, ... in order to achieve the inversion of the voltage polarity described above. do.

The operation inside the source driver will now be described with reference to the simplified block diagram of FIG. 3A and the timing diagram of FIG. 3B.

The clock signal CLK is a signal supplied so that the source driver 21 operates in synchronization with a periodic clock. The shift register block 310 is sequentially driven by an SPi signal indicating a start of an operation to output a signal for driving the latch block 330.

The SPi signal is input from the timing controller 10 (FIG. 2) or input from SPo, which is an output terminal of the previous source driver, and is a signal for instructing a specific source driver among several source drivers to start operation.

As the SPi signal is input to the shift register block 310 inside one specific source driver, the sequential driving of the shift register block 310 starts, and when the sequential driving ends, the shift register block 310 outputs the SPo signal to the next. Deliver to the source driver of the stage. As shown in Fig. 2, this SPo signal becomes the Spi signal of the next stage source driver, instructing the next stage source driver to start operation. In this way, all the source drivers connected to the liquid crystal display panel are driven sequentially.

The driving of the source driver is performed in synchronization with the clock signal CLK, and the video signals R, G, and B are inputted to the specific source driver while a predetermined number (assuming m) clock signals CLK are input. Therefore, the completion of the video signal input of a specific source driver and the next source driver is delayed by mT _CLK .

In order to describe the operation of the latch block 330 in more detail, reference may be made to the timing diagram illustrated in FIG. 4. The latch block 330 is electrically connected to the output terminal of the shift register block 310 to sequentially sequence the video signals R, G, and B from the data register block 320 according to the output signal of the shift register block 310. As a result, the latch block 310 is sampled. The video signals R, G, and B input to the latch block 330 are input to the DAC block 340 having N outputs (hereinafter, DAC block) 340 according to the load signal LOAD at one time. After the latch block 330 is configured in two stages so that the sampling and loading operations can be properly performed in the latch block 330, the latches of the first stage perform the sampling operation and the latches of the first stage perform the load operation. It's okay.

The gamma correction voltages V1 to V2 and V3 to V4 are transmitted to the output of the DAC block 340 in response to the video signal input from the latch block 330 to the DAC block 340. The output voltages of these DAC blocks 340 drive n source lines among numerous source lines of the liquid crystal display panel by an n-output circuit block (hereinafter, an output circuit block) 350 having n outputs.

At this time, the POL signal determines the voltage polarity of the output signal of the output circuit block 350.

The above-described operation is repeated periodically so that the source driver drives the liquid crystal display panel, and when the next LOAD signal is input, the phase of the polarity signal POL is changed to reverse the polarity of the output signal of the output circuit block 350. That is, the polarity of the voltage applied to the liquid crystal display panel is alternately changed at each cycle of T _LOAD in which the phase of the POL signal is inverted.

In more detail, as shown in the timing diagram of FIG. 4, the phase of the POL signal is inverted every one period (T _LOAD ) of the LOAD signal, and thus the odd-numbered output of the output circuit block 350 (FIG. The voltage polarities of even-numbered outputs alternate with each other. To better illustrate this relationship, a relative timing diagram for the LOAD signal, the POL signal, and the output of the source driver 21 is shown in FIG. If the number of source drivers connected to the liquid crystal display panel is y, the period of T _LOAD becomes approximately y times m times T_CLK, and the phase of the POL signal is reversed every y times m times T_CLK time.

As shown in the timing diagram, one LOAD signal is input every cycle T, and the corresponding POL signal is also inverted every cycle T _LOAD . In response to the inversion of the POL signal, a multiplexer (not shown) inside the output circuit block 350 controls the polarity of the output voltage of the output circuit block 350 to change.

 Hereinafter, the operation of the conventional source driver will be described in more detail with reference to FIG. 5. For convenience of description, only four output terminals are displayed among the n output terminals, and it should be noted that multiplexers 3501 and 3502 not shown in FIG. 3 are shown in the output circuit block 350. The DAC block 340 includes first DACs (PDACs) and second DACs (NDACs) that output values of voltage ranges having different polarities.

For example, during a period in which the POL signal is “high,” the first DACs PDPD output values of a voltage range between V1 and V2, which are the first polarity voltages, among the gamma correction voltages according to the data output of the latch block 330. 2 DACs (NDACs) output values of a voltage range between V3 and V4, which are second polarity voltages, among the gamma correction voltages according to the data output of the latch block 330.

These voltages of different polarities are transmitted to the output buffers 351, 352, 353, and 354 through solid paths (hereinafter, solid lines) inside the multiplexers 3501 and 3502 to drive the source lines of the liquid crystal display panel. Signal (out 1 to out 4). Thus, during the period where the POL signal is "high," the odd-numbered output buffers 351 and 353 in the output block 350 output the value of the first polar voltage and the even-numbered output buffers 352 and 354. ) Outputs the value of the second polar voltage.

Next, during the period in which the POL signal is "low", the multiplexers 3501 and 3502 are connected by a path indicated by a dotted line (hereinafter, referred to as a dotted line path). Therefore, the odd numbered output buffers 351 and 353 in the output circuit block 350 output the second polarity voltage and the even numbered output buffers 352 and 354 output the first polarity voltage. In the liquid crystal display panel, voltages having different polarities are alternately applied to each signal section, that is, when the POL signal is inverted.

However, this conventional method has the following problems. Hereinafter, the problem of the conventional method will be described with reference to FIG. 6A.

The source driver is designed and manufactured as integrated circuits, mounted on a liquid crystal display panel, and controlled by a signal commonly provided from the timing controller 10 (FIG. 2) of the liquid crystal display panel 30 (FIG. 1). During the period of " high ", the odd-numbered output of the source driver outputs a voltage having positive polarity (or negative polarity), and the even-numbered output outputs a voltage having negative polarity (or positive polarity). Since the number of output terminals of a conventional source driver is an even number, polarity inversion occurs without difficulty even between source lines connected to adjacent source drivers. That is, the polarity of the last output terminal belonging to one source driver and the polarity of the first output terminal belonging to the next source driver are also inverted.

However, as shown in FIG. 6A, when the number of output terminals of the source driver is an odd number, the polarity of the last output terminal out 2k-1 belonging to one source driver 21 and the next source driver 22 belong to the next source driver. The polarities of the first output terminal out 1 are the same without being inverted with each other, causing a problem with the image. This is because all the source drivers are commonly controlled by the timing controller as described above. Therefore, in order to invert source lines of all liquid crystal display panels, there is a problem in that the number of output terminals of the source driver must be configured even.

In addition, when the number of outputs of the source drivers is even and the number of source lines of the liquid crystal display panel is odd, the last source line of the panel may not be connected to the output terminal of the source driver or the output terminals may remain.

Even if the number of output terminals of the source driver is even, the number of source lines of the liquid crystal display panel is not sufficient even if the number of source lines of the liquid crystal display panel is equal to realize the case of horizontal two-dot inversion in which the polarity is inverted by pairing two pixels. There is also a problem that must be a multiple of 4. A detailed illustration of this problem is shown in Figure 6b, which indicates that horizontal two-dot inversion is not possible at the boundary of adjacent source drivers when the output of the source driver is not even a multiple of four but only an even number (10). will be.

The present invention has been made to solve such problems, and by adding a dummy DAC circuit and an output buffer inside the source driver, a source driver having an odd number of output terminals as well as a source driver having an even number of output terminals are unreasonable. It has a reverse function without.

In addition, even if the number of source lines of the liquid crystal display is odd, the pixels of each source line can perform an appropriate inversion operation.

Furthermore, by properly designing the polarity control unit for controlling the voltage polarity of the output terminal of the source driver, the voltage polarity of the output terminal can be alternately repeated even if the number of source driver output terminals is even or odd.

In order to achieve the above object, a liquid crystal display panel driving circuit according to an aspect of the present invention

Shift registers sequentially operating according to a periodic clock signal; Latches for latching a video signal; First digital-to-analog converters for outputting a first polarity voltage by controlling the output of the latches; Second digital-to-analog converters for outputting a second polarity voltage under the control of the output of the latches and disposed adjacent to the first digital-to-analog converter; A dummy digital-to-analog converter for outputting a first polarity voltage by controlling the output of the latches; Path selection circuits for selecting one of an output of the first digital-to-analog converters and an output of the second digital-to-analog converters; A polarity control unit controlling selection of path selection circuits; And an output circuit unit receiving the output of the path selection circuits to drive the liquid crystal display panel.

The liquid crystal display panel drive system according to another aspect of the present invention for achieving the above object is

Latches for latching a video signal; First digital-to-analog converters for outputting a first polarity voltage by controlling the output of the latches; Second digital-to-analog converters for outputting a second polarity voltage under the control of the output of the latches and disposed adjacent to the first digital-to-analog converter; A dummy digital-to-analog converter for outputting a second polarity voltage by controlling the output of the latches; Path selection circuits for selecting one of an output of the first digital-to-analog converters and an output of the second digital-to-analog converters; And output buffers driving the liquid crystal display panel by receiving the outputs of the path selection circuits; and a polarity control unit for selectively controlling the polarity of the output voltage of the output buffer of the liquid crystal display driving integrated circuit. Characterized in that it comprises a.

According to another aspect of the present invention for achieving the above object, a liquid crystal display panel driving system includes: latches for latching a video signal; First digital-to-analog converters for outputting a first polarity voltage by controlling the output of the latches; Second digital-to-analog converters for outputting a second polarity voltage under the control of the output of the latches and disposed adjacent to the first digital-to-analog converter; A first dummy digital-to-analog converter for outputting a first polarity voltage by controlling the output of the latches; A second dummy digital-analog converter for outputting a second polarity voltage by controlling the output of the latches; Output buffers receiving an output of the first digital-to-analog converters, an output of the second digital-to-analog converters, an output of the first dummy digital-to-analog converter, and an output of the second dummy digital-to-analog converter; Path selection circuits for selecting one of an output of an odd-numbered output buffer and an output of an even-numbered output buffer among the output buffers; And a polarity control unit for controlling the selection operation of the path selection circuit of the liquid crystal display driving integrated circuit.

According to another aspect of the present invention, a liquid crystal display panel driving system includes: gate driving integrated circuits driving a gate of a liquid crystal panel pixel; Source driving integrated circuits driving a source of the liquid crystal panel pixel and having an odd number of output terminals; A controller configured to generate signals for controlling the source driver integrated circuits and the gate driver integrated circuits; A polarity control unit for alternately changing the voltage polarity of the output signals of the source driving integrated circuits, the polarity control unit receiving a polarity signal generated from the control unit, and having an even number in the odd number of the source driving integrated circuits And supplying the output polarity signals inverted to each other to the source driving integrated circuit located at the second position.

According to another aspect of the present invention, a liquid crystal display panel driving system includes: gate driving integrated circuits driving a gate of a liquid crystal panel pixel; Source driving integrated circuits driving a source of the liquid crystal panel pixel; And a control unit for generating signals for controlling the source driving integrated circuits and the gate driving integrated circuits. The polarity control unit included in the source driving integrated circuit includes an input of an input terminal indicative of a hole and a polarity signal from the control unit. The alternating polarity inversion of the output voltage of the source driving integrated circuit is controlled by the combined logic operation.

In accordance with another aspect of the present invention, an integrated circuit for driving a source of a liquid crystal display panel includes: shift registers sequentially operating according to a periodic clock signal; Latches for latching a video signal; Digital-to-analog converters for outputting an analog voltage by controlling the output of the latches; An output circuit unit receiving the analog output voltage of the digital-analog converter to drive the liquid crystal display panel; It is characterized in that it comprises a counter by counting the periodic clock, in addition, by the detection operation of the counter, the voltage polarity of each adjacent output terminal of the output circuit part alternately in opposite polarity with each other when there is a detection operation. It is characterized by a change.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

7 is a diagram illustrating an embodiment of the present invention. For convenience of explanation, it is assumed that the source driving circuit has four even output lines.

The latch block 330 latches the video signal transmitted from the data register block 320 (FIG. 3) and delivers it to the DAC block 340, which is a digital-to-analog conversion block at an appropriate moment.

The DAC block 340 is an analog signal of the first polarity voltage (V1 ~ V2) and the second polarity voltage of the gamma correction voltage (gamma correction voltage) by the control of the video signal transmitted from the latch block 330 ( V3 to V4) are output to the multiplexers 3501 to 3504.

For the inverting operation of the liquid crystal display panel as described above, the analog signals V1 to V2 of the first polarity voltage may be voltages having a positive polarity, and the analog signals of the second polarity voltage are voltages having a negative polarity. It can be (V3 ~ V4).

On the contrary, the voltage having the negative polarity of the analog signals V1 to V2 of the first polarity voltage may be the voltage having the positive polarity of the analog signals V3 to V4 of the second polarity voltage.

The multiplexers 3501 to 3504 appropriately select analog signals of the first polarity voltage and the second polarity voltage received from the DAC block 340 according to the control of the POL signal, the polarity selection signal, to the output buffers 351 to 354). To pass.

The output block 350 is a circuit for transmitting the input signal of the first polarity voltage and the signal of the second polarity voltage to the liquid crystal display panel.

The polarity control unit 360 causes the odd-numbered PDAC blocks 341 and 343 to output the analog signals V1 to V2 of the first polarity voltage in the normal phase timing period in which the multiplexers 3501 to 3504 drive the liquid crystal display panel. The odd-numbered output buffers 351 and 353 are delivered, and the even-numbered NDAC blocks 342 and 344 transmit analog signals V3 to V4 of the second polarity voltage to the even-numbered output buffers 352 and 354. It serves to control the multiplexers (3501 ~ 3504) so as to. That is, the solid line path of the multiplexers 3501 to 3504 is selected by the POL signal.

In the POL timing section in the opposite phase, the output signals of the even-numbered NDAC blocks 342 and 344 are transmitted to the odd-numbered output buffers 351 and 353, and the output signals of the odd-numbered PDAC blocks 341 and 343 are even-numbered. The multiplexers 3501 to 3504 are controlled to be transferred to the first output buffers 352 and 354. In this case, the POL signal causes the multiplexers 3501 to 3504 to select a dotted line path.

In order to represent the operation according to the POL timing section of the normal phase and the POL timing section of the opposite phase, the output of the DAC block 340 and the output of the multiplexers 3501 to 3504 are shown in solid and dotted lines, respectively. .

As described above, the source lines out1 to out4 of the liquid crystal display have a first polarity voltage V1 to V2 and a second polarity voltage V3 in the first normal phase POL timing section and the next antiphase POL timing section, respectively. Will have an alternate value of ~ V4).

The dummy DAC 346, which is located at the end of the DAC block 340, is additional, and the value of the first polarity voltage passes through the dummy DAC-multiplexer 3504-output buffer 354 in the POL timing interval in the opposite phase. It is to let go.

As described above, a source driver having four outputs (out1 to out4) has been described as an example in order to describe an embodiment of the present invention shown in FIG. 7, but the present invention is not limited to four outputs, but has an even number of outputs. Applicable to any kind of source driver.

Furthermore, the present invention can be applied to a source driver having an odd number of outputs as shown in FIG. Similar to FIG. 7, the gamma correction voltage input to the dummy DAC 346 is a value of the second voltage range. The multiplexer 3505 transmits the output voltage of the PDAC 345 to the output buffer 355 in the POL timing section of the normal phase by the polarity signal POL, and outputs the dummy DAC 346 in the POL timing section of the opposite phase. Control to transfer to the output buffer (355). In the case of FIG. 8, since the unit DACs 341 to 346 include dummy DACs 346, there is always one more than the number of output buffers 351 to 355 as in the case of FIG. 7.

9, even if the dummy DACs 345 and 346 are present in pairs in the source driver having an odd number of outputs, the spirit of the present invention can be implemented. Unlike the case of FIG. 8, the number of unit DACs including the dummy DACs 345 and 346 and the number of output buffers 3501 to 3506 are the same. In addition, unlike the configuration of FIG. 7 or FIG. 8, the output buffers 3501 to 3506 are located at the front end of the multiplexers 3501 to 3503 within the output circuit block 350. 7 to 9, the relative positions of the output buffer and the multiplexer may be interchanged.

The multiplexer 3503 connected to out 2k-1, which is the last output of the output circuit block 350, differs from other multiplexers 3501 through 3502. The other multiplexers 3501-3502 are similar in operation to the prior art. However, the last multiplexer 3503 operates to transfer the first polarity voltage from the output buffer 355 to the output terminal out 2k-1 in the timing section in which the POL signal is in phase normal, and outputs in the timing section in the opposite phase of the POL signal. The second polarity voltage from the buffer 356 is transferred to the output terminal out 2k-1. In FIG. 9, the connection paths of the multiplexers 3501 to 3503 according to the phase of the POL signal are indicated by solid and dotted lines, respectively.

FIG. 10 is a diagram illustrating a case where a source driver such as FIG. 7 having an even number of output terminals according to the present invention is connected to a liquid crystal display panel. The source drivers 21 and 22 have an even number of output signals, and each of the adjacent source drivers has a polarity control unit 360 therein. The input signal POL of the polarity control unit 360 transmitted from the timing control unit 10 (FIG. 2) is configured so that the voltage polarity of the source line of the liquid crystal display panel is inverted at every T _LOAD cycle. 22) The internal output circuit block 350 (not shown) is appropriately controlled. The polarity control unit 360 is embedded in each source driver as shown, and the polarity signal POL from the timing control unit 10 (Fig. 2) is commonly connected to all the source drivers.

However, as shown in another example of the present invention illustrated in FIG. 11, the polarity control unit 360 is configured separately from the source driver, and the output circuit block in the source drivers 21 and 22 is output by the output signal POL_out of the polarity control unit 360. 350 may be controlled.

12 illustrates another embodiment of configuring a liquid crystal display panel system using a source driver when the source driver has an odd number of outputs according to the inventive concept. For convenience, the input signal of the polarity control unit 360 is denoted by POL, the output signal is denoted by POLout and / POLout, and POLout and / POLout are opposite phase signals. In addition, the inside of the polarity control unit 360 is briefly shown as an inverter, but this is merely to simplify the function of the present invention and the actual configuration may be variously modified.

The polarity control unit 360 is provided separately from the source drivers 21 to 24 and may be an integrated circuit having a simple digital logic circuit. In addition, the polarity control unit 360 may be provided inside the timing control unit 11 (see FIG. 2) which oversees the control of the liquid crystal display panel system.

In FIG. 12, the source lines that belong to different source drivers but are adjacent to each other, for example, the output out 2k-1 of the source driver 21 and the output 1 out of the source driver 22 have opposite polarities in every T _{LOAD period} . The polarity signals POLout and / POLout input to the odd source drivers 21 and 23 and the even source drivers 22 and 24 may be opposite phases. In this case, the source drivers 21 to 24 may be driven in this manner as long as they have an odd number of output terminals.

The operation of the polarity control unit 360 is similar to that already described above. In the POL timing section of the first normal phase, the odd-numbered outputs (out1, out3, .... out 2k-1) of the odd-numbered source drivers 21 and 23 represent the value of the first polar voltage, and the even-numbered output (out2). The output is controlled to indicate the value of the second polarity voltage. This is done by the polarity control unit 360 controlling the output block 350 (Fig. 8) inside the odd-numbered source drivers 21, 23.

In contrast, the odd-numbered outputs (out1, out3, .out. 2k-1) of the even-numbered source drivers 22, 24 represent the value of the second polarity voltage in the first normal phase POL timing section. The outputs (out2, out4,...) Outputs represent the value of the first polarity voltage so that adjacent source lines of adjacent source drivers, e.g., outputs 2k-1 of source driver 21 and out 1 of source driver 22, are output. The outputs-are controlled to have opposite polarities to each other.

In the POL timing section of the opposite phase, the odd-numbered outputs (out1, out3, .out. 2k-1) of the odd-numbered source drivers 21, 23 represent the value of the second polarity voltage, and the even-numbered outputs (out2, out4). The output is controlled to indicate the value of the first polar voltage. This is the polarity control unit 360 controls the output block 350 (Fig. 8) inside the odd-numbered source drivers (21, 23). On the contrary, the odd-numbered outputs (out1, out3, .out. 2k-1) of the even-numbered source drivers 22, 24 represent the value of the first polar voltage, and the even-numbered outputs (out2, out4, ...) The output represents the value of the second polarity voltage such that adjacent source lines of adjacent source drivers, e.g., the output out 2k-1 of the source driver 21 and the out 1 output of the source driver 22, have opposite polarities. Controlled.

Even in the case of a source driver having an odd number of output terminals, if the polarity control unit is properly designed, the polarity control unit can be placed inside the source driver.

Hereinafter, another embodiment of the present invention will be described with reference to FIG. 13.

When the polarity control unit 360 is designed as shown in Fig. 13, if the source driver mounted on the liquid crystal display panel is mounted odd-numbered, the ground voltage GND is mounted on the even-numbered input terminal E / O. If the power supply voltage VDD is connected to the input signal E / O, the wiring of the panel is designed. In the odd-numbered source driver 21, the POL signal and the POLout signal transmitted from the timing controller 10 (FIG. 2) by the operation of the internal polarity control unit 360 have the same phase. On the other hand, the even-numbered source driver 22 has a phase opposite to that of the POL signal and the POLout signal transmitted from the timing controller 10 (FIG. 2) by the operation of the internal polarity control unit 360. Since the phases of the POLout controlling the polarity of the odd-numbered source driver 21 and the POLout controlling the polarity of the even-numbered source driver 22 are always opposite to each other, these signals are the same in the multiplexer inside the source driver of each of the even and holes. By controlling the solid line path and the dotted line path, the polarity of the output can be easily reversed even when the number of source driver output terminals is odd. The polarity control unit 360 shown in FIG. 13 is merely exemplary and may have various design forms.

Another embodiment of the present invention is to control the operation of the polarity control unit using a clock signal and a counter (counter). This embodiment can control the odd-numbered source driver and the even-numbered source driver similarly to the method of FIG. 13. In this embodiment, voltage polarity reversal is achieved by controlling the polarity signals of the odd-numbered source drivers and the polarity signals of the even-numbered source drivers to have opposite phases with each other by using a counter that counts the clock signal CLK. An advantage of this embodiment is that the polarity control unit including the counter can be designed inside the source driver, so that it is not necessary to make a separate polarity control unit in the liquid crystal display panel.

 Hereinafter, another embodiment of the present invention will be described with reference to the circuit diagram of FIG. 14A and the timing diagram of FIG. 14B. Note that the subscripts in all symbols are for convenience only to indicate the source driver's location.

As described above, since several source drivers mounted on the liquid crystal display panel operate sequentially, the start timing of the operation is different. As shown in FIG. 14B, after the image data of the previous horizontal line is loaded, alpha clock cycles are required until the first source driver 21 receives the SPi signal starting the video signal input operation, that is, from LOAD to SPi. Assume that After the first SPi signal is input, the shift register inside the first source driver 21 sequentially operates for m clock cycles to latch the video signal into the source driver 21. The latch operation is completed when the alpha + m clock has passed from the LOAD signal. When the latch operation is completed, the first source driver 21 generates a SPo_1 signal and transmits the signal to the SPi terminal of the second source driver 22 so that the second source driver 22 starts to operate. To latch the video signal. After the alpha + 2m clock signal, the SPo_2 signal generated by the second source driver is input to the SPi terminal of the next source driver. In this order, all the source drivers connected to the liquid crystal display panel are sequentially operated to latch the video signal.

Next, when the second LOAD signal comes in, appropriate gamma correction voltage is output by the video signals latched in all source drivers, and is transferred to the liquid crystal display panel to finish the video display of one horizontal line. The phase of the polarity signal POL is kept constant during the period in which one LOAD signal and the next LOAD signal are received. Each time the LOAD signal comes in, the phase of the POL signal changes and the polarity reversal of the panel is achieved, as described above.

In order to understand the specific operation of the counter, Fig. 14C shows the operation timing of the counter. Hereinafter, the operation of the counter will be described with reference to FIGS. 14A, 14B, and 14C.

The counter is an m-bit counter that counts m clock signals, and preferably a ring counter in which the binary logic value of its output continuously changes when the m clock signals are counted.

As described above, the number m is the number of clock signals required until one source driver accepts all of the video signals.

First, when the power supply voltage and the clock signal CLK start to be applied to the counter, the counter controller 3610 detects the LOAD signal that is applied first and transitions the Rst_Load signal to "high" to turn all counters to "low". Reset This Rst_Load signal is generated only once after the counter is powered up, and is not a pulse signal generated for every LOAD signal.

 The Rst_Load signal may be simply implemented in the counter controller 3610 by combining a power-on-reset (POR) signal (not shown) and a LOAD signal existing in most integrated circuit systems.

When the first LOAD signal comes in, all counters are enabled, and the outputs of all counters are set to "high" and begin counting the number of clocks CLK. At this time, as soon as the number of clocks reaches m, the counter stops operating and Cout_1 keeps the value "high" at that moment. Therefore, the output POLout_1 of the polarity control unit 360 maintains "high" which is in phase with the POL signal.

The second counter is enabled at the same time as the first counter and starts counting. The output Cout_2 of the second counter keeps the output toggled low when the number of clocks has reached m. As soon as the number of counted clocks reaches 2m, the counter stops operating and Cout_2 keeps the value "low" at that moment. Therefore, the output POLout_2 of the polarity control unit 360 of the second source driver 22 maintains the phase out of the POL signal.

In this way, all counters belonging to each source driver operate so that the internal polarity control signals (POLout_1, POLout_2, ...) of odd and even source drivers have opposite phases.

Therefore, according to the embodiment of the present invention using a counter, it is possible to supply polarity signals of different phases depending on the number of sources of the source driver.

As described above, the first source driver 21 and the second source driver 22 having the odd number of output terminals are controlled by the multiplexer path selection signals of different phases, so that all adjacent source lines of the liquid crystal display panel Appropriately opposite voltages will occur.

As described above, the source driver constituting the system of FIG. 12 has an odd number of output terminals. Conventionally, only a source driver having an even number of output terminals has been designed, but according to the core idea of the present invention, a source driver having an odd number of output terminals may be well applied to an inversion operation of a liquid crystal display panel.

Another embodiment of the present invention is to allow one source driver to realize both dot inversion and horizontal two dot inversion.

Hereinafter, the operation will be described with reference to the circuit diagram of FIG. 15.

First, the signal H2D is a signal for determining whether the source driver performs a simple dot inversion operation or a horizontal two dot inversion operation. The signal H2D should be set to "low" for dot inversion and "high" for horizontal two dot inversion.

When the signal H2D is "low", the transfer gate TG1 is "off", TG2 is "on" and the polarity signal POL is applied to all the multiplexers in the same phase. Therefore, since the multiplexer selects the solid line path when the POL signal is "high" and the dotted line path when the POL signal is "low", the output circuit block 350 of the source driver outputs a voltage by simple dot inversion.

When the signal H2D is "high", the transfer gate TG1 is "on", TG2 is "off" and the polarity signal POL is applied to the odd-numbered multiplexer and the even-numbered multiplexer in different phases. Therefore, when the POL signal is "high", the odd-numbered multiplexer selects the solid line path and the even-numbered multiplexer selects the dotted line path. In contrast, when the POL signal is "low", the odd-numbered multiplexer selects the dotted line path and the even-numbered multiplexer selects the solid line path. In this case, the output circuit block 350 of the source driver outputs a voltage by horizontal two dot inversion.

Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the source driver of the present invention described above, even if the source driver has an odd number of source output lines, the source lines of the liquid crystal display panel can be inverted from each other.

According to another effect of the present invention, the polarity control unit may be designed inside the source driver to control the polarity of the output terminal of the source driver, and the same effect may be provided when the polarity control unit is installed outside the source driver or the wiring of the liquid crystal display panel is changed. Can be obtained.

1A is a diagram illustrating line inversion of a liquid crystal display panel.

1B is a diagram illustrating dot inversion of the liquid crystal display panel.

Figure 1c is a diagram showing a horizontal two-dot inversion of the liquid crystal display panel.

2 is a block diagram showing a general liquid crystal display driving system.

3A is a simplified block diagram of a source driver.

3B is a partial timing diagram of the source driver.

4 is a timing diagram showing the polarity relationship between the LOAD and POL signals and the source driver output terminal.

5 is a block diagram illustrating a conventional method for driving a source line.

6A is a block diagram illustrating a problem of the conventional method.

6B is a block diagram illustrating another problem of the conventional method.

7 is a block diagram illustrating an embodiment of a source driver according to the present invention.

8 is a block diagram illustrating another embodiment of a source driver according to the present invention.

9 is a block diagram illustrating still another embodiment of a source driver according to the present invention.

10 is a block diagram illustrating a first embodiment in which a source driver according to the present invention drives a liquid crystal display panel.

11 is a block diagram illustrating a second embodiment in which a source driver according to the present invention drives a liquid crystal display panel.

12 is a block diagram illustrating a third embodiment in which a source driver according to the present invention drives a liquid crystal display panel.

13 is a block diagram illustrating a fourth embodiment in which a source driver according to the present invention drives a liquid crystal display panel.

14A is a block diagram illustrating still another embodiment of a source driver according to the present invention.

FIG. 14B shows a timing diagram in which the circuit of FIG. 14A operates.

FIG. 14C is a timing diagram for describing an operation of the counter of FIG. 14A.

Figure 15 shows another embodiment of the present invention that enables horizontal two-dot inversion.

Claims (26)

In the liquid crystal display panel drive circuit, Shift registers sequentially operating according to a periodic clock signal; Latches for latching a video signal; First digital-to-analog converters for outputting a first polarity voltage by controlling the output of the latches; Second digital-to-analog converters for outputting a second polarity voltage under the control of the output of the latches and disposed adjacent to the first digital-to-analog converter; A dummy digital-analog converter for outputting a first polarity voltage by controlling the output of the latches; Path selection circuits for selecting one of the output of the first digital-to-analog converters and the output of the second digital-to-analog converters; A polarity control unit controlling the selection of the path selection circuits; And An output circuit unit receiving the output of the path selection circuits to drive a liquid crystal display panel; And a liquid crystal display panel drive circuit. The liquid crystal display panel driving circuit as claimed in claim 1, wherein the number of output lines of the output circuit unit is an even number. The liquid crystal display panel driving circuit as claimed in claim 1, wherein the first polarity voltage and the second polarity voltage are opposite polarities. The liquid crystal display panel driving circuit as claimed in claim 1, wherein the output voltages of the output buffers alternately change the first polarity voltage and the second polarity voltage by a control operation of the polarity control unit. In the liquid crystal display panel drive system, Latches for latching a video signal; First digital-to-analog converters for outputting a first polarity voltage by controlling the output of the latches; Second digital-to-analog converters for outputting a second polarity voltage under the control of the output of the latches and disposed adjacent to the first digital-to-analog converter; A dummy digital-analog converter for outputting a second polarity voltage by controlling the output of the latches; Path selection circuits for selecting one of the output of the first digital-to-analog converters and the output of the second digital-to-analog converters; And Output buffers receiving the output of the path selection circuits to drive a liquid crystal display panel; A liquid crystal display driving integrated circuit comprising: And a polarity control unit for selectively controlling the polarity of the output voltage of the output buffer of the liquid crystal display driving integrated circuit. 6. The liquid crystal display panel drive system as claimed in claim 5, wherein the number of output lines of the output buffers is odd. 6. The liquid crystal display panel driving circuit as claimed in claim 5, wherein the first polarity voltage and the second polarity voltage are opposite polarities. The method of claim 5, wherein the polarity control unit has a function of controlling the path selection circuits such that the output voltages of the output buffers alternately change the first polarity voltage and the second polarity voltage. LCD display panel drive system. The liquid crystal display device according to claim 8, wherein the polarity control unit has a function of controlling the alternating change to occur at a predetermined timing interval of a periodic polarity signal applied to the source driver and at an adjacent predetermined timing. Display panel drive system. In the liquid crystal display panel drive system, Latches for latching a video signal; First digital-to-analog converters for outputting a first polarity voltage by controlling the output of the latches; Second digital-to-analog converters for outputting a second polarity voltage under the control of the output of the latches and disposed adjacent to the first digital-to-analog converter; A first dummy digital-analog converter for outputting a first polarity voltage by controlling the output of the latches; A second dummy digital-analog converter for outputting a second polarity voltage by controlling the output of the latches; Conveying the output of the first digital-to-analog converters, the output of the second digital-to-analog converters, the output of the first dummy digital-to-analog converter, and the output of the second dummy digital-to-analog converter Receiving output buffers; Path selection circuits for selecting one of an output of an odd-numbered output buffer and an output of an even-numbered output buffer among the output buffers; A liquid crystal display driving integrated circuit comprising: And a polarity control unit for controlling the selection operation of the path selection circuit of the liquid crystal display driving integrated circuit. The path selection circuit of claim 10, wherein the path selection circuit for selecting an output of the output buffers receiving the outputs of the first dummy digital-analog converter and the second dummy digital-analog converter among the path selection circuits has one output terminal. A liquid crystal display panel drive system, characterized in that. The liquid crystal display panel system which drives a liquid crystal panel, Gate driving integrated circuits driving a gate of the liquid crystal panel pixel; Source driving integrated circuits driving a source of the liquid crystal panel pixel and having an odd number of output terminals; A controller configured to generate signals for controlling the source driver integrated circuits and the gate driver integrated circuits; A polarity control part for alternating voltage polarities of output signals of the source driving integrated circuits; The polarity control unit receives a polarity signal generated from the controller, and supplies an output polarity signal inverted to each other to a source driving integrated circuit in an odd number and a source driving integrated circuit in an even number among the source driving integrated circuits. A liquid crystal display panel drive system. 13. The liquid crystal display panel drive system as claimed in claim 12, wherein the number of output terminals of the source driving integrated circuit is odd. In a liquid crystal display panel system for driving a liquid crystal panel, Gate driving integrated circuits driving a gate of the liquid crystal panel pixel; Source driving integrated circuits driving a source of the liquid crystal panel pixel; And a controller configured to generate signals for controlling the source driver integrated circuits and the gate driver integrated circuits. In the polarity control unit included in the source driving integrated circuit, an alternating polarity inversion of the output voltage of the source driving integrated circuit is controlled by a combined logic operation of an input of an input terminal indicating an even hole and a polarity signal from the control unit. A liquid crystal display panel drive system. 15. The liquid crystal display panel driving system as claimed in claim 14, wherein an input state indicating an even number of the source driving integrated circuits is a binary logic different from an odd source driving integrated circuit and an even source integrated circuit. . 15. The liquid crystal display panel drive system as claimed in claim 14, wherein the state of the input indicating the hole of the source driver integrated circuit is determined by the electrical wiring of the liquid crystal display panel drive system. 15. The liquid crystal display panel drive system as claimed in claim 14, wherein the number of output terminals of the source driving integrated circuit is odd. 15. The liquid crystal display panel drive system as claimed in claim 14, wherein the logic states of the inputs indicating the holes of the source driving integrated circuits are different binary logics between adjacent source driving integrated circuits. In an integrated circuit for driving the source of the liquid crystal display panel, Shift registers sequentially operating according to a periodic clock signal; Latches for latching a video signal; Digital-to-analog converters for outputting an analog voltage by controlling the output of the latches; An output circuit unit receiving the analog output voltage of the digital-analog converter to drive a liquid crystal display panel; And a counter for counting and detecting the periodic clock when the sequential operation of the shift registers is completed. And the voltage polarity of the adjacent output terminals of the output circuit portion is alternately changed to the opposite polarity each time the detection operation is performed by the detecting operation of the counter. 20. The integrated circuit of claim 19, wherein the counter outputs a binary output of the counter every time the sequential operation is completed. 20. The method of claim 19, wherein the integrated circuits driving the sources of the panel are connected to a plurality of liquid crystal display panels adjacent to each other, and the binary outputs of the binary outputs of the counters of the plurality of integrated circuits connected to each other are inverted from each other. An integrated circuit for driving the source of the liquid crystal display panel characterized in that. In the liquid crystal display panel drive circuit, Shift registers sequentially operating according to a periodic clock signal; Latches for latching a video signal; First digital-to-analog converters for outputting a first polarity voltage by controlling the output of the latches; Second digital-to-analog converters for outputting a second polarity voltage under the control of the output of the latches and disposed adjacent to the first digital-to-analog converter;  An output circuit unit receiving the outputs of the first digital-to-analog converter and the second digital-to-analog converter to drive a liquid crystal display panel; And A polarity control unit for alternately changing the voltage polarity of the output terminal of the output circuit unit at predetermined intervals; And a liquid crystal display panel drive circuit. The method of claim 22, And the output circuit unit comprises a path selection unit and an output buffer in which the transfer path of the voltage polarity of the output terminal is changed at predetermined intervals. The method of claim 22, The output circuit unit includes a path selection unit receiving the output of the first digital-to-analog converters and the second digital-analog converters, and an output buffer receiving the output transmitted from the path selection unit. Display panel drive circuit. A liquid crystal display panel drive circuit comprising a selector and an output buffer. The method of claim 23, wherein The output buffer is a liquid crystal display panel drive circuit, characterized in that the output is received from the path selector. A liquid crystal display panel drive circuit comprising a selector and an output buffer. The method of claim 22, The polarity control unit is a liquid crystal display panel driving circuit, characterized in that for controlling the dot inversion and horizontal two dot inversion.