KR101358222B1 - Liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, in a structure in which a pixel is driven with two pixel electrodes, that is, a first pixel electrode and a second pixel electrode for each pixel, the data transmission frequency is low and the source sampling of the data driver is performed. The present invention relates to a liquid crystal display device in which the screen quality is increased by lowering the frequency SSC, minimizing electromagnetic interference (EMI), and ensuring sufficient latch timing margin.

The present invention includes a first substrate in which a plurality of horizontal pixel columns and a vertical pixel column including a plurality of pixels are defined; First to n-th data lines formed at each boundary of the vertical pixel column and formed on the left side of the first vertical pixel column and the right side of the last vertical pixel column; First to m-th gate lines which are formed to cross the data lines, and are formed in two lines in each of the horizontal pixel columns and sequentially driven; Two thin film transistors each formed in the pixel to be connected to the same gate line, and connected to opposite gate lines between odd and even pixels based on a horizontal pixel column; First and second pixel electrodes connected to each of the two thin film transistors provided in the pixels; A switching signal generator configured to generate a switching signal according to a driving time of each of the odd-numbered pixels and the even-numbered pixels based on the horizontal pixel column; Each pixel data input from the outside is converted into two first pixel signals and two second pixel signals which are the same signals, and the odd-numbered pixels are based on a horizontal pixel column using a switching signal supplied from the switching signal generator. Switching paths of the first pixel signal and the second pixel signal according to the driving time of any one of the and even-numbered pixels, when driving the odd-numbered pixels, starting from the first data line [n-1] A switching unit for switching the transmission path toward the data line and switching the transmission path from the second data line to the n-th data line when driving even pixels; The first and second pixel electrodes after converting the first pixel signal and the second pixel signal received from the switching unit into first and second pixel voltages having the same magnitude but inverted phases with respect to the reference voltage. A data driver for supplying to the pixel to drive each pixel; Lt; / RTI >

LCD, Data Driver, Frequency

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, in a structure in which a pixel is driven with two pixel electrodes, that is, a first pixel electrode and a second pixel electrode for each pixel, a source sampling input to a shift register of a data driver is performed. The present invention relates to a liquid crystal display device having a lower frequency of the clock (SSC).

Generally, the liquid crystal display device has a tendency of widening its application range due to features such as light weight, thinness, and low power consumption driving. Accordingly, liquid crystal display devices are widely used as portable computers such as notebook PCs, office automation devices, and audio / video devices.

In general, a liquid crystal display device displays a desired image on a screen by controlling a light transmission amount according to an image signal applied to a plurality of switching elements for control arranged in a matrix form.

Such a liquid crystal display includes a liquid crystal panel in which a color filter substrate as an upper substrate and a thin film transistor array substrate as a lower substrate are opposed to each other, and a liquid crystal layer is filled therebetween, and a scan is performed on the liquid crystal panel. And a driver for supplying signals and image information to operate the liquid crystal panel.

A conventional liquid crystal display having such a configuration will be described with reference to FIG. 1 as follows.

Referring to FIG. 1, the liquid crystal panel includes a first substrate 1 as a thin film transistor array substrate and a second substrate (not shown) as a color filter substrate, and between the first substrate 1 and the second substrate. A liquid crystal layer (not shown) is formed.

Gate lines G1 to Gm and data lines D1 to Dn cross each other on the first substrate 1 to define a plurality of pixels, and the gate lines G1 to Gm and the data lines of each pixel are defined. The thin film transistor 2 is provided at the point where G1 to Gn intersect.

Each pixel includes a pixel electrode 3 connected to the drain terminal of the thin film transistor 2, and a common electrode 30 connected to the common voltage line 40 to be alternated with each other.

The driving unit for operating the liquid crystal panel includes a gate driver 10 for driving the gate lines G1 to Gm, and a data driver 6 for driving the data lines D1 to Dn. The driving unit includes a timing controller 7 for supplying a control signal or pixel data to the gate lines G1 to Gm and the data lines D1 to Dn, and a timing with the gate driver 10 and the data driver 6. Each of the control units 7 includes a power supply unit 8 for supplying power required.

In the liquid crystal display having the above configuration, a structure in which two pixel electrodes are provided and driven without the common voltage line 40 and the common electrode 30 has been proposed. In this regard, FIGS. 2 and 3 are described. Referring to the following.

Referring to FIG. 2, the first substrate 11 constituting the liquid crystal panel has a plurality of horizontal pixel columns and vertical pixel columns defined by a plurality of pixels, but data lines D1 to Dn are formed at each boundary of the vertical pixel columns. And a left side of the first vertical pixel column and a right side of the last vertical pixel column, and two gate lines G1 to Gm are formed for each horizontal pixel column.

Two thin film transistors 12a and 12b are provided at the intersection of the gate lines G1 to Gm and the data lines D1 to Dn of each pixel, and the thin film transistors 12a and 12b formed in each pixel are the same. It is formed to be connected to the gate lines G1 to Gm, respectively, and is connected to other data lines D1 to Dn, and the gate lines G1 to Gm opposite to each other are formed between the odd and even pixels based on the horizontal pixel column. Connected with

Each pixel includes a first pixel electrode 13a and a second pixel electrode 13b connected to the thin film transistors 12a and 12b.

The driving unit for operating the liquid crystal panel includes a gate driver 20 for driving gate lines G1 to Gm, and a data driver 16 for driving data lines D1 to Dn. In addition, the driver includes a timing controller 17 for supplying a control signal or pixel data to the gate lines G1 to Gm and the data lines D1 to Dn, and a timing with the gate driver 20 and the data driver 16. Each of the control units 17 is provided with a power supply unit 19 for supplying power.

Referring to FIG. 3, the data driver 16 of the liquid crystal display of FIG. 2 may sequentially output a sampling signal in response to a source shift clock (SSC) from the timing controller 17. An analog pixel for the digital pixel data from the latch unit 16b; and a latch unit 16b for sequentially latching and simultaneously outputting pixel data from the timing controller 17 in response to the sampling signal. And a digital-to-analog converter 16c for converting the voltage, and a buffer unit 16d for buffering the pixel voltage from the digital-analog converter 16c and outputting the buffered voltage to the data lines D1 to Dn.

In the LCD having the above structure, as the gate lines G1 to Gm are sequentially driven one by one, the odd-numbered pixels of the first horizontal pixel column are driven first and then the even-numbered pixels are driven. The odd-numbered pixels of the horizontal pixel column are driven first, and then the even-numbered pixels are driven. In this manner, the even-numbered pixels of the last horizontal pixel column are driven to display one frame of the screen.

Recently, the number of pixels formed in the liquid crystal panel has increased according to the trend of increasing the size of the liquid crystal display, and the number of pixels formed per unit area of the liquid crystal panel has also increased according to the high resolution trend of the liquid crystal display. Increasingly, the problem of increasing electromagnetic interference (EMI) in transmission lines is increasing.

When the transmission frequency of the pixel data increases as described above, the frequency of the source shift clock SSC supplied from the timing controller 17 to the shift register unit 16a of the data driver 16 also increases. Accordingly, the latch cycle of the latch unit 16b is shortened, thereby reducing the timing margin for latching the correct pixel data. As described above, when the latch timing margin is reduced, the latch timing of the pixel data is shifted, and the pixel voltage supplied to the data lines D1 to Dn is distorted by latching wrong pixel data.

Accordingly, an object of the present invention is to solve the problems of the prior art as described above. The present invention provides a liquid crystal display device having a low frequency and a low frequency of the source sampling clock SSC, thereby increasing the screen quality of the liquid crystal display device.

According to an embodiment of the present invention, a liquid crystal display device includes: a first substrate in which a plurality of horizontal pixel columns and a vertical pixel column including a plurality of pixels are defined; First to n-th data lines formed at each boundary of the vertical pixel column and formed on the left side of the first vertical pixel column and the right side of the last vertical pixel column; First to m-th gate lines which are formed to cross the data lines, and are formed in two lines in each of the horizontal pixel columns and sequentially driven; Two thin film transistors each formed in the pixel to be connected to the same gate line, and connected to opposite gate lines between odd and even pixels based on a horizontal pixel column; First and second pixel electrodes connected to each of the two thin film transistors provided in the pixels; A switching signal generator configured to generate a switching signal according to a driving time of each of the odd-numbered pixels and the even-numbered pixels based on the horizontal pixel column; Each pixel data input from the outside is converted into two first pixel signals and two second pixel signals which are the same signals, and the odd-numbered pixels are based on a horizontal pixel column by using the switching signal supplied from the switching signal generator. Switching paths of the first pixel signal and the second pixel signal according to the driving time of any one of the and even-numbered pixels, when driving the odd-numbered pixels, the [n-1] data from the first data line A switching unit for switching the transmission path toward the line and switching the transmission path from the second data line to the n-th data line when driving even pixels; The first and second pixel electrodes after converting the first pixel signal and the second pixel signal received from the switching unit into first and second pixel voltages having the same magnitude but inverted phases with respect to the reference voltage. A data driver for supplying to the pixel to drive each pixel; .

In the liquid crystal display having the above configuration, the transmission frequency of the pixel data output from the timing controller and the first pixel signal and the second pixel signal in which the pixel data are converted into the same two signals is lowered.

Accordingly, electromagnetic interference (EMI) in the transmission line through which the pixel data, the first pixel signal, and the second pixel signal are transmitted may be minimized.

As described above, when the transmission frequency of the pixel data output from the timing controller and the first pixel signal and the second pixel signal in which the pixel data are converted into the same two signals is lowered, the timing register controls the shift register unit of the data driver. The frequency of the source shift clock (SSC) supplied to is also lowered.

As a result, the latch period of the latch portion in the data driver becomes longer, thereby increasing the timing margin for accurate latching of the first pixel signal and the second pixel signal. There is an effect that the pixel voltage and the second pixel voltage are supplied to the data line without distortion.

Therefore, the screen display quality of the liquid crystal display device is improved.

Hereinafter, a liquid crystal display according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

4 and 5, a liquid crystal display according to an exemplary embodiment of the present invention includes a first substrate 101 in which a horizontal pixel column and a vertical pixel column including a plurality of pixels are defined; First to n-th data lines D1 to Dn formed one by one boundary of the vertical pixel column and formed on the left side of the first vertical pixel column and the right side of the last vertical pixel column; First to m-th gate lines G1 to Gm which are formed to cross the data lines D1 to Dn, and are formed to have two lines in each of the horizontal pixel columns; Two thin film transistors are formed in each pixel to be connected to the same gate lines G1 to Gm, and are connected to opposite gate lines G1 to Gm between odd and even pixels based on a horizontal pixel column. 102a, 102b; First and second pixel electrodes 103a and 103b connected to each of the two thin film transistors 102a and 102b provided in each pixel; A switching signal generator 104 generating a switching signal SS according to a driving time of each of the odd-numbered pixels and the even-numbered pixels based on the horizontal pixel column; Each of the pixel data data_D input from the outside is converted into two first pixel signals data_S1 and second pixel signals data_S2 which are the same signals, and are supplied from the switching signal generator 104. Switching paths of the first pixel signal data_S1 and the second pixel signal data_S2 according to the driving time of any one of the odd-numbered pixels and the even-numbered pixels based on the horizontal pixel column using SS. However, when driving the odd pixels, the transmission path is switched from the first data line D1 to the [n-1] data line D [n-1] and when driving the even pixels. A switching unit 105 for switching the transmission path from the second data line D2 to the nth data line Dn; Each of the first pixel signal data_S1 and the second pixel signal data_S2 received from the switching unit 105 have the same magnitude with respect to a reference voltage but have inverted phases. a data driver 106 for converting the data_D2 into the first and second pixel electrodes 103a and 103b to drive each pixel; .

The components of the liquid crystal display device having such a configuration will be described in detail.

Referring to FIG. 4, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel including a first substrate 101 which is a thin film transistor array substrate and a second substrate which is a color filter substrate (not shown). A liquid crystal layer (not shown) is formed between the first substrate 101 and the second substrate.

As shown in FIG. 4, the first substrate 101 includes a plurality of pixels, and the plurality of pixels form a plurality of horizontal pixel columns and a vertical pixel column.

The first substrate 101 is formed at each boundary of the vertical pixel column, and a plurality of data lines D1 to Dn are formed on the left side of the first vertical pixel column and the right side of the last vertical pixel column. ˜Dn) is defined as first to nth data lines. As a result, [n-1] pixels constitute each horizontal pixel column.

In addition, gate lines G1 to Gm formed on the first substrate 101 so as to cross the data lines D1 to Dn, and two lines are formed in each of the horizontal pixel columns, and the plurality of gate lines G1 to Gm are defined as first to mth gate lines.

Each of the gate lines G1 to Gm corresponds to one of odd-numbered pixels and even-numbered pixels based on the corresponding horizontal pixel column. That is, each of the gate lines G1 to Gm corresponds to [n-1] / 2 pixels on the basis of the corresponding horizontal pixel column.

Referring to FIG. 4, two thin film transistors 102a and 102b connected to the same gate line G1 to Gm are formed in each pixel on the first substrate 101. That is, the two thin film transistors 102a and 102b formed in each pixel are connected to the same gate line G1 to Gm among the gate lines G1 to Gm formed above or below the corresponding horizontal pixel column. The odd-numbered and even-numbered pixels are connected to different gate lines G1 to Gm based on the column.

Referring to FIG. 4, a first pixel electrode 103a and a second pixel electrode 103b connected to each of the two thin film transistors 102a and 102b provided in each pixel are formed on the first substrate 101.

In describing the liquid crystal display according to the preferred embodiment of the present invention, the pixel electrode connected to the thin film transistor 102a formed on the left side in each pixel is defined as the first pixel electrode 103a and formed on the right side of the thin film transistor 102b. ) Is defined as a second pixel electrode 103b.

The first pixel electrode 103a and the second pixel electrode 103b are connected to one of the data lines D1 to Dn disposed on the left and right sides of the corresponding pixel, and are connected to different data lines D1 to Dn. The first pixel voltage data_V1 is supplied to the first pixel electrode 103a through the data lines D1 to Dn, and the second pixel voltage dats_V2 is supplied to the second pixel electrode 103b through the data lines D1 to Dn. ) Is supplied to drive the liquid crystal layer.

In the liquid crystal panel having such a configuration, each gate line G1 to Gm may have [n-1] / 2 pixels, that is, the corresponding horizontal pixel column to which the gate line G1 to Gm corresponds, based on the corresponding horizontal pixel column. Since the pixel corresponds to one of odd-numbered pixels and even-numbered pixels, the [n-1] pixels constituting each horizontal pixel column have two gate lines G1 to Gm formed above and below the corresponding horizontal pixel column. Only the odd-numbered pixels and the even-numbered pixels must be driven to be driven.

Here, the n-th data line Dn is not driven when driving odd pixels based on the horizontal pixel column, and the first data line D1 is not driven when driving even pixels.

Detailed descriptions related to such driving will be given in the following description of the data driver 106.

Referring to FIG. 4, a liquid crystal display according to an exemplary embodiment of the present invention includes a timing controller 107, a power supply 108, a data driver 106, and a gate driver 110 to drive a liquid crystal panel, that is, each pixel. Various drive means such as are provided.

Such driving means will be described in turn as follows.

Referring to FIG. 4, the timing controller 107 generates a control signal for driving the liquid crystal panel using signals input from the outside, rearranges and outputs the pixel data data_D input from the outside. The timing controller 107 includes a control signal generator (not shown), a pixel data reordering unit (not shown), and a switching signal generator 104.

The control signal generator generates a gate start pulse (GSP), a gate shift clock (GSC), and a gate to control the gate driver by using a main clock signal and horizontal and vertical synchronization signals input from the outside. Generates gate control signals such as gate output enable (GOE), etc., and controls the source driver so that the source start pulse (SSP), source shift clock (SSC), and source output enable A data control signal such as a signal (Sourse Output Enable (SOE)), a data polarity selection (Data Reverse; REV), and a polarity control signal (Polarity; POL) is generated.

The data rearranging unit rearranges and outputs red, green, and blue pixel data (data_D) supplied from the outside.

In the liquid crystal display according to the preferred embodiment of the present invention, the data rearranging unit simultaneously outputs six pixel data data_D through each transmission line, and each of the six pixel data data_D output from the data rearranging unit The same signal is converted into two first pixel signals date_S1 and second pixel signals data_S2 and supplied to the data driver 106 through a total of 12 transmission paths.

In the description of the liquid crystal display according to the preferred embodiment of the present invention, the transmission line for outputting the pixel data (data_D) from the data rearranging unit of the timing controller 107 is six, but the present invention is not limited thereto. The number may be variously changed without departing from the scope of the present invention.

The switching signal generator 104 may be disposed inside the timing controller 107 or may be disposed outside the timing controller 107. However, the switching signal generator 104 may be disposed inside the timing controller 107. I will take that as an example.

The switching signal generator 104 generates a switching signal SS corresponding to the driving time of each of the odd-numbered pixels and the even-numbered pixels based on the horizontal pixel column, and transmits the switching signal SS to the switching unit 105.

That is, the switching signal SS output from the switching signal generator 104 is generated to be synchronized with the time of driving the odd-numbered pixel and the time of driving the even-numbered pixel, respectively, based on the horizontal pixel column. The switching signal SS generated at the time of driving the first pixel and the switching signal SS generated at the time of driving the even pixel are distinguished from each other as shown in FIG. 8.

Referring to FIG. 5, the switching unit 105 includes a first pixel signal data_S1 and a second pixel signal data_S2 in which pixel data data_D is output from the timing controller 107 and converted into two identical signals. The switching signal SS is input from the switching signal generator 104.

The switching unit 105 determines the first pixel according to which of the odd-numbered pixels and the even-numbered pixels are driven by the switching signal SS supplied from the switching signal generator 104. The progress paths of the signal data_S1 and the second pixel signal data_S2 are switched.

Referring to FIG. 5, the switching unit 105 switches the advancing paths of the first pixel signal data_S1 and the second pixel signal data_S2 according to the switching signal SS. Drive the switching paths from the first data line D1 to the [n-1] data line D [n-1] and the second data line D2 when driving even-numbered pixels. Switch the transmission path toward the nth data line Dn. That is, the switching unit 105 switches as shown in FIG. 7A when driving odd pixels, and as shown in FIG. 7B when driving even pixels.

The switching unit 105 may be disposed inside the data driver 106 or outside the data driver 106. However, in the description of the liquid crystal display device according to the preferred embodiment of the present invention, the former is used. For example. Therefore, the detailed description regarding the switching unit 105 will be described below with the detailed description of the data driver 106.

4 and 5, the liquid crystal display according to the exemplary embodiment of the present invention includes a power supply unit 108 including a gamma power supply unit 109.

The power supply unit 108 generates various voltages required for driving each component of the liquid crystal display, that is, the timing controller 107, the data driver 106, and the gate driver 110, and supplies them to the corresponding components.

Referring to FIG. 4, the gate driver 110 shifts the gate start pulse GSP supplied from the timing controller 107 according to the gate shift clock GSC to sequentially gate high to the gate lines G1 to Gm. The voltage VGH is supplied to drive the corresponding gate lines G1 to Gm, and the gate low voltage VGL is supplied in a period when the gate high voltage VGH is not supplied to the gate lines G1 to Gm.

The data driver 106 converts the pixel data data_D output from the timing controller 107 into two identical signals and references each of the input first and second pixel signals data_S1 and data_S2. Each pixel is driven by converting the first and second pixel voltages data_V1 and data_V2 having the same magnitude with respect to the voltage but having inverted phases, and supplying them to the first and second pixel electrodes 103a and 103b. .

The data driver 106 having such a configuration includes a plurality of data drive integrated circuits (ICs) for dividing and driving the plurality of data lines D1 to Dn into a plurality of groups.

Hereinafter, the data driver 106 including a plurality of data drive integrated circuits will be described in detail with reference to FIGS. 5 and 6.

For reference, FIG. 5 is a block diagram illustrating the first data drive integrated circuit 106a among the first through i-th data drive integrated circuits constituting the data driver 106 of FIG. 4, and FIG. 6 is shown in FIG. 4. Fig. 1 is a block diagram showing the second to [i-1] th data drive integrated circuits 106b among the first to ith data drive integrated circuits constituting the data driver included in the present invention.

In describing the first to i th data drive integrated circuits constituting the data driver 106, first the first data drive integrated circuit 106a will be described in detail, and then the second to [i-1] data drivers. 106b and the i th data driver (not shown) will be further described.

Referring to FIG. 5, the first data drive integrated circuit 106a includes a shift register section 16ba that sequentially outputs sampling signals in response to a control signal from the timing controller 107, and the timing controller ( A latch unit 106ab for sequentially latching and simultaneously outputting the first pixel signal data_S1 and the second pixel signal data_S2 from the switching unit 105 in response to the control signal from the control unit 107 and the sampling signal SS. And the first pixel voltage data_S1 and the second pixel signal data_S2 from the latch unit 106ab are analog signals having the same magnitude but a phase inverted from each other with respect to a reference voltage. The digital-to-analog converter 106ac converting the second pixel voltage data_V2 to output the first pixel voltage data_V1 and the second pixel voltage data_V2 from the digital-analog converter 106ac. Buffer section 106ad for buffering and outputting It is configured to include.

In addition, the first data drive integrated circuit 106a is configured to output various control signals from the timing controller 107 and pixel data data_D to corresponding components in the first data drive integrated circuit 106a. The control unit 106ae is further provided. However, in the description of the present invention will not be mentioned anymore for convenience of description.

The shift register unit 106aa sequentially shifts the source start pulses SSP_odd and SSP_even from the timing controller 107 according to the source sampling clock signal SSC to supply the latch unit 106ab. Sampling signal. Here, the source start pulses SSP_odd and SSP_even, that is, the odd source start pulse SSP_odd and the even source start pulse SSP_even are signals transmitted from the timing controller 107 to the shift register unit 106aa through the same transmission line. However, since the signal is used as an odd source start pulse (SSP_odd) or an even start pulse (SSP_even) according to the operating state of the switching unit 105, the odd start pulse (SSP_odd) and the even start pulse (SSP_even) for convenience of description. Will be defined as an individual name as described above.

The shift register section 106aa will be described in more detail. When the shift register section 106aa drives an odd-numbered pixel with respect to a horizontal pixel column, the corresponding odd source starts as shown in FIG. 8. The pulse SSP_odd is input, shifted in sequence according to the source sampling clock signal SSC, and output as a sampling signal to the latch unit 106ab. In the case of driving even-numbered pixels based on a horizontal pixel column, FIG. As shown in the figure, the corresponding even source start pulse SSP_even is received and output to the latch unit 106ab once at the same time as the previous time, and the even source is then generated according to the source sampling clock signal SSC. The start pulse SSP_even is sequentially shifted and output to the latch portion 106ab as a sampling signal.

For reference, in FIG. 8, when a period in which two gate lines G1 to Gm are driven to drive one horizontal pixel column is referred to as a horizontal period 1H, an odd source start pulse SSP_odd and an even source start pulse are shown. A waveform diagram of the signal SSP_even 'and the switching signal SS in which SSP_even and the even source start pulse SSP_even are shifted once is shown.

Here, the last sampling signal of the shift register section 106aa of the first data drive integrated circuit 106a is supplied to the latch section 106ab and the source start pulse SSP_even is applied to the second data drive integrated circuit 106b of FIG. 6. , SSP_odd), which will be described in detail later with reference to the second to [i-1] th data drive integrated circuits 106b.

As illustrated in FIG. 5, the latch unit 106ab sequentially samples the first pixel signal data_S1 and the second pixel signal data_S2 by a predetermined unit in response to a sampling signal from the shift register unit 106aa. Latch Here, the first pixel signal data_S1 and the second pixel signal data_S2 are the same as the first pixel signal data_S1 and the pixel signal data_D output from the timing controller 107 as described above. The two pixel signal data_S2 is converted into two signals and input to the switching unit 105.

Subsequently, the latch unit 106ab simultaneously outputs the first pixel signal data_S1 and the second pixel signal data_S2 that are latched in response to the source output enable signal SOE output from the timing controller 107. The digital-to-analog converter 106ac is supplied.

The digital-to-analog converter 106ac converts the digital first pixel signal data_S1 and the second pixel signal data_S2 output from the latch unit 106ab by using the gamma reference voltage of the gamma voltage supply unit 109. The first pixel voltage data_V1 and the second pixel voltage data_V2 are converted to the buffer unit 106ad. Here, the first pixel voltage data_V1 and the second pixel voltage data_V2 are the same in magnitude with respect to the reference voltage but inverted only in phase.

Although not shown in the figure, the digital-to-analog converter 106ab includes a P (positive) decoding unit and a N (negative) decoding unit multiplexer (MUX) unit.

The [n / i] P decoders included in the P decoder (not shown) may use the first pixel signal data_S1 or the second pixel signal data_S2 input from the timing controller 107 to generate the positive gamma reference voltages. The first pixel voltage data_V1 or the second pixel voltage data_V2, which is a positive analog signal, is converted to the second pixel voltage. That is, if the first pixel signal data_S1 passes through the P decoder, it will be converted into the positive analog first pixel voltage data_V1, and if the second pixel signal data_S2 passes through the P decoder, the analog analog second pixel voltage will be converted to (data_V2).

In addition, the [n / i] N decoders included in the N decoding unit (not shown) may have a negative gamma reference based on the first pixel signal data_S1 or the second pixel signal data_S2 input from the timing controller 107. The voltages are converted into the first pixel voltage data_V1 or the second pixel voltage data_V2 which are the negative analog pixel signals. That is, when the first pixel signal data_S1 passes through the N decoder, it will be converted to the negative analog first pixel voltage data_V1. When the second pixel signal data_S2 passes through the P decoder, the negative analog second It will be converted to the pixel voltage data_V2.

The [n / i] multiplexers included in the multiplexer unit (not shown) may receive the first pixel voltage data_V1 from the P decoder and the N decoder in response to the polarity control signal POL from the timing controller 107. Any one of the first pixel voltages data_V1 is selected and output, and either one of the second pixel voltage data_V2 from the P decoder and the second pixel voltage data_V2 from the N decoder is selected and the buffer unit 106ad. One of the first pixel voltage data_V1 and the second pixel voltage data_V2 selects and outputs a positive analog signal, and the other selects and outputs a negative analog signal.

That is, when the first pixel voltage data_V1 output from the multiplexer is a positive analog signal, the second pixel voltage data_V2 is a negative analog signal, and when the first pixel voltage data_V1 is a negative analog signal, The pixel voltage data_V2 may be a positive analog signal.

Accordingly, the first pixel voltage data_V1 and the second pixel voltage data_V2 output from the multiplexer unit are buffered through the buffer unit 106ad and output to the data lines D1 to Dn, respectively. The first pixel voltage 106a and the second pixel electrode 103b connected to the formed data lines D1 to Dn have the same magnitude with respect to the reference voltage but have opposite phases, and thus have the first pixel voltage data_V1 and the second pixel voltage. (data_V2) is applied to each.

A second disposed at a rear end of the first data drive integrated circuit 106a having the configuration and operation as described above, and for managing a portion of the data line after the last data line managed by the first data drive integrated circuit 106a; The [i-1] th data drive integrated circuit 106b will be described with reference to FIGS. 4 and 6 as follows.

The second to [i-1] data drive integrated circuits 106b include a shift register section 106ba which sequentially outputs sampling signals in response to a control signal from the timing controller 107, and the timing. A latch unit 106bb that sequentially latches and simultaneously outputs the first pixel signal data_S1 and the second pixel signal data_S2 from the switching unit 115 in response to the control signal from the control unit 107 and the sampling signal. And the first pixel voltage data_D1 and the first pixel signal data_S1 and the second pixel signal data_S2 from the latch unit 106bb are analog signals having the same magnitude with respect to a reference voltage but are inverted in phase with each other. The digital-analog converter 106bc converts and outputs the two pixel voltages data_D2, and buffers the first pixel voltage data_V1 and the second pixel voltage data_V2 from the digital-analog converter 106bc. Output buffer section 106ad .

The shift register unit 106ba of the second to [i-1] data drive integrated circuits 106b receives the source start signals SSP_odd and SSP_even transmitted from the data drive integrated circuits of the previous stages. Are sequentially shifted accordingly to be supplied to the latch portion 106bb.

In the case of driving the even-numbered pixel based on the horizontal pixel column, as shown in FIG. 8, the even-numbered source start signal SSP_even is received from the data drive integrated circuit of the previous stage and is supplied to the data drive integrated circuit of the previous stage. At the same time as the data line, the output is first output to the latch unit 106bb, and then the even source start signal SSP_even is shifted according to the sampling clock signal SSC from the next time point and output to the latch unit 106bb. In the case of driving even-numbered pixels based on the horizontal pixel column, the pixels positioned at the boundary of each data drive integrated circuit are placed on the right side of the last data line and the pixel managed by the data driver integrated circuit positioned on the left side of the pixel. This is because the first pixel voltage data_V1 and the second pixel voltage data_V2 are driven through the first data line managed by the data driver integrated circuit.

The latch unit 106bb of the second to [i-1] data drive integrated circuits 106b is configured to respond to the sampling signal from the shift register unit 106ba in response to the first pixel signal data_S1 and the second pixel signal ( data_S2) is sequentially sampled by a predetermined unit and latched. As described above, the first pixel signal data_S1 and the second pixel signal data_S2 are the same as the first pixel signal data_S1 and the pixel signal data_D output from the timing controller 107. The two pixel signal data_S2 is converted into two signals and then input to the switching unit 115.

Here, in the latch unit 106bb, driving of the first data line managed by the latch unit 106bb is the same as in the case of the data drive integrated circuit in the previous stage when driving the odd pixel based on the horizontal pixel column. When driving the even pixels based on the pixel column, the last signal managed by the previous data drive integrated circuit managed by the previous node is supplied with the same signal as the last second pixel signal data_S2 supplied to the previous data drive integrated circuit. It is made at the same time as driving for the data line.

Subsequently, the latch unit 106bb simultaneously outputs the first pixel signal data_S1 and the second pixel signal data_S2 that are latched in response to the source output enable signal SOE output from the timing controller 107. The digital-to-analog converter 106bc is supplied.

The digital-to-analog converter 106bc uses the gamma reference voltages of the gamma voltage supply unit 109 to convert the digital first pixel signal data_S1 and the second pixel signal data_S2 output from the latch unit 106bb. The analog first pixel voltage data_V1 and the second pixel voltage data_V2 are converted into the buffer unit 106bd. Here, the first pixel voltage data_V1 and the second pixel voltage data_V2 are the same in magnitude with respect to the reference voltage but inverted only in phase.

The buffer unit 106bd buffers the first pixel voltage data_V1 and the second pixel voltage data_V2 output from the digital-analog converter 106bc and outputs the buffered data to the data lines D1 to Dn.

The i-th data drive integrated circuit (not shown) disposed at the rear of the [i-1] data drive integrated circuit 106b having the configuration and operation as described above is the [i-1] data drive integrated circuit 106b. It has a similar configuration and operation to), but since there are no more data drive integrated circuits at the rear, both data lines connected to the last vertical pixel column managed by itself when driving the even pixel based on the horizontal pixel column The difference is that the data drive integrated circuit itself drives.

Since other configurations and operations are the same as those of the second to [i-1] th data drive integrated circuits 106b, detailed descriptions thereof will be omitted.

In the liquid crystal display according to the exemplary embodiment of the present invention having the above-described configuration and operation, the first pixel signal data_S1 and the second pixel in which the pixel data data_D output from the timing controller 107 are the same two signals are the same. The shift registers 106aa and 106ba output the sampling signals using the low frequency source shift clock SSC because the signal is converted to the pixel signal data_S2 and supplied to the latch units 106ab and 106bb. 106bb latches the first pixel signal data_S1 and the second pixel signal data_S2 in a predetermined unit at a low frequency.

Accordingly, the transmission frequencies of the pixel data data_D, the first pixel signal data_S1, and the second pixel signal data_S2 are lowered, thereby minimizing electromagnetic interference EMI of the transmission line.

In addition, since the latch periods of the latch units 106ab and 106bb are extended, the timing margin for accurate latching of the first pixel signal data_S1 and the second pixel signal data_S2 increases, so that the first pixel signal data_S1 Since the latch timing of the second pixel signal data_S2 is correct, the first pixel voltage data_V1 and the second pixel voltage data_V2 are supplied to the data lines D1 to Dn without distortion.

1 is a block diagram showing an example of a conventional general liquid crystal display device.

2 is a block diagram showing another example of a conventional general liquid crystal display device.

3 is a block diagram illustrating a data driver of the liquid crystal display of FIG. 2.

4 is a block diagram showing a liquid crystal display according to a preferred embodiment of the present invention.

FIG. 5 is a block diagram illustrating a first data drive integrated circuit among first to nth data drive integrated circuits configuring the data driver of FIG. 4. FIG.

FIG. 6 is a block diagram illustrating second through [n-1] data drive integrated circuits among the first through nth data drive integrated circuits configuring the data driver of FIG. 4; FIG.

7A is a block diagram illustrating a switching state of a switching unit when driving an odd pixel based on a horizontal pixel column in the liquid crystal display of FIGS. 4 to 6.

7B is a block diagram illustrating a switching state of a switching unit when driving an even pixel based on a horizontal pixel column in the liquid crystal display of FIGS. 4 to 6.

FIG. 8 illustrates a signal SSP_even 'in which the odd source start pulse SSP_odd and the even source start pulse SSP_even and the even source start pulse SSP_even are shifted once in the liquid crystal display of FIGS. Waveform diagram showing a switching signal SS.

DESCRIPTION OF REFERENCE NUMERALS

1st to mth gate line: G1 to Gm

1st to nth data lines: D1 to Dn

Thin Film Transistors: 102a, 102b

103a: first pixel electrode 103b: second pixel electrode

104: switching signal generator 107: timing controller

106: data driver 110: gate driver

106a: first data drive integrated circuit

106b: second to [i-1] data drive integrated circuits

105, 115: switching unit

106aa, 106ba: Shift register section 106ab, 106bb: Latch section

106ac, 106bc: digital-to-analog converter 106ad, 106bd: buffer

Claims (3)

A first substrate having a plurality of horizontal pixel columns and a vertical pixel column formed of a plurality of pixels; First to n-th data lines formed at each boundary of the vertical pixel column and formed on the left side of the first vertical pixel column and the right side of the last vertical pixel column; First to m-th gate lines which are formed to cross the data lines, and are formed in two lines in each of the horizontal pixel columns and sequentially driven; Two thin film transistors each formed in the pixel to be connected to the same gate line, and connected to opposite gate lines between odd and even pixels based on a horizontal pixel column; First and second pixel electrodes connected to each of the two thin film transistors provided in the pixels; A switching signal generator configured to generate a switching signal SS according to a driving time of each of the odd-numbered pixels and the even-numbered pixels based on the horizontal pixel column; Each pixel data input from the outside is converted into two first pixel signals and two second pixel signals which are the same signals, and the odd-numbered pixels are based on a horizontal pixel column using a switching signal supplied from the switching signal generator. Switch the traveling paths of the first and second pixel signals according to the driving time of any one of the and even-numbered pixels, and when driving the odd-numbered pixels, the [n-1] data from the first data line. A switching unit for switching the transmission path toward the line and switching the transmission path from the second data line to the n-th data line when driving even pixels; The first and second pixel electrodes after converting the first pixel signal and the second pixel signal received from the switching unit into first and second pixel voltages having the same magnitude but inverted phases with respect to the reference voltage. A data driver for supplying to the pixel to drive each pixel;  And the liquid crystal display device. The method of claim 1, The data driver consists of at least one data drive integrated circuit and is defined as the i th data drive integrated circuit from the first data drive integrated circuit, In the case of driving the even pixels based on the horizontal pixel column, the second to i-th data drive integrated circuits are supplied with the same signal as the last second pixel signal supplied to the previous data drive integrated circuits, and thus, the first to be managed by the second to i-th data drive integrated circuits. And driving a data line, wherein the first data line managed by the data line is driven at the same time as the last data line managed by the data drive integrated circuit. The apparatus of claim 2, further comprising a timing controller configured to generate a control signal for driving each pixel using signals input from the outside and to rearrange and output pixel data from the outside. Each data drive integrated circuit constituting the data driver, A shift register section for sequentially outputting a sampling signal in response to a control signal from the timing controller; A latch unit sequentially latching and simultaneously outputting a first pixel signal and a second pixel signal from a switching unit in response to a control signal from the timing controller and the sampling signal; A digital-to-analog converter for converting the first pixel signal and the second pixel signal from the latch unit into first pixel voltages and second pixel voltages that are analog signals having the same magnitude but inverted phases with respect to a reference voltage; A buffer unit buffering and outputting a first pixel voltage and a second pixel voltage from the digital-analog converter; And the liquid crystal display device.

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