WO2010061184A1

WO2010061184A1 - Interleaving or de-interleaving for variable data block sizes and continuous data reception

Info

Publication number: WO2010061184A1
Application number: PCT/GB2009/002750
Authority: WO
Inventors: Christopher Ryan Nokes; Oliver Paul Haffenden
Original assignee: British Broadcasting Corporation
Priority date: 2008-11-25
Filing date: 2009-11-25
Publication date: 2010-06-03
Also published as: GB2465611A; GB0821570D0; GB2465611B; EP2377248A1

Abstract

An apparatus for interleaving or de-interleaving a stream of data has a memory with M serially-numbered logical memory locations. The read-address generator and write-address generator are each configured to address memory locations as a function of an increment value which itself is a function of an increment value used for a previous block of data multiplied by a dimension used for interleaving or de-interleaving the previous block. The dimension is the number of columns of data to be interleaved or de-interleaved where the number of columns is an integer factor of the number of memory locations. The use of such an increment value ensures that data elements can be read in turn from a de-interleaver for a previous block while elements from the present block are written to locations that have been used.

Description

INTERLEAVING OR DE-INTERLEAVING FOR VARIABLE DATA BLOCK SIZES AND CONTINUOUS DATA RECEPTION

BACKGROUND OF THE INVENTION

This invention relates to the interleaving and de-interleaving of a stream of data received in successive blocks

Digital communication systems such as the proposed DVB-T2 (Digital Video Broadcasting - Second Generation Terrestrial Broadcasting) system achieve good error performance in the presence of bursts of errors by a combination of forward error correction (FEC) coding followed by interleaving at the transmitter. Bursts of errors in the channel are distributed as evenly as possible by the de- interleaving process in the receiver, so that the error rate after de-interleaving should always be low enough to allow errors to be corrected by the receiver's FEC decoder.

One common type of interleaver is a block interleaver, where data is written in groups of bits defined as symbols (also referred to as cells or data elements) for example, into the columns of a block of memory, and read out in rows.

If it is desired to operate such an interleaver continuously, so that data may be read into and out of the interleaver at the same constant rates, then a conventional approach to the design would require two blocks of memory each capable of holding a block of data. Data is written into the first block of memory until a whole block has been loaded. Data is then ready to be output from the first block, and while this happens a second block of data can simultaneously be written into the second memory block. When a third block of data is received, the second block of memory is full, so output data is now taken from here, whilst the input data is switched back to the first block. In this way, interleaving can then operate continuously. This approach requires twice the minimum amount of memory. For the large interleavers used in DVB-T2, this doubling of memory could have a significant cost implication for the receiver, and this is disadvantageous. An alternative known design of interleaver, which would allow the same memory to be re-used, would make use of a 'square' block of memory, where the number of rows and columns is the same. Data is first written into the columns and then read out in rows. In this case, as each data symbol is read out of a row, it is replaced by a new input symbol, allowing for continuous operation. The square design means that the data for the second block, which was input row-wise, can be read out in columns to achieve the same interleaving effect.

A further known design of interleaver allows less than a full block of memory to be used for the specific example of data arranged in few columns, but large numbers of rows. For example, with a data block comprising 3 columns and 32 rows it can be shown that less than a full block of memory is needed if a cycle of operations is chosen so that data is only held in a store until needed and then replaced by other data. However, this only works for specific fixed block sizes and numbers of columns and rows.

Furthermore, in the context of DVB-T2, it is desired to have blocks of data where the amount of data varies from block to block. This is to allow each service to be coded and interleaved separately, whilst sharing out the total (constant) transmission capacity dynamically between the services. In this context a 'service' refers to the collection of data elements which a receiver needs to receive simultaneously, such as the video, audio and data related to a single television programme. It is usual for various services to be transmitted together, but to allow the instantaneous data rates to vary, whilst the total data rate of all services remains constant - this is known as statistical multiplexing.

Our co-pending UK patent application GB 0721853.0 describes an improved arrangement allowing a block of memory to be efficiently used by using a read/write sequence in which an address generator addresses memory locations which correspond to memory locations addressed in a previous block that are an integer number n of memory locations apart, with n > 1 , and each time the address generator reaches the end of the serially-numbered locations it restarts at the beginning of the serially-numbered locations subject to an increment. This approach allows a single block of memory to be used that is equal in size to the maximum data block size, but subject to certain limitations of data rate and data block size.

SUMMARY OF THE INVENTION We have appreciated that the interleaver (and more importantly the de- interleaver) for a system in which the data block size varies can be implemented using a memory block of significantly less than twice the maximum data block size whilst allowing for variability of data block size and continuous data reception.

The invention in its various aspects is defined in the independent claims below to which reference may now be made. Advantageous features are set forth in the dependent claims.

Preferred embodiments of the invention, described in more detail below with reference to the drawings, take the form of a block interleaver or de-interleaver for interleaving or de-interleaving blocks of data of variable size. A block of data is the amount of data within which interleaving is to be performed and comprises a plurality of data elements (sometimes referred to as symbols). The elements themselves may be bits, bytes, constellation points or any suitable unit of data.

The embodiments are particularly suited to DVB data which comprises data elements arranged in FEC blocks. In an example interleaver embodiment, one block of data comprises 68 FEC blocks of data elements arranged in a number Nr of rows and a number Nc of columns. The number of rows in the interleaver is chosen to be a fixed integer and the number of columns is a variable allowing a variable block size of data to be interleaved. At the interleaver data is written in columns and read in rows to perform interleaving. Of course, the concepts of row and column are interchanged merely by conceptually turning a memory through ninety degrees and consequently an arrangement that interchanges these terms falls within the scope of the invention as defined in the claims.

In a de-interleaver embodying the invention, a memory has M serially numbered memory locations in which the received data blocks are written and read according an addressing scheme in which for a given block of data the read- address generator and write-address generator are each configured to generate the addresses of memory locations as functions of at least an increment value which itself is a function of an increment value used for a previous block multiplied by a dimension used for de-interleaving the previous block.

The use of an increment value for generating addresses for a given block that is a function of the increment value used for the previous block multiplied by a dimension for the previous block, ensures that data elements can be read in turn from the de-interleaver for a previous block while elements from the present block are written to the locations that have been read. The dimension used in the addressing scheme is related to the number of columns of data interleaved at the interleaver. Where the number of columns is a factor of the memory size M of the de-interleaver, the dimension is the number of columns Nc used for interleaving data at the interleaver. Where the number of columns Nc used for interleaving is not a factor of the memory size M, the dimension is equal to the next factor Nc' of M that is greater than or equal to Nc. This allows the memory to simultaneously read a previous block whilst writing the present block, even though the block size is variable.

An embodiment may further include an additional buffer, such as a FIFO, into which data may be written prior to writing to the memory. The use of this buffer allows for the situation that the write address pointer advances faster than the read address pointer, as would happen in the addressing scheme for certain block sizes. Careful choice of the memory size M minimises the size of buffer needed. The row column memory may also be treated as a modified circular buffer, which enables a more efficient implementation of the previous feature.

The embodiment may also use memory locations, which would be otherwise unused for the current block, as the addresses for writing the first few elements of a given block as a further measure to minimise the situations in which the write address pointer advances ahead of the read address pointer. BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in more detail by way of example with reference to the drawings, in which: Figures 1(a), (b) and (c) show the conceptual rearrangement of data for interleaving and de-interleaving ;

Figures 2(a), (b) and (c) show the conceptual rearrangement of data for interleaving and de-interleaving for a second block of data;

Figures 3(a), (b) and (c) show the conceptual rearrangement of data for a third block of data;

Figure 4 shows the conceptual rearrangement of data for variable data;

Figure 5 shows a memory and use of spare cells for writing input data to use memory efficiently; and

Figure 6 (a) and (b) are block diagrams of an interleaver and de-interleaver.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A basic interleaver is shown in the block diagram of Figure 6(a). The interleaver 10 has an interleaver memory 12 which is addressed by an address generator 14. Input data symbols (which may also be called data elements or data items) are received at an input 16 and output data symbols appear at an output 18 forming an interleaved sequence.

During each block (except the first) data symbols are read out one at a time from the interleaver memory 12 according to the addressing sequence produced by the address generator 14. For each symbol read out, a new symbol from the input is written into the memory at the same address; this memory location has just been cleared by reading the output symbol.

As mentioned previously, the de-interleaver is almost identical to the interleaver. The basic de-interleaver is shown in the block diagram of Figure 6(b). The de-interleaver 20 has a de-interleaver memory 22 which is addressed by an address generator 24. Input data elements in interleaved format are received at an input 26 and output data elements appear at an output 28 forming a straight sequence.

During each block (except the first) data symbols are read out one at a time from the de-interleaver memory 22 according to the addressing sequence produced by the address generator 24. For each symbol read out, a new symbol from the input is written into the memory at the same address, as this memory location has just been cleared by reading the output symbol.

This is thus essentially identical to the interleaver of Figure 6(a), save that all references to rows and columns are interchanged. (Indeed, an equally valid interleaver could have been defined where data was written to the rows and then read out of the columns.)

Suppose the interleaver to be implemented is defined to have data input into Nc columns, with each column having Nr rows, as shown in the conceptual illustration of Figure 1. The total memory of the interleaver is therefore defined by:

M = Nr x Nc symbols or memory locations.

The actual block of memory to be used may be implemented as a sequential, linear or one-dimensional block of memory. In such a memory the terms "rows" and "columns" have no meaning, they simply define sub-blocks of data; they remain, however, convenient conceptual terms as will be seen. What matters is that they are simply examples of integers. It is necessary in such a memory to ensure that the address generator 14 provides the correct address sequence. The addresses of the elements of the memory will be calculated by index /, where:

O ≤ z ≤ M - 1

In the remaining examples, data can be considered as being written in columns and read in rows at the interleaver, and written in rows and read in columns at the de-interleaver. As stated above, the concept of row and column is completely interchangeable and is logical, rather than physical. The use of rows and columns aids understanding, but the actual addressing of memory is performed using address values. For simplicity, we will also take the number of rows of input data to be a fixed value and assume that the number of columns may vary.

In order to minimise the size of memory M, and allow the apparatus and method to operate with a variable number of columns of data, we have appreciated that it is desirable that the memory size M has as factors the possible column sizes of

^~ the input data which it is desired to use. Taking a simple example, as shown in

Figure 1 , suppose the interleaver comprises 6 rows and 4 columns. The variable data rate is achieved by filling any number of the columns, from 0 to 4, and interleaving is achieved by reading out in rows. The number of rows is fixed at 6.

Each of the allowed number of columns is preferably a factor of the total memory size of 24. (To be strictly accurate, it is necessary to exclude the special case of no data, or 0 columns).

To implement the de-interleaver in such a case, it is a convenient concept to consider that the memory has been "reshaped" to have the number of columns required for the data rate in question. In the above example, the memory can be considered as 24x1 , 12x2, 8x3 or 6x4.

Suppose the time de-interleaving memory is to be filled in the first block with 3 columns of data (3 x 6 = 18 cells), and then in the second block a smaller amount with 2 columns worth (2 x 6 = 12 cells), and finally by a third block with the full 4 columns (4 x 6 = 24 cells). Suppose also that the data before time interleaving was represented by a sequence of numbers starting from zero. In the transmitter's interleaver, the data will be written into memory in columns as shown in Figure 1 (a). The incomplete rows will be read out, and so the interleaved transmission sequence will be 0, 6, 12, 1 , 7, 13, 2, etc.

In order to de-interleave this data, the de-interleaver will conceptually reshape its memory to 8x3. However, in practice, since this is the first block, it will simply write the received data into memory (along rows) in sequential order of addressing. In effect the memory will then appear as shown in Figure 1 (b). Since the empty column from the interleaver was never transmitted, the empty cells of the de-interleaver will all appear at the end. The "reshaping" allows the data to be read along columns to re-establish the original non-interleaved order. The reading along columns in the de-interleaver is in reality achieved by generating appropriate read addresses. The de-interleaving addressing sequence may be explained by the following equation:

⁽D

Where: a is the address value i is the index of each address j is the number of the block k is an increment value used for a given block M is the memory size used in the de-interleaver

It will be shown later that this equation can be re-written in an equivalent form given below, although note that this obscures the simplicity of implementation evident from equation (1) above:

^a'^{J ~}

The increment value k₀ used for writing the first block of data will be 1. The increment value k-i to read this block will be 3, corresponding to the three columns of data transmitted (rather than the 4 columns with which the interleaver's memory was originally dimensioned). So we can see that, in this simple first case, by incrementing the read address by the value of the number of columns of data at the interleaver, we effectively read along columns (every third address being the next cell down the column).

However, on reaching the bottom of the first column (i.e. after the fixed number of rows, 6), the de-interleaver will need to skip to the start of the next column. This can easily be achieved, since the start of the next column can always be stored by calculating from the start of the current column, and adding the writing address increment (which in this case was simply 1). This gives a "jump" to the next address at address 0+ write increment (1) = 1.

So to achieve the full de-interleaving, the read addressing sequence will be addresses 0, 3, 6, 9, 12, 15, 1 , 4, 7, 10, 13, 16, 2, 5, 8, 11 , 14, 17. The jump from 15 to 1 is the jump to the start of the next column. This can be represented by an incremental equation for the read address:

rd_tJ = (rd^_j + k_J+l) if rd_t__{λ J} < M - k_J+l j for i > O₅ unless i mod Nr = O

(3) rd_tJ = K^ - (M - k_J+l - 1)) if rd^ ≥ M - k_J+l J rd = c when i mod Nr = 0

The value of c_q (where q=i/Nr), which represents the start of each column, can be calculated from a modified form of the general increment equation:

C_n = O

(4) c_q = (c_q__λ -(M-k_J -I)) when c,., > M-k_J ^r

As can be seen from Figure 1 (b) reading these addresses returns the de- interleaved data values.

These equations can again be expressed in a non-iterative form, by noting that, for the /th element of the sequence to be read, the position within the current column being read is given by / mod Nr, where Nr is the fixed number of rows, and the start of each column is given by (/ div Λ/r)^χ/W/Λ/c_y-?, where No^₁ is the number of columns of data in the interleaver corresponding to the writing of the previous (j-ftb) block. Hence, when taken together with equation (2), the non- iterative read address equation can be written as:

To re-enforce the fact that the concept of memory re-shaping is convenient for understanding, but not a physical phenomenon, the memory of Figure 1(b) is re- drawn as a linear memory in Figure 1 (c). As can be seen, the read increment value k=3 retrieves the de-interleaved data up until address 15 containing the data value 5 at which point the read pointer must jump to the start of the next column, here address 1 containing data value 6.

Now, while this first block of data is being de-interleaved, the second block will be being received. In the example, this had just 2 columns of data, so the transmitted sequence will be 0, 6, 1, 7, 2, 8, 3, 9, 4, 10, 5, 11 (namely the first two columns of data shown in Figure 1(a)). In order to allow the de-interleaver to work continuously, this must be written into the memory slots that have already been read from. Hence the write addressing sequence must follow the read- addressing sequence for the first block. In this case however, there is no need, and it is undesirable, to jump to the start of the next column. The write- addressing will simply fill all of the conceptual columns of the 8x3 memory, as shown in Figure 2.

Figure 2(a) shows that the memory shape can be considered to be that of the previously read memory shape. Figure 2(b) shows the conceptual re-shaping of the memory for reading.

In this case, the write addressing sequence will therefore be 0, 3, 6, 9, 12, 15, 18, 21 , 1 , 4, 7, 10. To calculate these addresses, the write-address-pointer will use equation (1) with an increment value k-i of 3 and M = 24, hence it will correctly jump from address 21 to 1. Note that this follows the read address sequence initially, but then uses previously unused addresses 18 and 21 and so the read pointer for the previous block will definitely be ahead of the write pointer for the present block, because the read pointer did not take time to visit these cells. This is a useful point to note as the write pointer cannot be allowed to attempt to write to an address that has not yet been read. The jump from address 21 to 1 is explained by the third line of equation (1).

To de-interleave this second block of data, the de-interleaver will need to calculate a new increment value k₂. This is achieved using an equation of the form of equation (6) below, but once again it will need to use the actual number of columns of data in the interleaver for the transmitted block of data:

*n k K_ji

where:

NC_j is the number of columns in a given block j

Note that successive values of k_j may be stored in a similar way to the method described uur co-pending UK patent application GB 0721853.0, although a side chain will now be required, which counts Nc₁.-, iterations of an address generator of the form of equation (1), with an increment of /c_y-r, and storing the resulting address as the value of k_s for the subsequent block.

So the value of k₂ will be (k-i . Nc₁) mod (M-1) which is 2x3=6. Once again, equations (3) and (4) or (5) will be used to generate the correct sequence, so that after reading the first 6 elements (corresponding to the fixed number of rows), the read-address-pointer will jump to the top of the next column. Hence the read- addressing sequence will be 0, 6, 12, 18, 1 , 7, 3, 9, 15, 21, 4, 10.

The jumps from address 18 to 1 and address 21 to 4 are caused by the normal operation of equation (1) (the address given for the address after 18 is given by the third line of equation (1) because the address 18 is within the increment k of the end of the memory, hence the next address is 18 - (24 - 6 - 1) =1). However, the jump from address 7 to 3 is caused by the jump to the start of the next column (the column being shown in the re-shaped memory of Figure 2(b)). As before, the start of the next column is calculated from the start of the current column (address 0), and adding the writing address increment (here 3) giving the address to skip to 0 + 3 = 3. For clarity of understanding, the addressing sequence is shown in Figure 2(c) in a re-drawn linear memory. The point at which to jump to the next column is determined by the number of rows. The jump must occur every Nr increments (where Nr is the number of rows), as discussed previously.

For the final block of data (4 x 6 = 24 cells), this process will be repeated again. As before, the write-address-pointer sequence will follow the read-address- pointer sequence, but will not skip the unused rows. Hence this sequence of addresses will be O, 6, 12, 18, 1 , 7, 13, 19, 2, 8, 14, 20, 3, 9, 15, 21 , 4, 10, 16, 22, 5, 11 , 17, 23. Note again how this sequence actually follows the read-address sequence, but visits some unused locations along the way (when the read-pointer jumps to the top of the next column). Hence the read-pointer gets ahead of the write pointer - this will be an important feature in a later stage.

To read out the de-interleaved final block of data, the increment is recalculated from equation (6) as (6x4) mod 23 = 1 , and it happens that in this case, de- interleaving is done simply by reading in sequential order. This is something of a special case. No jumping is required since there were no unused rows.

The interleaver is here shown in Figure 3(a) showing the transmitted sequence of data 0, 6, 12, 18, 1 , 7....23 which when written according to the sequence above as shown in Figure 3(b) results in the special case of sequential reading, shown in linear form in Figure 3(c).

In summary, this technique can be described by the following equations, although note that the iterative forms lead to a simpler implementation; in this description, the block being written into the de-interleaver memory is block j and the block being read out is block j-1 :

The write-address sequence is given by:

Ui x k_j ) mod(M - 1) when 0 < j < M - 1^"

Wi j = (7) M -I when i == M M -- 11 and the read-address sequence is given by:

where the increment kj is calculated from a slightly modified increment equation:

Jc₀ = I k_j = (k_j_ι .Nc_j_ι)moά(M - 1) O)

The method described in the previous section will not only work for the case when all of the possible numbers of columns are factors of the memory size, but it will also work for other memory sizes, provided that the allowed input number of columns is restricted to values that are factors of the memory size. So if the example above is modified to 4 rows and 5 columns (i.e. 20 cells in total), it would work for any number of input columns except 3. We have appreciated that a further technique will allow all numbers of columns to be handled.

The modification to deal with all input column numbers arranges to skip input addresses when the interleaved data is being written. For the example with an interleaver defined to have 4 rows and a maximum of 5 columns, if the first block of data to be written has 3 columns, an input address will be skipped after every 3 cells, which will create the effect of having written the data into the memory as though it actually comprised 4 columns, with the last column empty, as shown in Figure 4.

Therefore the write-address-sequence will be given by the following equation:

0

w^rij = ) (W}__W + k_j) if wη_] j < M-ki otherwise (10)

(w_MJ -(M -k_j -I)) if wi_/_i j ≥ M -kj where r_o = O

_ fa ^{+ k}j+ι ^{) when r}q ^{< M ~ k}j+ι

^{Vq+l '} V^rq - (^M - */+l - ^X)) ^{When r}<7 ^{≥ M} - */+l and

Jc₀ = I k_j+i = (fy x Nc' _j )mod(M - 1)

NC_j is the number of columns of data in the interleaver for block j Nc) is the first factor of M greater than or equal to Λ/c,- This can be expressed in a non-iterative form as:

Note that successive values of k_} may be stored in a similar way to the method described previously. In this case the side chain will count Nc) iterations of an address generator of the form of equation (1), with an increment of k_j, and storing the resulting address as the value of k_j+1 for the subsequent block.

The reading sequence will follow a similar procedure as before, reading out the columns and skipping the unused rows as before, although in this case, only 3 of the 4 columns will need to be read.

If this technique was used just as described, there would be a problem. When the write-pointer skips any unused columns, it will tend to catch up or overtake the read pointer. To prevent this, a further buffer is needed to hold back the input data. In the above example, a buffer (or FIFO) of 3 additional cells would be required (1 less than a whole column comprising the fixed number of rows, 4)

Suppose now that a first block of data has been received which has the full 5 columns, and so the memory is full. A second block is being received comprising 3 columns. To visualise this, consider the memory as a sequential block, with the cells shaded according to the block to which they belong. The first view is of a memory full of a first block:

I o I 4 I I 8 I 12 J 1¹⁶ 1 M g J 13 17 I 2 I I 6 io I I 14 I I 18 I | 3 I 7 I 11 j 15 19 I

Now consider the second block being received and written into memory (grey blocks), with the first block being read out in de-interleaved order. The increment required to do the de-interleaving corresponds to the number of columns from the first block, 5 in this case. The second block had 3 columns. Look at the memory after the first 3 cells have been written. The first three received cells, with values 0, 4, 8, have now been written to the grey block positions where data from the first block has been read out.

|ΛO •^' 4 ⁸ 12 I 16 I' 4'"| 5 9 13 17 I'.,M| ⁶ 10 I ¹⁴ 18 3 7 I 11 I 15 19 I

In order to get the data written correctly into the memory, we are going to skip the next column. Hence we need to do 2 increments (2x5=10 cells), starting from address 10, taking us to memory location (10+10) mod 19 = 1. This is currently occupied by the 4, but the next value to be read out will be the 3. The '1' in the second row of the second block must be put in the FIFO whilst the 3 from the first block is read out (once the 3 is read, the cell will be unused, shown in black):

12 16 4 13 17 8 ^l 6 10 14 18 FIFO:

^■ 1

As the next two values are received (5 then 9), they will be buffered through the FIFO, but the values taken from the FIFO are put in the correct places in the memory:

0 1 8 12 16 4 13 17 8

FIFO:

At this point another column will be skipped, so the next cell (2) will be stored in the buffer as the 7 from the first block is read out: 0 M I 8 I 12 I 16 I 4 I 5 I 9 I 13 I 17 I 8 I 6 I 10 I 14 I 18 11 15 19 FIFO:

1 ² 9 I I

This process continues writing the 6 and 10 via the FIFO:

I 0 I 1 I 2 I 12 I 161,415J 9 I 13 I 17 [_tβ 10 14 11 I 15 I 19

FIFO:

10 ^ι 6

then another column is skipped:

jo_f|

The last 2 cells are written via the FIFO: d I f ^J 2 I 12 16 I 4 \ 5 > 6 I 13 17 I 8 | 9 10¹ 14 18

FIFO:

InT 3

At this point, there is no more data to write, and then as the remaining cells from the first block are read out, the final contents of the FIFO are put into the main memory, ready to be de-interleaved:

0 1 2 3 4 5 6 7 8 9 10 11

FIFO:

Using this technique, any number of input columns can in principle be handled. Consider the case where the memory size is 90 rows by 10 columns, or 900 cells in total. 900 has factors up to 10 of 1 , 2, 3, 4, 5, 6, 9, 10, and so each of these column sizes can be handled without a FIFO. For column sizes 7 and 8, a FIFO would be required. The FIFO needs to be 2x90=180 cells. So the total memory requirement is 1080 cells.

However, a more efficient use of memory may be found, by choosing a main memory size with a better distribution of facϊors. For examp]e, if the main memory size was chosen to be 960 cells, this has factors of 1 , 2, 3, 4, 5, 6, 8, 10. In this case, a FIFO is required when 7 and 9 columns of data are to be de-interleaved, but in each case, only one column, or 90 cells, needs to be buffered. So the total requirement is 1050 cells.

In general, an exhaustive search can be carried out to find the optimum size of memory, for any given desired basic de-interleaver shape, and for this structure 1050 is the optimum choice.

As noted earlier, the process of skipping unused rows leads the read-address- pointer to get ahead of the write-pointer. In a similar way, it can be seen that the need to skip columns when writing would cause the write-pointer to overtake the read-pointer, and this cannot be allowed, otherwise data to be de-interleaved will be overwritten before it is read out. The FIFO prevents this from happening.

We have appreciated that when the memory is configured such that there are some spare rows, and the read-pointer is getting ahead, it will not be necessary to buffer so much data. This will allow a smaller FIFO to be used. We must plan for the worst case, or the smallest number of spare rows. This will occur when we have the largest number of input columns. In most of the examples so far, there have been no spare rows under this condition. But in the last example given, with a main memory size of 960 cells, there will be 6 spare rows. These allow for some reduction of the FIFO size, in this case a reduction from 90 cells to 48 cells

(see below), i.e. a reduction of the total to 1008.

It might be considered whether further increasing the main memory size might allow the FIFO to be eliminated altogether. Whilst this is true, it does not necessarily lead to a greater efficiency. For example, to achieve sufficient spare rows that no FIFO is required, a main memory size of 1080 cells is required.

In order to be able to make use of this optimum reduction technique, it is important that the writing process starts by writing into some spare memory, to give the reading process a chance to get ahead. One way to achieve this is to treat the memory as though it were a form of circular buffer, and to start in the spare rows at the end of the last column. The de-interleaver memory may be treated as circular, by first noting that usually the rth value of equation (1) can be found from:

cij_j = (i x k_j ) mod(M - 1) .

This works except for the very last value when the memory is full i.e. i = M - 1 , which would return ay = 0, whereas the correct value is ay = M - 1. Therefore equation (1) could be re-written:

(ix k_j)mod(M -l) when O ≤ / < M -l

(12)

°^lJ } [TMW --I\ wwώheenn zZ^" == M M --lI J

The introduction of the modulo term shows that the memory may be treated as a form of circular buffer. A generalised starting address a_Oj can now also be introduced:

However note that the second line of this equation now treats the location M-1 in a very special way. In practice this treatment is only needed when the there are no spare rows or columns in the memory (which is the only time / reaches /W- 1 and the first line can never generate the answer M-1).

As described above, a good place to start writing the current block of data is immediately following the end of the last column of data from the previous block. This will use the spare rows first, and then wrap around and continue to use the memory freed up by reading out the previous block. Therefore, the general starting address a_o,j can be written as:

«o,o =

^a°^{J ~}

The condition Nc_H = MINr means that the memory was completely filled during the writing of the previous block - i.e. that there were no columns to skip, and no spare rows - and so in this case Nc'j.i = Nc_j.i. As no extra rows are available the starting address must be reused. This is the only condition under which the memory address M - 1 will be used.

The term with Λ/c'_H— 1 skips to the last column, using the increment for writing the previous block, k^, and the term with Nr skips to the cell after the end of that column, using the increment for writing the new block, k_j, which is also used for reading the previous block. This process is illustrated in Figure 5.

Equation (14) may be simplified by noting that k_j = k_j^xNc^' (the mod [M-1] may be ignored given that k_j is part of an additive expression within another mod [M- 1]):

An equally valid way to compute the a_Oj, since the memory is now treated as though it were circular, is to calculate backwards by one fewer than the number of spare rows:

and this too may be simplified to: «o,o = α°'^J

Note that equations (15) to (17) are equivalent. The full set of equations for addressing the de-interleaver with variable data rate and minimum memory can therefore be written as:

M

(i div Nr) x aQ,j +^kj+l ^x J NVJc'_jy mod(M -l) if 0 < / <M-l r^dU = (19)

+/ mod JVr

M-I where

(20) it, = (k_j_, .Nό₃__x )mod(M - 1)

Nc_j is the number of columns of data in the interleaver for block j

Nc_j' is the first factor of M greater than or equal to Λ/c,

Nr is the fixed number of rows used for interleaving the data

/ is the index of the cell within the block, and so for each block it counts

Note that: the/th block of data will be written at the same time that they-fth block is being read; the address rd_M._1J = MA (and wr_M._1:, = M-I) will only be used for blocks for which the following are true:

Nc) = MfNr and

Nc_j = Nc'_j

Equations (18) - (21) may now be re-written in iterative forms to aid implementation: = 0 ≠ 0 (22)

where

\j = ^aQ,j

r^q+]

where co,j = «0,7

and kn = l fy+1 = (A₇- x Nc' j )mod(M - 1) and a_Qj is given by any of equations (14) to (17)

As described above, the technique of the previous section allows us to use a smaller FIFO, since the spare rows allow the read-address-pointer to skip ahead. We now need to calculate the required reduced size of the FIFO.

For relatively large blocks of memory, the address skipping during both reading and writing processes can effectively be considered to continue indefinitely. Hence what is important is the average rate at which each of the pointers skips addresses.

Suppose the read-pointer has to read from Λ/_rows rows and can then skip Λ/_extraRows rows. Λ/_ex_tr_aRows represents the minimum guaranteed number of additional rows available when the maximum number of columns is used. Suppose the write pointer is writing A/_C0|_S columns of data, and has to skip Λ/_extraCθ|_S. Without using the extra rows, the size of the FIFO required would therefore have been

WextraColsXΛ/rows-

The total number of cells to be written in a given block will be Λ/_rowsχΛ/_CO|_S. Assuming that one cell is always read every time that a cell is written, the read- pointer will advance by Λ/_rθws⁺Λ/_eχt_raRows increments during the time it takes to read (or write) Λ/_rows cells. So by the time all of the data has been written, the read- pointer will have advanced by: ^rows +^extraRo_Ws _{χ (/Yrows χ N∞h) =} ^^ _{+ /}Y_extraRows)xN_co]s -^* rows

Similarly, the write pointer will advance N_cois+N_exiraCoi_s during the time it takes to write Λ/_coi_s elements. Hence at the end of the block, it will have advanced by:

^cols +JWtCoIs _{χ (/}y_{rows χ /}y_{cols) β (Λ}Γ_COJS + N_3x^c₀₁₈)_XNr_0W8

Λ'cols The FIFO required is therefore the difference between these two:

FIFO = (N_col8 + NextraCols) ^x -^rows ~ (^rows + ^extraRows) ^x ^cols = M extraCols ^x -^rows ^~ ^ extraRows ^{x •}" cols

(If this calculation yields a negative number, no FIFO is required).

To calculate the maximum size of FIFO required, this calculation must be repeated for each combination of N_co[s and Λ/_extrac_oi_s- In the above example, where

(since this is always the minimum value), there are two cases to consider:

; hence FIFO=48; and

A/cois=9; Λ/_extraCois=1 ; hence FIFO=36.

Hence the worst case FIFO required is 48 cells.

There is a further particular case to consider for DVB-T2, where the total memory of the de-interleaver is to be shared between two streams, known as a "data PLP" and a "common PLP". (The physical layer is divided internally into pipes, known as physical layer pipes, or PLPs, mostly carrying individual service data, which may have some data common to several PLPs in a separate "common PLP". The specification states that the receiver must be able to decode one data PLP and its associated common PLP, and that the de-interleaver memory to do this will be shared).

The problem in this case is fundamentally the same problem as before, although there is an additional complication if it is required to keep the memory to a minimum. The DVB-T2 signal will convey a configuration parameter which will define how the sharing of the memory between the two streams will occur, and there is a limited subset of choices. For any given size of data stream, the optimum memory size can be calculated as above, along with the required FIFO size. In general, if the data PLP requires a large proportion of the memory, a bigger FIFO will be required and the converse is also true. Hence by careful allocation of the memory between the two streams and the FIFOs, the total memory required can be kept to around 8.5% more than the size of the single block defined in the DVB-T2 specification. If, however, the FIFO memories are kept separate from the de-interleaving memory, they each need to be large enough to handle the largest FIFO required, and the total memory requirement increases to 17% more than the single block. If the FIFOs are in a separate memory, but combined together (i.e. two FIFOs are implemented with a configurable partition), then 11.2% more than the single block is required.

In the optimum memory configuration, a single block of memory will be used, and it will be. configured, according to the signalled parameters, into four separate areas - two for the main memories of the de-interleavers for each of the common and data PLPs, and two for the FIFOs for each of the PLPs. Other strategies could be adopted, although they will use more memory - for example, it may be possible to configure the memory as a large set of small parallel memories which can be addressed simultaneously, and then different numbers of the small memories allocated to the jobs of FIFO and de-interleaving according to the required configuration.

Assuming the optimum memory strategy is used, there are potentially 7 operations that might need to be conducted during each clock cycle - reading out a de-interleaved cell for both of the data and common PLPs; reading from the FIFO for the data PLP and then writing this value to the time de-interleaver for the data PLP; doing the same for the common PLP; writing an input cell from either the data or the common PLP into the relevant FIFO.

Note that the channel can only ever deliver either a cell for a data PLP or the common PLP, and hence there can only ever be one input operation. However, as the number of cells for the common and data PLPs vary, it is likely that the operations to read out data for the common PLP and the data PLP will overlap at times - the new cells being received from the channel will need to be stored, and hence the cells currently in the memory for the corresponding PLP will need to be read out, but at the same time, the cells for the other PLP may not have all been read out. In principle it might be possible to wait until later to read the data out, since there will always be enough time - the danger is that this could impose too much delay on reading out the required data.

Suppose for a simplistic but extreme example to illustrate the issue, that a frame of data contains 10 cells for the common PLP and 90 cells for the data PLP (usually there would be other PLPs as well, but ignore these for the moment), and they have been received and stored in the de-interleaving memory. Now suppose on the next frame that there are only 5 cells for the common PLP and 95 for the data PLP. The 5 common PLP cells would be received, and the first 5 cells from the previous frame would be de-interleaved and read out. Next the 95 data PLP cells would arrive. Whilst the first 90 cells are arriving, the 90 data PLP cells from the previous frame would be de-interleaved and read out. Whilst the final 5 data PLP cells are being received, they will be stored in the data PLP de- interleaver memory, but there are no further cells from the previous frame to be read out, and so this will be the only opportunity to read out the common PLP cells. In this extreme case, the first 5 common PLP cells were read out at the beginning of the frame and the final 5 at the end of the frame. It would need to be established whether this was acceptable for a given implementation - if not, then parallel reading out during the overlap will be required.

It is likely that similar arguments will apply to the operations moving data from the FIFOs to the de~interleaver memories - they are likely to need to happen in parallel for the common and data PLPs.

In order to achieve the optimum memory size, values of de-interleaver memory must be carefully chosen for any given configuration. For example, if the configuration requires the data PLP to have a maximum of 62 FEC blocks each with 8100 cells, we can select that the main de-interleaver memory should be configured to 514800 cells, and the FIFO would be 16950 cells. The optimum memory size for a given configuration could be stored in a set of tables. The main memory size can be stored in an efficient way by storing two tables giving the number of extra rows and the number of extra columns for any configuration. The main memory size can then be calculated by taking the number of FEC blocks from the configuration, multiplying by 5, adding the number of extra columns for that number of FEC blocks, and multiplying by the total number of rows (equal to the fixed number of rows from the specification plus the number of extra rows from the table).

The implementation of the de-interleaver for DVB-T2 could therefore consist of the following steps:

Configuration:

Take the signalled maximum number of FEC blocks for each of the data PLP and common PLP, look up the numbers of extra rows and columns from the tables, and calculate the two main de-interleaver memory sizes from these numbers. Look up the corresponding two FIFO memory sizes.

Calculate and store, for each of the data PLP and common PLPs, a list of factors of the memory size from 5 up to the smallest factor greater than or equal to 5 times the maximum number of FEC blocks

Operation:

As each block is received, calculate the number of columns used for the interleaving (5 times the signalled number of FEC blocks for that Tl-block). This is the value of Nc. Look up the next largest factor from the list stored above. This is Nc'. Operate the de-interleavers as previously described.

While particular examples of the implementation of the invention have been given, it will be appreciated by those skilled in the art that many variations may be made. In particular, elements shown as hardware elements may be implemented in software. Other equivalents to the mathematical criteria shown by way of example may be employed.

As explained herein, an embodiment comprises an interleaver having an integer Nr rows and a variable Nc number of columns of data. The corresponding de- interleaver uses the numbers of rows and columns in the de-interleaving addressing sequences. The de-interleaver may have knowledge of the values Nr and Nc in various ways. The value Nr may be a fixed value for the system as a whole. The variable Nc may be transmitted to the de-interleaver along with the data or via a separate communication path. The variable Nc may also be also be communicated along with the data or via a separate communication path, or may vary according to a scheme known to the interleaver and de-interleaver.

Claims

1. Apparatus for interleaving or de-interleaving a stream of data consisting of successive data blocks of Nr x Nc data elements, where Nr is an integer and Nc is a variable, comprising: an input for receiving an input data stream of input data elements; a memory coupled to the input, the memory having M serially-numbered logical memory locations 0 to M - 1 ; a write-address generator coupled to the memory to address the memory locations of the memory to write data elements received in the data stream at the input to memory locations in the memory; a read-address generator coupled to the memory to address the memory locations of the memory to read data elements from the memory locations in the memory; and an output coupled to the memory to receive and output the data elements from memory locations read from the memory to form an output data stream; in which for a given block of data the read-address generator and write- address generator are each configured to generate the addresses of memory locations as functions of at least an increment value which itself is a function of an increment value used for a previous block multiplied by a dimension used for interleaving or de-interleaving the previous block.

2. Apparatus according to claim 1 , wherein Nr is a fixed integer.

3. Apparatus according to claim 1 , wherein the dimension is equal to Nc₁ where Nc is an integer factor of M.

4. Apparatus according to claim 1 , wherein the dimension is equal to a factor Nc' of M that is greater than or equal to Nc .

5. Apparatus according to claim 4, wherein the dimension is the smallest such factor of M.

6. Apparatus according to any of claims 1 to 5, in which the read address generator is configured to generate addresses for successive blocks that are of constant length.

7. Apparatus according to any of claims 1 to 5, in which the read address generator is configured to generate addresses for successive blocks that are of variable length by skipping unused memory locations.

8. Apparatus according to claim 7, in which the read address generator is further configured to generate addresses such that after every Nr elements the read-address generator jumps to a location by applying the increment value that was used to write the block to the address of the previous such location, and wherein the first such jump is calculated from the starting address.

9. Apparatus according to claim 1, in which the read address generator operates substantially in accordance with equations (3) and (4).

10. Apparatus according to claim 1, in which the read address generator operates substantially in accordance with equation (5).

11. Apparatus according to claim 1 , in which the write address generator is configured to generate addresses for successive blocks that are of variable length by skipping unused memory locations

12. Apparatus according to claim 1 , in which the write address generator operates substantially in accordance with equation (10).

13. Apparatus according to claim 1 , in which the write address generator operates substantially in accordance with equation (11).

14. Apparatus according to any preceding claim being a row column de- interleaver, wherein Nr is the integer number of logical rows and Nc is the integer number of logical columns of a corresponding row-column interleaver used to produce the stream of data.

15. Apparatus according to any preceding claim, further comprising a buffer coupled to the input and arranged to provide data elements to the memory.

16. Apparatus according to claim 15, wherein the buffer is arranged to receive data elements if the read and write addresses generated by the address generators are such that the apparatus would otherwise need to write an incoming data element to a location that has not yet been read.

17. Apparatus according to claim 15 or 16, wherein the memory is arranged to receive data from the buffer if data is present in the buffer and to receive data from the input if there is no data in the buffer.

18. Apparatus according to claim any of claims 15, 16 or 17, wherein the buffer is a FIFO.

19. Apparatus according to any preceding claim, wherein the write address generator is arranged to start the writing sequence at otherwise unused memory locations at the end of the read-address sequence.

20. Apparatus according to claim 19, arranged to operate in accordance with equations (18) to (21).

21. A DVB-T2 receiver incorporating de-interleaving apparatus in accordance with any preceding claim.

22. A DVB-T2 transmitter incorporating interleaving apparatus according to any of claims 1 to 20.

22. A method of interleaving or de-interleaving a stream of data consisting of successive data blocks of Nr x Nc data elements, where Nr is an integer and Nc is a variable using a memory having M serially-numbered logical memory locations 0 to M- 1, comprising: receiving an input data stream of input data elements; writing to the memory using a write-address generator coupled to the memory to address the memory locations of the memory to write data elements received in the data stream at the input to memory locations in the memory; reading from the memory using a read-address generator coupled to the memory to address the memory locations of the memory to read data elements from the memory locations in the memory; and providing an output of the output data elements from memory locations read from the memory to form an output data stream; in which for a given block of data the read-address generator and write- address generator generate the addresses of memory locations as functions of at least an increment value which itself is a function of an increment value used for a previous block multiplied by a dimension used for interleaving or de-interleaving the previous block.

23. A method according to claim 22, wherein Nr is a fixed integer.

24. A method according to claim 22, wherein the dimension is equal to Nc, where Wc is an integer factor of M.

25. A method according to claim 22, wherein the dimension is equal to a factor Nc' of M that is greater than or equal to Nc .

26. A method according to claim 25, wherein the dimension is the smallest such factor of M.

27. A method according to any of claims 22 to 26, comprising generating addresses for successive blocks that are of constant length.

28. A method according to any of claims 22 to 27, comprising generating addresses for successive blocks that are of variable length by skipping unused memory locations.

29. A method according to claim 28, comprising generating addresses such that after every Nr elements the read-address generator jumps to a location by applying the increment value that was used to write the block to the address of the previous such location, and wherein the first such jump is calculated from the starting address.

30. A method according to claim 22, in which the read address generator operates substantially in accordance with equations (3) and (4).

31. A method according to claim 22, in which the read address generator operates substantially in accordance with equation (5).

32. A method according to claim 22, in which the write address generator is configured to generate addresses for successive blocks that are of variable length by skipping unused memory locations

33. A method according to claim 22, in which the write address generator operates substantially in accordance with equation (10).

34. A method according to claim 22, in which the write address generator operates substantially in accordance with equation (11).

35. A method according to any of claims 22 to 34, being for de-interleaving data, wherein Nr is the integer number of logical rows and Nc is the integer number of logical columns of a corresponding row-column interleaver used to produce the stream of data.

36. A method according to any proceeding of claims 22 to 35, further comprising buffering data elements using a buffer prior to the memory.

37. A method according to claim 36, wherein the buffer is arranged to receive data elements if the read and write addresses generated by the address generators are such that the apparatus would otherwise need to write an incoming data element to a location that has not yet been read.

38. A method according to claim 36 or 37, wherein the memory is arranged to receive data from the buffer if data is present in the buffer and to receive data from the input if there is no data in the buffer.

39. A method according to claim any of claims 36, 37 or 38, wherein the buffer is a FIFO.

40. A method according to any of claims 22 to 39, wherein the write address generator is arranged to start the writing sequence at otherwise unused memory locations at the end of the read-address sequence.

41. A method according to claim 40, arranged to operate in accordance with equations (18) to (21).

42. A method according to claim 40, arranged to operate in accordance with equations (22) to (23).

43. Apparatus according to claim 18, arranged to operate in accordance with equations (22) to (23).