WO2009060185A2

WO2009060185A2 - Interleaving or de-interleaving a stream of data received in successive frames

Info

Publication number: WO2009060185A2
Application number: PCT/GB2008/003726
Authority: WO
Inventors: Christopher Ryan Nokes
Original assignee: British Broadcasting Corporation
Priority date: 2007-11-07
Filing date: 2008-11-05
Publication date: 2009-05-14
Also published as: GB2456292A; GB2456292B; GB0721853D0; WO2009060185A3

Abstract

A block interleaver or de-interleaver for interleaving or de-interleaving a stream of data symbols received in successive frames has a memory (12; 22) with M serially-numbered logical memory locations 0 to M - 1. For a first frame the address generator (14; 24) for the memory generates the addresses of memory locations in accordance with the numbered sequence of memory locations. For each subsequent frame the address generator addresses memory locations which correspond to memory locations addressed in the previous frame that are an integer number n of memory locations apart, with n > 1. Each time the address generator reaches the end of the serially-numbered locations it restarts at the beginning, subject to an increment such that all the memory locations are addressed in each frame. Each memory location read from is then written to with the next input data symbol. In this way the amount of memory required is reduced. The address generator is adapted to generate addresses for successive frames that are of variable length by skipping unused memory locations. The de-interleaver is particularly suitable for use in a DVB-T2 receiver.

Description

INTERLEAVING OR DE-INTERLEAVING A STREAM OF DATA RECEIVED IN

SUCCESSIVE FRAMES

BACKGROUND OF THE INVENTION

This invention relates to the interleaving and de-interleaving of a stream of data received in successive frames.

Digital communication systems such as the proposed DVB-T2 (Digital Video Broadcasting - Terrestrial, Version 2) system achieve good error performance in the presence of bursts of errors by a combination of forward error correction

(FEC) coding followed by interleaving at the transmitter. Bursts of errors in the channel are distributed as evenly as possible by the de-interleaving process in the receiver, so that the error rate after de-interleaving should always be low enough to allow errors to be corrected by the receiver's FEC decoder.

One common type of interleaver is a block interleaver, where data is written in groups of bits defined as symbols, for example, into the columns of a block of memory, and read out in rows. The total size of the memory used for a given number of symbols defines a frame of data (in this specification the term 'frame' is used in this sense).

If it is desired to operate such an interleaver continuously, so that data may be read into and out of the interleaver at the same constant rates, then a conventional approach to the design would require two blocks of memory each capable of holding a frame of data. Data is read into the first block of memory until a whole frame has been loaded. Data is then ready to be output from the first block, and while this happens data can simultaneously be read into the second block. When a second frame of data has been received, the second block of memory is full, so output data is now taken from here, whilst the input data is switched back to the first block. In this way, interleaving can then operate continuously. This approach requires twice the minimum amount of memory. For the large interleavers being considered in DVB-T2, this doubling of memory could have a significant cost implication for the receiver, and this is disadvantageous. An alternative known design of interleaver, which would allow the same memory to be re-used, would make use of a 'square' block of memory, where the number of rows and columns is the same. Data is first read into the columns and then read out in rows. In this case, as each data symbol is read out of a row, it is replaced by a new input symbol, allowing for continuous operation. The square design means that the data for the second frame, which was input row-wise, can be read out in columns to achieve the same interleaving effect.

A further known design of interleaver allows less than a full frame of memory to be used for the specific example of data arranged in few columns, but large numbers of rows. For example, with a data frame comprising 3 columns and 32 rows it can be shown that less than a full frame of memory is needed if a cycle of operations is chosen so that data is only held in a store until needed and then replaced by other data. However, this only works for specific fixed frame sizes and numbers of columns and rows.

Furthermore, in the context of DVB-T2, it is desired to have frames of data where the amount of data varies from frame to frame. This is to allow each service to be coded and interleaved separately, whilst sharing out the total (constant) transmission capacity dynamically between the services. In this context a 'service' refers to the collection of data elements which a receiver needs to receive simultaneously, such as the video, audio and data related to a single television programme. It is usual for various services to be transmitted together, but to allow the instantaneous data rates to vary, whilst the total data rate of all services remains constant - this is known as statistical multiplexing.

The interleaver for a single such variable-rate service might therefore take the form of a block of memory where data is read into the columns and read out in rows as before, but this time the number of columns of the memory that are used is determined by the data rate for that service during the corresponding frame period, up to a specified maximum defined by the size of the interleaver memory. When the service is operating at the maximum data rate, the memory will be filled each time, but when the interleaver is operating at below the maximum data rate, the interleaver memory will be only partly filled. This is illustrated in Figure 1 of the drawings. In this figure the shaded columns correspond to those filled with data for the current frame, and the blank columns represent unused portions of memory for this frame. Thus the 'square¹ approach described above cannot be used with such a variable-rate service.

It will be seen that with the variable-rate system just described, the interleaving effect will also vary with the data rate. In general, the performance of such a block interleaver will be determined by the smaller of the number of rows and the number of columns. Therefore as the number of columns is reduced with the data rate, it might be expected that the effectiveness of the interleaver would be reduced. In the specific case of DVB-T2 being considered, this is not expected to be a problem, since other operations within the overall DVB-T2 system design ensure that sufficient protection of the data is achieved.

SUMMARY OF THE INVENTION We have appreciated that the interleaver (and more importantly the de- interleaver) for such a system can be implemented with just a single sequential block of memory. The main problem to be solved is addressing the memory in the case when the data rate is at its maximum, and the memory is being constantly read from and written to, and is thus always full. We have furthermore appreciated that this method can be adapted so that when the data rate is below the maximum, continuous operation is, in effect, still achieved.

The invention in its various aspects is defined in the independent claims below to which reference may now be made. Advantageous features are set forth in the dependent claims.

Preferred embodiments of the invention, described in more detail below with reference to the drawings, take the form of a block interleaver or de-interleaver for interleaving or de-interleaving a stream of data symbols received in successive frames has a memory with M serially-numbered logical memory locations 0 to M - 1. Of course, the memory locations are logical locations, rather than physical locations and so the serial numbering of the logical locations may or may not result in serial numbering of physical locations. For a first frame the address generator for the memory generates the addresses of memory locations in accordance with the numbered sequence of memory locations. For each subsequent frame the address generator addresses memory locations which correspond to memory locations addressed in the previous frame that are an integer number n of memory locations apart, with n > 1. Each time the address generator reaches the end of the serially-numbered locations it restarts at the beginning, subject to an increment such that all the memory locations are addressed in each frame. Each memory location read from is then written to with the next input data symbol. In this way the amount of memory required is reduced.

The interleaver/de-interleaver can be adapted to generate addresses for successive frames that are of variable length by skipping unused memory locations.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described in more detail by way of example with reference to the drawings, in which:

Figure 1 is a diagram illustrating the operation of an interleaver operating at below maximum data rate;

Figure 2(a) and Figure 2(b) are block diagrams of an interleaver and a de-interleaver respectively;

Figure 3 shows at (a) a conceptualised interleaver memory with r rows and c columns, and at (b) a linear sequential block of memory as actually used in accordance with this invention; and

Figure 4 is a block diagram of an interleaver/de-interleaver address generator embodying the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The implementation of the invention in a constant bit-rate system and in a variable bit-rate system will both be considered.

Constant bit-rate system

An interleaving method embodying the invention for a constant bit-rate will first be described. A de-interleaver for the constant bit-rate case is almost identical. The basic interleaver is shown in the block diagram of Figure 2(a). The interleaver 10 has an interleaver memory 12 which is addressed by an address generator 14. Input data symbols (data items) are received at an input 16 and output data symbols appear at an output 18 forming an interleaved sequence.

During each frame (except the first) data symbols are read out one at a time from the interleaver memory 12 according to the addressing sequence produced by the address generator 14. For each symbol read out, a new symbol from the input is written into the memory at the same address; this memory location has just been cleared by reading the output symbol.

Suppose the interleaver to be implemented is defined to have data input into c columns, with each column having r rows, as shown in the conceptual illustration of Figure 3(a). The total memory of the interleaver is therefore defined by:

M = r x c symbols or memory locations.

The actual block of memory to be used will however be implemented as a sequential, linear or one-dimensional block of memory, as shown in Figure 3(b). In such a memory the terms "rows" and "columns" have no meaning, they simply define sub-blocks of data; they remain, however, convenient conceptual terms as will be seen. What matters is that they are simply examples of integers n where /7>1. It is necessary in such a memory to ensure that the address generator 14 provides the correct address sequence. The addresses of the elements of the memory will be calculated by index /, where:

0 ≤ / < M - l

For the first frame of data, data is received and written into the memory in sequential order. During this frame only, when the interleaver memory is first being filled, no output data is produced. Once the whole frame has been input, data is ready to be output. The address generator must calculate the output sequence. We have appreciated that this can be done from the parameters defining the interleaver.

The first row of the output sequence is found by addressing the sequential memory in the order: 0, r, 2r, Zr, .... (c-1).r The address sequence for the second row is:

1 , r+1, 2r+1, 3r+1 (c-1).r+1

In general, the address generator must calculate an initial value for each new address from the previous address by adding an increment, k_j, which varies with frame number j. Whilst the very first input data frame was being received (J=O), /C₀ = 1. When the second frame of input data is being received, the first frame must be read out, and so the increment Zc₁ must be equal to r. To calculate the correct address for all rows, the initial address calculated must be modified according to: βo.i = O

(1)

«, i ⁼ (^α _ι-i i ^{+ r}) ^m°d M + (α,_, , + r) divM for / > 0 where: a_u is the address of the /* element of they* input data frame mod is the integer modulo operator div is the integer division operator, that is it selects the integer part only of the result of the division.

This corresponds to performing modulo division by M on the address value, followed by the addition of a 'carry' signal. The carry signal has value 1 whenever a is within r of the end of the frame and value zero otherwise. Thus, in practice, since the value (a_/.^ + r) will always be less than 2M, equation (1) can be simplified to:

«o_,i = O α,,\ = («,-u + ^r) ^when O,-i,i + r) < M] (2) for i > 0

«u = («,-υ + O - (M - I) when (β,_, , + r) ≥ M\ or:

«o_,, = O α,_Λ = (α,__u + r) when α,_, , < M — r j (3) for / > 0 α,_,\ = («,-i_,i - (M - r - 1)) when α,__u > M - r

Consider as an example the case when the interleaver has 5 rows and 8 columns and the memory 40 locations. The address sequence generated for this frame is 0, 5, 10, 15, 20, 25, 30, 35, 1 , 6, 11...29, 34, 39. This describes the addresses to be generated to read out the first frame of interleaved data. However, the same address will also be used to write the new data symbols. Therefore, when this second input data frame has all been stored, it too will be need to be read out in interleaved sequence.

Once again, the addresses of the output sequence can be calculated using an increment of r, but this now refers to increments through the interleaved sequence of the previous frame. Returning to the previous example, every 5^th address is required from the sequence 0, 5, 10, 15, 20, 25, 30, 35, 1, 6, 11...29, 34, 39. In other words, the actual memory addresses will be given by the sequence 0, 25, 11 , 36, 22, 8, ...28, 14, 39. This sequence can be calculated exactly as before, but this time the increment is now r²:

«0,2 = 0

°,,2 (4)

«,,₂

The process now continues as before with data being read and written continuously. In general, the address sequence for any input frame j of data can be calculated using the increment k/.

^Oo,, = 0

(5)

where:

*o = l k_j = (k_J__l.r)modM + (k_J__l .r) div M which simplifies to:

*o = l

(6) k_j = (k_j__λ .r) mod M + k^ div c

So continuing with the previous example, k₃ = 8, and it can be seen that the addressing sequence 0, 8, 16, 24, 32, 1 , ... , 23, 31 , 39 will be correctly generated. For this example, the next frame generates k_A = 1, and the interleaver returns to the initial state, where data is input in sequential order into the interleaver memory.

Thus it is seen that for a first frame the address generator generates the addresses of memory locations in accordance with the numbered sequence of memory locations, and for each subsequent frame the address generator addresses memory locations which correspond to memory locations addressed in the previous frame that are an integer number n of memory locations apart, with n > 1 , and each time the address generator reaches the end of the serially- numbered locations it restarts at the beginning of the serially-numbered locations subject to an increment such that all the memory locations are addressed in each frame.

A simpler worked example of a complete sequence is given by way of example in the following table. This is purely to illustrate the process, and r is chosen to be 3 and c to be 5, so that M is 15. The sequence is:

What this table shows is that in the first frame the memory locations are addressed sequentially in the order: location 0, 1 , 2 ... . Actually the location numbers refer to logical locations (the physical locations, of course, could be randomly allocated in the memory but there would be no advantage in this and conceptually they remain a linear sequence of memory locations). For the second frame the memory locations are addressed sequentially in the order: location 0, 3, 6 ... . For the third frame the memory locations are addressed sequentially in the order: location 0, 9, 4 ..., and so on. It is seen that the first location is always zero and the last location is always M-λ . Consideration of Figure 3(a) will confirm this. When M is odd, the middle location will also be unchanged throughout. The pattern repeats after a limited number of frames or cycles. Each repeat explores all the values 0 to M-V, this will be apparent because M is an exact multiple of r, and the start of each frame is incremented by one relative to the previous frame.

The values of k_s produced from the formula of equation (6) must always be in the range 0 to M-1. It can be seen immediately that negative numbers cannot be generated, since only addition of positive quantities is involved. Consider first the modulo term of equation (6). The value k^.r is clearly a multiple of r, but since M is also a multiple of r, the result of the modulo operation will still be a multiple of r.

Therefore the maximum value for this term after the modulo operation will be M-r.

Considering the integer division term of equation (6), if A)_-1 is always less than M, then the result of the integer division will be less than the integer MIc, but since

M=r.c, the maximum value of the result of the integer division will be r-1. Hence the maximum value of k_j will be:

M - r + (r - l) = M - l as required.

A practical implementation to generate the required address sequence can operate as follows. At the start of each frame, the address generator is reset to 0. Subsequent addresses are then calculated by modulo M addition of the increment for that frame, kj, with a 'carry¹ to be added if M is exceeded.

The value of k_j can easily be stored from the previous frame, since it will be equal to the address generated at the (r+1) input value of the previous frame. So in the second frame of the above example with 40 memory locations, the address generator waits until the 6^th address has been generated (from the sequence 0, 5, 10, 15, 20, 25, 30...), which is 25 in this case, and stores this as the value of /9 for the third frame. Similarly in the third frame, the address generator stores the 6^th value of the sequence 0, 25, 11 , 36, 22, 8... and correctly stores 8 as the value of /c₃. Finally the 6^th value of the last sequence 0, 8, 16, 24, 32, 1... is stored and the generator returns to its initial state on the next frame. An example of a full implementation of the constant bit-rate interleaver address generator is shown in Figure 4. The interleaver includes a modulo-M counter 100 which counts every data symbol and corresponding generated address in each frame. It also produces a 'reset' pulse at the start of each frame. The reset pulse triggers a first sample-and-hold circuit 110, which generates the required increment value (kj) for the current frame. The increment value is connected to an adder 120, which is also connected to receive the address generator output, so the output of the adder is the unmodified value for the next address, calculated from the sum of the current address and the increment.

The unmodified value for the next address, that is the output from adder 120, is modified by means of a comparator 130, a switch 140 and a subtractor 150. The output of adder 120 is connected to comparator 130, which generates the value +1 when its input is ≥ M, but 0 otherwise. This signal operates switch 140 which selects either 0 or /W-1 as the minus (inverting) input to subtractor 150. The sum (non-inverting) input of subtractor 150 is also connected to the output of adder 120, and so the output of the subtractor 150 equals the address value calculated by adder 120 but reduced by M-1 if it exceeded M. This modification process is therefore equivalent to performing modulo (or integer) division by M on the address value, followed by the addition of a 'carry' signal, as required by equation (1).

Subtractor 150 therefore generates the correctly-modified value for the next address in the sequence. This is stored for one clock cycle by a unit delay 160, and therefore becomes the next output of the address generator when fed via a switch 170, which is normally set to pass data straight through. A reset pulse output from the counter 100 causes switch 170 to operate, and this resets the address generator output to 0 at the start of each frame.

The new value of the increment k_j for the first adder 120 is calculated by storing the correct output address in a second sample-and-hold circuit 180, and by the first sample-and-hold circuit 110, as follows. The output of counter 100 is connected to comparator 200, which tests whether the counter has reached the value r. When this condition is satisfied, sample-and-hold circuit 180 is triggered and the current value of the output address is stored. This value will form the next increment for adder 120, but it is not required until the beginning of the next frame. The output of sample-and-hold circuit 180 is therefore connected via switch 190 to sample-and-hold circuit 110, which is in turn triggered at the start of each frame when counter 100 resets. The stored value of the increment k_} is thus correctly updated.

Switch 190 is normally set to pass data straight through, but when the address generator is first started, or if it is required to re-initialise it, a pulse is applied to its initialisation input, which operates switch 190 and restarts the counter 100. The operation of switch 190 resets the stored increment back to its starting value of 1 , and the generator is therefore correctly initialised.

De-interleaver

As mentioned previously, the de-interleaver is almost identical to the interleaver. The basic de-interleaver is shown in the block diagram of Figure 2(b). The de-interleaver 20 has a de-interleaver memory 22 which is addressed by an address generator 24. Input data symbols in interleaved format are received at an input 26 and output data symbols appear at an output 28 forming a straight sequence.

During each frame (except the first) data symbols are read out one at a time from the de-interleaver memory 22 according to the addressing sequence produced by the address generator 24. For each symbol read out, a new symbol from the input is written into the memory at the same address, as this memory location has just been cleared by reading the output symbol.

This is thus essentially identical to the interleaver of Figure 2(a), save that all references to rows and columns are interchanged. (Indeed, an equally valid interleaver could have been defined where data was written to the rows and then read out of the columns.) The circuit of Figure 4 can, therefore, equally be used as a de-interleaver. The equation governing the address generation becomes: a<u = 0 α,J = O.-.,, ^{+ k}J ) ^{When α}-l,7 ^{< M} ~ ^kJ _K ϊ f ,or i . > _Λ 0 U) α,_j = («_<-._,, - W - k, - 1)) when α,__{X j} > M - k_J where:

*o = l k_j = (k_j__λ .c) mod M + k_j__λ div r and the comparator 200 shown in Figure 4 now tests whether the counter had reached the value c.

Thus it is seen that the generation of an addressing sequence that allows a block interleaver or de-interleaver to be implemented using a single block of sequential memory has been described for a constant data rate.

Variable bit-rate

The description above is for the case of a constant bit-rate, with any arbitrary interleaver defined by any number of rows and columns. This forms the core of an interleaver or de-interleaver operating at a variable bit-rate, where the number of rows or columns varies from block to block. In this variable data rate case, the basic method can be adapted so that unused addresses are skipped, and it is shown below that this will still work given certain constraints.

The modifications necessary for the case of a variable bit-rate will now be outlined. Although not an essential requirement of this method, it simplifies the implementation if it is assumed that the system is constrained so that bit-rate variations are such that there are always an integer number of columns worth of data at the input to interleaver, for any one frame. (If this is not the case it can be made so by padding.)

With the above assumption, the method described above for using a single block of memory can be adapted to the variable bit-rate case. Instead of a single address generator, which is used for both reading and writing, two similar address generators are employed, one for reading and one for writing, but they are differently timed. It is necessary to ensure that the following constraints apply:

(i) both generators produce the same sequence,

(ii) the 'read¹ address generator is always in time with or ahead of the

'write¹ generator, and

(iii) they are both reset at the beginning of each frame. Each generator also needs to keep track of the number of sub-blocks (rows or columns) in its corresponding frame of data, i.e. the 'read¹ address generator must know the number of sub-blocks (e.g. 'columns') in the current transmission frame, and the 'write' address generator must know the number of sub-blocks (e.g. 'rows') in the frame currently being stored in the interleaver memory (i.e. the next frame of data to be transmitted).

In order to produce the correctly-interleaved sequence when the data-rate is below its maximum, the read address generator must correctly 'skip' the addresses which correspond to unused columns of the interleaver memory. These can be calculated with a modulo c counter. If this counter exceeds the number of columns of data written during the previous frame, then the address from the read generator is skipped. This continues until the counter reaches c again, when it will be reset to 0 and the skipping will stop. Similarly the write address generator must perform this same skipping operation.

In the case of an interleaver for DVB-T2 as employed for transmission, the constraints mentioned above may require further buffering, which in itself requires additional memory, and so it may be more practical for the whole interleaver to be implemented in another way. For example, it has already been recognised that it is likely that two frame buffers will be required for each service in order to assist with the process of assembling data corresponding to several services into a larger transmission frame. These two buffers can simply be used as the memory from which data is read in interleaved sequence - no additional memory being required. Memory and complexity are not usually significant problems for broadcast transmitter installations.

However in the case of the receiver de-interleaver for DVB-T2, unlike the transmitter interleaver, it is important to ensure that the memory to be used can be kept to a minimum.

For the de-interleaver, data is received from the channel in bursts. In the case of

DVB-T2, it is assumed that any frame of transmitted data is separated into 4 to 6 bursts of data, with a gap of at least 1/4-1/6 frame between each burst. (When the system is operating at maximum data rate, the data burst and the gaps are exactly the same duration, so the maximum throughput data rate is half the peak data rate.) So once all the data for one frame has been received, it can be assumed that there will be a gap of duration at least 1/4-1/6 of a frame before any new data for the next frame will be received. The question therefore to be considered is therefore whether the interleaver structure described meets the constraints (i) to (iii) above in these circumstances.

As soon as a whole frame of data has been received, the receiver can start de- interleaving and processing the data. At this point the receiver can start clocking the read address generator to find the memory locations of the stored data in de- interleaved sequence. If the frame of data just received was at maximum data rate, the de-interleaver memory will be full, and no addresses will be skipped. Assuming the de-interleaver (and the down-stream processing) is operating at the peak bit-rate (i.e. the data rate corresponding to the reception of data during the bursts mentioned above), at the end of the gap period (when it is guaranteed no new data will be received), the de-interleaver will have read out 1/4-1/6 of a frame of data, and so the read address generator will have advanced to 1/4-1/6 of the way through its sequence for a whole frame. Suppose for example that frames currently consist of 6 bursts of data - in this case the duration of the gap will be equivalent to the time to receive 1/6 of a frame of data - so at the end of the gap the first 1/6 of a frame of de-interleaved data will have been read out.

Now suppose data for a second frame is being received, but in this case it is at a lower data rate. Suppose data is received at 1/4 of the maximum overall data rate for this second frame. The interleaver in this case would appear as shown previously in Figure 1 where eventually only the first 1/4 of the columns will be filled (due to the low data rate).

In this case, the transmitted data in the first burst will consist of 1/6 of the total data for the whole frame, i.e. the first two shaded rows. Remember from the previous description that the first 1/6 frame (the first two full rows) will have already been read out (as the previous frame was at maximum data rate, these were all occupied). When the new data is received, the write address generator will cause data to be stored in the correct locations - the ones just cleared by the 'read¹ operation, skipping the addresses for which it does not have data. During this time, and the gap which follows (which will be at least 1/6 of a frame), the third and fourth rows of data will be being read out. So it can be seen that the read address generator will be able to always be a little ahead of the write address generator, as required.

Having considered this case, the case when the data rate goes from quite low back up to the maximum also needs to be considered. Suppose therefore that the second frame as described above has now been completely received, and reception of a third frame at maximum data rate is about to start. The de- interleaver memory is therefore in the same condition as shown in Figure 1. The downstream processing can start reading out the data corresponding to the first two rows, shaded columns only, during the gap of at least 1/6 frame, and it is very clear that it will have cleared the space it needs (the first two full rows) before the data that needs to be written into this memory is received.

Thus it can be seen that the de-interleaver with memory equal to a single block can be used even in the case of the variable bit-rate system described, provided that there are adequate gaps in transmission.

While particular examples of the implementation of the invention have been given, it will be appreciated by those skilled in the art that many variations may be made. In particular, elements shown as hardware elements may be implemented in software. Other equivalents to the mathematical criteria shown by way of example may be employed.

Claims

1. Apparatus for interleaving or de-interleaving a stream of data received in successive frames, the apparatus comprising: an input for receiving an input data stream of input data items; a memory coupled to the input, the memory having M serially-numbered logical memory locations 0 to M- 1 ; an address generator coupled to the memory to address the memory locations of the memory to write data input items received in the data stream at the input to memory locations in the memory and to read data items from the memory locations in the memory; and an output coupled to the memory to receive and output the data items from memory locations read from the memory to form an output data stream; in which for a first frame the address generator generates the addresses of memory locations in accordance with the numbered sequence of memory locations, and for subsequent frames the address generator addresses memory locations which correspond to memory locations addressed in the previous frame that are an integer number n of memory locations apart, with n > 1 , and each time the address generator reaches the end of the serially-numbered locations it restarts at the beginning of the serially-numbered locations subject to an increment such that all the memory locations are addressed in each frame.

2. Apparatus according to claim 1 , in which each memory location read from is then written to with the next input data item.

3. Apparatus according to claim 1 or 2, including means for resetting the address generator for each frame.

4. Apparatus according to claim 1 , 2 or 3, in which the address generator operates substantially in accordance with equations (5) and (6) herein.

5. Apparatus according to any of claims 1 to 4, in which the address generator is adapted to generate addresses for successive frames that are of constant length.

6. Apparatus according to any of claims 1 to 4, in which the address generator is adapted to generate addresses for successive frames that are of variable length by skipping unused memory locations.

7. Apparatus according to claim 6, arranged to generate separate address sequences for writing and reading respectively, the sequences being the same but differently timed.

8. Apparatus according to claim 7, having two address generators each arranged to generate the separate address sequences for writing and reading respectively.

9. Apparatus according to claim 7 or 8, in which the read address sequence is always in time with or ahead of the write address sequence.

10. Apparatus according to claim 8 or 9, in which both address sequences are reset for each frame.

11. Apparatus according to any of claims 5 to 10, in which the address generator is adapted to receive input data that is received in bursts with gaps between them, the duration of the gaps being at least equal to the duration of the bursts.

12. Apparatus for interleaving or de-interleaving a stream of data received in successive frames substantially as herein described with reference to Figure 4 of the drawings.

13. A DVB-T2 receiver incorporating de-interleaving apparatus in accordance with any preceding claim.

14. A DVB-T2 transmitter incorporating interleaving apparatus according to any of claims 1 to 12.

15. A method of interleaving or de-interleaving a stream of data received in successive frames, the method comprising: providing a memory, the memory having M serially-numbered logical memory locations 0 to M - 1 ; receiving an input data stream of input data items and writing them into the memory in locations indicated by an address generator; reading and outputting the data items from memory locations indicated by the address generator to form an output data stream; in which for a first frame the addresses of memory locations indicated by the address generator are in accordance with the numbered sequence of memory locations, and for subsequent frames the addresses of memory locations indicated by the address generator correspond to memory locations addressed in the previous frame that are an integer number n of memory locations apart are addressed, with n > 1, and when the end of the serially-numbered locations is reached the addressing restarts at the beginning of the serially-numbered locations subject to an increment such that all the memory locations are addressed in each frame.

16. A method according to claim 15, in which each memory location read from is then written to with the next input data item.

17. A method according to claim 15 or 16, including resetting the address generator for each frame.

18. A method according to claim 15, 16 or 17, in which the address generator operates substantially in accordance with equations (5) and (6) herein.

19. A method according to any of claims 15 to 18, in which the address generator is adapted to generate addresses for successive frames that are of constant length.

20. A method according to any of claims 15 to 18, in which the address generator is adapted to generate addresses for successive frames that are of variable length by skipping unused memory locations.

21. A method according to claim 20, in which separate address sequences are generated for writing and reading respectively, the sequences being the same but differently timed.

22. A method according to claim 21, in which two address generators are each arranged to generate the separate address sequences for writing and reading respectively.

23. A method according to claim 21 or 22, in which the read address sequence is always in time with or ahead of the write address sequence.

24. A method according to claim 22 or 23, in which both address sequences are reset for each frame.

25. A method according to any of claims 15 to 24, in which an address generator is adapted to receive input data that is received in bursts with gaps between them, the duration of the gaps being at least equal to the duration of the bursts.