CN1377142A - Method and device for implementing fast deinterleave - Google Patents
Method and device for implementing fast deinterleave Download PDFInfo
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- CN1377142A CN1377142A CN01105713A CN01105713A CN1377142A CN 1377142 A CN1377142 A CN 1377142A CN 01105713 A CN01105713 A CN 01105713A CN 01105713 A CN01105713 A CN 01105713A CN 1377142 A CN1377142 A CN 1377142A
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Abstract
The invention discloses a high-speed method and device for first time relieving interlace. Based on the transformed address, the data to be processed are directly written to a double ports random access memory (DPRAM), then the data are read out from the DPRAM in sequence so as to complete the first time relieving interlace. The said device can be realized by processing unit, or by hardware outside the processing unit. Thus, the invented device provides features of high speed, real time storage space saving and very small processing time delay so as to increase the processing speed and throughput of the system.
Description
The present invention relates to the implementation method and the device of deinterleaving for the first time in Wideband Code Division Multiple Access (WCDMA) (being WCDMA) the communication field demultiplexing process.
In order to resist the unexpected error that produces in the transmission course, in cataloged procedure, to add the process that some interweave, unexpected error is distributed to whole decode block, utilize the good error correcting capability of error correcting code again random error, can improve the gain of decoding, thereby improve the quality of communication.Interweave for the first time be in Wideband Code Division Multiple Access (WCDMA) (WCDMA) multiplex process the step that interweaves; Deinterleaving for the first time is the requisite step in the WCDMA demultiplexing process.The method of deinterleaving for the first time is as follows in Wideband Code Division Multiple Access (WCDMA) (WCDMA) system:
The first step is according to input information group length K, and the ranks of the used rectangle of determining to interweave are counted R, C;
The second step information sequence writes rectangle R * C matrix by row;
Displacement one various combination according to transport service between the 3rd step row is to the displacement between being listed as of the array that interweaves;
The 4th goes on foot sensor matrix line by line, finishes deinterleaving for the first time.
Deinterleaving for the first time is that interframe interweaves, just can carry out after waiting the data collection of several frames to finish, to wait until exactly all input information K data of the first step all set after, can begin to handle, needed buffer storage length is K, if during the length of information sets to be processed long (value of K is bigger), will expend very big memory space; In second step, to write data into earlier in the memory block, in writing process, also to expend a lot of time, even utilize the very fast processor of read or write speed, if when the information data length K of input was big, time delay also can't be stood, all will take the time of decoding in these times of processing, the follow-up decoding processing time is had higher requirement, and the performance of deinterleaver will directly have influence on the performance of whole decoder for the first time.
Also do not retrieve at present the special patent documentation of the realization aspect of deinterleaver for the first time of discussing.
An object of the present invention is to propose address after a kind of data based conversion that will need the to handle dual port random access memory (DPRAM) that writes direct, reading of data from dual port random access memory (DPRAM) in order then, thus carry out the method for deinterleaving for the first time at a high speed.
Another object of the present invention is to propose a kind of device of realizing said method in Wideband Code Division Multiple Access (WCDMA) (WCDMA) communication system.
High speed of the present invention is de-interweaving method for the first time, may further comprise the steps:
1, according to Transmission Time Interval (TTI) and the class of business handled, the row of the used matrix of determining to interweave
Number R and columns C;
2, determine the step-length of initialization address and address according to the columns of Transmission Time Interval and processing at present;
3, data are write the data storage area, the address adds address step size;
4, judge whether to finish the write operation of row; If do not finish, jump to step 3;
5, judge whether to finish the write operation of all row, if do not finish, columns adds one, jumps to step 2;
6, finish deinterleaving for the first time, call over the data after the i.e. deinterleaving for the first time of data in the memory block.
The matrix columns that interweaves used in the described step 1 is determined as follows:
If Transmission Time Interval TTI is 10ms then columns C=1; If the Transmission Time Interval TTI month is 20ms then columns C=2; If Transmission Time Interval TTI is 40ms then columns C=4; If the Transmission Time Interval TTI month is 80ms then columns C=8.
The step-length of address is determined as follows in the described step 2:
If Transmission Time Interval TTI is 10ms then address step size is 1; If the Transmission Time Interval TTI month is 20ms then address step size is 2; If Transmission Time Interval TTI is 40ms then address step size is 4; If the Transmission Time Interval TTI month is 80ms then address step size is 8.
Initial address is determined as follows in the described step 2:
For transmitting the business that data break TTI equals 10ms and 20ms, the value of initial address equals the columns when pre-treatment; If transmission data break TTI equals 40ms, have 4 columns according to will handling, the value of initial address is being to be respectively 0,2,1,3 under 0,1,2,3 the situation when the pre-treatment columns; If transmission data break TTI equals 80ms, have 8 columns according to will handling, the value of initial address is being to be respectively 0,4,2,6,1,5,3,7 under 0,1,2,3,4,5,6,7 the situation when the pre-treatment columns;
The write operation of described step 3 is meant: utilize address after the conversion as the address of memory block, directly data are write the memory block.When first number of each row, write address is an initial address, and later number is that last address adds address step size.
In Wideband Code Division Multiple Access (WCDMA) (WCDMA) system, a kind of fast deinterleave device based on above method comprises the initial address selector, the address step size selector, the line number selector, the columns selector, row accumulator, row comparator, the row accumulator, the row comparator, address generating module, Double Port Random Memory;
Described initial address selector is used for selecting initial write address according to Transmission Time Interval with when the columns of pre-treatment;
Described address step size selector is used for selecting according to Transmission Time Interval the step-length of address increase;
Described line number selector is used for according to line number and the columns of Transmission Time Interval selection at different transport service correspondences with the columns selector;
Described capable comparator and row comparator are determined output according to the input of comparator, if two inputs equate, then be output as 1, if unequal then be output as 0;
Described capable accumulator and row accumulator be used to add up line number and columns when pre-treatment.
Described address generating module is used for the write address according to initial address and address step size generation Double Port Random Memory;
Described Double Port Random Memory is used to deposit the data of having finished deinterleaving for the first time;
Initial address selector and address step size selector output to address generating module according to Transmission Time Interval with initial address and address step size, address generating module is delivered to the address that produces in the Double Port Random Memory, as write address, in writing data into memory; The line number of while accumulation process, the row comparator receives the result of row accumulator and line number selector, if they equate that then columns adds one, simultaneously next initial address is chosen in line number zero clearing and address, writes other one data that are listed as again; The result of row accumulator delivers to initial address selector and row comparator simultaneously, the selection of control initial address.The output of columns selector also is connected in the row comparator, if the result of row accumulator equates with column selector, then the end of output signal represents to have finished deinterleaving for the first time, and the data that at this moment read out from Double Port Random Memory in order are exactly the data through deinterleaving for the first time.
Further specify the present invention below in conjunction with drawings and Examples.
Fig. 1 is the up code multiplexing block diagram of single channel of Wideband Code Division Multiple Access (WCDMA) (WCDMA) system.
Fig. 2 is apparatus of the present invention block diagrams;
Fig. 3 is a method flow diagram of the present invention;
Fig. 1 is the up code multiplexing block diagram of single channel of Wideband Code Division Multiple Access (WCDMA) (WCDMA) system.Its key step has: check digit CRC is additional, the transmission block segmentation, and chnnel coding, the radio frames equilibrium interweaves for the first time, radio frame segmentation, rate-matched, transmission channel is multiplexing, and physical channel segmentation interweaves for the second time, the physical channel mapping.The process of demultiplexing is the inverse process of multiplex process, and the deinterleaving position first time involved in the present invention is between radio frame segmentation and the radio frames equilibrium.
Fig. 2 is apparatus of the present invention block diagrams.It is by initial address selector (202), address step size selector (201), line number selector (203), columns selector (204), row accumulator (207), row comparator (208), row accumulator (209), row comparator (210), address generating module (205), Double Port Random Memory (206) is formed.
The working method of apparatus of the present invention is as follows:
Address step size selector (201) is selected the step-length of address according to Transmission Time Interval, outputs to address generating module.If Transmission Time Interval TTI is 10ms then address step size is 1; If the Transmission Time Interval TTI month is 20ms then address step size is 2; If Transmission Time Interval TTI is 40ms then address step size is 4; If the Transmission Time Interval TTI month is 80ms then address step size is 8.
Initial address selector (202) is selected initial address according to Transmission Time Interval with when the columns of pre-treatment, outputs to address generating module.For transmitting the business that data break TTI equals 10ms and 20ms, the value of initial address equals the columns when pre-treatment; If transmission data break TTI equals 40ms, have 4 columns according to will handling, the value of initial address is being to be respectively 0,2,1,3 under 0,1,2,3 the situation when the pre-treatment columns; If transmission data break TTI equals 80ms, have 8 columns according to will handling, the value of initial address is being to be respectively 0,4,2,6,1,5,3,7 under 0,1,2,3,4,5,6,7 the situation when the pre-treatment columns:
Columns selector (204) is selected columns to be processed according to Transmission Time Interval, delivers in the row comparator.If Transmission Time Interval TTI is 10ms then columns C=1; If the Transmission Time Interval TTI month is 20ms then columns C=2; If Transmission Time Interval TTI is 40ms then columns C=4; If the Transmission Time Interval TTI month is 80ms then columns C=8.
Line number selector (203) is selected line number to be processed according to the concrete business of Transmission Time Interval and transmission, and the output of row selector is received in the capable accumulator.
Row accumulator (207) is used for the line number of accumulation process, if handle the line number that line number equals row selector (203), then zero clearing.
The output of row accumulator (207) and line number selector (203) is connected to capable comparator (208), if both output equates that columns adds one, this part is finished by row accumulator (209).Equate the signal that row comparator (210) output deinterleaving is finished if receive row accumulator (209) output of row comparator (210) and the output of columns selector (204).Row comparator (208) also outputs to address generating module (205), if handle delegation, and will be with the address zero clearing.
Address generating module (205) is delivered in the Double Port Random Memory (210) according to the initial address and the address step size generation write address of input, and data are write.After all line numbers of certain row are write, the address zero clearing, columns adds one, reselect initial address, if all row have all been write, row comparator (210) will be exported an end signal, show to finish row deinterleaving for the first time, at this moment in order Double Port Random Memory (210) being read, is exactly the result after the deinterleaving.
Double Port Random Memory (210) is used to store the data through deinterleaving for the first time.
Fig. 3 is a method flow diagram of the present invention; Flow process is as follows:
Step 301 is determined matrix line number and the columns that interweaves used for the first time according to Transmission Time Interval.
Step 302 is according to Transmission Time Interval and determine the step-length of initial address and address when the columns of pre-treatment.
Step 303 writes the memory block with data by the address that calculates, and then the address is added address step size.
Step 304 judges whether to handle all row of certain row of being over, if handle the data of the row that are over, then jumps to step 305; If do not handle, then jump to step 303, continue to handle.
Step 305 judges whether to handle all row that are over, if processing finishes, exports one and handles end mark, and deinterleaving for the first time finishes; If do not handle, after adding 1 with columns, step 306 jumps to step 302, begin to handle the new row of another one.
The present invention discloses a kind of implementation method and device of the deinterleaving first time.Described method has real-time, and the data that processor will be handled write the memory block through behind the address mapping, has just finished the process of deinterleaving for the first time, processing time that need not be extra and memory space; Described device can be realized in processor, also can utilize the hardware of processor outside to realize, use the de-interleaving apparatus first time of method design of the present invention, have at a high speed, in real time, save characteristics such as memory space, the time-delay of handling is very little, can improve the processing speed and the throughput of system, give the more processing time of subsequent treatment, in official hour, can handle more data.Deinterleaving for the first time is the necessary procedure of demultiplexing in Wideband Code Division Multiple Access (WCDMA) (WCDMA) system, and broadband CDMA system is can data quantity transmitted very big, to the delay requirement height of demultiplexing, so will reduce the time-delay in each step as much as possible.The present invention goes to realize that than traditional algorithm in the standard that utilizes the method for deinterleaving for the first time is faster, and can reduce the requirement of deinterleaving for the first time to memory space, along with the maturation and the commercialization of 3G (Third Generation) Moblie, the present invention will inevitably be more widely used.
Claims (7)
1, a kind of implementation method of fast deinterleave is characterized in that may further comprise the steps:
Step 1:, determine the used matrix that interweaves according to the class of business of Transmission Time Interval (TTI) and processing
Line number R and columns C (301);
Step 2:, determine the step of initialization address and address according to Transmission Time Interval and the present columns of handling
Long (302):
Step 3: data are write the data storage area, and the address adds address step size (303);
Step 4: the write operation that judges whether to finish row; If do not finish, forward step 3 (304) to;
Step 5: judge whether to finish the write operation of all row,, columns is added one, forward to if do not finish
Step 2 (305);
Step 6: finish deinterleaving for the first time, the data that call in the memory block are after the deinterleaving for the first time
Data (306).
2, the implementation method of fast deinterleave according to claim 1 is characterized in that: the matrix columns that interweaves used in the described step 1 is determined as follows:
If Transmission Time Interval TTI is 10ms then columns C=1; If the Transmission Time Interval TTI month is 20ms then columns C=2; If Transmission Time Interval TTI is 40ms then columns C=4; If the Transmission Time Interval TTI month is 80ms then columns C=8.
3, the implementation method of fast deinterleave according to claim 1 and 2 is characterized in that: the step-length of address is determined as follows in the described step 2:
If Transmission Time Interval TTI is 10ms then address step size is 1; If the Transmission Time Interval TTI month is 20ms then address step size is 2; If Transmission Time Interval TTI is 40ms then address step size is 4; If the Transmission Time Interval TTI month is 80ms then address step size is 8.
4, the implementation method of fast deinterleave according to claim 1 is characterized in that: initial address is determined as follows in the described step 2:
For transmitting the business that data break TTI equals 10ms and 20ms, the value of initial address equals the columns when pre-treatment; If transmission data break TTI equals 40ms, have 4 columns according to will handling, the value of initial address is being to be respectively 0,2,1,3 under 0,1,2,3 the situation when the pre-treatment columns; If transmission data break TTI equals 80ms, have 8 columns according to will handling, the value of initial address is being to be respectively 0,4,2,6,1,5,3,7 under 0,1,2,3,4,5,6,7 the situation when the pre-treatment columns.
5, the implementation method of fast deinterleave according to claim 1 is characterized in that; The write operation of described step 3 is meant: utilize address after the conversion as the address of memory block, directly data are write the memory block, when first number of each row, write address is an initial address, and later number is that last address adds address step size.
6, a kind of fast deinterleave device, it is characterized in that: described device comprises address step size selector (201), initial address selector (202), line number selector (203), columns selector (204), address generating module (205), Double Port Random Memory (206), row accumulator (207), row comparator (208), row accumulator (209), row comparator (210);
Described initial address selector and address step size selector output to described address generating module according to Transmission Time Interval with initial address and address step size, described address generating module is delivered to the address that produces in the Double Port Random Memory, as write address, in writing data into memory; The line number of while accumulation process, the row comparator receives the result of row accumulator and line number selector, if they equate that then columns adds one, simultaneously next initial address is chosen in line number zero clearing and address, writes other one data that are listed as again; The result of row accumulator delivers to initial address selector and row comparator simultaneously, the selection of control initial address, the output of columns selector also is connected in the row comparator, if the result of row accumulator equates with column selector, end of output signal then, deinterleaving has for the first time been finished in expression, and the data that at this moment read out from Double Port Random Memory in order are exactly the data through deinterleaving for the first time.
7, the device of fast deinterleave according to claim 6 is characterized in that: described initial address selector is used for selecting initial write address according to Transmission Time Interval with when the columns of pre-treatment;
Described address step size selector is used for selecting according to Transmission Time Interval the step-length of address increase;
Described line number selector is used for according to line number and the columns of Transmission Time Interval selection at different transport service correspondences with the columns selector;
Described capable comparator and row comparator are determined output according to the input of comparator, if two inputs equate, then be output as 1, if unequal then be output as 0;
Described capable accumulator and row accumulator be used to add up line number and columns when pre-treatment;
Described address generating module is used for the write address according to initial address and address step size generation Double Port Random Memory;
Described Double Port Random Memory is used to deposit the data of having finished deinterleaving for the first time.
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| CN011057130A CN1377142B (en) | 2001-03-22 | 2001-03-22 | Method and device for implementing fast deinterleave |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1838562B (en) * | 2005-03-25 | 2010-04-21 | 华为技术有限公司 | Transmission channel data buffer method |
| CN101610089B (en) * | 2008-06-17 | 2013-06-05 | 中兴通讯股份有限公司 | Methods and devices for secondly interlacing and deinterlacing |
| CN108377176A (en) * | 2018-02-06 | 2018-08-07 | 深圳竹信科技有限公司 | Method for transmission processing, equipment, system and the storage medium of electrocardiogram (ECG) data |
| CN108880566A (en) * | 2017-05-15 | 2018-11-23 | 华为技术有限公司 | A kind of Polar decoding transmission method and device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0773639B1 (en) * | 1995-11-09 | 2003-09-24 | NTT DoCoMo, Inc. | Transmitter receiver for mobile communication system with frequency division duplex (FDD) and time division duplex (TDD) |
| KR100306282B1 (en) * | 1998-12-10 | 2001-11-02 | 윤종용 | Apparatus and for interleaving and deinterleaving frame date in communication system |
-
2001
- 2001-03-22 CN CN011057130A patent/CN1377142B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1838562B (en) * | 2005-03-25 | 2010-04-21 | 华为技术有限公司 | Transmission channel data buffer method |
| CN101610089B (en) * | 2008-06-17 | 2013-06-05 | 中兴通讯股份有限公司 | Methods and devices for secondly interlacing and deinterlacing |
| CN108880566A (en) * | 2017-05-15 | 2018-11-23 | 华为技术有限公司 | A kind of Polar decoding transmission method and device |
| CN108880566B (en) * | 2017-05-15 | 2020-08-25 | 华为技术有限公司 | Polar code transmission method and device |
| US11171741B2 (en) | 2017-05-15 | 2021-11-09 | Huawei Technologies Co., Ltd. | Polar code transmission method and apparatus |
| CN108377176A (en) * | 2018-02-06 | 2018-08-07 | 深圳竹信科技有限公司 | Method for transmission processing, equipment, system and the storage medium of electrocardiogram (ECG) data |
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