CN1198416C - TURBO coding and interleaving method and device for W-CDMA system - Google Patents
TURBO coding and interleaving method and device for W-CDMA system Download PDFInfo
- Publication number
- CN1198416C CN1198416C CNB021241074A CN02124107A CN1198416C CN 1198416 C CN1198416 C CN 1198416C CN B021241074 A CNB021241074 A CN B021241074A CN 02124107 A CN02124107 A CN 02124107A CN 1198416 C CN1198416 C CN 1198416C
- Authority
- CN
- China
- Prior art keywords
- bit
- data structure
- value
- memory
- interleaving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000012545 processing Methods 0.000 claims abstract description 6
- 238000003860 storage Methods 0.000 claims description 29
- 239000011159 matrix material Substances 0.000 claims description 14
- 239000000284 extract Substances 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 2
- 238000013507 mapping Methods 0.000 claims 1
- 230000006870 function Effects 0.000 abstract description 5
- 238000010295 mobile communication Methods 0.000 abstract description 5
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000008713 feedback mechanism Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Landscapes
- Error Detection And Correction (AREA)
Abstract
The present invention relates to a method adopting DSP to realize a TURBO encoder, which skillfully establishes a set of inner interwoven data structure. The functions of interweaving in rows and interweaving among rows can be simultaneously completed according to the corresponding inner interwoven data structure. The needed inner interwoven processing time in the process of coding can be obviously reduced. Thereby, the real-time coding of a Turbo code in a wideband code division multiple access mobile communication system is successfully realized, and the practical application requirements of high-speed data transmission can be satisfied. The present invention adopts a combined method of software and hardware to realize a high-speed interwoven encoder, and therefore, the present invention has large application flexibility. The method is suitable for an inner interwoven device of Turbo coding, and likewise, can also be used for realizing an anti-interwoven device of Turbo coding.
Description
(1) technical field:
The present invention relates to Wideband Code Division Multiple Access (WCDMA) (WCDMA) digital mobile communication system, particularly relate to Turbo Methods for Coding and device in this system of a kind of real-time implementation.
(2) background of invention:
In WCDMA mobile communication system, Turbo code coding and convolutional encoding are two kinds of transmission channel codings that requirement is adopted.Usually, the performance of Turbo code is better than the performance of convolution code, because the approximately high 1.0dB to 1.5dB of its more traditional convolution code of coding gain.So for guaranteeing the transmission quality of high-rate service, the many coding with Turbo code of WCDMA system replaces convolutional encoding.
The Turbo code encoder of standard is made of two the identical recursive systematic convolutional code that has feedback mechanism (RSC sign indicating number) encoders and an interleaver parallel cascade.Wherein, the realization of interleaver is very complicated, and it mainly finishes following three functions:
1. determine the line number R and the columns C of interleaver matrix with the method for being divided by and seek prime number;
2. ask the computing of greatest common divisor and remainder, finish interlace operation in the row;
3. according to certain capable interlacing rule, finish interlace operation in the ranks at last.
Because realizing the process of above-mentioned functions comprises a large amount of divisions, rems, seeks prime number and asks lengthy and tedious operation such as greatest common divisor, the operand of algorithm of interweaving in causing in the Turbo code encoder is too big, consuming time too much, so, if adopt existing Turbo code coding techniques, such as using DSP to realize the function of interleaver simply,, can't satisfy the demand that 3-G (Generation Three mobile communication system) requires to finish in real time the Turbo code coding probably then because of being subjected to the restriction of device calculation process speed.Therefore, the contradiction between the real-time computing of interweaving in how solving that limited calculation process ability of DSP and Turbo code encoder require, this is a crucial research contents that realizes the efficient coding of Turbo code encoder high speed.
Though the researcher is being devoted to work out the interleaver that a kind of efficiently method and apparatus of quick, suitable DSP processing feature is realized the Turbo encoder always, the patent documentation that has not yet to see relevant this respect is delivered.
(3) summary of the invention:
The objective of the invention is to propose a kind of high-speed Turbo code coder interleaver implementing method, and a kind of interleaver device that adopts said method.
The present invention realizes that the method for high-speed Turbo code coder interleaver comprises following step:
(1) reads in high-speed memory set up one group of interior interleaving data structure according to the algorithm that interweaves of TS 25.212 standard codes with special format;
(2) length K of calculating incoming bit stream;
(3) determine the line number R and the columns C of interleaver matrix, make K≤R * C;
(4) select accordingly interleaving data structure in certain according to the K value of calculating;
(5) variable M=M+1 is set, the initial value of M is zero;
(6) be that pointer reads the word (16 bit) in the interleaving data structure in proper order with M;
(7) according to the value N of reading word N
m, (N by formula
m-[N
m/ 8] * 8) calculate [N from input store
m/ 8] position of the extraction bit of exporting in the individual byte, wherein: N
mValue be 1～R * C, R and C are respectively the line number and the columns of interleaver matrix;
(8) to N
mValue judge, if it is greater than K, then changes step (10), otherwise continue next step;
(9) bit-order of being extracted is given output storage output;
(10) if value of judgement pointer M is M＜(R * C), return step (5); Otherwise continue step (11);
(11) finish interweaving encoding.
For realizing said method, the present invention also provides interior interlaced device to comprise digital signal processor, input store, output storage, read-only slow memory and high speed random asccess memory.
After interior interlaced device initial reset, the interior interleaving data structure in the read-only slow memory is read in the high speed random asccess memory; Digital signal processor is from the input store reading of data, and interleaving data structure in determining according to the bit number K of input; The interleaving data structure to the internal storage of digital signal processor, is carried out interleaving treatment through direct memory access (DMA) passage high speed reads in inciting somebody to action accordingly then, and the result sends into output storage with gained.
Beneficial effect of the present invention: interleaving data structure in 1, the present invention has set up a group dexterously, and finish the function that interweaves and interweave in the row simultaneously in the ranks according to interleaving data structure in corresponding, interweave the required processing time in having reduced in the cataloged procedure significantly, thereby successfully realized the real-time coding of Turbo code in the WCDMA mobile communication system, can satisfy the practical application request of high speed data transfer.
2, the present invention's method of adopting software and hardware to combine realizes the high speed interleaving coder, thereby very big application flexibility is arranged.
Described method is not only applicable to the interleaver of Turbo coding, equally can be used for the realization of the deinterleaver of Turbo decoding yet.
(4) description of drawings:
Fig. 1 is the flow chart of the method for the invention embodiment.
Fig. 2 is the principle schematic of the interleaver of realization Turbo encoder of the present invention.
Fig. 3 is the interleaver embodiment block diagram of realization Turbo encoder of the present invention.
(5) embodiment:
Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described.
In Fig. 1, step 1 is to read in high-speed memory setting up one group of interior interleaving data structure with special format according to the algorithm that interweaves of TS 25.212 standard codes; Step 2 is to calculate the length K of bit stream in the input store; Step 3 is to determine the line number R and the columns C of interleaver matrix, makes K≤R * C; Step 4 is to select corresponding interleaving data structure in certain according to the K value; Step 5 is that a variable M=M+1 is set, and its initial value is zero; Step 6 is to be that pointer reads the word in the interleaving data structure in proper order with M; Step 7 is the positions of calculating the bit that should extract according to the value of the word N that reads from input store; Step 8 is that the value of N is differentiated, if it greater than K, then changes step 10, otherwise continue next step; Step 9 is to give output storage output with the bit-order of being extracted; Step 10 is to differentiate the value of pointer M, if M＜(R * C), return step 5, otherwise, enter step 11 and finish interleaving process.
Figure 2 shows that the basic principle schematic of interleaver of the present invention.Interweave in the Turbo coding and comprise in the row and interweave and in the ranks interweaved for two steps.In the complexity that interweaves be that each bit arrangement position in output storage after interweaving of each row of input store has nothing in common with each other.By relevant Turbo coding interleaver description partly among the 3GPP standard TS 25.212 as can be known, the input data bit is counted K should adopt the Turbo coding between 320 to 5114, and according to different K values, can obtain the interleaver matrix of the combination of 134 kinds of different line numbers and columns, promptly have 134 kinds of different interlace modes.
In order to simplify the complexity of interleaving process, the present invention has constructed and 134 kinds of corresponding data structures of different interlace modes.These data structures are deposited in the external memory storage, only need related data structure is called in the DSP internal memory when interweaving computing, carry out real-time ranks interlace operation then according to this; Do the processing speed that can improve interweaving encoding like this.
The length of interleaving data structure is that (R * C)+1, wherein R is the line number of output matrix, and C is the columns of output matrix in each.The elementary cell of data structure is a word, wide 16 bits of each word.Bit number when expiring matrix under the current input bit length of the value representation of first data structure word situation, the i.e. value of R * C; Thereafter the content N of R * C word respectively represents N bit in the input traffic.Because input bit is deposited by byte in input store, so, need just can determine which input bit to give output storage in proper order with through calculating, and M bit in the back output stream that interweaves in becoming.
Fig. 3 is an interleaver embodiment block diagram of realizing the Turbo encoder.In this embodiment, digital signal processor 400 is the core component of Turbo coding interleaver; Low speed external memory storage ROM500 deposits interleaving data structure in all, the data protection when being mainly used in power down; When being used in digital signal processor 400 work, high speed external memory 600 stores interleaving data structure in all, to satisfy the requirement of its high-speed cruising speed; 200 of digital signal processor internal storages are deposited a certain selected interior interleaving data structure.Because 134 interior interleaving data structures of corresponding all situations that interweave of storage need 500K bytes of memory space at least, are impossible so all data structures are all moved in the internal storage 200.
The present invention adopts read-only slow memory ROM500, high speed random asccess memory 600 and 200 3 grades of storage organizations of digital signal processor internal storage, behind the electrification reset, interior interleaving data structure among the read-only slow memory ROM500 is moved to high speed random asccess memory 600, can be when making the digital signal processor high-speed cruising based on high speed external memory reading of data.In case counting K according to input bit has determined after the interior interleaving data structure, digital signal processor only need utilize the direct memory access (DMA) passage that related data structure is moved into the internal storage 200 from high speed random asccess memory 600, has so just further improved the processing speed of the computing that interweaves.For conserve storage, the data in the input and output memory all are that unit is deposited with the byte.Suppose input bit by bytes store in input store 100, output bit by bytes store in output storage 200.
Interior interweaving encoding divides three processes to carry out.At first, directly count the sequence number that K determines interior interleaving data structure according to input bit.It is as shown in table 1 below that input bit is counted the example of corresponding relation of K and interleaving data structure sequence number.
Table 1: input bit is counted the corresponding relation between K and interleaving data structure sequence number
| The data structure sequence number | |
| 1 | 320-320 |
| 2 | 321-340 |
| 3 | 341-360 |
| 4 | 361-380 |
| … | …… |
| 131 | 4841-5000 |
| 132 | 5001-5020 |
| 133 | 5021-5040 |
| 134 | 5041-5114 |
Secondly, after the definite interior interleaving data structure sequence number of K value, from high speed external memory 600, read corresponding interior interleaving data structure; Its first location contents is S=R * C, and the required cycling number of times that carries out of interior interweaving encoding of K bit is finished in expression.
At last, interweaving encoding operation in carrying out, concrete operating process is as follows:
● digital signal processor 400 second unit of memory 200 internally begins reading of content N1, and N1 represents that the 1st bit in the output storage 300 is from N1 bit in the input store 100.Because DSP is by the byte store data, so N1 the position of bit in input store 100 can be by calculating, promptly it should be the (N1-[N1/8] * 8) bit of [N1/8] individual byte.Extract this bit, and with its first bit as interleaver output.
● continue to read the content of the next unit in the internal storage 200 by above method, and extract second the output bit of the corresponding bits of input store 100 as output storage 300.
● and the like, till all unit in having read internal storage 200 in order.
Need to prove, since interior interleaving data structure during by full matrix situation set up, therefore, when input bit is counted K＜S, be that input bit is not filled in full R * C interleaver matrix, at this moment must when extracting certain bit of input, judge whether this bit is present in the incoming bit stream earlier.The method that is adopted is when reading in the data structure M location contents Nm (value of Nm is 1～R * C, and R and C are respectively the line number and the columns of interleaver matrix), to judge that whether Nm is greater than K; If greater than, represent that then this bit is not present in the incoming bit stream, just do not need it as the output bit yet.
Claims (2)
1, a kind of method that realizes Turbo code interleaving in the W-CDMA system is characterized in that comprising following step:
(1) reads in high-speed memory set up one group of interior interleaving data structure according to the algorithm that interweaves of TS 25.212 standard codes with special format;
(2) length K of bit stream in the calculating input store;
(3) determine the line number R and the columns C of interleaver matrix, make K≤R * C;
(4) select accordingly interleaving data structure in certain according to the K value of calculating;
(5) variable M=M+1 is set, the initial value of M is zero;
(6) be that pointer reads the word in the interleaving data structure in proper order with M;
(7) according to reading word N
mValue, (N by formula
m-[N
m/ 8] * 8) calculate [N from input store
m/ 8] position of the extraction bit of exporting in the individual byte, wherein: the value of m is 1～R * C, R and C are respectively the line number and the columns of interleaver matrix;
(8) to N
mValue judge, if it is greater than K, then changes step (10), otherwise continue next step;
(9) bit-order of being extracted is given output storage output;
(10) if value of judgement pointer M is M＜(R * C), return step (5); Otherwise enter step (11);
(11) finish interweaving encoding.
2, a kind of device of realizing Turbo code interleaving in the W-CDMA system, it is characterized in that: comprise and comprise digital signal processor (400), input store (100), output storage (300), read-only slow memory (500) and high speed random asccess memory (600);
After interior interlaced device initial reset, one group of interior interleaving data structure in the read-only slow memory (500) is read in the high speed random asccess memory (600); Digital signal processor (400) at first calculates the length K of the bit number of being stored in the input store (100), and according to the K value of calculating, according to the corresponding relation of K value in the mapping table between input bit length K and interleaving data structure sequence number and interleaving data structure sequence number, from high speed random asccess memory (600), select corresponding interleaving data structure; And read bit and write output storage (300) in order from input store (100) to finish interweaving encoding according to described data relation;
Digital signal processor (400) begins reading of data from first byte of selected interleaving data structure, and incite somebody to action corresponding interior interleaving data structure through the direct memory access (DMA) passage, high speed random asccess memory (600) is read to the internal storage (200) of digital signal processor (400);
Digital signal processor (400) is by reading of data in the internal storage (200); It begins reading of content Nm in m unit of memory (200) internally, and wherein: the value of Nm is 1～R * C, and R and C are respectively the line number and the columns of interleaver matrix; Nm represents that m bit in the output storage (300) is from Nm bit in the input store (100); Nm the position of bit in input store (100) be by calculating, and promptly it should be (Nm-[Nm/8] * 8) bit of [Nm/8] individual byte;
Afterwards, digital signal processor (400) is judged the size of Nm value, if N
m≤ R * C then extracts Nm bit, and it is sent into m bit of output storage (300);
If Nm＞R * C, then judge the size of m value again, m≤R * C does not then send Nm bit into output storage (300), and continuation reads data in the internal storage (200) according to said sequence, end interweaving encoding processing procedure when m＞R * C; It promptly is coded data stream that the gained coding result is stored in output storage (300) the i.e. output of this memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021241074A CN1198416C (en) | 2002-07-12 | 2002-07-12 | TURBO coding and interleaving method and device for W-CDMA system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021241074A CN1198416C (en) | 2002-07-12 | 2002-07-12 | TURBO coding and interleaving method and device for W-CDMA system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1399429A CN1399429A (en) | 2003-02-26 |
| CN1198416C true CN1198416C (en) | 2005-04-20 |
Family
ID=4745329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021241074A Expired - Fee Related CN1198416C (en) | 2002-07-12 | 2002-07-12 | TURBO coding and interleaving method and device for W-CDMA system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1198416C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101043284B (en) * | 2007-04-10 | 2011-04-20 | 中兴通讯股份有限公司 | Interleaver of TURBO coder in WCDMA system |
| CN101771418B (en) * | 2009-01-07 | 2014-11-05 | 华为技术有限公司 | Encoding method and device thereof |
| CN109150198B (en) * | 2017-06-16 | 2021-05-14 | 华为技术有限公司 | Interleaving processing method and device for polarization code |
-
2002
- 2002-07-12 CN CNB021241074A patent/CN1198416C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1399429A (en) | 2003-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1122371C (en) | Interleaving / deinterleaving device and method for communication system | |
| CN101777924B (en) | Method and device for decoding Turbo codes | |
| CN100574116C (en) | Turbo-interleaving device and method | |
| CN1112776C (en) | Puncturing device and method for turbo encoder in mobile communication system | |
| CN1183683C (en) | Position adaptive coding method using prefix prediction | |
| CN101079641A (en) | 2-dimensional interleaving apparatus and method | |
| JP2002532941A (en) | Turbo code interleaver using linear congruential sequences | |
| CN1193427A (en) | Method of and device for coding digital information signal | |
| JP4298175B2 (en) | Inline sorting for turbo codes | |
| US7170432B2 (en) | Addresses generation for interleavers in turbo encoders and decoders | |
| CN102904580B (en) | X-BIT Coding Compression Algorithm | |
| CN1198416C (en) | TURBO coding and interleaving method and device for W-CDMA system | |
| CN1306348A (en) | Method of effectively crossing length variable data group | |
| CN1157854C (en) | High-speed Turbo code decoder | |
| CN1575547A (en) | Non linear scaling of reliability values in a turbo decoder system | |
| CN1147169C (en) | Decoding method and decoder for Turbo code | |
| CN1171392C (en) | Method and device for interleaving and deinterleaving of parallel cascade convolution code | |
| CN1129257C (en) | Maximum-likelihood decode method f serial backtracking and decoder using said method | |
| CN1142629C (en) | Decoding method and decoder for Tebo code | |
| CN1219363C (en) | Rate matching device for CDMA communication system | |
| CN101540651A (en) | Method and device for realizing column interleaving | |
| CN1738229A (en) | Woven convolutional code error detection and correction coder, encoder in TD-SCDMA system | |
| CN1428951A (en) | Bit uniformly-inserted parallel cascaded code interleaving method and its interleaving device | |
| CN1133276C (en) | Decoding method and decoder for high-speed parallel cascade codes | |
| CN1145267C (en) | High-efficiency convolution coding method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |