CN1428951A - Bit uniformly-inserted parallel cascaded code interleaving method and its interleaving device - Google Patents
Bit uniformly-inserted parallel cascaded code interleaving method and its interleaving device Download PDFInfo
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Abstract
The parallel cascaded code interleaving method by uniformly inserting bit includes the following steps: defining the position of every insertion bit in code flow of data packet with a certain length; in the interior of interleaving device separating data bit from insertion bit in the code flow; respectively interleaving data bits and insertion bits; after interleaving, according to the interleaving sequence placing the insertion bits into the interleaved space fixed positions successively; after interleaving, placing the data bits into data bit positions; and synthesizing system coda packet for output. Said invention can make output system code flow uniformly distribute insertion bits on defined positions, after said code flow is passed through of coder end, the decoder can better utilize energy given by insertion bit to raise the stability of decoder and decoding efficiency, and coding and decoding performance.
Description
Technical field
The present invention relates to error correction/encoding method and device in a kind of digital communication system, particularly a kind of in 3-G (Generation Three mobile communication system), realize bit uniformly-inserted parallel cascade codes (Turbo Code) interweave production method and interleaver.Belong to communication technical field.
Background technology
Parallel cascade codes is a kind of coding and decoding method that generally adopts in 3-G (Generation Three mobile communication system), can improve the decoding performance of data packet services greatly.Parallel cascade codes its performance in Gaussian channel approaches the Shannon capacity limit, and parallel cascade codes adopts iteration, the decoding algorithm of soft input/soft output, and performance substantially exceeds traditional convolutional encoding under identical decoding complex degree.Because the capacity and the Signal-to-Noise of Wideband Code Division Multiple Access (WCDMA) (WCDMA-WidebandCode Division Multiple Access) system are in close relations, so performance improvement has directly improved power system capacity.The encoder of general parallel cascade codes is by two parallel recursive convolutional encoder devices, and the interleaver (Turbo interleaver) before the second recursive convolutional encoder device is formed.These two convolution coders are called the composition encoder of parallel cascade codes, information bit is by these two encoder encodes, first convolution coder is according to input original order coding, the information bit sequential encoding of second convolution coder after according to interleaver change order.According to the code check that sets, export from the parity bit of prime information bit and two convolution coders respectively.
The parallel cascade code decoder is composed as follows: first becomes the system and parity bits soft-decision (maximum likelihood) information of demal to be input to first decoder.Soft-decision likelihood value after first decoder will upgrade is sent into second decoder through behind the interleaver.In addition, second decoder also receives the original information bits of upgrading, and corresponding to parity bits channel soft decision information.About the likelihood information that upgraded, the soft-decision output from second decoder feeds back to first decoder, repeats this process then.This process can repeat arbitrarily repeatedly, but only need limited just passable several times, otherwise too much iteration can cause output saturated.Last very hard decision output.
Shannon (shannon) information theory is pointed out, when on noisy channel, using grouping error correction coding or convolution code etc., have only when the constraint length n of block length or convolutional encoding is tending towards infinity, the performance of error correction coding could be near the theoretical limit of Shannon, as utilize the random code average behavior can reach theoretical value, but be difficult to realize.The most frequently used interpretation method is maximum likelihood algorithm (ML), and index increases but the complexity of this algorithm is with the increase of n, up to the degree that in fact can not realize.Therefore people are seeking code check near the Shannon theory value always for a long time, and the error rate is little, the good sign indicating number that decoding complexity is low, and the method for good yard of many structures has been proposed.The parallel cascade codes of people such as Berrou proposition in 1993 is actually the ingenious comprehensive and development of previous work, initial report achievement shows that its decoding performance can be near the Shannon theory value, as to utilize two code checks be the parallel cascade codes that 1/2 convolution code parallel cascade forms, when signal to noise ratio was 0.7dB, bit error rate can reach 10
-5But owing to mainly be The results of numerical simulation at that time, lack theory analysis, therefore initial people's reaction is to suspect, but the research of several years each side has not only repeated The above results later on, and the development of a lot of theories and practical application is arranged, and shows that parallel cascade codes provides the approach of the good sign indicating number of structure really, therefore parallel cascade codes becomes the research focus of international information opinion and coding theory circle very soon, and attempts to be applied to various communication systems.
In 3-G (Generation Three mobile communication system), comprise broadband CDMA system (WCDMA), (the CDMA2000 of CDMA 2000 system, Code Division Multiple Access), the synchronization code multi-address division system of time division way (TD-SCDMA, Time Division-Synchronization Code DivisionMultiple Access) system all adopts the coding and decoding mode of parallel cascade codes as data channel.The parallel cascade codes decoding performance obviously is better than convolution code, and it is long more to divide into groups, and performance improves obvious more, is very suitable for the coding and decoding of the big grouping of data channel.But parallel cascade codes has two shortcomings of two maximums: iterative algorithm is adopted in decoding, prolongs the decoding algorithm complexity during decoder; Under low signal-to-noise ratio, situations such as iteration failure or decoding performance difference appear in decoding effect instability.In U.S. Patent No. 6,272, mentioned the parallel cascade code structure that employing is punchinged in digital system in 183 patents, the parallel cascade codes that employing is punchinged can realize that multiple code rate is with the adaptive channel mass change, but do not consider can cause systematic code and check code skewness because of punchinging at diverse location, the efficient of decoding is relatively poor; No.6 has mentioned in 26 3,467 patents and has adopted a kind of parallel cascade codes decoder architecture that improves the system symbol migration probability, though can improve decoder performance, does not consider the architecture advances of interleaver, and decoding performance is inhomogeneous.The improved interleaver of employing in the parallel cascade codes of punchinging that we propose, the known bits energy that can evenly distribute evenly improves decoder performance, improves the randomness of decoding, has improved decoding performance.
Summary of the invention
Main purpose of the present invention is to provide a kind of bit uniformly-inserted parallel cascaded code interleaving method and interleaver at the deficiency of prior art, it changes the interleaving mode of transmitting terminal parallel cascade code coder interleaver, insert bit on the position that the output system code stream is determined, insert the high energy of bit signal at receiving terminal by utilizing, balanced each decoder for decoding performance that improves.
The purpose of this invention is to provide a kind of bit uniformly-inserted parallel cascaded code interleaving method and interleaver; evenly distribute during system's code stream that it exports the transmitting terminal interleaver is determined and insert bit; thereby solve the unequal error protection problem, improve the decoding performance of parallel cascade codes.
For achieving the above object, method and technology scheme of the present invention may further comprise the steps:
Step 1: before interweaving,, for example be the packet of N to length to the data grouping, total M insertion bit.Insert the position of bit before at first determining to interweave, evenly insert in the data bit according to 1: 9 ratio, determine the position of each insertion bit as inserting bit;
Step 2:, data bit in the code stream and insertion bit are separated in interleaver inside; Respectively data bit and insertion bit are interweaved; Select to insert the deinterleaving method of bit,, select to adopt random interleaving or other interleaving mode to interweave according to the principle that interleaver interweaves with largest random;
Step 3: the insertion bit after will interweaving is according to interleaved order, and back place, fixed position at interval successively interweaves; Select to insert in the interleaver specific position of bit, principle be with interweave before the insertion bit position apart from maximum, evenly insert in the data bit as inserting bit according to 1: 9 ratio, insert bit in the position 1,11,21,31 ..., the insertion bit position after then selecting to interweave is 5,15,25, with the preceding bit position 1 of inserting that interweaves, 11,21,31 distances 5 more than the bit all can effectively increase the distance of code word;
Step 4: put into data bit location after data bit interweaves.Interweaving of data bit can be selected multiple interleaving mode;
Step 5: the synthetic whole back systematic code grouping output that interweaves.
Interleaver of the present invention is a kind of bit uniformly-inserted parallel cascaded code interleaving device, which comprises at least as lower device:
First device, the code stream of reception certain-length packet;
Second device is used for determining that code stream inserts the position of bit, and distinguishes data bit and insert bit;
First interlaced device, the insertion bit that is used to interweave, and the insertion bit after will interweaving is according to interleaved order, back place, fixed position at interval successively interweaves;
Second interlaced device is used for the interleaving data bit, and puts into data bit location after data bit interweaved;
Synthesizer is used for data bit after interweaving respectively and the output of the synthetic grouping of insertion bit code stream.
According to the principle that interleaver interweaves with largest random, first interlaced device adopts the random interleaving method to interweave, or other interleaving mode interweaves.
First interlaced device will insert bit and be uniformly-spaced to insert evenly distributedly, and the fixed position of inserting is insertion bit distance centre position before interweaving, and this distance is a ultimate range, can effectively increase the distance of code word.
According to the technique scheme analysis as can be known, the present invention changes the interleaving mode of transmitting terminal parallel cascade code coder interleaver, make output system code stream mean allocation on the position of determining insert bit, make it by behind the channel, decoder end interweaves and deinterleaver adopt with encoder in same method or the structure of interleaver, decoder can utilize well and insert the energy that bit is endowed, strengthened the stability of decoder, significantly do not increasing under the condition of coding redundancy, reduce iterations, balancedly improved the decoding efficiency and the coding and decoding performance of decoder.
Description of drawings
Fig. 1 is a parallel cascade code coder theory diagram.
Fig. 2 is a parallel cascade code decoder theory diagram.
Fig. 3 is the inventive method flow chart.
Fig. 4 is an interleaver internal structure schematic diagram of the present invention.
Fig. 5 is systematic code flow structure figure before and after the interleaver of prior art interweaves.
Fig. 6 for adopt the present invention insert bit interleaver interweave before and after systematic code flow structure figure.
Fig. 7 is that the performance of different interleaving device compares schematic diagram.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is done detailed description further.
Fig. 1 is a parallel cascade code coder theory diagram.The encoder of general parallel cascade codes comprises two polynomial reponse system convolution codes of identical generation (RSC), forms as 101 and 102 and interleavers among the figure 103.Systematic code is from the output of X end, and 101 encoder output verification sign indicating number Y1 behind the original information bits process interleaver 103, has upset order, through output verification sign indicating number Y2 behind 102 encoders.Behind the parallel cascade code coder, information bit has increased by 2 times redundancy check bit, and code rate is 1/3.Parallel cascade codes can have higher code rate, can increase redundant bit by the quantity that increases encoder and interleaver and improve decoding performance.
Fig. 2 is a parallel cascade code decoder schematic diagram.First system and parity bits soft-decision (maximum likelihood) information of forming sign indicating number is input to first decoder 201.Soft-decision likelihood value after first decoder will upgrade is sent into second decoder 203 through behind the interleaver 202.In addition, second decoder also receives through the original information bits X behind the interleaver 206, and corresponding to parity bits channel soft decision information Y2.The likelihood information that upgraded, the soft-decision output from second decoder 203 feeds back to first decoder through deinterleaver 205, repeats this process then.This process can repeat arbitrarily repeatedly, but only need limited just passable several times, otherwise too much iteration can cause output saturated.Afterbody is through carrying out hard decision output behind the deinterleaver 204.
In decoder, in the structure of deinterleaver and the encoder is oppositely, and known bits in will dividing into groups earlier and data bit separately adopt the interweave principle opposite with interleaver to carry out deinterleaving then, synthesize the grouping of the data bit and the known bits of origin-location, send into decoder.
Fig. 5 is the code flow structure schematic diagram that adopts traditional interleaver deinterleaving method output.Its data bit and insertion bit interweave together, and the skewness of bit is inserted in the back that interweaves, and it is many that bit is inserted in some zone, performance can be better during decoding, bit is not just inserted in some zone, and decoding performance does not improve, and causes the inhomogeneous of decoding performance.
Referring to Fig. 3,6, method of the present invention to the data grouping, for example is the packet of N to length before interweaving, total M insertion bit.Insert the position of bit before at first determining to interweave, evenly insert in the data bit according to 1: 9 ratio, determine the position of each insertion bit as inserting bit; Determine the position of each insertion bit; In interleaver inside, data bit in the code stream and insertion bit are separated; Respectively data bit and insertion bit are interweaved; Select to insert the deinterleaving method of bit,, select to adopt random interleaving or other interleaving mode to interweave according to the principle that interleaver interweaves with largest random; Insertion bit after will interweaving is according to interleaved order, and back place, fixed position at interval successively interweaves; Select to insert in the interleaver specific position of bit, principle be with interweave before the insertion bit position apart from maximum, evenly insert in the data bit as inserting bit according to 1: 9 ratio, insert bit in the position 1,11,21,31 ..., the insertion bit position after then selecting to interweave is 5,15,25, with the preceding bit position 1 of inserting that interweaves, 11,21,31 distances 5 more than the bit all, can effectively increase the distance of code word, shown in the code flow structure schematic diagram of Fig. 6 interleaver deinterleaving method output of the present invention; After interweaving, puts into data bit data bit location.Interweaving of data bit can be selected multiple interleaving mode; The synthetic whole back systematic code grouping output that interweaves.
Therefore, a kind of bit uniformly-inserted parallel cascaded code interleaving device of the present invention which comprises at least as lower device: first device, the code stream of reception certain-length packet; Second device is used for determining that code stream inserts the position of bit, and distinguishes data bit and insert bit.In the 103 interleaver inside of Fig. 1, shown in Fig. 4,6,401 will import and be divided into known bits and data bit two parts among the figure, interweave in 402 and 403 respectively, merge output according to inserting rule in 404 then.If block length is 100, the ratio of inserting bit and information bit is 1/9, inserts bit before interweaving and is in position 1,11,21,31 ..., 91, the position, back that then interweaves is defined as 5,15,25 ..., 95, so evenly branch inserts bit, and before and after interweaving maximum change in location is arranged.First interlaced device, the insertion bit that is used to interweave, and the insertion bit after will interweaving is according to interleaved order, back place, fixed position at interval successively interweaves; According to the principle that interleaver interweaves with largest random, first interlaced device adopts the random interleaving method to interweave, or other interleaving mode interweaves.First interlaced device will insert bit and be uniformly-spaced to insert evenly distributedly, and the fixed position of inserting is insertion bit distance centre position before interweaving, and this distance is a ultimate range, can effectively increase the distance of code word.As shown in Figure 6.Insert bit and exchange mutually, adopt at random or specific switching method, the centre position before the fixed position of inserting interleaver then successively, fixed position are chosen in and interweave.If block length is 100, the ratio of inserting bit and information bit is 1/9, insert bit before interweaving and be in position 1,11,21,31,, 91, the position, back that then interweaves is defined as 5,15,25 ..., 95, so evenly branch inserts bit, and maximum change in location is arranged before and after interweaving, and make the decoder 203 among Fig. 2 also can make full use of the energy that inserts bit, improve its decoding performance, make the decoding performance of 201 among Fig. 2 and 203 two decoders reach consistent, make full use of the resource of decoder.
Second interlaced device is used for the interleaving data bit, and puts into data bit location after data bit interweaved.Synthesizer is used for data bit after interweaving respectively and the output of the synthetic grouping of insertion bit code stream.
Interleaver among Fig. 2 and deinterleaver adopt same procedure shown in Figure 3, and just data are through the soft decision signal after the demodulation.Information bit can adopt deinterleaving method arbitrarily, is filled into remaining position after interweaving.
Fig. 7 is that interleaver of the present invention is 800 in block length, and the decoder iterations is under 12 conditions, adopts TC and traditional TC of IB interleaver, and the performance of inserting bit TC (do not adopt the IB interleaver, adopt random interleaver) compares.As can be seen from Figure, adopt the insertion bit TC effect of IB interleaver best, under Gaussian channel, improve more than 1.2～1.5dB with the performance of the other two kinds of parallel cascade codes that do not adopt this interleaver.
The present invention has improved the decoding performance of parallel cascade codes, and uniform distribution insertion bit can improve decoding performance to greatest extent in interleaver.Adopting the shortcoming of random interleaver in inserting bit TC is the known bits of uniform distribution in first encoder, through behind the random interleaving, has upset the order of inserting bit before second encoder, has produced the problem of unequal error protection.At first interleaver is divided into two parts, information bit part and known bits part are inserted bit and are all uniformly-spaced filled, so the information bit around the insertion bit can make full use of the high energy of known bits, improve the reliability of its decoding.And in the grouping before and after the interleaver, there is certain difference the position of inserting bit, increases the effect of inserting bit.Insert the position of bit in interleaver and will satisfy even distribution, then in second decoder, can make full use of the energy that inserts bit when information bit is deciphered.
Claims (10)
1, a kind of bit uniformly-inserted parallel cascaded code interleaving method is characterized in that: which comprises at least following steps:
Step 1: before interweaving, determine that each inserts the position of bit in the code stream of certain-length packet;
Step 2:, data bit in the code stream and insertion bit are separated in interleaver inside;
Step 3: respectively data bit and insertion bit are interweaved;
Step 4: the insertion bit after will interweaving is according to interleaved order, and back place, fixed position at interval successively interweaves;
Step 5: put into data bit location after data bit interweaves;
Step 6: synthesis system sign indicating number grouping output.
2, bit uniformly-inserted parallel cascaded code interleaving method according to claim 1 is characterized in that: interweaving of bit be random interleaving for inserting in the described step 2.
3, bit uniformly-inserted parallel cascaded code interleaving method according to claim 1 is characterized in that: insert bit in the described step 3 for uniformly-spaced inserting evenly distributedly.
4, bit uniformly-inserted parallel cascaded code interleaving method according to claim 1 is characterized in that: described fixed position is for inserting the bit distance centre position before interweaving.
5, bit uniformly-inserted parallel cascaded code interleaving method according to claim 4 is characterized in that: inserting bit distance before described interweaving is ultimate range.
6, a kind of bit uniformly-inserted parallel cascaded code interleaving device is characterized in that: which comprises at least as lower device:
First device, the code stream of reception certain-length packet;
Second device is used for determining that code stream inserts the position of bit, and distinguishes data bit and insert bit;
First interlaced device, the insertion bit that is used to interweave, and the insertion bit after will interweaving is according to interleaved order, back place, fixed position at interval successively interweaves;
Second interlaced device is used for the interleaving data bit, and puts into data bit location after data bit interweaved;
Synthesizer is used for data bit after interweaving respectively and the output of the synthetic grouping of insertion bit code stream.
7, bit uniformly-inserted parallel cascaded code interleaving device according to claim 1 is characterized in that: described first interlaced device adopts the random interleaving method to interweave.
8, bit uniformly-inserted parallel cascaded code interleaving device according to claim 1 is characterized in that: described first interlaced device will insert bit for uniformly-spaced inserting evenly distributedly.
9, bit uniformly-inserted parallel cascaded code interleaving device according to claim 1 is characterized in that: described first interlaced device is put into the fixed position of inserting bit and is insertion bit distance centre position before interweaving.
10, bit uniformly-inserted parallel cascaded code interleaving device according to claim 1 is characterized in that: inserting bit distance before described interweaving is ultimate range.
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| CN101291313B (en) * | 2007-04-19 | 2012-01-11 | 华为技术有限公司 | Wireless signal transmitting method, system and mobile station |
| CN102427397A (en) * | 2011-11-16 | 2012-04-25 | 东南大学 | Construction and decoding method of space-frequency-domain 2-dimensional bar code |
| CN101447960B (en) * | 2007-11-28 | 2012-08-29 | 华为技术有限公司 | Interlayer modulation method, device, orthogonal frequency division multiple access method and transmitter |
| CN104811410A (en) * | 2014-01-26 | 2015-07-29 | 上海数字电视国家工程研究中心有限公司 | Construction method, transmitting method and demodulation method of physical frames |
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| JP2002522943A (en) * | 1998-08-06 | 2002-07-23 | サムスン エレクトロニクス カンパニー リミテッド | Apparatus and method for channel coding / decoding in communication system |
| EP1048114B1 (en) * | 1998-08-20 | 2006-06-07 | Samsung Electronics Co., Ltd. | Device and method for inserting previously known bits in input stage of channel encoder |
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| CN101291313B (en) * | 2007-04-19 | 2012-01-11 | 华为技术有限公司 | Wireless signal transmitting method, system and mobile station |
| CN101447960B (en) * | 2007-11-28 | 2012-08-29 | 华为技术有限公司 | Interlayer modulation method, device, orthogonal frequency division multiple access method and transmitter |
| CN102427397A (en) * | 2011-11-16 | 2012-04-25 | 东南大学 | Construction and decoding method of space-frequency-domain 2-dimensional bar code |
| CN102427397B (en) * | 2011-11-16 | 2014-04-16 | 东南大学 | Construction and decoding method of space-frequency-domain 2-dimensional bar code |
| CN104811410A (en) * | 2014-01-26 | 2015-07-29 | 上海数字电视国家工程研究中心有限公司 | Construction method, transmitting method and demodulation method of physical frames |
| CN104811410B (en) * | 2014-01-26 | 2018-05-04 | 上海数字电视国家工程研究中心有限公司 | Construction method, sending method and the demodulation method of physical frame |
| WO2019062829A1 (en) * | 2017-09-30 | 2019-04-04 | 电信科学技术研究院有限公司 | Information interleaving method, information deinterleaving method, and related device |
| CN109600195A (en) * | 2017-09-30 | 2019-04-09 | 电信科学技术研究院 | A kind of information deinterleaving method, information de-interweaving method and relevant apparatus |
| CN109600195B (en) * | 2017-09-30 | 2020-09-25 | 电信科学技术研究院 | Information interleaving method, information de-interleaving method and related device |
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