CN101075812A - Method for constructing system low-density code with parallel cascade - Google Patents
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Abstract
本发明并行级联结构的系统形式低密度码的构造方法,特征是根据交换矩阵H1′与初始矩阵H1之间的列重相关性设计一个相关性最小的交织器;利用该交织器将两个系统形式低密度码的编码器并行级联起来作为编码器;利用该设计的交织器和对应的解交织器将两个系统形式低密度码的解码器串联起来作为解码器;即构造出编码复杂度低而性能较好的并行级联结构的系统形式低密度码。本发明方法中设计的交织器为编码序列引入了更多的校验关系,因此性能比系统形式低密度码有较大的提升;同时由于并行级联操作不会破坏用于级联的系统形式矩阵的结构特点,所构造出的并行级联结构的系统形式低密度码最大程度上保留了系统形式低密度码结构简单、编码复杂度低的优点。
The construction method of the system form low-density code of the parallel concatenation structure of the present invention is characterized in that an interleaver with minimum correlation is designed according to the column re-correlation between the exchange matrix H 1 ' and the initial matrix H 1 ; utilize this interleaver to The encoders of two systematic low-density codes are connected in parallel as an encoder; the designed interleaver and the corresponding deinterleaver are used to connect the decoders of two systematic low-density codes in series as a decoder; that is, the A low-density code in the form of a parallel cascaded structure with low coding complexity and good performance. The interleaver designed in the method of the present invention introduces more check relations for the coding sequence, so the performance is greatly improved compared with the low-density code in the system form; at the same time, the system form used for the concatenation will not be destroyed due to the parallel concatenation operation Due to the structural characteristics of the matrix, the system-form low-density code with a parallel cascade structure is constructed to the greatest extent retaining the advantages of the system-form low-density code with simple structure and low coding complexity.
Description
技术领域:Technical field:
本发明属于信道编解码技术领域,特别涉及并行级联结构的系统形式低密度码的构造方法。The invention belongs to the technical field of channel coding and decoding, and in particular relates to a method for constructing a systematic low-density code with a parallel cascade structure.
背景技术:Background technique:
低密度码(LDPC Codes)技术被普遍认为是第四代移动通信系统中的重要技术。Low-density codes (LDPC Codes) technology is generally considered to be an important technology in the fourth generation mobile communication system.
美国《无线电工程师学会学报(信息理论期刊)》(IRE Transactions on InformationTheory,vol.IT-8,NO.1,p21-28,January,1962)首先提出了LDPC码的概念,文中对LDPC码的各项特性进行了分析,但是并没有给出一种固定的构造方法。这是因为LDPC码的构造方法具有很大的灵活性。普通LDPC码的编码复杂度很高,主要是因为在LDPC码编码过程中涉及的矩阵乘法运算和矩阵存储都很难简化。美国《国际电子与电气工程师协会消费电子学报(电路与系统国际座谈会)》(IEEE International Symposium on Circuitsand Systems,vol.2,p26-29,May,2002)提出了一种具有系统形式结构的LDPC码,其校验矩阵是一个标准的系统形式矩阵,因此编码过程可以直接利用校验矩阵完成,又由于该校验矩阵是一个稀疏矩阵,所以编码的复杂度大大降低。但由于其校验矩阵中含有大量列重为1的列,影响了该LDPC码的纠错性能,因此该方法构造出的LDPC码性能较差。The United States "Journal of the Institute of Radio Engineers (Information Theory Journal)" (IRE Transactions on Information Theory, vol.IT-8, NO.1, p21-28, January, 1962) first proposed the concept of LDPC codes. Item characteristics are analyzed, but a fixed construction method is not given. This is because the construction method of the LDPC code has great flexibility. The encoding complexity of ordinary LDPC codes is very high, mainly because the matrix multiplication operation and matrix storage involved in the encoding process of LDPC codes are difficult to simplify. The United States "International Institute of Electronics and Electrical Engineers Consumer Electronics Journal (International Symposium on Circuits and Systems)" (IEEE International Symposium on Circuits and Systems, vol.2, p26-29, May, 2002) proposed a LDPC with a system form structure code, its parity check matrix is a standard system form matrix, so the encoding process can be completed directly using the parity check matrix, and because the parity check matrix is a sparse matrix, the complexity of encoding is greatly reduced. However, because the check matrix contains a large number of columns with a column weight of 1, which affects the error correction performance of the LDPC code, the performance of the LDPC code constructed by this method is poor.
发明内容:Invention content:
本发明提出一种并行级联结构的系统形式低密度码的构造方法,以构造一类复杂度较低并且性能较好的低密度码,能在保留系统形式低密度码结构简单、编码复杂度低的优点的同时使纠错性能有较大的提升。The present invention proposes a method for constructing a system-form low-density code with a parallel cascade structure to construct a class of low-density codes with lower complexity and better performance, which can maintain the system-form low-density code with simple structure and high coding complexity. The advantage of low error correction performance is greatly improved at the same time.
本发明并行级联结构的系统形式低密度码的构造方法,包括:构造一个系统形式低密度码和一个交织器,该系统形式低密度码的校验矩阵H的大小为m×n,其中m<n,校验矩阵H的左边是一个大小为m×(n-m)的初始矩阵H1,右边是一个大小为m×m的单位矩阵I;The method for constructing the systematic form low-density code of the parallel concatenated structure of the present invention comprises: constructing a systematic form low-density code and an interleaver, the size of the check matrix H of the systematic form low-density code is m×n, wherein m <n, the left side of the check matrix H is an initial matrix H 1 with a size of m×(nm), and the right side is an identity matrix I with a size of m×m;
其特征在于:It is characterized by:
采用如下方式设计出使得两路校验序列之间的相关性最小的交织器:首先对初始矩阵H1进行列交换,然后通过下式计算经过列交换后的交换矩阵H1′与初始矩阵H1之间的列重相关性:The following method is used to design an interleaver that minimizes the correlation between the two check sequences: first perform column exchange on the initial matrix H 1 , and then calculate the column exchanged exchange matrix H 1 ′ and the initial matrix H by the following formula Column-heavy correlation between 1 :
其中,m和n分别表示校验矩阵H的行数和列数,Ci表示交换矩阵H1′的第i列与初始矩阵H1的第i列之间的列重相关系数,W表示交换矩阵H1′与初始矩阵H1的列重相关系数;最后将W最小的情况下所对应的列交换顺序作为交织器的交织顺序;Among them, m and n respectively represent the number of rows and columns of the check matrix H, C i represents the column re-correlation coefficient between the i-th column of the exchange matrix H 1 ' and the i-th column of the initial matrix H 1 , and W represents the exchange The column re-correlation coefficient of matrix H 1 ' and initial matrix H 1 ; Finally, the column exchange order corresponding to the case where W is the smallest is used as the interleaving order of the interleaver;
利用该交织器将两个构造的系统形式低密度码的编码器并行级联起来作为编码器,所述用于并行级联的两个编码器分别为第一编码器和第二编码器,这两个编码器完全相同;对原始编码序列进行交织处理后得到交织编码序列,然后分别利用第一编码器和第二编码器同时对原始编码序列和交织编码序列进行编码,分别得到原始校验序列和交织校验序列;最后按原始编码序列、原始校验序列和交织校验序列的顺序将这三个序列组合起来作为一个完整的编码帧;Utilize this interleaver to concatenate the encoders of two structured systematic low-density codes in parallel as encoders, and the two encoders used for parallel concatenation are respectively the first encoder and the second encoder, which The two encoders are exactly the same; the original coded sequence is interleaved to obtain the interleaved coded sequence, and then the original coded sequence and the interleaved coded sequence are encoded by the first encoder and the second encoder at the same time, respectively, to obtain the original check sequence and interleaved check sequence; finally, these three sequences are combined in the order of the original coded sequence, original check sequence and interleaved check sequence as a complete coded frame;
再利用该交织器和对应的解交织器将两个系统形式低密度码的解码器串联起来作为解码器,所述用于串联的两个解码器分别为第一解码器和第二解码器,这两个解码器采用相同或不同的常规低密度码解码算法,包括和积解码算法、最小和解码算法或者后验概率解码算法;先利用第一解码器对原始编码序列的置信度和原始校验序列的置信度进行解码,然后将第一解码器输出的原始编码序列的置信度经过交织器处理后得到交织编码序列的置信度,再利用第二解码器对交织编码序列的置信度和交织校验序列的置信度进行解码,再将第二解码器输出的交织编码序列的置信度通过解交织器处理后得到更新后的原始编码序列的置信度,然后按这个流程在两个解码器之间进行迭代,一直到满足解码终止条件为止,即构造出编码复杂度较低而性能较好的并行级联结构的系统形式低密度码。Utilizing the interleaver and the corresponding deinterleaver to connect the decoders of the two systematic low-density codes in series as a decoder, the two decoders used in series are respectively the first decoder and the second decoder, These two decoders use the same or different conventional low-density code decoding algorithms, including sum product decoding algorithm, minimum sum decoding algorithm or posterior probability decoding algorithm; The confidence degree of the test sequence is decoded, and then the confidence degree of the original coded sequence output by the first decoder is processed by the interleaver to obtain the confidence degree of the interleaved coded sequence, and then the confidence degree of the interleaved coded sequence and the interleaved coded sequence are obtained by the second decoder. The confidence degree of the check sequence is decoded, and then the confidence degree of the interleaved coded sequence output by the second decoder is processed by the deinterleaver to obtain the confidence degree of the updated original coded sequence, and then according to this process between the two decoders Iterate until the decoding termination condition is satisfied, that is, construct a system form low-density code with a parallel cascaded structure with low coding complexity and good performance.
系统形式低密度码的优点是其校验矩阵的系统形式结构,非常有助于降低编码复杂度,而缺点则是纠错性能较差;本发明构造方法是将两个系统形式低密度码通过特殊设计的交织器并行级联起来构造一种并行级联结构的系统形式低密度码,由于并行级联操作完全不会影响用于级联的校验矩阵的系统形式结构,因此本发明构造的低密度码具有和系统形式低密度码相当的简单结构和低编码复杂度。同时由于并行级联结构中的交织器为编码序列引入了更多的约束关系,因此本发明构造的低密度码的性能比现有系统形式低密度码的性能有较大提升。The advantage of the systematic form low-density code is that the systematic form structure of its parity check matrix is helpful to reduce coding complexity very much, and the shortcoming is that error correction performance is relatively poor; The construction method of the present invention is to pass two systematic form low-density codes through Specially designed interleavers are concatenated in parallel to construct a systematic form low-density code with a parallel concatenated structure. Since the parallel concatenated operation will not affect the systematic form structure of the parity check matrix used for concatenation, the present invention constructs Low-density codes have a simple structure and low coding complexity comparable to systematic low-density codes. At the same time, because the interleaver in the parallel cascaded structure introduces more constraint relations to the coding sequence, the performance of the low-density code constructed by the present invention is greatly improved compared with that of the existing system form low-density code.
本发明方法构造出的并行级联结构的系统形式低密度码,拥有与现有一般系统形式低密度码相当的低编码复杂度,而具有更加优异的纠错性能,因此比现有一般系统形式低密度码具有更大的实际应用价值。The system form low-density code of the parallel cascade structure constructed by the method of the present invention has low coding complexity equivalent to the existing general system form low-density code, and has more excellent error correction performance, so it is better than the existing general system form Low-density codes have greater practical application value.
附图说明:Description of drawings:
图1是大小为675×1800的系统形式矩阵H的结构示意图。Figure 1 is a schematic diagram of the structure of a system form matrix H with a size of 675×1800.
图2是并行级联结构的系统形式低密度码的编码器结构示意图。Fig. 2 is a schematic structural diagram of an encoder of a systematic low-density code with a parallel cascaded structure.
图3是并行级联结构的系统形式低密度码的解码器结构示意图。Fig. 3 is a schematic diagram of the decoder structure of the system form low-density code of the parallel cascade structure.
图4是分别采用相关交织器和不相关交织器的并行级联结构的系统形式低密度码的性能仿真比较曲线。Fig. 4 is a performance simulation comparison curve of a system form low-density code using a parallel cascaded structure of a correlated interleaver and an uncorrelated interleaver respectively.
图5是并行级联结构的系统形式低密度码和系统形式低密度码的性能仿真比较曲线。Fig. 5 is a performance simulation comparison curve of the system-form low-density code and the system-form low-density code of the parallel cascade structure.
具体实施方式:Detailed ways:
实施例1:Example 1:
一、构造大小为675×1800的系统形式矩阵H作为低密度码的校验矩阵:1. Construct a systematic form matrix H with a size of 675×1800 as the check matrix of the low-density code:
构造一个大小为675×1800的系统形式矩阵H,该矩阵左边是一个大小为675×1125的初始矩阵H1,右边是一个大小为675×675的单位矩阵I;以系统形式矩阵H作为低密度码的校验矩阵,能够构造一组系统形式低密度码。图1所示的矩阵即为本实施例中构造的大小为675×1800的系统形式矩阵H;图中的斜线实际上是由一系列连续的点所构成,这些点表示系统形式矩阵H中对应位置上的元素是1,空白则表示对应位置上的元素是0;图中左半部分的短斜线代表初始矩阵H1中的元素1,由于元素1的随机分布性导致了不同短斜线之间的长度差异,右半部分的长斜线表示单位矩阵I中对角线上的元素1。Construct a system form matrix H with a size of 675×1800. The left side of the matrix is an initial matrix H 1 with a size of 675×1125, and the right side is an identity matrix I with a size of 675×675; the system form matrix H is used as a low-density The check matrix of the code can construct a set of low-density codes in systematic form. The matrix shown in Figure 1 is the system form matrix H with a size of 675×1800 constructed in this embodiment; the oblique lines in the figure are actually composed of a series of continuous points, and these points represent the system form matrix H The element at the corresponding position is 1, and blank means that the element at the corresponding position is 0; the short oblique line in the left half of the figure represents
系统形式矩阵的大小可以根据实际需求设计,只须保证其系统形式即可。本实施例中设定其大小为675×1800只是一个任意选取的例子。若构造出的系统形式矩阵的大小是m×n,其中m<n,则本发明方法构造出的并行级联结构的系统形式低密度码的码长是n+m,编码速率是(n-m)/(n+m)。The size of the system form matrix can be designed according to actual needs, as long as its system form is guaranteed. Setting its size to 675×1800 in this embodiment is just an example of random selection. If the size of the systematic form matrix constructed is m×n, wherein m<n, then the code length of the systematic form low-density code of the parallel concatenated structure constructed by the method of the present invention is n+m, and the coding rate is (n-m) /(n+m).
二、设计相关性最小的交织器2. Design the interleaver with the least correlation
为了能尽可能引入更多的约束关系,必须根据初始矩阵H1的列重分布来设计相关性最小的交织器。In order to introduce as many constraint relationships as possible, an interleaver with the least correlation must be designed according to the column redistribution of the initial matrix H 1 .
交织器操作实际就是初始矩阵H1的列交换,通过列交换得到的交换矩阵H1′与初始矩阵H1之间的列重相关性可以利用式(1)来计算,其中W越小说明这两个矩阵之间的列重相关性越小,对应的交织器的相关性也越小,满足W=0的交织器是不相关交织器。交织器的相关性越小,两路校验序列之间的相关性就越小,性能提升也就越明显。The operation of the interleaver is actually the column exchange of the initial matrix H 1 , and the column re-correlation between the exchange matrix H 1 ′ obtained through column exchange and the initial matrix H 1 can be calculated by using formula (1), where the smaller W indicates that this The smaller the column re-correlation between two matrices is, the smaller the correlation of the corresponding interleavers is, and the interleaver satisfying W=0 is an uncorrelated interleaver. The smaller the correlation of the interleaver, the smaller the correlation between the two check sequences, and the more obvious the performance improvement.
为了更形象地说明这个问题,本实施例中特意选用了一个W=3375的相关交织器和W=0的不相关交织器进行比较。图4给出了分别采用相关交织器和不相关交织器的并行级联结构的系统形式低密度码的性能仿真比较曲线:相关交织器性能曲线b表示采用了W=3375的相关交织器的并行级联结构的系统形式低密度码的性能;不相关交织器性能曲线c表示采用了W=0的不相关交织器的并行级联结构的系统形式低密度码的性能。从仿真比较结果可以看到采用不相关交织器的低密度码比采用相关交织器的低密度码有0.4dB左右的性能提升。In order to illustrate this problem more vividly, in this embodiment, a correlated interleaver with W=3375 and an uncorrelated interleaver with W=0 are deliberately selected for comparison. Fig. 4 has provided the performance emulation comparison curve of the system form low-density code of the parallel concatenated structure adopting correlative interleaver and non-correlative interleaver respectively: Correlation interleaver performance curve b has adopted the parallel interleaver of W=3375 Performance of systematic low-density codes with concatenated structure; uncorrelated interleaver performance curve c represents the performance of systematic low-density codes with parallel concatenated structure of non-correlated interleavers with W=0. From the simulation comparison results, it can be seen that the performance of the low-density code using the uncorrelated interleaver is about 0.4dB higher than that of the low-density code using the correlated interleaver.
需要说明的是,对于不同结构特点的初始矩阵H1,根据式(1)设计的交织器会有很大差异,对于有的初始矩阵H1可能无法设计出不相关交织器,而对于有的则可能设计出多个不同的不相关交织器,因此实际设计时只需选取W最小的交织器即可。针对本实施例中构造的初始矩阵H1可以设计出多个不相关交织器,在此只是任意选用了其中一个。It should be noted that for initial matrices H 1 with different structural characteristics, the interleavers designed according to formula (1) will be very different, for some initial matrices H 1 it may not be possible to design an uncorrelated interleaver, and for some Then it is possible to design multiple different uncorrelated interleavers, so it is only necessary to select the interleaver with the smallest W during actual design. Multiple irrelevant interleavers can be designed for the initial matrix H1 constructed in this embodiment, and only one of them is selected arbitrarily here.
三、构造并行级联结构的系统形式低密度码的编码器3. Construct a system-form low-density code encoder with a parallel cascaded structure
利用上述设计的交织器将两个相同的系统形式低密度码的编码器并行级联起来,就得到本发明方法构造的并行级联结构的系统形式低密度码的编码器。By using the interleaver designed above to connect two identical encoders of systematic low-density codes in parallel, the encoder of systematic low-density codes with parallel cascaded structure constructed by the method of the present invention is obtained.
图2给出了该编码器的结构示意图。如图2中所示,本发明中的编码器的工作步骤为:Figure 2 shows the structure diagram of the encoder. As shown in Figure 2, the working steps of encoder among the present invention are:
(1)、由交织模块A对原始编码序列1进行交织处理后得到交织编码序列2;(1), the original coded
(2)、由第一编码模块B对原始编码序列1进行编码处理得到原始校验序列3,由第二编码模块C对交织编码序列2进行编码处理后得到交织校验序列4;(2), the first encoding module B encodes the
(3)、按原始编码序列1、原始校验序列3和交织校验序列4的顺序组合起来,即为最终的编码序列。(3) The
四、构造并行级联结构的系统形式低密度码的解码器4. Constructing a system-form low-density code decoder with a parallel cascaded structure
利用上述设计的交织器和对应的解交织器把两个系统形式低密度码的解码器串联起来,就得到本发明方法构造的并行级联结构的系统形式低密度码的解码器。Using the interleaver designed above and the corresponding de-interleaver to connect two decoders of systematic low-density codes in series, a decoder of systematic low-density codes with a parallel concatenated structure constructed by the method of the present invention is obtained.
图3给出了该解码器的结构示意图,图中的P1f表示原始编码序列1的信道后验概率;P3f表示原始校验序列3的信道后验概率;P4f表示交织校验序列4的信道后验概率;P1e和P2e分别表示原始编码序列1和交织编码序列2的解码输入先验概率;P1和P2分别表示原始编码序列1和交织编码序列2的解码输出后验概率。如图3中所示,本发明中的解码器的工作步骤为:Figure 3 shows the schematic diagram of the structure of the decoder, P 1f in the figure represents the channel posterior probability of the
(1)、由第一解码模块D对P1f和P3f进行解码;(1), decode P 1f and P 3f by the first decoding module D;
(2)、由第一判断模块C判断第一解码模块D的解码结果是否正确,如果正确,则把原始编码序列1的解码输出后验概率P1送至硬判决模块H,并由该模块输出最终解码结果,否则送至交织模块E进行交织处理;(2), whether the decoding result of the first decoding module D is judged by the first judging module C is correct, if correct, then the decoding output posterior probability P1 of the original
(3)、由第二解码模块F对交织模块E的交织结果P2e和P4f进行解码;(3), the interleaving results P 2e and P 4f of the interleaving module E are decoded by the second decoding module F;
(4)、由第二判断模块I检查第二解码模块F的解码结果是否正确,如果正确,则把交织编码序列2的解码输出后验概率P2送至硬判决模块H,并由该模块输出最终解码结果,否则送至解交织模块G进行解交织处理;(4), whether the decoding result of the second decoding module F is checked by the
(5)、由第一解码模块D对解交织模块G的解交织结果P1e和步骤(1)中第一解码模块D解码得到的原始校验序列的解码后验概率进行解码;(5), the deinterleaving result P 1e of the deinterleaving module G and the decoding a posteriori probability of the original check sequence that the first decoding module D decodes in step (1) is decoded by the first decoding module D;
(6)、重复步骤(2)-(5)直至解码结束。(6) Steps (2)-(5) are repeated until the decoding ends.
本实施例中的第一解码模块D和第二解码模块F均采用了和积解码算法,其解码过程如下:Both the first decoding module D and the second decoding module F in this embodiment have adopted the sum-product decoding algorithm, and the decoding process is as follows:
设系统采用二进制相移键控(BPSK)调制方式,信道是加性高斯白噪声信道(AWGN)。如果待发送的编码序列是x=(x1,x2,……xN),其中N是编码序列的长度,那么接收机接收的数据可以写作:y=(y1,y2,……yN),其中:Suppose the system adopts binary phase-shift keying (BPSK) modulation mode, and the channel is an additive Gaussian white noise channel (AWGN). If the coded sequence to be sent is x=(x 1 , x 2 ,...x N ), where N is the length of the coded sequence, then the data received by the receiver can be written as: y=(y 1 , y 2 ,... y N ), where:
yi=si+ni i=1,2,…Ny i =s i +n i i=1, 2,...N
si=2xi-1 i=1,2,…N(1)s i =2x i -1 i=1, 2, ... N(1)
其中ni是均值为零,方差是N0/2的高斯白噪声。where n i is Gaussian white noise with zero mean and N 0 /2 variance.
为了便于说明,先定义以下几个概念:For the sake of illustration, the following concepts are first defined:
N(m):{n:Hmn′=1},表示校验矩阵H′第m行中所有值为1的列,N(m)\n则表示N(m)中除去第n列以外的其他所有列。N(m): {n: H mn ′=1}, which means all columns with a value of 1 in the mth row of the parity check matrix H’, and N(m)\n means that except the nth column in N(m) All other columns of .
M(n):{m:Hmn′=1},表示校验矩阵H′第n列中所有值为1的行。M(n)\m则表示M(n)中除去第m行以外的其他所有行。M(n): {m: H mn ′=1}, indicating all rows with a value of 1 in the nth column of the parity check matrix H′. M(n)\m means all lines in M(n) except line m.
Lmn:表示从校验节点m传递给比特节点n的概率信息。L mn : represents the probability information transmitted from the check node m to the bit node n.
qmn:表示从比特节点n传递给校验节点m的概率信息。q mn : Indicates the probability information transmitted from bit node n to check node m.
qn:表示第n个比特的后验概率信息,也是解码硬判决输出的依据。q n : Indicates the posterior probability information of the nth bit, which is also the basis for decoding the hard decision output.
需要注意的是,这里涉及到的概率信息都是对数域的概率(Log-Likelihood Ratio,LLR),根据以上的定义,可以把和积解码算法简单归纳如下:It should be noted that the probability information involved here is the probability of the logarithmic domain (Log-Likelihood Ratio, LLR). According to the above definition, the sum-product decoding algorithm can be simply summarized as follows:
初始化,即根据接收信号和信道信息计算初始后验概率:Initialization, that is, calculate the initial posterior probability according to the received signal and channel information:
横向迭代,即根据qmn计算Lmn:Horizontal iteration, that is, calculate L mn according to q mn :
其中αmn=sign(qmn)where α mn =sign(q mn )
βmn=|qmn|β mn = |q mn |
纵向迭代,即根据Lmn计算qmn:Vertical iteration, that is, calculate q mn according to L mn :
判决输出以及终止条件:Judgment output and termination conditions:
当满足H′x′=0或者迭代次数达到上限时,终止解码过程并且输出解码结果x′=(x′1,x′2,……x′N),否则继续迭代过程。When H'x'=0 is satisfied or the number of iterations reaches the upper limit, the decoding process is terminated and the decoding result x'=(x' 1 , x' 2 , . . . x' N ) is output, otherwise the iterative process continues.
以上算法的详细介绍可参见美国《国际电子与电气工程师协会消费电子学报(信息理论期刊)》(IEEE Transactions on Information Theory,vol.45,NO.2,p399-431,March,1999)。The detailed introduction of the above algorithm can be found in the American "International Institute of Electronics and Electrical Engineers Consumer Electronics Journal (Information Theory Journal)" (IEEE Transactions on Information Theory, vol.45, NO.2, p399-431, March, 1999).
第一解码模块D和第二解码模块F还可以采用最小和解码算法或者后验概率解码算法,它们可以分别采用相同或不同的解码算法,所述的最小和解码算法和后验概率解码算法可参见美国《国际电子与电气工程师协会消费电子学报(通信期刊)》(IEEETransactions on Communications,vol.47,NO.5,p673-680,May,1999)和美国《国际电子与电气工程师协会消费电子学报(通信期刊)》(IEEE Transactions on Communications,vol.53,NO.8,p1288-1298,August,2005)。The first decoding module D and the second decoding module F can also use a minimum sum decoding algorithm or a posterior probability decoding algorithm, and they can respectively adopt the same or different decoding algorithms, and the minimum sum decoding algorithm and the posterior probability decoding algorithm can be See the US "International Institute of Electronics and Electrical Engineers Consumer Electronics Journal (Communication Journal)" (IEEETransactions on Communications, vol.47, NO.5, p673-680, May, 1999) and the US "International Institute of Electronics and Electrical Engineers Consumer Electronics Journal" (Communication Journal)" (IEEE Transactions on Communications, vol.53, NO.8, p1288-1298, August, 2005).
五、仿真性能5. Simulation performance
利用软件进行性能仿真,在加性高斯白噪声(AWGN)信道条件下和二进制相移键控(BPSK)调制方式下,比较本发明方法构造的并行级联结构的系统形式低密度码和系统形式矩阵H所对应的系统形式低密度码的性能。Utilize software to carry out performance emulation, under additive Gaussian white noise (AWGN) channel condition and binary phase-shift keying (BPSK) modulation mode, compare the system form low-density code and system form of the parallel concatenated structure that the method of the present invention constructs Performance of low-density codes in systematic form corresponding to matrix H.
图5给出了并行级联结构的系统形式低密度码和系统形式低密度码的性能仿真比较曲线:性能较差曲线d表示码长为1125、码率为0.4的系统形式低密度码的性能,性能较好曲线e表示用本发明方法构造的码长2475、码率0.455的并行级联结构的系统形式低密度码的性能。从图5中的仿真结果可以看到,本发明方法构造的并行级联结构的系统形式低密度码性能比系统形式低密度码的性能高大约1.5dB。Figure 5 shows the performance simulation comparison curves of the system-form low-density code and the system-form low-density code of the parallel concatenated structure: the poor performance curve d represents the performance of the system-form low-density code with a code length of 1125 and a code rate of 0.4 , better performance. Curve e represents the performance of the system form low-density code with a code length of 2475 and a code rate of 0.455 constructed by the method of the present invention. It can be seen from the simulation results in FIG. 5 that the performance of the systematic low-density code with the parallel cascaded structure constructed by the method of the present invention is about 1.5 dB higher than that of the systematic low-density code.
六、运算复杂度比较6. Comparison of Computational Complexity
由于并行级联结构中的两个系统形式矩阵是完全一样的,因此并不会导致存储空间的增加。虽然并行级联结构的系统形式低密度码的编码运算量是原系统形式低密度码的两倍,但是由于系统形式低密度码本身的编码运算量非常低,因此并行级联结构的系统形式低密度码的编码运算量相对普通的低密度码而言依然很低。码长为1125、码率0.4的系统形式低密度码的模2运算量是3375次,存储空间需要33750比特;码长为2475、码率0.455的并行级联结构的系统形式低密度码的模2运算量是6750次,存储空间需要33750比特。Since the two system form matrices in the parallel cascaded structure are exactly the same, it does not lead to an increase in storage space. Although the encoding operation amount of the systematic low-density code of the parallel cascaded structure is twice that of the original systematic low-density code, but because the encoding operation amount of the systematic low-density code itself is very low, the systematic form of the parallel cascaded structure is low. Compared with ordinary low-density codes, the encoding calculation amount of density codes is still very low. The
本发明方法利用设计的交织器将两个系统形式低密度码并行级联起来,为编码序列引入了更多的校验关系,因此性能比系统形式低密度码有较大提升;同时由于并行级联操作不会破坏用于级联的系统形式矩阵的结构,所以构造出的并行级联结构的系统形式低密度码从最大程度上保留了系统形式低密度码结构简单,编码复杂度低的优点,具有非常利于硬件实现的简单结构。本发明所构造的并行级联结构的系统形式低密度码很适合应用在资源较为紧张而对纠错性能又有一定要求的系统中。The method of the present invention utilizes the designed interleaver to concatenate two systematic form low-density codes in parallel, and introduces more verification relations for the coding sequence, so the performance is greatly improved compared with the systematic form low-density code; The concatenation operation will not destroy the structure of the system form matrix used for concatenation, so the constructed system form low-density code with parallel concatenation structure retains the advantages of simple structure and low coding complexity of the system form low-density code to the greatest extent , has a simple structure that is very favorable for hardware implementation. The system-form low-density code with parallel cascading structure constructed by the invention is very suitable for application in systems with relatively tight resources and certain requirements for error correction performance.
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