CN101075812A - Method for constructing system low-density code with parallel cascade - Google Patents

Abstract

The method comprises: according to the column correlation between the switching matrix H1'and the initial matrix H1, designing an interleaver with least correlation; using said interleaver to parallel cascade the encoders of low density code in two system formations as encoder so as to construct a system formation low density code in parallel cascade structure, which has low encode complexity and better performance.

Description

A kind of building method of system form low-density code of parallel cascade structure

Technical field:

The invention belongs to the channel coding/decoding technical field, particularly the building method of the system form low-density code of parallel cascade structure.

Background technology:

Low-density code (LDPC Codes) technology is generally believed it is important technology in the 4th third-generation mobile communication system.

U.S.'s " Institute of Radio Engineers journal (information theory periodical) " (IRE Transactions on InformationTheory, vol.IT-8, NO.1, p21-28, January, 1962) at first proposed the notion of LDPC sign indicating number, the every characteristic to the LDPC sign indicating number in the literary composition is analyzed, but does not provide a kind of fixing building method.This is because the building method of LDPC sign indicating number has very big flexibility.The encoder complexity of common LDPC sign indicating number is very high, mainly is because matrix multiplication operation that relates in LDPC sign indicating number cataloged procedure and matrix stores all are difficult to simplify.U.S.'s " international electronics and The Institution of Electrical Engineers's consumer electronics journal (international forum of Circuits and Systems) " (IEEE International Symposium on Circuitsand Systems, vol.2, p26-29, May, 2002) a kind of LDPC sign indicating number with system form structure has been proposed, its check matrix is the system form matrix of a standard, therefore cataloged procedure can directly utilize check matrix to finish, again because this check matrix is a sparse matrix, so the complexity of coding reduces greatly.But owing to contain a large amount of column weights in its check matrix is 1 row, influenced the error-correcting performance of this LDPC sign indicating number, so the LDPC code performance that this method construct goes out is relatively poor.

Summary of the invention:

The present invention proposes a kind of building method of system form low-density code of parallel cascade structure, constructing the low-density code of the lower and better performances of a class complexity, can be simple in structure, make error-correcting performance that bigger lifting be arranged in the advantage that encoder complexity is low in retention system form low-density code.

The building method of the system form low-density code of parallel cascade structure of the present invention, comprise: construct a system form low-density code and an interleaver, the size of the check matrix H of this system form low-density code is m * n, m＜n wherein, the left side of check matrix H is that a size is the initial matrix H of m * (n-m) ₁, the right is the unit matrix I that a size is m * m;

It is characterized in that:

Design the interleaver of the correlation minimum that makes between the two-way verification sequence in the following way: at first to initial matrix H ₁Be listed as exchange, calculate through the switching matrix H after the row exchange by following formula then ₁' with initial matrix H ₁Between the column weight correlation:

$C_i=\underset{k=1}{\overset{m}{\mathrm{\&Sigma;}}}{H}_1(k,i){\&times;\mathrm{<figure-callout\; id="1"\; label="H"\; filenames="A20071002359400112.png"\; state="\{\{state\}\}">H</figure-callout>}}_1^{\&prime;}(k,i),1\&le;i\&le;n-m$

$W=\underset{i}{\mathrm{\&Sigma;}}{C}_i,1\&le;i\&le;n-m$ (1)

Wherein, m and n represent the line number and the columns of check matrix H, C respectively _iExpression switching matrix H ₁' i row and initial matrix H ₁I row between the column weight coefficient correlation, W represents switching matrix H ₁' with initial matrix H ₁The column weight coefficient correlation; At last under the situation with the W minimum pairing row exchange sequence as the interleaved order of interleaver;

Utilize this interleaver that the encoder parallel cascade of the system form low-density code of two structures is risen and be used as encoder, described two encoders that are used for parallel cascade are respectively first encoder and second encoder, and these two encoders are identical; The original coding sequence is carried out obtaining the interweaving encoding sequence after the interleaving treatment, utilize first encoder and second encoder simultaneously original coding sequence and interweaving encoding sequence to be encoded then respectively, obtain the original checksums sequence respectively and the verification sequence that interweaves; By the order of original coding sequence, original checksums sequence and the verification sequence that interweaves these three combined sequence are risen at last and be used as a complete coded frame;

Utilize this interleaver and corresponding deinterleaver that the decoder of two system form low-density codes is together in series as decoder again, described two decoders that are used to connect are respectively first decoder and second decoder, these two decoders adopt identical or different conventional low-density code decoding algorithm, comprise and long-pending decoding algorithm, minimum and decoding algorithm or Probability Decoding algorithm; Utilize first decoder that the confidence level of original coding sequence and the confidence level of original checksums sequence are decoded earlier, obtain the confidence level of interweaving encoding sequence after the confidence level of the original coding sequence that first decoder is exported is handled through interleaver then, utilize second decoder that the confidence level of interweaving encoding sequence and the confidence level of the verification sequence that interweaves are decoded again, the confidence level of the original coding sequence after obtaining upgrading after the confidence level of the interweaving encoding sequence that second decoder is exported is handled by deinterleaver again, between two decoders, carry out iteration by this flow process then, until satisfy till the decoding end condition, promptly construct the system form low-density code of the parallel cascade structure of the lower and better performances of encoder complexity.

The advantage of system form low-density code is the system form structure of its check matrix, helps very much to reduce encoder complexity, and shortcoming then is that error-correcting performance is relatively poor; Building method of the present invention is the system form low-density code of two system form low-density codes being got up to construct a kind of parallel cascade structure by the interleaver parallel cascade of particular design, because the parallel cascade operation can not influence the system form structure of the check matrix that is used for cascade fully, so the low-density code of the present invention's structure has simple structure suitable with the system form low-density code and low encoder complexity.Simultaneously because the interleaver in the parallel cascade structure is that coded sequence has been introduced more restriction relation, so the performance of the low-density code of the present invention's structure has a distinct increment than the performance of existing system form low-density code.

The system form low-density code of the parallel cascade structure that the inventive method constructs, have and the suitable low encoder complexity of existing General System form low-density code, and have excellent more error-correcting performance, therefore have bigger actual application value than existing General System form low-density code.

Description of drawings:

Fig. 1 is that size is the structural representation of 675 * 1800 system form matrix H.

Fig. 2 is the coder structure schematic diagram of the system form low-density code of parallel cascade structure.

Fig. 3 is the decoder architecture schematic diagram of the system form low-density code of parallel cascade structure.

Fig. 4 is the performance simulation comparison curves of system form low-density code that adopts the parallel cascade structure of relevant interleaver and uncorrelated interleaver respectively.

Fig. 5 is the performance simulation comparison curves of the system form low-density code and the system form low-density code of parallel cascade structure.

Embodiment:

Embodiment 1:

One, the structure size is 675 * 1800 the system form matrix H check matrix as low-density code:

Construct a size and be 675 * 1800 system form matrix H, this matrix left side is that a size is 675 * 1125 initial matrix H ₁, the right is that a size is 675 * 675 unit matrix I; With the check matrix of system form matrix H, can construct a group system form low-density code as low-density code.It is 675 * 1800 system form matrix H that matrix shown in Figure 1 is the size of constructing in the present embodiment; Oblique line among the figure is actually by a series of continuous points and is constituted, and the element in these some expression system form matrix H on the correspondence position is 1, and is blank then represent that the element on the correspondence position is 0; The virgule of left-half is represented initial matrix H among the figure ₁In element 1 because the random distribution of element 1 has caused the difference in length between the different virgules, the element 1 among the long oblique line representation unit matrix I of right half part on the diagonal.

The size of system form matrix can design according to the actual requirements, need only guarantee that its system form gets final product.Set its size in the present embodiment and be 675 * 1800 examples of choosing arbitrarily just.If the size of the system form matrix that constructs is m * n, m＜n wherein, then the code length of the system form low-density code of the parallel cascade structure that constructs of the inventive method is n+m, code rate is (n-m)/(n+m).

Two, the interleaver of design correlation minimum

In order to introduce more restriction relation as far as possible, must be according to initial matrix H ₁Column weight distribution design the interleaver of correlation minimum.

The interleaver operation is actual to be exactly initial matrix H ₁Row exchanges, the switching matrix H that obtains by the row exchange ₁' with initial matrix H ₁Between the column weight correlation can utilize formula (1) to calculate, wherein the column weight correlation between these two matrixes of the more little explanation of W is more little, the correlation of corresponding interleaver is also more little, the interleaver that satisfies W=0 is uncorrelated interleaver.The correlation of interleaver is more little, and the correlation between the two-way verification sequence is just more little, and performance boost is also just obvious more.

For this problem is described vividerly, specially selected for use the relevant interleaver of a W=3375 and the uncorrelated interleaver of W=0 to compare in the present embodiment.Fig. 4 has provided the performance simulation comparison curves of the system form low-density code of the parallel cascade structure that adopts relevant interleaver and uncorrelated interleaver respectively: relevant interleaver performance curve b has represented to adopt the performance of system form low-density code of parallel cascade structure of the relevant interleaver of W=3375; Uncorrelated interleaver performance curve c has represented to adopt the performance of system form low-density code of parallel cascade structure of the uncorrelated interleaver of W=0.Can see that from the emulation comparative result low-density code of the relevant interleaver of low-density code ratio employing that adopts uncorrelated interleaver has the performance boost about 0.4dB.

Need to prove, for the initial matrix H of different structure characteristics ₁, have very big-difference according to the interleaver of formula (1) design, for the initial matrix H that has ₁Possibly can't design uncorrelated interleaver, then may design a plurality of different uncorrelated interleavers for what have, so the interleaver that only need choose the W minimum during actual design gets final product.At the initial matrix H that constructs in the present embodiment ₁Can design a plurality of uncorrelated interleavers, just select one of them arbitrarily for use at this.

Three, the encoder of the system form low-density code of structure parallel cascade structure

Utilize the encoder parallel cascade of the interleaver of above-mentioned design, just obtain the encoder of system form low-density code of the parallel cascade structure of the inventive method structure two identical system form low-density codes.

Fig. 2 has provided the structural representation of this encoder.As shown in Figure 2, the job step of the encoder among the present invention is:

(1), by interleaving block A original coding sequence 1 is carried out obtaining interweaving encoding sequence 2 after the interleaving treatment;

(2), by the first coding module B original coding sequence 1 is carried out encoding process and obtains original checksums sequence 3, by the second coding module C interweaving encoding sequence 2 is carried out obtaining interweaving after the encoding process verification sequence 4;

(3), by the sequential combination of original coding sequence 1, original checksums sequence 3 and the verification sequence 4 that interweaves, be final coded sequence.

Four, the decoder of the system form low-density code of structure parallel cascade structure

Utilize the interleaver of above-mentioned design and corresponding deinterleaver that the decoder of two system form low-density codes is together in series, just obtain the decoder of system form low-density code of the parallel cascade structure of the inventive method structure.

Fig. 3 has provided the structural representation of this decoder, the P among the figure _1fThe channel posterior probability of expression original coding sequence 1; P _3fThe channel posterior probability of expression original checksums sequence 3; P _4fThe interweave channel posterior probability of verification sequence 4 of expression; P _1eAnd P _2eThe decoding input prior probability of representing original coding sequence 1 and interweaving encoding sequence 2 respectively; P ₁And P ₂The decoding output posterior probability of representing original coding sequence 1 and interweaving encoding sequence 2 respectively.As shown in Figure 3, the job step of the decoder among the present invention is:

(1), by the first decoder module D to P _1fAnd P _3fDecode;

(2), judge by the first judge module C whether the decoded result of the first decoder module D is correct, if correctly, then the decoding of original coding sequence 1 output posterior probability P ₁Deliver to hard decision module H, and export final decoded result, carry out interleaving treatment otherwise deliver to interleaving block E by this module;

(3), by interweave the as a result P of the second decoder module F to interleaving block E _2eAnd P _4fDecode;

(4), check by the second judge module I whether the decoded result of the second decoder module F is correct, if correctly, then the decoding of interweaving encoding sequence 2 output posterior probability P ₂Deliver to hard decision module H, and export final decoded result, carry out the deinterleaving processing otherwise deliver to de-interleaving block G by this module;

(5), by the first decoder module D to the deinterleaving of de-interleaving block G P as a result _1eAnd the decoding posterior probability of the original checksums sequence that first decoder module D decoding obtains in the step (1) is decoded;

(6), finish until decoding repeating step (2)-(5).

The first decoder module D and the second decoder module F in the present embodiment have all adopted and long-pending decoding algorithm, and its decode procedure is as follows:

The system of setting up departments adopts binary phase shift keying (BPSK) modulation system, and channel is additive white Gaussian noise channel (AWGN).If coded sequence to be sent is x=(x ₁, x ₂... x _N), wherein N is the length of coded sequence, the data of receiver reception can be write so: y=(y ₁, y ₂... y _N), wherein:

y _i＝s _i+n _i i＝1，2，…N

s _i＝2x _i-1 i＝1，2，…N(1)

N wherein _iBe that average is zero, variance is N ₀/ 2 white Gaussian noise.

For convenience of explanation, define following notion earlier:

N (m): { n:H _Mn'=1}, expression during check matrix H ' m is capable all values be 1 row, N (m) n then represent to remove among the N (m) other all row beyond the n row.

M (n): { m:H _Mn'=1}, all values is 1 row in expression check matrix H ' n row.M (n) m then represent to remove among the M (n) m other all row beyond capable.

L _Mn: expression passes to the probabilistic information of bit node n from check-node m.

q _Mn: expression passes to the probabilistic information of check-node m from bit node n.

q _n: representing the posterior probability information of n bit, also is the foundation of decoding hard decision output.

It should be noted that the probabilistic information that relates to here all be log-domain probability (Log-Likelihood Ratio, LLR), according to above definition, can be simply being summarized as follows with long-pending decoding algorithm:

Initialization, promptly calculate initial posterior probability according to received signal and channel information:

$q_{\mathrm{mn}}=\frac{4y_n}{N_0}---\left(2\right)$

Horizontal iteration is promptly according to q _MnCalculate L _Mn:

$L_{\mathrm{mn}}=\left(\underset{n^{\&prime;}\&Element;N\left(m\right)\backslash n}{\mathrm{\&Pi;}}{\mathrm{\&alpha;}}_{m{n}^{\&prime;}}\right)\&times;Q\left(\underset{n^{\&prime;}\&Element;N\left(m\right)\backslash n}{\mathrm{\&Pi;}}Q\left({\mathrm{\&beta;}}_{m{n}^{\&prime;}}\right)\right)$

α wherein _Mn=sign (q _Mn)

β _mn＝|q _mn|

$Q\left(x\right)=\log \frac{e^x+1}{e^x-1}$ (3)

Vertical iteration is promptly according to L _MnCalculate q _Mn:

$q_{\mathrm{mn}}=\frac{4y_n}{N_0}+\underset{m^{\&prime;}\&Element;M\left(n\right)\backslash m}{\mathrm{\&Sigma;}}{L}_{m^{\&prime;}n}---\left(4\right)$

Judgement output and end condition:

$q_n=\frac{4y_n}{N_0}+\underset{m\&Element;M\left(n\right)}{\mathrm{\&Sigma;}}{L}_{\mathrm{mn}}$

${x^{\&prime;}}_n=\left\{\begin{array}{cc}1,& q_n>0\\ 0,& q_n<0\end{array}\right.$ (5)

Reach in limited time when satisfying H ' x '=0 or iterations, stop decode procedure and output decoder as a result x '=(x ' ₁, x ' ₂... x ' _N), otherwise continue iterative process.

The detailed introduction of above algorithm can be referring to U.S.'s " international electronics and The Institution of Electrical Engineers's consumer electronics journal (information theory periodical) " (IEEE Transactions on Information Theory, vol.45, NO.2, p399-431, March, 1999).

The first decoder module D and the second decoder module F can also adopt minimum and decoding algorithm or Probability Decoding algorithm, they can adopt identical or different decoding algorithm respectively, described minimum can be referring to U.S.'s " international electronics and The Institution of Electrical Engineers's consumer electronics journal (periodical of communicating by letter) " (IEEETransactions on Communications with decoding algorithm and Probability Decoding algorithm, vol.47, NO.5, p673-680, May, 1999) with U.S.'s " international electronics and The Institution of Electrical Engineers's consumer electronics journal (periodical of communicating by letter) " (IEEE Transactions on Communications, vol.53, NO.8, p1288-1298, August, 2005).

Five, simulation performance

Utilize software to carry out performance simulation, under additive white Gaussian noise (AWGN) channel condition and under binary phase shift keying (BPSK) modulation system, the system form low-density code of the parallel cascade structure of comparison the inventive method structure and the performance of the pairing system form low-density code of system form matrix H.

Fig. 5 has provided the performance simulation comparison curves of the system form low-density code and the system form low-density code of parallel cascade structure: the performance that poor-performing curve d represents that code length is 1125, code check is 0.4 system form low-density code, better performances curve e represents the performance with the system form low-density code of the parallel cascade structure of the code length 2475 of the inventive method structure, code check 0.455.Simulation result from Fig. 5 can see that the system form low-density code performance of the parallel cascade structure of the inventive method structure is than the high approximately 1.5dB of performance of system form low-density code.

Six, computational complexity relatively

Because two system form matrixes in the parallel cascade structure are duplicate, therefore can't cause the increase of memory space.Though the coding operand of the system form low-density code of parallel cascade structure is the twice of original system form low-density code, but because the coding operand of system form low-density code itself is very low, so the common relatively low-density code of the coding operand of the system form low-density code of parallel cascade structure is still very low.Code length is 1125, the Modulo-two operation amount of the system form low-density code of code check 0.4 is 3375 times, and memory space needs 33750 bits; Code length is 2475, the Modulo-two operation amount of the system form low-density code of the parallel cascade structure of code check 0.455 is 6750 times, and memory space needs 33750 bits.

The interleaver of the inventive method utilization design gets up two system form low-density code parallel cascades, and for coded sequence has been introduced more verification relation, so performance has a distinct increment than system form low-density code; Simultaneously because the parallel cascade operation can not destroy the structure that is used for cascaded system form matrix, so the system form low-density code of the parallel cascade structure that constructs is simple in structure from having kept the system form low-density code to the full extent, the advantage that encoder complexity is low has and is beneficial to very much hard-wired simple structure.It is comparatively nervous and error-correcting performance is had certain requirements in the system that the system form low-density code of the parallel cascade structure that the present invention constructed is well suited for being applied in resource.

Claims (1)

1, a kind of building method of system form low-density code of parallel cascade structure, comprise: construct a system form low-density code and an interleaver, the size of the check matrix H of this system form low-density code is m * n, m＜n wherein, the left side of check matrix H is that a size is the initial matrix H of m * (n-m) ₁, the right is the unit matrix I that a size is m * m;

It is characterized in that:

Design the interleaver of the correlation minimum that makes between the two-way verification sequence in the following way: at first to initial matrix H ₁Be listed as exchange, calculate through the switching matrix H after the row exchange by following formula then ₁' with initial matrix H ₁Between the column weight correlation:

$C_i=\underset{k=1}{\overset{m}{\mathrm{\&Sigma;}}}{H}_1(k,i)\&times;H_1^{\&prime;}(k,i),1\&le;i\&le;n-m$

$W=\underset{i}{\mathrm{\&Sigma;}}{C}_i,1\&le;i\&le;n-m$ (1)

Wherein, m and n represent the line number and the columns of check matrix H, C respectively _iExpression switching matrix H ₁' i row and initial matrix H ₁I row between the column weight coefficient correlation, W represents switching matrix H ₁' with initial matrix H ₁The column weight coefficient correlation; At last under the situation with the W minimum pairing row exchange sequence as the interleaved order of interleaver;

Utilize this interleaver that the encoder parallel cascade of the system form low-density code of two structures is risen and be used as encoder, described two encoders that are used for parallel cascade are respectively first encoder and second encoder, and these two encoders are identical; The original coding sequence is carried out obtaining the interweaving encoding sequence after the interleaving treatment, utilize first encoder and second encoder simultaneously original coding sequence and interweaving encoding sequence to be encoded then respectively, obtain the original checksums sequence respectively and the verification sequence that interweaves; By the order of original coding sequence, original checksums sequence and the verification sequence that interweaves these three combined sequence are risen at last and be used as a complete coded frame;

Utilize this interleaver and corresponding deinterleaver that the decoder of two system form low-density codes is together in series as decoder again, described two decoders that are used to connect are respectively first decoder and second decoder, these two decoders adopt identical or different conventional low-density code decoding algorithm, comprise and long-pending decoding algorithm, minimum and decoding algorithm or Probability Decoding algorithm; Utilize first decoder that the confidence level of original coding sequence and the confidence level of original checksums sequence are decoded earlier, obtain the confidence level of interweaving encoding sequence after the confidence level of the original coding sequence that first decoder is exported is handled through interleaver then, utilize second decoder that the confidence level of interweaving encoding sequence and the confidence level of the verification sequence that interweaves are decoded again, the confidence level of the original coding sequence after obtaining upgrading after the confidence level of the interweaving encoding sequence that second decoder is exported is handled by deinterleaver again, between two decoders, carry out iteration by this flow process then, until satisfy till the decoding end condition, promptly construct the system form low-density code of parallel cascade structure.

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