WO2010060294A1 - 时间同步方法和装置 - Google Patents
时间同步方法和装置 Download PDFInfo
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- WO2010060294A1 WO2010060294A1 PCT/CN2009/071965 CN2009071965W WO2010060294A1 WO 2010060294 A1 WO2010060294 A1 WO 2010060294A1 CN 2009071965 W CN2009071965 W CN 2009071965W WO 2010060294 A1 WO2010060294 A1 WO 2010060294A1
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- time
- network element
- element node
- clock
- module
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
Definitions
- the present invention relates to the field of communications, and in particular to a time synchronization method and apparatus.
- frequency synchronization that is, the signals of the source end and the destination end maintain a certain relationship in frequency or phase, that is, the frequencies of the source end and the destination end are The same precision remains the same, the phase difference is constant, frequency synchronization is also commonly called clock synchronization, for example, synchronous Ethernet, E1 interface clock synchronization, etc.; another type of synchronization is time synchronization, that is, not only the same frequency, but also the same phase. And have the same time count ruler.
- the above-mentioned frequency synchronization and time synchronization are two levels of time synchronization requirements of the wireless network, and the wireless system based on the Time Division Duplex (TDD) mode includes Code Division Multiple Access (Code Division Multiple Access, Referred to as CDMA) 200/Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) and the corresponding version of Worldwide Interoperability for Microwave Access (WiMAX) Strict time synchronization is required to ensure that the cell handover can be successfully completed.
- CDMA Code Division Multiple Access
- TD-SCDMA Time Division-SCDMA
- WiMAX Worldwide Interoperability for Microwave Access
- Strict time synchronization is required to ensure that the cell handover can be successfully completed.
- the frequency synchronization can be solved by the ground clock signal distribution, and the time synchronization mainly tracks the coordination world by installing a Global Position System (GPS) module at the base station. Time (Universal Time Coordinated, referred to as UTC) timing implementation.
- the frequency synchronization can be realized by sequentially locking the clock synchronization signals (such as E1, synchronous Ethernet, n-level synchronous transmission module STM-N, Synchronous Transmission Module level n, etc.) by each network element node.
- Each network element node clock and other fixed frequency sources together form a frequency (clock) synchronization network.
- the main implementation method is GPS timing or time synchronization protocol (such as IEEE 1588-2008, NTP, etc.) to adjust the time deviation between the master clock and the slave clock to achieve time synchronization.
- the time synchronization protocol also enables frequency synchronization between the master clock and the slave clock.
- the Packet Transfer Network (PTN) device implements the frequency in the network through the IEEE 1588-2008 Precision Time Protocol (PTP or 1588). Rate synchronization and time synchronization to solve the problem of base station GPS replacement.
- the technology for the time transfer of most manufacturers to implement the PTP function is not related to the frequency synchronization network. That is to say, the current frequency synchronization network can realize network clock synchronization, but cannot achieve precise time synchronization.
- the present invention has been made in view of the fact that the phase transfer cumulative effect in the related art causes relatively significant delay and unreliability, and the present invention is directed to a time synchronization method and apparatus for solving the above problems.
- the present invention discloses a time synchronization method, including:
- Each network element node locks a clock synchronization signal of its upper-level network element node through a physical channel; and establishes a clock synchronization network;
- Each of the network element nodes performs time counting using the locked clock synchronization signal, and performs time synchronization by time compensation according to the time count.
- performing time compensation according to the time count, and implementing time synchronization includes:
- the time count is set as a time count scale, and time synchronization is implemented according to the time count scale.
- the method further includes: when a clock of a network element node of each of the network element nodes is switched, the method further includes:
- the time compensation is stopped for the network element node, and the network element node stops using the locked clock synchronization signal to perform time counting, and uses a clock synchronization signal generated by a fixed stable frequency source to perform time counting.
- the method further includes:
- the network element node performs time counting using the re-locked clock synchronization signal, and performs time compensation on the network element node.
- the invention also discloses a time synchronization device, comprising a locking module, a first counting module and a supplementary module, which are sequentially connected, wherein:
- the locking module is configured to lock a clock synchronization signal of the upper-level network element node by using a physical channel; the first counting module is configured to perform time counting using the locked clock synchronization signal; Time synchronization is implemented by time compensation according to the time counting according to the time synchronization.
- the compensation module includes a setting sub-module and a compensation sub-module connected to each other;
- the setting submodule is configured to set the time count as a time count scale
- the compensation sub-module is configured to perform time compensation according to the time counting scale to implement time synchronization.
- the method further includes a first control module connected to the compensation module;
- the first control module is configured to control whether to perform time compensation on the network element node, where the first control module controls the compensation module to stop the network element node when the clock of the network element node is switched Time compensation.
- the device further includes a second control module connected to the first counting module, and a second counting module connected to the second control module;
- the second control module is configured to control whether to use the locked clock synchronization signal to perform time counting
- the second counting module is configured to perform time counting using a clock synchronization signal generated by a fixed stable frequency source when the second control module determines that the locked clock signal is not used for time counting .
- the method further includes: a recovery module, configured to recover a clock according to a message with time information from a higher-level network element node that cannot provide a clock synchronization signal;
- a calibration module configured to perform calibration and operation of the local clock time signal according to a clock frequency recovered by the recovery module.
- each network element node uses the locked clock signal to perform time counting, and performs time compensation according to the time counting to realize time synchronization, which solves the phase transfer cumulative effect in the related art, which leads to a relatively obvious phase delay.
- the problem, which reduces phase delay, is high precision, high noise immunity and reliability.
- FIG. 1 is a flow chart of a time synchronization method according to an embodiment of the present invention.
- FIG. 2 is a detailed flowchart of a time synchronization method according to an embodiment of the present invention.
- FIG. 3 is a first schematic diagram of a time synchronization method according to an embodiment of the present invention.
- FIG. 4 is a second schematic diagram of a time synchronization method according to an embodiment of the present invention.
- FIG. 5 is a third schematic diagram of a time synchronization method according to an embodiment of the present invention.
- FIG. 6 is a structural block diagram of a time synchronization apparatus according to an embodiment of the present invention.
- FIG. 7 is a block diagram showing a specific structure of a time synchronization apparatus according to an embodiment of the present invention. Preferred embodiment of the invention
- the embodiment of the present invention provides a time synchronization method and apparatus, which implements time network synchronization and edge nodes on the basis of a clock synchronization network. It is compatible with non-clock synchronization networks, which in turn reduces phase delay. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments.
- a time synchronization method is provided.
- 1 is a flow chart of a time synchronization method in accordance with an embodiment of the present invention. It should be noted that the steps described in the following methods may be performed in a computer system such as a set of computer executable instructions, and although in FIG. The logical order is shown, but in some cases the steps shown or described may be performed in an order different than that herein. As shown in FIG. 1, the method mainly includes the following steps S102 and S104, and the specific operations are as follows:
- Step S102 The network element node transmits frequency information through a physical channel (such as a synchronous Ethernet link), and each network element node is locked to the upper-level network element node (hereinafter also referred to as a primary node or an upstream network element node) or a fixed by a phase locked loop.
- a stable clock synchronization signal from the frequency source is output to establish a frequency synchronization network.
- Step S104 each network element node uses the locked clock synchronization signal to perform time counting, and performs time synchronization according to time counting according to a time synchronization protocol, such as PTP, that is, setting the time count to The time counts the scale and performs time compensation based on the time count ruler to achieve time synchronization.
- a time synchronization protocol such as PTP
- each network element node uses the locked clock synchronization signal to perform time counting, and performs time compensation according to the time count to realize time synchronization, thereby solving the phase transfer cumulative effect in the related art, which leads to a relatively obvious phase delay.
- the problem at the time which in turn reduces the phase delay.
- FIG. 2 is a detailed flowchart of a time synchronization method according to an embodiment of the present invention. As shown in FIG. 2, the method includes the following steps S202 to S214, and the specific operations are as follows:
- Step S202 The network element node determines whether the interface is a frequency synchronization network interface. If the determination result is yes, the process proceeds to step S204. If the determination result is negative, the process proceeds to step S212. In this step, The existing network is compatible, and the network element node determines whether the interface is a frequency synchronization network interface. When the interface of the network element node is a frequency synchronization network interface, the technical solution of the present invention is used, and when the interface of the network element node is non-frequency When the network interface is synchronized, it can be processed according to the prior art. For details, refer to steps S212 to S214.
- Step S204 implementing frequency synchronization between the network element nodes of the synchronization network, that is, using the locking module to track the locked clock synchronization signal, to establish frequency synchronization between the network element nodes (ie, step S102 described above);
- Step S206 enabling the PTP protocol, Achieve phase synchronization.
- the network element node clock locks uses the locked clock synchronization signal to perform time counting, and uses a standard starting time as the reference time, and sets the time count as a time counting scale, and interacts through some time synchronization protocol, such as PTP. Perform time compensation on the local element node to implement time synchronization (ie, step S104 described above);
- the network element node uses the locked clock synchronization information, that is, the frequency after synchronization to perform time counting, and uses a standard start time (for example, UTC epoch or TAI epoch) as the reference time to determine that the local transmission 1588 message is sent.
- Timestamp 1 ie, the time offset between the current time and the reference time determined by the time count
- extracting the timestamp 2 from the received 1588 message, and the timestamp 3 of the local receiving 1588 message according to these
- the timestamp information and the time synchronization protocol perform time compensation on the local element node to implement time synchronization.
- Step S208 When a clock of a network element node is switched, the network element enters a time hold state, and no time is transmitted;
- the clock enters the process of relocking, and the time synchronization protocol is stopped to compensate the time of the network element node, and the time of the network element node is counted.
- the frequency stops acquiring from the phase-locked loop and is obtained from a fixed stable frequency source, that is, the network element node stops using the locked clock synchronization signal for time counting, and uses a fixed stable frequency source for time counting, and time transmission is entered. Keep, no longer track network reference time.
- step S206 if no network element node clock is switched, execution proceeds to step S206 to achieve time synchronization of the entire network.
- Step S210 the clock switching of the network element node is completed, and after the clock of the network element node is re-locked, the time transfer is released, that is, the time network is released, and the network element re-uses the synchronized frequency for time counting, which is a time synchronization protocol.
- time counting which is a time synchronization protocol.
- the network element node uses the re-locked clock synchronization signal to perform time counting, and performs phase compensation on the network element node, and ends the process;
- Step S212 the non-frequency synchronization network interface part recovers the clock according to the peer time protocol information (for example, 1588);
- the clock can be recovered according to the time protocol information of the peer end according to the prior art.
- Step S214 according to the recovered clock frequency and the local network element The node frequency relationship completes the calibration and operation of the local clock time to achieve time synchronization.
- a downstream network element node also referred to as a lower-level network element node
- an upstream network element node also referred to as a lower-level network element node
- the local clock time signal is calibrated and operated with the "memanical information" of the time information and the clock frequency of the downstream network element node.
- a 1588 time transmission method based on frequency synchronization is provided, which greatly reduces the phase transfer error between nodes, and cooperates with the non-frequency synchronized ⁇ node to effectively reduce the phase error during large-scale networking. .
- FIG. 3 is a first schematic diagram of a time synchronization method according to an embodiment of the present invention.
- a network element node 1, a network element node 2, a network element node 3, and a network element node 5 are all ⁇ devices, nodes. 4 is a fixed clock source.
- the above-mentioned network element node ⁇ device uses a locking module as a clock generator, and the locking module supports all functions of a digital phase locked loop (DPLL), including: phase-locking loop phase discrimination, Filtering, oscillating, and frequency division, and can automatically complete reference source monitoring, loop operation status detection and switching, loop parameter setting and other functions.
- DPLL digital phase locked loop
- the external Temperature Control Crystal Oscillator (TCXO) is the reference source for the digital phase-locked loop and is the basis for the stable operation of the entire system.
- FIG. 4 is a second schematic diagram of a time synchronization method according to an embodiment of the present invention.
- a Field Programable Gate Array (FPGA) logic completes reference source selection and cooperates to complete debounce. deal with.
- the FPGA logic and the external Voltage Control Crystal Oscillator (VCXO for short) form an analog phase-locked loop, debounce the 38.88M clock of the lock module, and send the 38.88M clock to the frequency synthesizer after debounce to generate the motherboard.
- the 125M signal is used as the time count signal.
- the clock synchronizing signal operates at a frequency of 125M, and each clock is a unit of length of 8 ns, which is the minimum unit of the time counter scale.
- the time count scales of the network element nodes in the clock synchronization network are the same.
- the working time of the network element node is composed of a register of 80 bits (10 bytes), and the counter is synchronized in the clock. Add 1 to the signal drive.
- 1588 1588
- the timestamp is a time offset value.
- the time of the current time and the reference time is given by a standard start time (UTC epoch or TAI epoch). Deviation, in ns.
- FIG. 5 is a third schematic diagram of a time synchronization method according to an embodiment of the present invention.
- the lower 16 bits are a fractional part, that is, a portion smaller than Ins; the upper 64 bits are an integer part. That is, an integer multiple of Ins.
- the time synchronization method according to the embodiment of the present invention includes the following steps:
- the clocks of the network element nodes are locked to the network element node 4, that is, the clock lock network element node 4 of the network element node 1, the clock of the network element node 2 locks the network element node 1, and the clock of the network element node 3 Locking the network element node 2, after frequency synchronization, the time count scales of the network element nodes 1, 2, 3 are agreed (ie, step S102 described above), before running time 1588 to implement time compensation, the network element nodes 1 and 2 , 3 has a fixed time difference.
- Each Ethernet interface of the network element node supports the 1588 protocol. Each port performs time extraction on the incoming 1588 and the transmitted 1588 packets. The timestamp is accurately dependent on the network element node counter. The extracted timestamp information is submitted to the protocol processing module of the 1588 of the network element node to calculate the slaves.
- the time compensation value between the node (also referred to as the lower-level network element node) and the master node (also referred to as the upper-level network element node) compensates for the time offset of the slave node and achieves the consistency of the master-slave time (ie, step S104 described above)
- the network element node 1 is the upper-level network element node of the network element node 2
- the network element node 2 is the lower-level network element node of the network element node 1.
- the clock source of the network element node When the clock source of the network element node is switched, for example, the connection between the network element nodes 2 and 1 is faulty, the clock time source of the network element node 2 needs to be provided by the network element node 5, and the lock of the network element node 2 The phase loop relocks the clock source of the network element node 5.
- the 125M clock signal output by the lock module has a frequency fluctuation, which will result in a certain time count unit relative to 8 ns. Deviation, the time difference between the calculated network element node time and its master node is calculated, and if it continues to be transmitted to the next network element node, the time network fluctuates.
- the node time count will switch to the frequency generated by the fixed crystal oscillator in the network element node, and the PTP protocol will be closed, and the time change of the master node will not be tracked, and the time information will not be released to the downstream node.
- the network element node enters the hold state, and depends on the accuracy of its own crystal oscillator, starting from the time before the switch.
- the clock is recovered according to the SYNC message of the peer 1588, and then the local clock is calibrated and run according to the recovered clock frequency and the frequency relationship of the local node. 1588 time synchronization.
- a time synchronization method based on a synchronous network is provided, so that the synchronization frequency is the basis of the time synchronization protocol, and the phase difference of the large-scale networking time transmission can be greatly reduced.
- a time synchronization device is provided.
- 6 is a block diagram showing the structure of a time synchronization apparatus according to an embodiment of the present invention. As shown in FIG. 6, the apparatus includes: a locking module 62, a first counting module 64, and a compensation module 66. The above structure will be described in detail below.
- the locking module 62 is configured to lock the clock signal of each network element node through the phase locked loop; the first counting module 64 is connected to the locking module 62 for performing time counting using the clock synchronization signal locked by the locking module 62; The module 66 is connected to the first counting module 64 for performing time compensation according to the time count of the first counting module 64 to implement time synchronization.
- a time synchronization device that can achieve frequency and phase synchronization is provided.
- FIG. 7 is a block diagram showing a specific structure of a time synchronization apparatus according to an embodiment of the present invention.
- the compensation module 66 includes: a setting sub-module 662, which is used to set a time count as a time scale of a time stamp;
- the module 664 is connected to the setting sub-module 662 for performing time compensation according to the time counting scale set by the setting sub-module 662.
- the above apparatus further includes: a first control module 72, a second control module 74, a second counting module 76, a recovery module 78, and a calibration module 70.
- the above structure will be described in detail below.
- the first control module 72 is connected to the compensation module 66 for controlling whether the compensation module 66 performs time compensation on the network element node. When the clock of the network element node is switched, the control compensation module 66 stops time compensation for the network element node. .
- the second control module 74 is connected to the first counting module 64 for controlling whether to use the clock synchronization signal for time counting. When the clock of the network element node is switched, the first counting module 64 is controlled to stop using the clock synchronization signal.
- the second counting module 76 is connected to the second control module 74 for performing time using a fixed stable frequency source when the second control module 74 determines that the clock synchronization signal is not used for time counting. Calculate.
- the recovery module 78 is configured to recover the clock according to the time information from the network element node that cannot lock the clock synchronization signal; the calibration module 70 is connected to the recovery module 78, and is configured to perform calibration of the clock signal according to the clock frequency recovered by the recovery module 78. And running.
- each network element node phase-locked loop uses the locked clock synchronization signal to perform time counting, and performs time compensation according to time counting through a certain time synchronization protocol, such as PTP.
- Time synchronization solves the problem that the phase transfer cumulative effect in the related art leads to a relatively obvious phase delay, thereby reducing the phase delay.
- modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be separately fabricated into individual integrated circuit modules, or they may be Multiple modules or steps are made into a single integrated circuit module. Thus, the invention is not limited to any particular combination of hardware and software.
- each network element node uses the locked clock synchronization signal to perform time counting, and performs time compensation according to time counting to realize time synchronization, thereby solving the phase transfer cumulative effect in the related art, which leads to a relatively obvious phase.
- the delay problem reduces phase delay, with high precision, high noise immunity and reliability.
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/130,278 US20110221485A1 (en) | 2008-11-29 | 2009-05-25 | Time synchronization method and apparatus |
EP09828555A EP2352250A4 (en) | 2008-11-29 | 2009-05-25 | METHOD AND APPARATUS FOR TIME SYNCHRONIZATION |
RU2011121058/08A RU2468521C1 (ru) | 2008-11-29 | 2009-05-25 | Способ и устройство временной синхронизации |
BRPI0921953A BRPI0921953A2 (pt) | 2008-11-29 | 2009-05-25 | método e aparelho para sincronização de tempo |
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CN200810179540A CN101431795B (zh) | 2008-11-29 | 2008-11-29 | 时间同步方法和装置 |
CN200810179540.5 | 2008-11-29 |
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US (1) | US20110221485A1 (zh) |
EP (1) | EP2352250A4 (zh) |
CN (1) | CN101431795B (zh) |
BR (1) | BRPI0921953A2 (zh) |
RU (1) | RU2468521C1 (zh) |
WO (1) | WO2010060294A1 (zh) |
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CN113377060B (zh) * | 2021-08-13 | 2021-11-09 | 成都博宇利华科技有限公司 | 信号采集系统中获取每个采样点采样时刻的方法 |
CN114124616B (zh) * | 2022-01-25 | 2022-05-27 | 浙江中控研究院有限公司 | 基于epa总线结构的时钟同步优化方法 |
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WO2008025978A1 (en) * | 2006-08-29 | 2008-03-06 | Ubiquisys Limited | Synchronising base stations |
CN101431795A (zh) * | 2008-11-29 | 2009-05-13 | 中兴通讯股份有限公司 | 时间同步方法和装置 |
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US20110221485A1 (en) | 2011-09-15 |
EP2352250A4 (en) | 2012-11-14 |
BRPI0921953A2 (pt) | 2016-01-05 |
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CN101431795A (zh) | 2009-05-13 |
EP2352250A1 (en) | 2011-08-03 |
RU2468521C1 (ru) | 2012-11-27 |
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