Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B99/00—Subject matter not provided for in other groups of this subclass
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
  • H01L29/861—Diodes
  • H01L29/88—Tunnel-effect diodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
  • H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
  • H01L29/861—Diodes
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/957—Making metal-insulator-metal device

Definitions

• Embodiments of the invention generally relate to select devices, such as metal-insulator-insulator-metal (MIIM) diodes, that include an open volume, memory devices and electronic systems including such select devices, and to methods of fabricating such select devices.
• select devices such as metal-insulator-insulator-metal (MIIM) diodes
• MIIM metal-insulator-insulator-metal
• a metal-insulator-insulator-metal (MIIM) diode includes two electrical insulators disposed between two types of metals. The materials are tailored such that responsive to application of a forward bias, a quantum well forms between the two insulators enabling high-energy quantum tunneling. As a result, when a voltage is applied to the top metal that exceeds its threshold, tunneling electrons are accelerated across the quantum well. Quantum tunneling is faster than charging a switch junction in an integrated circuit, partially because charge travels through the metal rather than slower speed materials such as silicon.
• MIIM diodes can be broadly incorporated within circuits which use conventional CMOS manufacturing as well as other semiconductor and printed circuit technologies.
• the MIIM diode has a sharper forward current-to- voltage (I- V) curve than the metal insulator metal (MIM) diode and, thus, may be used as a tunneling device with very high speed performance capability that is potentially compatible with many substrate technologies.
• I- V forward current-to- voltage
• MIM metal insulator metal
• Use of MIIM diodes may potentially reduce cost, size, and improve performance of high-speed memory devices.
• the insulator materials used in MIIM diodes must be relatively thin compared to the de Broglie electron wavelength and, thus, conventional deposition processes may cause undesirable chemical intermixing at the interface of the metals and insulators.
• MIIM diodes may generally exhibit poor rectifying behavior. Increased asymmetry and nonlinearity in the I- V performance as might be achieved through avoidance of the aforementioned chemical intermixing and edge leakage exhibited by select devices as exemplified by coventional MIIM diodes would result in better rectification performance of such devices.
• select devices that may be scaled to smaller sizes while exhibiting an increased asymmetrical I-V curve and associated improved rectifying behavior as well methods of forming such select devices.
• FIG. IA is a partial cross-sectional side view illustrating an embodiment of a memory device of the present invention including select devices according to the present invention
• FIG. IB shows the electrodes, insulators and spacers of one select device shown in FIG. IA and is used to illustrate one manner of operation thereof;
• FIG. 2 is a diagram of a memory device of the present invention in which select devices according to the present invention are disposed in a simple matrix form;
• FIGs. 3A-3F are partial cross-sectional side views of embodiments of a workpiece and illustrate an embodiment of a method of forming the select device shown in FIGs. IA and IB;
• FIGs. 4A-4F are partial cross-sectional side views of embodiments of a workpiece and illustrate another embodiment of a method of forming the select device shown in FIGs. IA and IB;
• FIGs. 5A-5C are partial cross-sectional side views of embodiments of a workpiece and illustrate yet another embodiment of a method of forming the select device shown in FIGs. IA and IB; and FIG. 6 is a graph showing a comparison between a current- voltage (I- V) relationship for a select device of the present invention and a conventional select device.
• I- V current- voltage
• the present invention comprises methods of fabricating select devices, such as metal-insulator-insulator-metal (MIIM) devices, including an open volume that functions as an insulator.
• select devices such as metal-insulator-insulator-metal (MIIM) devices
• the present invention comprises memory devices and electronic systems that include one or more such select devices.
• the one or more such select devices may be in electrical communication with a memory cell to form a memory device.
• the present invention includes methods of forming such select devices. Such methods may include forming an open volume between a conductive material and an insulator material, the open volume functioning as a high bandgap insulator having a low dielectric constant.
• semiconductor means and includes a device that may operate as a switch that is either in an'Off ' state or an "on" state depending on the amount of voltage potential applied and, more particularly, switches to the on state when the applied current reaches a threshold or current voltage and in the off state may exhibit a substantially electrically nonconductive state.
• substrate means any structure that includes a layer of semiconductor type material including, for example, silicon, germanium, gallium arsenide, indium phosphide, and other III-V or II- VI type semiconductor materials.
• Substrates include, for example, not only conventional substrates but also other bulk semiconductor substrates such as, by way of nonlimiting example, silicon-on-insulator (SOI) type substrates, silicon-on-sapphire (SOS) type substrates, and epitaxial layers of silicon supported by a layer of base material. Semiconductor type materials may be doped or undoped. Furthermore, when reference is made to a "substrate" in the following description, previous process steps may have been utilized to at least partially form elements or components of a circuit or device in or over a surface of the substrate.
• the illustrations presented herein are not meant to be actual views of any particular select device, memory device, memory cell, or system, but are merely idealized representations which are employed to describe the present invention.
• FIG. IA is a partial cross-sectional schematic view of an embodiment of a memory device 100 of the present invention.
• the memory device 100 may include an integrated circuit comprising a plurality of select devices 102, each of which is coupled to a memory cell 104.
• the select devices 102 and memory cells 104 may be arranged in an array on or in a substrate 101.
• the select devices 102 maybe arranged in a plurality of rows and columns.
• FIG. IA is a partial cross-sectional view taken vertically through the substrate 101 and illustrates four select devices 102 in a common row or column of the array.
• Each of the select devices 102 may include conductive material 114, and a structure 106 disposed thereon, the structure 106 comprising an optional dielectric material 112, another dielectric material 110, another conductive material 108, and at least one open volume 118 within the select device 102.
• the select devices 102 are shown in FIG. 1 as occupying a major vertical portion of the substrate 101. It is understood, however, that in actuality the substrate 101 may be relatively thicker than illustrated, and the select devices 102 may occupy a relatively thinner portion of the substrate 101.
• only active elements of the select devices 102 i.e., the elements of the select devices 102 through which charge carriers travel), or materials used to form such active elements, are cross-hatched to simplify the cross-sectional figures herein.
• the select devices 102 may be disposed, for example, within another dielectric material 113. Each select device 102 may, optionally, be in physical or electrical contact with memory cell 104 via, for example, a conductive contact 124. In some embodiments, each select device 102 may communicate electrically with a memory cell 104 by way of a conductive contact 124, and each memory cell 104 may communicate electrically with a conductive line 126. As a non-limiting example, each of the memory cells 104 may include a charge-based memory cell or a phase change memory cell. Each select device 102 may also communicate electrically with another conductive line (not shown) by way of electrical contacts (not shown). In additional embodiments, the conductive material 114 may simply comprise a region or portion of another conductive line.
• FIG. IB is an enlarged view of the conductive material 114, the optional dielectric material 112, the another dielectric material 110, the another conductive material 108, and the open volume 118 of one select device 102 shown in FIG. 1 A.
• Spacers 116 may be disposed on the conductive material 114, overlying sidewalls 132 of the another conductive material 108, the another dielectric material 110, and the optional dielectric material 112.
• the open volume 118 may have an average depth, which is depicted as dl, of between about 5 A and about 20 A, and more particularly about 10 A.
• the open volume 118 of each select device 102 may, for example, extend into the dielectric material 112, as shown in broken lines in FIG. 1.
• the width of the open volume 118 may be selected, for example, based on the composition of the dielectric material 112, and the another dielectric material 110, and based on a thickness of the overlying another conductive material 108.
• the dielectric material 112 may be absent and the open volume 118 may substantially extend between adjacent spacers 116 to form a void between opposing surfaces of the another dielectric material 110 and the conductive material 114.
• the edge (i.e., an outer periphery) of the select device 102 forms a greater percentage of the total area of the select device 102 resulting in increased edge leakage, which may have negative effects on the rectifying behavior of the select device 102.
• the open volume 118 may be provided, open volume 118 functioning as a high band gap insulator having a dielectric constant of about one (1). Including the open volume 118 as an insulator in the select device 102 enables smaller scaling of the select devices 102 while minimizing fringe field effects (i.e., edge leakage) and providing a select device 102 exhibiting a larger asymmetrical current and an enhanced rectifying behavior.
• the memory device 200 may include an array of memory cells 204, each of which is coupled to a select device 202 arranged in a simple matrix form, for selectively writing information to the memory cells 204, or selectively reading information from the memory cells 204, and various circuits which include, for example, a first electrode 231, a first drive circuit 233 for selectively controlling the first electrode 231, a second electrode 235, a second drive circuit 237 for selectively controlling the second electrode 235, and a signal detection circuit (not shown).
• the first electrodes 231 may substantially function as word lines for line selection and second electrodes 235 may substantially function as bit lines for row selection arranged orthogonally to the first electrodes 231.
• the first electrodes 231 are arranged in a major plane of memory device 200 at a predetermined pitch in direction X and the second electrodes 235 are arranged at a predetermined pitch in direction Y orthogonal to direction X.
• the first and second electrodes 231 and 235, respectively may be reversed so that first electrodes 231 may substantially function as bit lines while the second electrodes 235 substantially function as word lines.
• a workpiece 300 may be provided, which includes a conductive material 314 and a dielectric material 312.
• the conductive material 314 may comprise a metal having a low work function such as, for example, tantalum suicide (TaSi 2 ), an alloy of tantalum and silicon, an alloy of tantalum and nitrogen, and may be formed using, for example, metal layer deposition techniques (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, thermal evaporation, or plating) known in the art of integrated circuit fabrication.
• CVD chemical vapor deposition
• PVD physical vapor deposition
• sputtering thermal evaporation, or plating
• the conductive material 314 may be formed over a substrate (not shown) which, as previously described, may comprise a full or partial wafer of semiconductor material or a material such as glass or sapphire. Additional features, such as, for example, conductive lines (which may simply comprise conductive pads in additional embodiments) and electrical contacts also may be formed on or in the surface of the substrate in a similar manner (prior and/or subsequent to forming the conductive material 314), although a substrate including such additional features is not illustrated in FIGs. 3A-3F to simplify the figures.
• the dielectric material 312 may be provided over the workpiece 300 (i.e., over an exposed major surface of the conductive material 314) and may have a thickness of less than about 1 nm and, more particularly, between about 5 A and about 20 A.
• the dielectric material 312 may comprise a material having a dielectric constant ( ⁇ ) of between about 2 to about 10, and having a band gap of between about 6 eV and about 10 eV.
• the dielectric material 312 may include an oxide such as silicon dioxide (SiO 2 ), a nitride such as silicon nitride (Si 3 N 4 ), amorphous carbon, or aluminum oxide (Al 2 O 3 ), and may be formed using a chemical vapor deposition (CVD) process, by decomposing tetraethyl orthosilicate (TEOS), by a spin-on process, or by any other process known in the art of integrated circuit fabrication.
• CVD chemical vapor deposition
• TEOS tetraethyl orthosilicate
• another dielectric material 310 may be formed over and in contact with the dielectric material 312.
• the another dielectric material 310 may include, for example, a crystalline material and include hafnium, zirconium, titanium, tellurium, oxides thereof, combinations thereof, and alloys thereof.
• the another dielectric material 310 may be formed to have a thickness of between about 2 nm and about 8 nm and, more particularly about 5 nm, using a conventional process such as an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process.
• ALD atomic layer deposition
• CVD chemical vapor deposition
• PVD physical vapor deposition
• the another dielectric material 310 may include multiple layers (not shown) that may be, for example, deposited using an atomic layer deposition (ALD) process to form a laminated or sandwiched structure.
• Another conductive material 308 may be formed over the another dielectric material 310 and may comprise, for example, a metal having a high work function such as platinum, titanium, titanium nitride, rhodium, iridium, ruthenium, combinations thereof, and alloys thereof.
• the another conductive material 308 may have an average thickness of between about 5 nm to about 30 nm and, more particularly, about 10 nm to about 20 nm, may be formed by using, for example, a physical vapor deposition (PVD) process (e.g., sputtering or thermal evaporation), a chemical vapor deposition (CVD) process, an electroless deposition process, or an electroless deposition process used to form a seed layer followed by a subsequent electroplating process.
• PVD physical vapor deposition
• CVD chemical vapor deposition
• openings 328 maybe formed through the another conductive material 308, the another dielectric material 310, and the dielectric material 312 forming structures 306 and exposing sidewalls 332 of each of the another conductive material 308, the another dielectric material 310, and the dielectric material 312.
• FIG. 3C shows a plurality of openings 328 to simplify the cross-sectional figures, a single opening 328 maybe formed.
• each of the openings 328 may be formed by removing a portion of each of the another conductive material 308, the another dielectric material 310, and the dielectric material 312 through an aperture in a mask (not shown) using, for example, an anisotropic dry reactive ion (i.e., plasma) etching process.
• the mask may be, for example, a photoresist material or a dielectric anti-reflective coating (DARC) material. Removal of a portion of each of the another conductive material 308, the another dielectric material 310, and the dielectric material 312 may expose a surface 330 of the conductive material 314.
• the particular composition of the etchant used to form the openings 328 may be selected based on the composition of the another conductive material 308, the another dielectric material 310, the dielectric material 312, the conductive material 314, and the mask.
• the another conductive material 308 may be platinum
• the another dielectric material 310 may be amorphous carbon
• the dielectric material 312 may be silicon dioxide
• the conductive material 314 may be tantalum nitride.
• a chlorine-containing etchant may be introduced to be used to selectively remove the another conductive material 308, the another dielectric material 310, the dielectric material 312 through apertures in the mask forming the openings 328.
• another portion of the dielectric material 312 may be removed to form undercuts 334 in the dielectric material 312, each of the undercuts 334 exposing opposing surfaces of the another dielectric material 310 and the conductive material 308.
• the undercuts 334 may be formed using an anisotropic wet etching process or an anisotropic dry (i. e. , reactive ion) etching process.
• the another conductive material 308 is platinum
• the another dielectric material 310 is hafnium oxide
• the dielectric material 312 is silicon dioxide
• the conductive material 314 is tantalum nitride
• a solution including water and hydrofluoric acid at a ratio of between about 500:1 and about 100:1 maybe applied to the sidewalls 332 to form undercuts 334 in the silicon dioxide.
• the dielectric material 312 may be formed from amorphous carbon and may be exposed to an oxygen plasma to form the undercuts 334 therein.
• a spacer material 336 may be deposited over the workpiece 300 (i.e., over exposed surfaces of the another conductive material 308 and the conductive material 314 and over sidewalls 332 of the openings 328) to form an open volume 318 defined by surrounding surfaces of the spacer material 336, the dielectric material 312, the another dielectric material 310 and the conductive material 314.
• the spacer material 336 may include, for example, silicon dioxide or silicon nitride and may be formed using an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process.
• ALD atomic layer deposition
• CVD chemical vapor deposition
• a conformal layer (not shown) of the spacer material 336 may be deposited over the workpiece 300 to a thickness sufficient to provide support for the open volume 318.
• spacer material 336 may then be removed to form spacers 316 disposed about a periphery of select devices 302, such as those shown in FIG. 3E.
• the spacers 316 may be formed using a conventional anisotropic etching process, which is not described in detail herein.
• the spacer material 336 may include silicon nitride and a plasma etching process may be performed using a mixture of hydrogen bromide (HBr) and sulfur hexafluoride (SF 6 ) to form spacers 316 laterally sealing the open volume 318.
• HBr hydrogen bromide
• SF 6 sulfur hexafluoride
• Each of the spacers 316 may extend from the surface 330 of the conductive material 314 overlying sidewalls 332.
• FIG. 3F shows a top-down view of the workpiece 300 shown in FIG. 3E, which includes a plurality of select devices 302, each of the select devices 302 including portions of the another conductive material 308, the dielectric material (not shown) and the another dielectric material (not shown), which are disposed over the conductive material 314.
• the open volume 318 which is represented in FIG. 3F by broken lines, is disposed about an outer periphery of the dielectric.
• Each of the select devices 302 may have lateral dimensions D 1 and D 2 of between about 25 nm and about 75 nm, and more particularly, about 50 nm.
• Spacers 316 are positioned on the surface 330 of the conductive material 314 overlying sidewalls 332.
• Formation of the open volume 318 provides an insulator having a dielectric constant ( ⁇ ) of about 1, which facilitates formation of select devices 302 having enhanced rectifying behavior, even at smaller device sizes.
• the processes utilized in the formation of the open volume 318 may be performed at sufficiently low temperatures so as to prevent chemical intermixing between the dielectic materials (i.e., the another dielectric material 310 and the dielectric material 312) and the conductive materials (i. e., another conductive material 308 and conductive material 314).
• a workpiece 400 may be provided that includes openings 328 formed exposing a surface 330 of a conductive material 314 through a dielectric material 312, and another dielectric material 310, and another conductive material 308.
• the workpiece 300 shown in FIG. 4 A may be formed in the manner previously described with reference to FIGs. 3A-3C.
• a sacrificial material 342 which is represented by broken lines, may optionally be applied to at least partially fill each of the undercuts 334.
• the sacrificial material 342 may be formed from a hard mask material, such as amorphous carbon, and may be deposited using conventional methods such as an atomic layer deposition (ALD) process. As shown in FIG.
• a spacer material 336 may be applied over the workpiece 400.
• the spacer material 336 may include silicon dioxide or silicon nitride, and may be formed using an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process.
• ALD atomic layer deposition
• CVD chemical vapor deposition
• the optional sacrificial material 342 may prevent the spacer material 336 from being deposited in the optional undercuts 334.
• a conventional spacer etch may then be performed, as previously described with respect to FIG.
• the spacers 316 may cover the another conductive material 308, the another dielectric material 310, and either the dielectric material 312 or the sacrificial material 342, filling the optional undercuts exposed along the sidewalls 332 of the openings 328.
• At least one of the spacers 316 may be removed from the sidewalls 332 to expose a portion of the dielectric material 312 or, if present, a portion of the sacrificial material 342, which is represented by broken lines. Removal of at least one of the spacers 316 may be performed by way of conventional patterning techniques (e.g., masking and etching), which are not described in detail herein. By way of non-limiting example, a mask (not shown) may be applied and selectively patterned to expose a surface of at least one of the spacers 316 through the mask, and at least one of the spacers 316 may be removed using, for example, a wet chemical etching process.
• FIG. 4E is a top-down view of the workpiece 400 shown in FIG. 4F after removal of one of the spacers 316 to expose at least one of the sidewalls 332.
• exposed portions of the sacrificial material 342, if present, and the dielectric material 312 may be removed to form an open volume 318.
• an anisotropic dry reactive ion (i.e., plasma) etching process may be used to selectively remove the sacrificial material 342 without removing the dielectric material 312 to form open volume 318 extending only partially into the dielectric material 312, as represented by broken lines.
• the dielectric material 312 may be substantially completely removed using, for example, an anisotropic dry reactive ion (i.e., plasma) etching process so as to form an open volume 318' exposing opposing surfaces of the dielectric material and the another metal between the spacers 316.
• an anisotropic dry reactive ion (i.e., plasma) etching process so as to form an open volume 318' exposing opposing surfaces of the dielectric material and the another metal between the spacers 316.
• a workpiece 500 may be provided, which includes a conductive material 314, a dielectric material 512, another dielectric material 310, and another conductive material 308.
• the conductive material 314 may include a metal having a low work function such as those previously described with respect to FIG.
• the dielectric material 512 may include an oxide such as silicon dioxide (SiO 2 ), a nitride such as silicon nitride (Si 3 N 4 ), amorphous carbon, or aluminum oxide (Al 2 O 3 ), and may include a plurality of nanodots 544, which may be distributed throughout the dielectric material 512.
• the nanodots 544 may include, for example, silicon particles or metal particles having an average diameter of between about 5 A and about 20 A.
• the another dielectric material 310 and the conductive material 308 maybe formed over the workpiece 500, and plurality of openings 328 may be formed using methods identical or substantially similar to those previously described in relation to FIG. 3B and 3C.
• the dielectric material 312 may be removed so that the nanodots 544 support overlying portions of the another dielectric material 310 and the conductive material 308.
• the dielectric material 312 is amorphous carbon
• the nanodots 544 are formed from a metal
• the carbon may be removed using an anisotropic oxygen plasma etch, while the nanodots 544 remain between surfaces of the another dielectric material 310 and the another conductive material 314. Removal of the dielectric material 312 results in the formation of open volume 318, which may function as an insulator having a dielectric constant of about 1 to reduce parasitic capacitance. Referring to FIG.
• spacers 316 maybe formed over the sidewalls 332 of the another conductive material 308, the another dielectric material 310, the dielectric material 312 using methods previously described with respect to FIG. 3E to enclose and provide additional support for the open volume 318.
• FIG. 6 shows a comparison of voltage-current density characteristics of a conventional select device 601 and of a select device including an open volume 602, such as the select device (102) shown in FIGs. IA and IB.
• Each of the select devices 601 and 602 may include a first electrode and a second electrode, which are spaced-apart from one another by a first insulator and a second insulator.
• the first insulator may be disposed over the second electrode, and the second insulator may be disposed between the first insulator and the first electrode.
• the first electrode may include a metal having a work function of about 4.40
• the second electrode may include a metal having a work function of about 5.25
• the second insulator may include a nanolaminate dielectric comprising hafnium oxide (HfO 2 ) and zirconium oxide (ZrO 2 ).
• the conventional select device 601 may include a first insulator comprising silicon dioxide and, in contrast, the select device 602 may include a first insulator comprising an open volume.
• a quantum well may form between the first insulator and the second insulator resulting in the forward curves shown in FIG. 6.
• the forward curve exhibits a dramatically sharper nonlinear current- voltage characteristic in comparison to the forward curve for select device 601, demonstrating decreased resistance and increased rectifying behavior. Therefore, utilizing an open volume as a first insulator in a select device results in a select device exhibiting increased nonlinearity and a highly asymmetric current-voltage characteristic.

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