WO2010058532A1 - Dispositif semi-conducteur, son procédé de fabrication, et dispositif d’affichage utilisant le dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur, son procédé de fabrication, et dispositif d’affichage utilisant le dispositif semi-conducteur Download PDF

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WO2010058532A1
WO2010058532A1 PCT/JP2009/005936 JP2009005936W WO2010058532A1 WO 2010058532 A1 WO2010058532 A1 WO 2010058532A1 JP 2009005936 W JP2009005936 W JP 2009005936W WO 2010058532 A1 WO2010058532 A1 WO 2010058532A1
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region
semiconductor layer
film
tft
gate insulating
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PCT/JP2009/005936
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Japanese (ja)
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牧田直樹
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シャープ株式会社
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Priority to US13/130,027 priority Critical patent/US20110227878A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/14—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the light source or sources being controlled by the semiconductor device sensitive to radiation, e.g. image converters, image amplifiers or image storage devices
    • H01L31/145—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the light source or sources being controlled by the semiconductor device sensitive to radiation, e.g. image converters, image amplifiers or image storage devices the semiconductor device sensitive to radiation being characterised by at least one potential-jump barrier or surface barrier

Definitions

  • the present invention relates to a semiconductor device including a thin film transistor (TFT) and a thin film diode (THD), a manufacturing method thereof, and a display device using the semiconductor device.
  • TFT thin film transistor
  • TDD thin film diode
  • TFT thin film transistor
  • TFD thin film diode
  • the device characteristics of TFTs and TFDs formed on the same substrate are most affected by the crystallinity of the semiconductor layer serving as the active region.
  • a method for obtaining a good crystalline semiconductor layer on a glass substrate a method of crystallizing an amorphous semiconductor film by irradiating a laser beam is generally used.
  • crystallization is performed by heat treatment.
  • the obtained crystalline semiconductor film may be irradiated with laser light in order to further improve the crystallinity.
  • a good semiconductor film having a uniform crystal orientation can be obtained by a low-temperature, short-time heat treatment as compared with a conventional crystalline semiconductor film crystallized only by laser irradiation.
  • Patent Document 1 discloses an image sensor including an optical sensor unit using TFD and a drive circuit using TFT on the same substrate.
  • an amorphous semiconductor film formed on a substrate is crystallized to form TFT and TFD semiconductor layers.
  • the TFT and the TFD are integrally formed on the same substrate, not only the semiconductor device can be miniaturized, but also a great cost merit such as a reduction in the number of parts can be obtained. Further, it is possible to realize a product with a new function that cannot be obtained by combining conventional parts.
  • Patent Document 2 discloses a TFT (crystalline silicon TFT) using crystalline silicon and a TFD (amorphous silicon film) using amorphous silicon using the same semiconductor film (amorphous silicon film).
  • TFT crystalline silicon TFT
  • TFD amorphous silicon film
  • a catalyst element that promotes crystallization of amorphous silicon is added only to a region where an active region of a TFT is to be formed in an amorphous silicon film formed on a substrate. Thereafter, by performing heat treatment, only a region where an active region of the TFT is to be formed is crystallized, and a silicon film in which a region to be a TFD is in an amorphous state is formed.
  • this silicon film is used, the crystalline silicon TFT and the amorphous silicon TFD can be easily manufactured on the same substrate.
  • Patent Document 3 uses the same semiconductor film (amorphous silicon film) to form a photosensor TFT that functions as a photosensor and a switching TFT that functions as a switching element.
  • the photosensor sensitivity is improved by making the silicon film in the channel region of the photosensor TFT thicker than the silicon film in the source / drain region and the active region of the switching TFT.
  • a half-exposure technique using a gray-tone mask is used in photolithography when an amorphous silicon film is made into an island, thereby making the amorphous film The silicon film is partially thinned.
  • the thinned regions of the amorphous silicon film are crystallized.
  • a region that has not been thinned a region that becomes a channel region of the photosensor TFT remains amorphous.
  • Patent Document 1 the same crystalline semiconductor film is crystallized to form both a TFT semiconductor layer and a TFD semiconductor layer.
  • this method has a problem that it is difficult to satisfy each device characteristic required for TFT and TFD at the same time.
  • Patent Document 2 and Patent Document 3 a part of the same amorphous semiconductor film is crystallized, a TFT (crystalline silicon TFT) is formed from the crystallized part, and remains amorphous.
  • a TFD amorphous silicon TFD
  • hydrogen contained in the original amorphous silicon film is lost in a heat treatment step of crystallizing a part of the amorphous silicon film into crystalline silicon. For this reason, there is a problem in that an electrically favorable amorphous silicon TFD cannot be manufactured using a portion that remains amorphous after the heat treatment step.
  • Patent Document 3 has the following problems.
  • the silicon film of the photosensor TFT can be made thicker than the silicon film of the switching TFT, which is advantageous in increasing the sensitivity of the photosensor.
  • half exposure and half etching are used to vary the thickness of the silicon film, which complicates the manufacturing process.
  • by thinning (etching) a silicon film in a specific region the region is made thinner than other regions. At this time, it is extremely difficult to control the thickness of the region to be thinned with high accuracy. As a result, the thickness of the silicon film of the switching TFT varies greatly, and there is a possibility that excellent characteristics cannot be obtained.
  • the present invention has been made in view of the above problems, and an object of the present invention is to realize respective characteristics required for a thin film transistor and a thin film diode in a semiconductor device including the thin film transistor and the thin film diode on the same substrate. is there.
  • the semiconductor device of the present invention is provided so as to cover a substrate, a first crystalline semiconductor layer that is supported by the substrate and includes a channel region, a source region, and a drain region, and the first crystalline semiconductor layer.
  • a second thin film transistor including a gate insulating film, a thin film transistor provided on the gate insulating film and having a gate electrode for controlling conductivity of the channel region, and a second electrode supported by the substrate and including at least an n-type region and a p-type region.
  • the p-type region, the source region, and the drain region contain the same impurity element.
  • the thickness d2 of the second crystalline semiconductor layer is larger than the thickness d1 of the first crystalline semiconductor layer.
  • the thin film transistor further includes an interlayer insulating layer in contact with the upper surface of the gate electrode
  • the thin film diode further includes an interlayer insulating layer in contact with the upper surface of the second crystalline semiconductor layer
  • the interlayer insulating layer of the thin film transistor and the interlayer insulating layer of the thin film diode are formed of the same insulating film.
  • a depth Dd from the upper surface of the n-type region or p-type region to the peak of the concentration profile of the same impurity element in the thickness direction of the n-type region or p-type region, and the gate insulating film is substantially equal.
  • the thickness d2 of the second crystalline semiconductor layer is larger than the sum (d1 + d3) of the thickness d1 of the first crystalline semiconductor layer and the thickness d3 of the gate insulating film.
  • the concentration profile of the same impurity element in the thickness direction of the n-type region or the p-type region preferably has a peak in the second crystalline semiconductor layer.
  • the concentration profile of the same impurity element in the thickness direction of the source region and the drain region preferably has a peak between the upper surface of the gate insulating film and the lower surface of the first crystalline semiconductor layer. More preferably, the concentration profile of the same impurity element in the thickness direction of the source region and the drain region has a peak in the first crystalline semiconductor layer.
  • the thickness d3 of the gate insulating film may be the thickness of the gate insulating film on the source region and the drain region of the first crystalline semiconductor layer.
  • the second crystalline semiconductor layer may include an intrinsic region located between the n-type region and the p-type region.
  • the gate electrode is formed of the same semiconductor film as the second crystalline semiconductor layer.
  • the substrate has a light-transmitting property, and may further include a light-shielding layer disposed between the second crystalline semiconductor layer and the substrate.
  • the light shielding layer is formed of the same semiconductor film as the first crystalline semiconductor layer.
  • the method for manufacturing a semiconductor device includes (a) a step of preparing a substrate having a first crystalline semiconductor film formed on a surface thereof, and (b) a part of the first crystalline semiconductor film. A step of forming a first island-shaped semiconductor layer that will later become an active region of the thin film transistor; (c) a step of forming a gate insulating film on the first island-shaped semiconductor layer; and (d) the gate insulating film. A step of forming a second crystalline semiconductor film in contact with the surface of the gate insulating film; and (e) an active region of a thin film diode later using a part of the second crystalline semiconductor film. Forming a second island-shaped semiconductor layer.
  • the thickness of the second crystalline semiconductor film is larger than the thickness of the first crystalline semiconductor film.
  • the thickness of the second crystalline semiconductor film is larger than the total thickness of the first crystalline semiconductor film and the gate insulating film.
  • the method includes a step of forming a gate electrode of a thin film transistor on the gate insulating film, wherein the thickness of the second crystalline semiconductor film is exposed from the gate electrode.
  • the region is larger than the total thickness of the first crystalline semiconductor film and the gate insulating film.
  • the method further includes a step of simultaneously doping the same impurity element.
  • step (F) After the step (e), (f) a step of doping a first impurity element into a region to be a source region and a drain region of the first island-like semiconductor layer through the gate insulating film; g) a step of doping an n-type region in the second island-shaped semiconductor layer with an n-type impurity element; and (h) a region in the second island-shaped semiconductor layer that becomes a p-type region. And a step of doping with a p-type impurity element.
  • the first impurity element may include an n-type impurity element, and the step (f) and the step (g) may be performed simultaneously.
  • the first impurity element may include a p-type impurity element, and the step (f) and the step (h) may be performed simultaneously.
  • the first island-shaped semiconductor layer includes a plurality of island-shaped semiconductor layers that later become active regions of n-channel thin film transistors and island-shaped semiconductor layers that later become active regions of p-channel thin film transistors.
  • an n-type semiconductor layer is formed through the gate insulating film with respect to an island-shaped semiconductor layer to be an n-channel thin film transistor later in the first island-shaped semiconductor layer.
  • the step (f1) is performed simultaneously with the step (g), and the step (f2) is performed simultaneously with the step (h).
  • the method includes a step of forming a gate electrode of a thin film transistor on the gate insulating film, and the step of forming the gate electrode patterns the second crystalline semiconductor film. This is a step of simultaneously forming a second island-shaped semiconductor layer that will later become an active region of the thin film diode and at least a part of the gate electrode.
  • the substrate is a light-transmitting substrate, and before the step (c), a lower portion of a region of the substrate where a second island-shaped semiconductor layer to be an active region of a thin film diode is formed later.
  • a step of forming a light shielding layer for shielding light incident from the surface on the opposite side of the substrate may be further included.
  • a first island-shaped semiconductor layer that will later become an active region of a thin film transistor, and at least a part of the light shielding layer, are simultaneously formed.
  • the step (a) includes: (a1) preparing a substrate having an amorphous semiconductor film formed on the surface; and (a2) irradiating the amorphous semiconductor film with a laser beam to thereby form the amorphous semiconductor.
  • a step of forming the first crystalline semiconductor film by crystallizing the film may be included.
  • the step (a) includes (a1) a step of preparing a substrate having an amorphous semiconductor film formed on the surface, and (a2) a step of adding a catalyst element for promoting crystallization to the amorphous semiconductor film. And (a3) performing a heat treatment on the amorphous semiconductor film to which the catalytic element is added to crystallize the amorphous semiconductor film, thereby forming a second crystalline semiconductor film; May be included.
  • the step (d) may be a step of depositing a second crystalline semiconductor film on the gate insulating film by a plasma CVD method.
  • Another semiconductor device of the present invention is a semiconductor device manufactured by any one of the manufacturing methods described above.
  • the display device of the present invention is a display device including a display region having a plurality of display units and a frame region located around the display region, further including an optical sensor unit including a thin film diode, and each display
  • the portion includes an electrode and a thin film transistor connected to the electrode, and the thin film transistor and the thin film diode are formed on the same substrate, and the thin film transistor includes a channel region, a source region, and a drain region.
  • the thin film diode includes a second crystalline semiconductor layer including at least an n-type region and a p-type region, and the second crystalline semiconductor layer includes the gate electrode.
  • the gate insulating film wherein it is formed on the surfaces of the gate insulating film, and the n-type region or the p-type region, and said source and drain regions contain the same impurity element.
  • the display unit further includes a backlight and a backlight control circuit that adjusts the luminance of light emitted from the backlight, and the light sensor unit is an illuminance signal based on the illuminance of external light. And output to the backlight control circuit.
  • each of the plurality of optical touch sensor units includes a plurality of optical touch sensor units each having the optical sensor unit, and each of the plurality of optical touch sensor units corresponds to each display unit or a set of two or more display units. Arranged in the display area.
  • the semiconductor layers of the TFT and the TFD are formed from different semiconductor films. Therefore, these semiconductor layers are required respectively. It can be optimized according to the device characteristics. Accordingly, it is possible to achieve both the device characteristics required for TFT and TFD.
  • a high-performance semiconductor device including TFT and TFD can be easily manufactured without increasing the manufacturing process and manufacturing cost, and the product can be made compact, high-performance, and low-cost. Can be achieved.
  • the second crystalline semiconductor layer that becomes the active layer of the TFD can be formed after the formation of the first crystalline semiconductor layer that becomes the active layer of the TFT, the thickness and crystallinity of each crystalline semiconductor layer Can be individually optimized depending on the characteristics required for the TFT or TFD. In addition, if the doping process for the TFT and TFD semiconductor layers is performed simultaneously, the number of processes can be further reduced.
  • the present invention can be suitably used for a liquid crystal display device with a sensor function.
  • a display device including, for example, a TFT used for a driving circuit and a TFT for switching a pixel electrode and a TFD used as a photosensor, it has a high field effect mobility and a low threshold voltage.
  • a TFT and a TFD having a low dark current value and a high SN ratio to light (current value ratio in light and dark) can be formed on the same substrate.
  • by optimizing the channel region that greatly affects the field effect mobility of the TFT and the semiconductor layer in the intrinsic region that greatly affects the photosensitivity of the TFD it is possible to obtain optimum device characteristics for each semiconductor element. Can do.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
  • FIGS. 3A to 3E are schematic cross-sectional views illustrating manufacturing steps of the semiconductor device according to the first embodiment of the present invention.
  • FIGS. (F) to (H) are schematic cross-sectional views showing manufacturing steps of the semiconductor device according to the first embodiment of the present invention.
  • (A) to (F) are schematic cross-sectional views showing manufacturing steps of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 1 A schematic cross-sectional views illustrating manufacturing steps of the semiconductor device according to the second embodiment of the present invention.
  • A) to (F) are schematic cross-sectional views showing manufacturing steps of the semiconductor device according to the third embodiment of the present invention.
  • (G) to (K) are schematic cross-sectional views showing manufacturing steps of the semiconductor device according to the third embodiment of the present invention.
  • (A) to (E) are schematic cross-sectional views illustrating manufacturing steps of a semiconductor device according to a fourth embodiment of the present invention.
  • (F) to (H) are schematic cross-sectional views illustrating manufacturing steps of the semiconductor device of the fourth embodiment according to the present invention.
  • (I) to (K) are schematic cross-sectional views illustrating manufacturing steps of the semiconductor device of the fourth embodiment according to the present invention.
  • FIG. 10 is a schematic plan view illustrating a back substrate in a touch panel liquid crystal display device according to a fifth embodiment of the invention. It is a perspective view which illustrates the liquid crystal display device with an ambient light sensor of 5th Embodiment by this invention.
  • a semiconductor device of the present invention includes a thin film transistor formed using a first crystalline semiconductor layer and a thin film diode formed using a second crystalline semiconductor layer on the same substrate, and a second crystal
  • the quality semiconductor layer is formed in contact with the surface of the gate insulating film, and the n-type region or p-type region of the thin film diode and the source region and drain region of the thin film transistor contain the same impurity element.
  • FIG. 1A is a sectional view schematically showing a preferred embodiment of a semiconductor device according to the present invention.
  • the semiconductor device 100 includes a substrate 101, a thin film transistor (TFT) and a thin film diode (TFD) supported by the substrate 101.
  • the TFT in this embodiment includes a semiconductor layer 107 including a channel region 115, a source region and a drain region 113, a gate insulating film 108 provided so as to cover the semiconductor layer 107, and a gate insulating film 108.
  • a gate electrode 109 which controls the conductivity of the region 115;
  • the semiconductor layer 107 is a crystalline semiconductor layer.
  • the TFD in this embodiment includes a semiconductor layer 110 including an intrinsic region 119 and an n-type region 114 and a p-type region 118.
  • the semiconductor layer 110 is a crystalline semiconductor layer, and is formed on the gate insulating film 108 in contact with the upper surface of the gate insulating film 108.
  • the n-type region 114 or the p-type region 118 and the source and drain regions 113 contain the same impurity element. That is, if the TFT is a channel type TFT, the source and drain regions 113 and the TFD n-type region 114 contain the same n-type impurity element. If the TFT is a p-channel TFT, the source and drain regions 113 and the p-type region 118 contain the same impurity element. Note that the semiconductor layer 110 only needs to include at least the n-type region 114 and the p-type region 118, and does not need to include the intrinsic region 119.
  • the interlayer insulating layer 130 is formed so as to be in contact with the upper surface of the TFT gate electrode 109 and the upper surface of the TFD semiconductor layer 110.
  • the interlayer insulating layers of the TFT and the TFD are formed of the same insulating film because the manufacturing process can be simplified.
  • the semiconductor layers 107 and 110 of the TFT and TFD are separate layers formed from different crystalline semiconductor films. Therefore, optimum characteristics can be realized for each element. Specifically, the device characteristics required for each device can be obtained by optimizing the film quality, thickness, crystal state, and the like of the semiconductor layers 107 and 110.
  • the crystalline semiconductor layer 107 is used as the active layer as in this embodiment, it is advantageous because high field effect mobility and a low threshold voltage can be realized. Regardless of the characteristics required for the semiconductor layer 110, the formation method, crystal state, thickness, and the like of the semiconductor layer 107 can be selected with a high degree of freedom in order to obtain desired field effect mobility and threshold voltage.
  • a switching TFT that switches pixel electrodes
  • it is required to suppress a leakage current when the TFT is turned off and to have a high ON / OFF ratio.
  • it is effective to set the thickness of the semiconductor layer 107 small.
  • the S value current rising characteristic at the time of the sub-threshold voltage
  • the semiconductor layer 107 is made too thin, a decrease in the current value during the ON operation appears. Therefore, a preferable range of the thickness of the semiconductor layer 107 is, for example, 30 nm to 60 nm.
  • the preferable crystal state and thickness of the semiconductor layer 110 are different from the crystal state and thickness of the semiconductor layer 107 of the TFT.
  • a reverse bias is applied to the TFD to turn it off to capture the increase or decrease in leakage current during light irradiation.
  • the photosensitivity at this time increases as the thickness of the semiconductor layer 110 increases. That is, it is contrary to the preferable thickness of the semiconductor layer 107 of the TFT.
  • high-quality crystallinity as required for the semiconductor layer 107 of the TFT is not required.
  • the semiconductor layer 110 is more amorphous. Is also preferably crystalline. Therefore, it is advantageous to use a crystalline semiconductor layer different from the TFT semiconductor layer 107 as the TFD semiconductor layer 110 and to make the thickness larger than the thickness of the TFT semiconductor layer 107.
  • the n-type region 114 or the p-type region 118 and the source and drain regions 113 are formed by the same doping process.
  • a semiconductor device including the above TFT and TFD on the same substrate 101 can be obtained by a simpler method, and a simple element configuration can be realized.
  • the semiconductor device 100 of the present embodiment has the following merits as compared with the semiconductor devices of Patent Documents 2 and 3 described above.
  • Patent Document 2 a part of the same amorphous semiconductor film is crystallized to form a TFT semiconductor layer, and a part that remains amorphous is used to form a TFD semiconductor layer.
  • this method it is difficult to obtain a TFD having sufficient characteristics as an optical sensor. This is because hydrogen contained in the original amorphous silicon film is lost in the heat treatment step of crystallizing a part of the amorphous silicon film into crystalline silicon.
  • the hydrogen atoms taken in at the time of film formation are combined with dangling bonds of Si atoms to form Si—H bonding, which is Si dangling bonds in the crystalline silicon film are inactivated.
  • Si—H bonding is broken and the Si dangling bond is activated. Since the bond energy of Si—H is about 400 ° C., when heat treatment at 400 ° C. or higher is performed, the bond is broken and hydrogen is released.
  • Si dangling bonds in which hydrogen bonds are broken form deep traps for electrons and holes, and greatly reduce the device performance of TFTs and TFDs.
  • the current value (dark current) in a dark atmosphere is greatly deteriorated and the base is raised.
  • Patent Document 2 an attempt is made to inactivate Si dangling bonds by recombining Si—H by supplying hydrogen to the TFD and TFT semiconductor layers after the crystallization step.
  • the TFD semiconductor layer which is an amorphous silicon layer, contains a large amount of dangling bonds that cannot be compared with a crystalline silicon layer, it is extremely difficult to return it to a good state after film formation.
  • Patent Document 3 half exposure and half etching are performed on the same amorphous silicon film, a part of the amorphous silicon film is thinned, and the film thickness difference between the TFT semiconductor layer and the TFD semiconductor layer is increased. Forming.
  • it is extremely difficult to control the etching at this time which causes the thickness of the thinned region, that is, the thickness of the semiconductor layer of the TFT to fluctuate. If the thickness of the semiconductor layer of the TFT varies, the TFT characteristics are greatly affected. Further, since the region to be thinned, that is, the surface of the semiconductor layer of the TFT is exposed to etching, the surface of the semiconductor layer is damaged by etching, which adversely affects the TFT characteristics and reliability.
  • the TFT semiconductor layer 107 and the TFD semiconductor layer 110 are formed by using different layers of semiconductor films, respectively. Thereby, the thickness and crystal state of these semiconductor layers 107 and 110 can be optimized independently, and film thickness fluctuation and etching damage do not occur.
  • a crystalline semiconductor layer is also used for the TFD semiconductor layer 110.
  • a TFD is used as an optical sensor
  • sensitivity is lower in the visible light region than in a TFD using an amorphous semiconductor layer, but more in the infrared region. High sensitivity is obtained.
  • TFD is used for a forward bias operation such as a reset operation
  • an amorphous semiconductor layer there is a large problem as described above in terms of manufacturing.
  • the method of Patent Document 3 requires an extra etching step for thinning a part of the silicon film, and therefore the increased number of steps is the second formation of the semiconductor film. It is only a process.
  • the thickness of the thinned portion of the silicon film is determined by the accuracy of the etching, and the thickness of the silicon film varies greatly.
  • the thickness of each semiconductor film can be appropriately selected according to the formation process of the semiconductor film for TFT and the semiconductor film for TFD, so that the thickness of each semiconductor film can be controlled more easily. Variations in the thickness of the semiconductor film can be greatly reduced.
  • the thickness d1 of the TFT semiconductor layer 107 is determined by the thickness of the TFT semiconductor film
  • the thickness d2 of the TFD semiconductor layer 110 is determined by the thickness of the TFD semiconductor film.
  • the thicknesses d1 and d2 of the TFT and TFD semiconductor layers 107 and 110 can be set independently. It is preferable to set the thickness d2 of the TFD semiconductor layer 110 to be larger than the thickness d1 of the TFT semiconductor layer 107. Thereby, in the TFT, the ON / OFF ratio can be improved and the threshold voltage can be reduced, so that the TFT performance can be improved. In the TFD, the bright current that is the photosensor sensitivity can be increased. Performance can be increased.
  • the thickness d2 of the TFD semiconductor layer 110 is larger than the sum (d1 + d3) of the thickness d1 of the TFT semiconductor layer 107 and the thickness d3 of the gate insulating film 108. (D2> d1 + d3), TFD performance can be further improved, and the manufacturing process can be further simplified. The reason will be described below.
  • the source and drain regions 113 in the TFT semiconductor layer (first crystalline semiconductor layer) 107 and the n-type region 114 or the p-type region 118 in the TFD semiconductor layer (second crystalline semiconductor layer) 110 are simultaneously doped.
  • the TFT semiconductor layer 107 is through-doping beyond the gate insulating film 108, whereas the TFD semiconductor layer 110 is so-called bare doping in which a dopant is directly implanted. Due to the implantation damage at this time, the crystal structure of the semiconductor layer 107 of the TFT and the semiconductor layer 110 of the TFD which are made of a crystalline material is not a little broken. In the subsequent heat treatment, the crystallinity is restored and the dopant is activated.
  • the n-type region 114 or the p-type region 118 has a high resistance, which may adversely affect device characteristics.
  • the dopant is implanted into the TFD semiconductor layer 110 by bare doping while the implantation is implanted into the TFT semiconductor layer 107 by through doping beyond the gate insulating film 108. Therefore, the implantation damage is caused by the TFD semiconductor. Layer 110 is higher.
  • this doping process must be performed under conditions optimized for the TFT semiconductor layer 107, and under such conditions, the crystal of the TFD semiconductor layer 110 is strongly broken, As a result, the n-type region 114 or the p-type region 118 may become high resistance.
  • each of the semiconductor layers 107 and 110 and the gate insulating film 108 is set so as to satisfy the above relationship d2> d1 + d3, even if the implantation is performed on the TFT semiconductor layer 107 under optimized conditions. , Excessive crystal breakage due to implantation damage to the TFD semiconductor layer 110 can be suppressed, and the resistance of the n-type region 114 or the p-type region 118 can be reduced.
  • FIG. 1B is a schematic partial cross-sectional view illustrating a concentration profile in the thickness direction of impurities doped in the semiconductor layers 107 and 110 in this embodiment.
  • the TFT semiconductor layer 107 is doped with an n-type or p-type impurity element through the thickness d3 of the gate insulating film 108 (through doping).
  • the TFD semiconductor layer 110 is doped with an impurity element directly, that is, without passing through the gate insulating film 108 (bare doping).
  • the concentration profile of the impurity element in the gate insulating film 108 and the semiconductor layer 107 in the depth direction from the upper surface of the gate insulating film 108 is shown by a curve Ct.
  • the concentration profile of the impurity element in the semiconductor layer 110 in the depth direction from the upper surface of the semiconductor layer 110 is indicated by a curve Cd.
  • the concentration profiles Ct and Cd become substantially equal. Accordingly, the depth Dt of the peak of the concentration profile Ct from the upper surface of the gate insulating film 108 is substantially equal to the depth Dd of the peak of the concentration profile Cd from the upper surface of the semiconductor layer 110 (Dt ⁇ Dd).
  • the doping conditions for the TFD semiconductor layer 110 are preferably set such that the peak depth Dd is smaller than the thickness d2 of the semiconductor layer 110 (Dd ⁇ d2).
  • the concentration profile Cd is preferably set to have a peak in the semiconductor layer 110.
  • the concentration profile has a peak in the semiconductor layer means that the concentration profile peak in the thickness direction of the semiconductor layer is located between the upper surface and the lower surface of the semiconductor layer. And the case where the maximum density is on the lower surface.
  • the peak depth Dd is located above the lowermost surface of the semiconductor layer 110 of the TFD, the impurity concentration on the lowermost surface can be kept lower than the peak concentration, and the excessive amount on the lowermost surface of the semiconductor layer 110 is excessive. Crystal breakage can be prevented. For this reason, in the heat treatment after doping, crystal recovery is performed from the lower surface side to the upper surface side of the semiconductor layer 110 in which the crystalline state is maintained. As a result, the n-type region 114 or the p-type region 118 of the TFD can be reduced in resistance, and an optical sensor TFD with a high contrast ratio can be obtained.
  • the peak depth Dd is larger than the thickness d2 of the semiconductor layer 110 (Dd> d2), the crystallinity of the semiconductor layer 110 is destroyed throughout the thickness due to doping, so that the starting point of crystal recovery is It will disappear. For this reason, even if heat treatment is performed after doping, the crystal state cannot be sufficiently recovered. As a result, the n-type region 114 or the p-type region 118 of the TFD has a high resistance, and a desired device performance cannot be obtained.
  • the doping condition for the semiconductor layer 107 of the TFT is set so that the peak depth Dt is smaller than the sum of the thickness d1 of the semiconductor layer 107 and the thickness d3 of the gate insulating film 108 (Dt ⁇ (d1 + d3)). It is preferable.
  • the concentration profile Ct preferably has a peak between the upper surface of the gate insulating film 108 and the lower surface of the semiconductor layer.
  • the source and drain regions 113 of the TFT can be reduced in resistance, and the on-resistance of the TFT can be reduced.
  • the peak depth Dt is larger than the sum of the thickness d1 of the semiconductor layer 107 and the thickness d3 of the gate insulating film 108 (Dt> (d1 + d3))
  • the crystallinity of the semiconductor layer 107 extends over the entire thickness. Therefore, the starting point of crystal recovery disappears, and even if a heat treatment is performed after doping, the crystal state cannot be sufficiently recovered.
  • the resistance of the source and drain regions 113 of the TFT increases, and the desired device performance cannot be obtained.
  • the doping conditions are set so that the peak depth Dt satisfies d3 ⁇ Dt ⁇ d1 + d3.
  • the concentration profile Ct has a peak in the semiconductor layer 107, so that the impurity concentration of the source and drain regions of the TFT can be increased, and the on-resistance of the TFT can be further reduced.
  • the peak depth Dt of the concentration profile Ct and the peak depth Dd of the concentration profile Cd become substantially equal (Dt ⁇ Dd), Dd ⁇ d1 + d3.
  • the peak depth Dd is always Dd ⁇ d2 (Dd ⁇ d1 + d3 ⁇ d2).
  • the doping condition peak depth Dt
  • the doping condition peak depth Dt
  • the doping condition is applied to the TFT semiconductor layer (first crystalline semiconductor layer) 107.
  • impurities are implanted into the TFD semiconductor layer (second crystalline semiconductor layer) 110 relatively deeply with respect to the thickness d2.
  • crystal breakdown due to implantation damage can be suppressed even on the lower surface of the semiconductor layer 110 (interface between the semiconductor layer 110 and the gate insulating film 108).
  • the resistance can be reduced.
  • the doping conditions required for the respective semiconductor layers 107 and 110 can be compatible.
  • the thickness d3 of the gate insulating film 108 is the thickness of the gate insulating film 108 over the source region and the drain region 113 of the semiconductor layer 107. Shall be pointed to.
  • the gate electrode 109 may be formed of the same crystalline semiconductor film as the TFD semiconductor layer 110. Thereby, a manufacturing process can be simplified.
  • a substrate having a light transmitting property such as a glass substrate
  • a light shielding layer (not shown) may be further provided between the TFD semiconductor layer 110 and the substrate 101.
  • the semiconductor layer 110 serving as an active layer needs to react only to external light.
  • a backlight is generally disposed on the back surface of the active matrix substrate (here, the substrate 101), so that the TFD does not detect light from the backlight.
  • a light shielding layer is provided on the backlight side.
  • the light shielding layer is provided at a position where the semiconductor layer 110 serving as an active region of the TFD is shielded from light.
  • it is provided between the semiconductor layer 110 and the substrate 101 so as to overlap with at least part of the semiconductor layer 110.
  • the whole or part of the light shielding layer is preferably formed of the same film as the semiconductor layer of the TFT. Thereby, the manufacturing process can be further simplified.
  • the manufacturing method includes a step of preparing a substrate having a first crystalline semiconductor film formed on the surface, and a portion of the first crystalline semiconductor film, which later becomes an active region of a thin film transistor.
  • the second crystalline semiconductor film for TFD is preferably formed to be thicker than the first crystalline semiconductor film. More preferably, the thickness of the second crystalline semiconductor film for TFD is set to be larger than the total thickness of the first crystalline semiconductor film and the gate insulating film. More preferably, the thickness is set to be larger than the total thickness of the thickness of the region exposed from the gate electrode formed on the gate insulating film in the first crystalline semiconductor film and the thickness of the gate insulating film.
  • the respective semiconductor layers of the TFT and TFD particularly the channel region of the TFT and the intrinsic region of the TFD
  • the optimum state required for each can be created separately.
  • a TFT for a driving circuit used in the driving circuit achieves a high driving capability with a high field-effect mobility and a low threshold voltage, and each pixel In the switching TFT functioning as a switching element, high switching characteristics can be obtained.
  • the TFD can obtain a low dark current and a high bright current, an excellent characteristic (high light / dark ratio (SN ratio)) can be realized as an optical sensor.
  • these two types of semiconductor elements can be manufactured on the same substrate without greatly increasing the number of processes and at a low manufacturing cost.
  • the size (area, thickness) of the semiconductor device is compared with the case where the TFT is formed on the substrate and then the TFD is mounted. ) Can be greatly reduced.
  • a region that becomes a later source region and drain region of the first island-shaped semiconductor layer is formed from above the gate insulating film.
  • a step of doping (through doping) an impurity element a step of directly doping (bare doping) an n-type impurity element into a region to be a later n-type region of the second island-shaped semiconductor layer, A step of directly doping (bare doping) a p-type impurity element into a region to be a later p-type region of the island-shaped semiconductor layer.
  • an n-type or p-type impurity region to be a source region and a drain region can be formed in the TFT semiconductor layer, and an n-type impurity region and a p-type impurity region can be formed in the TFD semiconductor layer.
  • each device can be completed on the same substrate.
  • the through-doping step is performed on the second island-shaped semiconductor layer.
  • this step be performed simultaneously with the step of bare doping an n-type impurity element into a region to be a later n-type region.
  • the through-doping step includes the second island-shaped semiconductor. It is preferable to perform simultaneously with the step of bare doping a p-type impurity element into a region to be a later p-type region in the layer.
  • the doping process for forming the source region and the drain region of the p-channel TFT and the doping process for forming the p-type impurity region of the TFD are performed as the same process, the manufacturing process can be further simplified. .
  • a plurality of first island-shaped semiconductor layers that later become active regions of n-channel thin film transistors and a first island-shaped semiconductor layer that becomes active regions of p-channel thin film transistors are provided on the same substrate.
  • a first island-shaped semiconductor layer may be formed.
  • an n-type impurity element is doped into the first island-shaped semiconductor layer that will later become an n-channel thin film transistor
  • a p-type impurity element is doped into the first island-shaped semiconductor layer that later becomes a p-channel thin film transistor. Doping.
  • the step of through-doping an n-type impurity element into the source region and drain region of the first island-shaped semiconductor layer that will later become an n-channel thin film transistor includes the n-type region after the second island-shaped semiconductor layer. It is preferable to be performed simultaneously with the step of bare doping an n-type impurity element in the region to be.
  • the step of through-doping a p-type impurity element into the source region and the drain region of the first island-shaped semiconductor layer, which will later become a p-channel thin film transistor, includes the following p-type region in the second island-shaped semiconductor layer: Preferably, this step is performed simultaneously with the step of bare doping a p-type impurity element in the region to be formed.
  • the doping process for forming the source region and the drain region of the n-channel TFT and the doping process for forming the n-type impurity region of the TFD are the same process.
  • the doping step for forming the source region and the drain region of the p-channel TFT and the doping step for forming the p-type impurity region of the TFD can be performed as the same step. Can be greatly simplified.
  • the thickness d1 of the first island-like semiconductor layer (that is, the thickness of the first crystalline semiconductor film) d1 and the gate
  • the thickness d3 of the insulating film and the thickness of the second island-shaped semiconductor layer (that is, the thickness of the second crystalline semiconductor film for TFD) d2 satisfy the relationship of d1 + d3 ⁇ d2, FIG. There are advantages as described above with reference to b).
  • the active region of the TFD Impurities are not implanted into the second island-shaped semiconductor layer to be relatively deep with respect to the thickness d2. Therefore, crystal breakdown due to implantation damage is also caused on the lower surface of the second island-like semiconductor layer (the interface between the second island-like semiconductor layer and the gate insulating film) serving as the active region of the TFD.
  • the lower surface of the island-like semiconductor layer can be kept lower.
  • the second island-shaped semiconductor layer although it is bare doping, crystal recovery can be achieved by a subsequent heat treatment, so that the resistance of the n-type region or the p-type region of the TFD can be reduced. In this way, the doping conditions required for each semiconductor layer can be achieved. Therefore, a semiconductor device having a semiconductor layer having an optimum state according to each application and having TFTs and TFDs having good characteristics on the same substrate can be manufactured without increasing the number of manufacturing steps and with low manufacturing. Can be provided at a cost.
  • a step of doping an n-type impurity element into a region to be a later n-type region of the second island-shaped semiconductor layer, and a later p-type region of the second island-shaped semiconductor layer The step of doping the region to be the p-type impurity element is performed in any of the above doping steps between the region to be the n-type region and the region to be the p-type region in the second island-shaped semiconductor layer. Is preferably performed so that a region (intrinsic region) that is not doped is formed.
  • the manufacturing method of this embodiment when forming the gate electrode of the thin film transistor on the gate insulating film, the second crystalline semiconductor film that forms the active region of the TFD is used, and the active region of the thin film diode is formed using the same layer.
  • the manufacturing process can be simplified.
  • a light-transmitting substrate may be used as the substrate in this embodiment.
  • the manufacturing method according to the present embodiment provides a light shielding layer for shielding light from the back surface of the substrate at a lower portion of a region where a second island-shaped semiconductor layer that will later become an active region of the thin film diode is formed. It is preferable to include the process of forming. Thereby, for example, in a liquid crystal display device, backlight light emitted from the back side of the substrate can be effectively blocked, so that the TFD can efficiently sense only light from above. More preferably, the first crystalline semiconductor film is patterned to simultaneously form a first island-shaped semiconductor layer that will later become an active region of the thin film transistor and at least a part of the light shielding layer. Thereby, the manufacturing process can be further simplified.
  • the formation of the first crystalline semiconductor film in the present embodiment includes a step of preparing a substrate having an amorphous semiconductor film formed on the surface, and irradiating the amorphous semiconductor film with laser light to thereby form the amorphous semiconductor film.
  • the step of crystallizing the film may be performed. Thereby, a crystalline semiconductor film having excellent crystallinity is obtained, and high performance of the TFT can be realized.
  • a step of preparing a substrate having an amorphous semiconductor film formed on the surface a step of adding a catalytic element for promoting crystallization to the amorphous semiconductor film, and an amorphous layer to which the catalytic element is added
  • a first crystalline semiconductor film is formed by performing a heat treatment on the semiconductor film to crystallize the amorphous semiconductor film. After adding a metal element that has the effect of promoting crystallization to an amorphous semiconductor film and then performing heat treatment to crystallize, the crystalline semiconductor film is crystallized compared to a crystalline semiconductor film crystallized only by general laser irradiation. A good crystalline semiconductor film with uniform orientation can be obtained. By using this good first crystalline semiconductor film as the active region of the TFT, the performance of the TFT can be further improved.
  • the formation of the second crystalline semiconductor film in the present embodiment may be performed by a step of directly forming the second crystalline semiconductor film on the gate insulating film by plasma CVD.
  • This method is particularly effective when the second crystalline semiconductor film is thick, and the better the crystallinity is, the thicker the second crystalline semiconductor film is. Therefore, it is advantageous to apply this method to the formation of the second crystalline semiconductor film, which is preferably thicker than the first crystalline semiconductor film in terms of TFD characteristics.
  • the heating temperature can be set considering the thermal deformation (thermal shrinkage) of the glass substrate. The lower one is desirable.
  • the substrate heating temperature can be suppressed to 450 ° C. or lower, and the subsequent pattern alignment (alignment) accuracy can be improved.
  • the semiconductor device of this embodiment includes an n-channel TFT and a TFD on the same substrate, and is used as, for example, an active matrix display device including a sensor unit.
  • FIG. 2 is a schematic cross-sectional view showing an example of the semiconductor device of the present embodiment.
  • the semiconductor device of this embodiment typically includes a plurality of TFTs and a plurality of TFDs provided on the same substrate.
  • a configuration of only a single TFT and a single TFD is illustrated. Yes.
  • the semiconductor device of this embodiment includes a thin film transistor 124 and a thin film diode 125 formed on a substrate 101 via base films 103 and 104.
  • the thin film transistor 124 includes a semiconductor layer 107 including a channel region 115 and source / drain regions 113, a gate insulating film 108 provided on the semiconductor layer 107, a gate electrode 109 that controls conductivity of the channel region 115, And electrode / wiring 122 connected to the source region and the drain region 113, respectively.
  • the thin film diode 125 is connected to the semiconductor layer 110 including at least the n-type region 114 and the p-type region 118 formed on the gate insulating film 108 of the thin film transistor, and the n-type region 114 and the p-type region 118, respectively. Electrode / wiring 123.
  • the semiconductor layer 110 of the thin film diode 125 is in contact with the upper surface of the gate insulating film 108.
  • an intrinsic region 119 is provided between the n-type region 114 and the p-type region 118 in the semiconductor layer 110.
  • a silicon nitride film 120 and a silicon oxide film 121 are formed as an interlayer insulating film.
  • a light shielding layer 102 is disposed between the semiconductor layer 110 of the thin film diode 125 and the substrate 101.
  • the semiconductor layer 107 of the thin film transistor 124 and the semiconductor layer 110 of the thin film diode 125 are crystalline semiconductor layers formed using different crystalline semiconductor films.
  • the thickness d2 of the semiconductor layer 110 of the thin film diode 125 is larger than the thickness d1 of the semiconductor layer 107 of the thin film transistor 124.
  • the thickness d2 of the semiconductor layer 110 of the thin film diode 125 is greater than the sum (d1 + d3) of the thickness d1 of the semiconductor layer 107 of the thin film transistor 124 and the thickness d3 of the gate insulating film 108.
  • the n-channel type thin film transistor 124 and the thin film diode 125 as shown in FIG. 2 are manufactured as follows, for example.
  • FIG. 3 and FIG. 4 are process cross-sectional views showing manufacturing steps of the thin film transistor 124 and the thin film diode 125 in this embodiment, and the manufacturing steps sequentially proceed in the order of FIG. 3 (A) ⁇ FIG. 4 (H).
  • a light shielding layer 102, a first base film 103, a second base film 104, and an amorphous semiconductor film 105 are formed in this order on the surface of the substrate 101 where TFTs and TFDs are formed.
  • a low alkali glass substrate or a quartz substrate can be used as the substrate 101.
  • a low alkali glass substrate is used.
  • heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point.
  • the light shielding layer 102 is disposed in the final product so as to block light from the back surface direction of the substrate with respect to the TFD. It can be formed using a metal film or a silicon film. In the case of using a metal film, refractory metal tantalum (Ta), tungsten (W), molybdenum (Mo), or the like is preferable in consideration of heat treatment in a later manufacturing process. In the present embodiment, the Mo film is deposited by sputtering, and is patterned to form the light shielding layer 102. The thickness of the light shielding layer 102 is 30 to 200 nm, preferably 50 to 150 nm. In this embodiment, it is set to 100 nm, for example.
  • the base films 103 and 104 can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like in order to prevent impurity diffusion from the substrate 101.
  • a silicon oxynitride film produced from a material gas of SiH 4 , NH 3 , and N 2 O by a plasma CVD method is formed as the first base film 103 as a lower layer, and plasma is similarly formed thereon.
  • a second base film 104 was formed by CVD using SiH 4 and N 2 O as material gases.
  • the thickness of the silicon oxynitride film of the first base film 103 is 30 to 400 nm, for example 200 nm, and the thickness of the silicon oxide film of the second base film 104 is 50 to 300 nm, for example 100 nm.
  • a two-layer base film is used, but a single-layer (for example, silicon oxide film) base film may be used.
  • a silicon film (a-Si film) having an amorphous structure is formed by using a known method such as a plasma CVD method or a sputtering method.
  • the thickness of the a-Si film 105 is set to 20 nm to 100 nm, preferably 30 to 70 nm.
  • an a-Si film (thickness: 50 nm) 105 is formed by plasma CVD. Note that since the base films 103 and 104 and the amorphous silicon film 105 can be formed by the same film formation method, both may be formed continuously. After the formation of the base film, it is possible to prevent contamination of the surface by not exposing it to the air atmosphere, and it is possible to reduce variations in characteristics of TFTs to be manufactured and variations in threshold voltage.
  • the a-Si film 105 is heated at a heating temperature of 400 to 550 ° C. for several tens of minutes to several hours to release hydrogen in the a-Si film 105. Thereafter, as shown in FIG. 3B, the laser beam 106 is irradiated. As a result, the a-Si film 105 is crystallized in the process of melting and solidifying by irradiation with the laser beam 106 to become a crystalline silicon film (first crystalline silicon film) 105c.
  • the reason for performing a heat treatment for dehydrogenation of the a-Si film 105 prior to the crystallization process by laser irradiation is that the a-Si film formed by a general CVD method contains a large amount of hydrogen. Therefore, if the laser is irradiated as it is, hydrogen bumping occurs and film jump occurs.
  • a XeCl excimer laser (wavelength: 308 nm) or a KrF excimer laser (wavelength: 248 nm) can be applied.
  • the beam size of the laser beam 106 is formed to be a long shape on the surface of the substrate 101, and the entire surface of the substrate is crystallized by sequentially scanning in the direction perpendicular to the long direction. At this time, it is preferable to perform scanning so that parts of the beams overlap each other, because laser irradiation is performed a plurality of times at any one point of the a-Si film 105, and uniformity can be improved.
  • the beam size is formed to be a long shape of 300 mm ⁇ 0.4 mm on the surface of the substrate 101, and scanning is sequentially performed with a step width of 0.02 mm in a direction perpendicular to the long direction. . That is, a total of 20 laser irradiations are performed at an arbitrary point on the silicon film.
  • a laser that can be used at this time a YAG laser, a YVO 4 laser, or the like can be used in addition to the aforementioned pulse oscillation type or continuous emission type KrF excimer laser and XeCl excimer laser.
  • the laser irradiation energy density is 250 to 450 mJ / cm 2 , for example, 350 mJ / cm 2 .
  • an unnecessary region of the first crystalline silicon film 105c is removed and element isolation is performed.
  • an island-shaped semiconductor layer 107 that later becomes an active region (source / drain region, channel region) of the TFT is obtained.
  • a gate insulating film 108 is formed so as to cover the island-shaped semiconductor layer 107. Further, the gate electrode 109 of the later TFT and the active region (n-type region, p-type) of the later TFD are formed. An island-like semiconductor layer 110 that becomes a region, an intrinsic region) is formed.
  • a silicon oxide film with a thickness of 20 to 150 nm is preferably used, and here, a silicon oxide film with a thickness of 100 nm is used.
  • the gate electrode 109 can be formed by depositing a conductive film on the gate insulating film 108 using a sputtering method, a CVD method, or the like, and patterning the conductive film.
  • a material for the conductive film at this time it is desirable to use any of refractory metals W, Ta, Ti, Mo, or alloy materials thereof.
  • the thickness of the conductive film is preferably 300 to 600 nm. In this embodiment, a molybdenum (Mo) film having a thickness of 450 nm is used as the conductive film.
  • the island-like semiconductor layer 110 is formed by forming a second crystalline silicon film on the gate insulating film 108 and patterning it.
  • the second crystalline silicon film can be formed using a plasma CVD method using SiH 4 gas as a material and a substrate heating temperature of 300 to 450 ° C.
  • hydrogen is used as the diluent gas, and the hydrogen dilution rate (SiH 4 / H 2 ) is set to 1/50 or less, so that the crystalline component is included together with the film formation.
  • the hydrogen dilution rate SiH 4 / H 2
  • Ar gas may be added to the dilution gas.
  • the pressure was 1 to 4 Torr, for example 2.5 Torr, and the RF power was 0.2 to 3 kW / m 2 , for example 2 kW / m 2 .
  • the second crystalline silicon film is directly formed.
  • “directly forming” a crystalline semiconductor film such as a crystalline silicon film refers to depositing a crystalline semiconductor film. For example, an amorphous semiconductor film is first deposited, and the crystalline semiconductor film is crystallized. It does not include the case where a crystalline semiconductor film is formed by forming.
  • the order of forming the gate electrode 109 and the semiconductor layer 110 is not particularly limited.
  • the thickness d2 of the island-shaped semiconductor layer 110 is preferably set so as to be larger than the thickness d1 (here, 50 nm) of the semiconductor layer 107 serving as the active region of the TFT. More preferably, the thickness is set to be larger than the sum (here, 150 nm) of the thickness d3 (here, 100 nm) of the gate insulating film 108 and the thickness d1 of the semiconductor layer 107.
  • the thickness d2 of the island-shaped semiconductor layer 110 is 250 nm.
  • a mask 111 made of a resist is formed so as to cover a part of the island-shaped semiconductor layer 110 that later becomes an active region of the TFD.
  • the entire surface of the substrate 101 is ion-doped with an n-type impurity (phosphorus) 112.
  • the ion doping of the phosphorus 112 is performed through the gate insulating film 108 in the island-shaped semiconductor layer 107 serving as the active region of the TFT, and is bare in the island-shaped semiconductor layer 110 serving as the active region of the TFD. Done in state.
  • phosphorus 112 is implanted into the region exposed from the resist mask 111 in the island-like semiconductor layer 110 of TFD and the region exposed from the gate electrode 109 in the semiconductor layer 107 of TFT.
  • the region covered with the resist mask 111 or the gate electrode 109 is not doped with phosphorus 112.
  • the region in which the phosphorus 112 is implanted in the semiconductor layer 107 of the TFT becomes the source region and the drain region 113 of the later TFT, and the region where the phosphorus 112 is not implanted by being masked by the gate electrode 109 It becomes the channel region 115 of the TFT.
  • the region into which phosphorus 112 is implanted becomes an n + region 114 of the later TFD.
  • the semiconductor layer serving as the active layer of the TFT since the thickness d1 of the semiconductor layer 107, the thickness d2 of the semiconductor layer 110, and the thickness d3 of the gate insulating film 108 satisfy the relationship d1 + d3 ⁇ d2, the semiconductor layer serving as the active layer of the TFT
  • the doping conditions can be optimized with respect to 107, and the resistance of the source and drain regions 113 can be reduced.
  • no impurity is implanted into the semiconductor layer 110 serving as an active layer of the TFD deeply relative to the thickness d2.
  • the doping damage in the vicinity of the lower surface of the semiconductor layer 110 is suppressed to be lower than that of the semiconductor layer 107 serving as the active layer of the TFT.
  • a mask 116 made of resist is formed so as to cover the entire island-like semiconductor layer 107.
  • the entire surface of the substrate 101 is ion-doped with p-type impurities (boron) 117.
  • boron 117 is implanted into a region exposed from the resist mask 116 in the island-like semiconductor layer 110 of TFD. The region covered with the resist mask 116 is not doped with boron 117.
  • the region where boron 117 is implanted becomes the p + region 118 of the later TFD, and boron 117 is not implanted in the region where phosphorus is not implanted in the previous step.
  • the region becomes a later intrinsic region 119.
  • the source / drain region 113 of the TFT and the n + region 114 and the p + region 118 of the TFD are recovered from doping damage such as crystal defects generated during the doping, and the doped phosphorus and boron are activated respectively.
  • the semiconductor layers 107 and 110 if the thicknesses d1, d2, and d3 are adjusted so as to suppress damage on the lower surface of the semiconductor layer, the semiconductor layers 107 and 110 have a smaller crystal breakdown than the lower surface side. Recrystallization occurs.
  • the good crystal state is recovered and the resistance is further reduced.
  • a general heating furnace may be used, but it is more preferable to use RTA (Rapid Thermal Annealing).
  • RTA Rapid Thermal Annealing
  • a system in which high temperature inert gas is blown onto the substrate surface and the temperature is raised and lowered instantaneously is suitable.
  • a silicon oxide film or a silicon nitride film is formed as interlayer insulating films 120 and 121.
  • an interlayer insulating film having a two-layer structure of a silicon nitride film 120 and a silicon oxide film 121 is formed.
  • annealing is performed at 350 to 450 ° C. in a nitrogen atmosphere of 1 atm or in a hydrogen mixed atmosphere, and the TFT semiconductor layer 107 and the TFD semiconductor layer 110 are hydrogenated to reduce crystal defects. That is, the dangling bonds in the crystalline semiconductor layer 107 of the TFT and the crystalline semiconductor layer 110 of the TFD are terminated and deactivated by hydrogen atoms, thereby improving the crystal quality.
  • the silicon nitride film 120 is formed so as to contain hydrogen, it is efficient because hydrogen can be used from the silicon nitride film 120.
  • contact holes are formed in the silicon nitride film 120 and the silicon oxide film 121 which are interlayer insulating films, and the TFT electrode / wiring 122 and the TFD electrode / wiring 123 are made of a metal material. And form. Thereby, the thin film transistor 124 and the thin film diode 125 are completed. If necessary, a protective film made of a silicon nitride film or the like may be provided on the thin film transistor 124 and the thin film diode 125 for the purpose of protecting these elements.
  • the respective semiconductor layers of the TFT and TFD in particular, the channel region of the TFT and the intrinsic region of the optical sensor TFD can be created separately. As a result, optimum element characteristics required for each of the TFT and the optical sensor TFD can be simultaneously realized.
  • the method of manufacturing a semiconductor device according to the present embodiment includes a step of forming a TFT semiconductor layer by crystallizing an amorphous semiconductor film using a catalytic element, and a TFT gate electrode and a TFD semiconductor layer. Is different from the manufacturing method of the first embodiment described above in that it is formed from the same crystalline semiconductor film.
  • FIG. 5 and 6 are cross-sectional views showing manufacturing steps of the thin film transistor 228 and the thin film diode 229 described here, and the manufacturing steps sequentially proceed in the order of FIG. 5 (A) ⁇ FIG. 6 (J).
  • a light shielding layer 202, a first base film 203, a second base film 204, and an amorphous semiconductor film 205 are formed in this order on the surface of a glass substrate 201 on which TFTs and TFDs are formed. Form with.
  • the light shielding layer 202 is disposed in the final product so as to block light from entering the TFD semiconductor layer from the back side of the substrate.
  • the Mo film is deposited by sputtering, and this is patterned to form the light shielding layer 202.
  • the thickness of the light shielding layer 202 is, for example, 100 nm.
  • the base films 203 and 204 can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like in order to prevent impurity diffusion from the substrate 201.
  • a silicon nitride film is formed as the first base film 203 as a lower layer, and a silicon oxide film is formed thereon as the second base film 204.
  • the thickness of the silicon nitride film of the first base film 203 is, for example, 200 nm, and the thickness of the silicon oxide film of the second base film 204 is, for example, 100 nm.
  • a two-layer base film is used, but a single-layer (for example, silicon oxide film) base film may be used.
  • a silicon film (a-Si film) having an amorphous structure is formed by using a known method such as a plasma CVD method or a sputtering method.
  • the thickness of the a-Si film 205 is set to 20 nm to 100 nm, preferably 30 to 70 nm.
  • an a-Si film (thickness: 50 nm) 205 is formed by plasma CVD. Note that since the base films 203 and 204 and the a-Si film 205 can be formed by the same film formation method, they may be formed continuously.
  • a catalyst element is added to the surface of the a-Si film 205.
  • An aqueous solution nickel acetate aqueous solution
  • a catalyst element in this embodiment, nickel
  • the catalyst element that can be used here is one selected from iron (Fe), cobalt (Co), tin (Sn), lead (Pb), palladium (Pd), and copper (Cu) in addition to nickel (Ni). Or it is more than one kind of element.
  • ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), etc. also function as catalytic elements.
  • the amount of the catalytic element to be doped is extremely small, and the concentration of the catalytic element on the surface of the a-Si film 205 is managed by the total reflection X-ray fluorescence (TRXRF) method. In this embodiment, it is about 5 ⁇ 10 12 atoms / cm 2 .
  • the surface of the a-Si film 205 may be slightly oxidized with ozone water or the like in order to improve the wettability of the surface of the a-Si film 205 during spin coating.
  • a method of doping nickel by spin coating is used.
  • a thin film containing a catalytic element in this embodiment, nickel film
  • a thin film containing a catalytic element is deposited on the a-Si film 205 by vapor deposition or sputtering. You may take the means to form.
  • heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere.
  • This heat treatment is preferably performed at 550 to 620 ° C. for 30 minutes to 4 hours.
  • the heat processing for 1 hour were performed at 590 degreeC as an example.
  • nickel added to the surface of the a-Si film is diffused into the a-Si film 205 and silicidation occurs, and crystallization of the a-Si film 205 proceeds using this as a nucleus.
  • the a-Si film 205 is crystallized into a crystalline silicon film 205a.
  • crystallization is performed here by heat treatment using a furnace, crystallization may be performed by an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source.
  • the crystalline silicon film 205a obtained by the heat treatment is irradiated with a laser beam 207, whereby the crystalline silicon film 205a is further recrystallized to improve crystallinity.
  • the formed crystalline silicon film 205b is formed.
  • an XeCl excimer laser (wavelength 308 nm) or a KrF excimer laser (wavelength 248 nm) can be applied.
  • the beam size of the laser light is formed to be a long shape on the surface of the substrate 201, and the entire surface of the substrate is recrystallized by sequentially scanning in a direction perpendicular to the long direction.
  • the beam size is formed to be a long shape of 300 mm ⁇ 0.4 mm on the surface of the substrate 201, and scanning is performed sequentially with a step width of 0.02 mm in the direction perpendicular to the long direction. It was. That is, a total of 20 laser irradiations are performed at an arbitrary point of the crystalline silicon film 205a.
  • a YAG laser, a YVO 4 laser, or the like can be used in addition to the above-described pulse oscillation type or continuous emission type KrF excimer laser and XeCl excimer laser.
  • the irradiation energy density 250 ⁇ 450mJ / cm 2, for example, to 330 mJ / cm 2.
  • the energy density of the laser beam is too high, there is a limitation that the crystalline state of the crystalline silicon film 205a obtained in the previous process is reset. Therefore, it is desirable to set it slightly lower than in the first embodiment.
  • the crystalline silicon film 205a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 205b.
  • the crystal plane orientation of the crystalline silicon region 205b thus obtained is almost determined in the solid phase crystallization process using the catalytic element, and is mainly composed of the ⁇ 111> crystal zone plane.
  • Plane orientation and (211) plane orientation have a characteristic plane orientation such that 50% or more of the entire region is occupied.
  • the domain diameter of the crystal domain was 2 to 5 ⁇ m.
  • an unnecessary region of the crystalline silicon film 205b is removed and element isolation is performed.
  • an island-shaped semiconductor layer 208 that later becomes an active region (source / drain region, channel region) of the TFT is obtained.
  • a gate insulating film 209 that covers the island-shaped semiconductor layer 208 is formed, and a second crystalline silicon film 210 is further formed thereon.
  • a silicon oxide film with a thickness of 20 to 150 nm is preferably used.
  • a silicon oxide film with a thickness of 100 nm is used.
  • the second crystalline silicon film 210 is formed by directly depositing a crystalline silicon film using a plasma CVD method using SiH 4 gas as a material under the same conditions as in the first embodiment. In the present embodiment, the thickness of the second crystalline silicon film 210 is 300 nm.
  • the method for forming the second crystalline silicon film is not limited to the above method, and the amorphous silicon film used when forming the first crystalline silicon film in the present embodiment is used.
  • Other crystallization methods such as a method of adding a catalytic element and crystallizing by heat treatment, and a method of crystallizing an amorphous silicon film by irradiating a laser beam can also be used.
  • the second crystalline silicon film 210 is patterned, and a semiconductor layer 211 to be a gate electrode of the TFT and an active region (n-type region, p-type region) of the later TFD Insular semiconductor layer 212 to be an intrinsic region) is formed.
  • the thickness d2 of the island-shaped semiconductor layer 212 is preferably set to be larger than the thickness d1 (here, 50 nm) of the semiconductor layer 208 to be the active region of the TFT. More preferably, the thickness is set to be larger than the sum of the thickness d3 (here, 100 nm) of the gate insulating film 209 and the thickness d1 of the semiconductor layer 208 (here, 150 nm).
  • the thickness d2 of the island-shaped semiconductor layer 212 is substantially equal to the thickness of the second crystalline silicon film 210, for example, 300 nm.
  • a mask 213 made of resist is formed so as to cover part of the island-shaped semiconductor layer 212 that will later become an active region of the TFD.
  • an n-type impurity (phosphorus) 214 is ion-doped on the entire surface from above the substrate 201.
  • ion doping of phosphorus 214 is performed through the gate insulating film 209 in the island-shaped semiconductor layer 208 serving as the active region of the TFT, and is bare in the island-shaped semiconductor layer 212 serving as the active region of the TFD. Done in state.
  • phosphorus 214 is implanted into a region exposed from the resist mask 213 in the TFD island-like semiconductor layer 212 and a region exposed from the semiconductor layer 211 in the semiconductor layer 208 of the TFT. Also, phosphorus 214 is implanted into the semiconductor layer 211 made of crystalline silicon in a bare state, and a gate electrode 216 made of n-type crystalline silicon is obtained. The semiconductor layer in the region covered with the resist mask 213 or the gate electrode 216 is not doped with phosphorus 214.
  • regions of the TFT semiconductor layer 208 where phosphorus 214 is implanted become source and drain regions 215 of the subsequent TFT, and regions where phosphorus 214 is not implanted due to masking by the gate electrode 216 It becomes the channel region 218 of the TFT.
  • the region into which phosphorus 214 is implanted becomes an n + region 217 of the later TFD.
  • the semiconductor layer 208 it is preferable to optimize the doping conditions for the semiconductor layer 208 to be the active layer of the TFT. Thereby, the resistance of the source region and the drain region 215 can be reduced.
  • the thickness d1 of the semiconductor layer 208, the thickness d2 of the semiconductor layer 212, and the thickness d3 of the gate insulating film 209 satisfy the relationship d1 + d3 ⁇ d2, in this doping step, the active layer of the TFD Impurities are not implanted into the resulting semiconductor layer 212 deeper than the thickness d2.
  • doping damage in the vicinity of the lower surface of the semiconductor layer 212 is suppressed to be lower than that of the semiconductor layer 208 serving as an active layer of the TFT.
  • the gate electrode 216 is similar to the semiconductor layer 212 serving as the active layer of the TFD, the doping damage near the lower surface of the gate electrode 216 is the semiconductor layer 208 serving as the active layer of the TFT despite the bare doping. Is kept lower.
  • a resist mask 219 is formed so as to cover the entire island-shaped semiconductor layer 208.
  • the entire surface of the substrate 201 is ion-doped with p-type impurities (boron) 220.
  • boron 220 is implanted into a region exposed from the resist mask 219 in the island-like semiconductor layer 212 of the TFD. The region covered by the resist mask 219 is not doped with boron 220.
  • the region into which boron 220 is implanted becomes the p + region 221 of the later TFD, and boron 220 is not implanted in the region where phosphorus is not implanted in the previous step.
  • the region becomes a later intrinsic region 222.
  • this is heat-treated in an inert atmosphere, for example, in a nitrogen atmosphere.
  • an inert atmosphere for example, in a nitrogen atmosphere.
  • the source / drain region 215 of the TFT, the n + region 217 and the p + region 221 of the TFD, and the gate electrode 216 of the TFT are recovered from doping damage such as crystal defects generated during doping, and are doped in each. Activates phosphorus and boron.
  • damage to the lower surface of the semiconductor layer is suppressed as described above.
  • Recrystallization occurs from the lower surface side of the semiconductor layer having a small breakdown toward the upper surface side. For this reason, the source / drain region 215 of the TFT, the n + region 217 and the p + region 221 of the TFD, and the gate electrode 216 of the TFT all recover a good crystal state. As a result, the resistance of these regions is reduced. Is done.
  • phosphorus doped in the source / drain region 215 increases the solid solubility of nickel in that region, and the nickel existing in the channel region 218 is removed.
  • the channel region 218 is moved from the channel region 218 to the source / drain region 215 in the direction indicated by the arrow 223.
  • the nickel concentration in these regions is higher than that of the channel region 218 and is 1 ⁇ 10 18 / cm 3 or more.
  • a general heating furnace may be used, but RTA (Rapid Thermal Annealing) is more desirable.
  • RTA Rapid Thermal Annealing
  • a system in which high temperature inert gas is blown onto the substrate surface and the temperature is raised and lowered instantaneously is suitable.
  • silicon oxide films or silicon nitride films are formed as interlayer insulating films 224 and 225.
  • an interlayer insulating film having a two-layer structure of a silicon nitride film 224 and a silicon oxide film 225 is formed.
  • annealing is performed at 350 to 450 ° C. in a nitrogen atmosphere of 1 atm or in a hydrogen mixed atmosphere, and the semiconductor layer 208 of the TFT and the semiconductor layer 212 of the TFD are hydrogenated to reduce crystal defects.
  • the dangling bonds in the crystalline semiconductor layer 208 of the TFT and the crystalline semiconductor layer 212 of the TFD are terminated by hydrogen atoms and deactivated, thereby improving the crystal quality.
  • the silicon nitride film 224 is formed so as to contain hydrogen, it is efficient because hydrogen can be used from the silicon nitride film 224.
  • a TFT electrode / wiring 226 and a TFD electrode / wiring 227 are formed of a metal material.
  • the thin film transistor 228 and the thin film diode 229 are completed.
  • a protective film made of a silicon nitride film or the like may be provided on the thin film transistor 228 and the thin film diode 229 for the purpose of protecting these elements.
  • the respective semiconductor layers of the TFT and TFD in particular, the channel region of the TFT and the intrinsic region of the optical sensor TFD can be created separately.
  • optimum element characteristics required for each of the TFT and the optical sensor TFD can be realized simultaneously.
  • the crystalline semiconductor layer of the TFT is formed by utilizing crystallization by a catalytic element, the TFT performance can be further improved as compared with the first embodiment, and the circuit configuration having a high current driving capability. Etc. are obtained.
  • the semiconductor layer which becomes the active region of the TFD and the gate electrode of the TFT are formed using the same crystalline silicon film (second crystalline silicon film), the manufacturing process can be simplified. Manufacturing cost can be reduced.
  • both the TFD and TFT semiconductor layers are formed by crystallizing an amorphous semiconductor film using a catalytic element.
  • a TFD light shielding layer is formed using the same crystalline semiconductor film as the TFT semiconductor layer, and a TFT gate electrode is formed using the same crystalline semiconductor film as the TFD semiconductor layer.
  • FIG. 7 and 8 are cross-sectional views showing manufacturing steps of the thin film transistor 330 and the thin film diode 331 described here, and the manufacturing steps sequentially proceed in the order of FIG. 7 (A) ⁇ FIG. 8 (K).
  • the first and second base films are formed.
  • 302 and 303 are formed in this order.
  • a silicon nitride film is used as the first base film 302
  • a silicon oxide film is used as the second base film 303.
  • an amorphous silicon (a-Si) film 304 having a thickness of 30 to 80 nm, for example, 50 nm is formed.
  • the base films 302 and 303 and the a-Si film 304 may be formed continuously without being released to the atmosphere.
  • a catalyst element is added to the surface of the a-Si film 304.
  • nickel is used as a catalytic element, and an aqueous solution (nickel acetate aqueous solution) containing, for example, 5 ppm of nickel in terms of weight is applied to the a-Si film 304 by spin coating as in the second embodiment.
  • a catalyst element-containing layer 305 is formed.
  • the concentration of the catalytic element on the surface of the a-Si film 304 is about 5 ⁇ 10 12 atoms / cm 2 .
  • heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere.
  • an annealing treatment at 550 to 620 ° C. for 30 minutes to 4 hours.
  • heat treatment is performed at a temperature of 600 ° C. for 1 hour and 30 minutes.
  • nickel added to the surface of the a-Si film 304 is diffused into the a-Si film 304 and silicidation occurs, and the a-Si film 304 is crystallized using this as a nucleus. In this way, a crystalline silicon film 304a is obtained as shown in FIG.
  • the crystalline silicon film 304a obtained by the heat treatment is irradiated with a laser beam 306, whereby the crystalline silicon film 304a is further recrystallized to improve crystallinity.
  • a crystalline silicon film 304b is formed.
  • the laser beam 306 a XeCl excimer laser (wavelength: 308 nm) is used as in the first and second embodiments.
  • an unnecessary region of the crystalline silicon region 304b is removed and element isolation is performed.
  • an island-shaped semiconductor layer 307 to be an active region (source / drain region, channel region) of the TFT later and an island-shaped semiconductor layer 308 to be a light-shielding layer of the later TFD are obtained.
  • the semiconductor layer 308 is disposed so as to block light from the back side of the substrate with respect to the TFD semiconductor layer.
  • a gate insulating film 309 is formed so as to cover the island-shaped semiconductor layer 307 serving as an active region of the TFT and the island-shaped semiconductor layer 308 serving as a light-shielding layer of the TFD.
  • a second amorphous silicon (a-Si) film 310 is formed thereon.
  • a catalytic element is added to the second amorphous silicon film 310 to form a catalytic element-containing layer 311.
  • the gate insulating film 309 a silicon oxide film having a thickness of 20 to 150 nm is preferably used, and a 100 nm silicon oxide film is used here.
  • the second a-Si film 310 is formed using a plasma CVD method.
  • the thickness of the second a-Si film 310 is set to 300 nm.
  • the gate insulating film 309 and the second a-Si film 310 may be continuously formed by a plasma CVD method.
  • the catalyst element-containing layer 311 uses nickel as a catalyst element, and an aqueous solution (nickel acetate aqueous solution) containing, for example, 25 ppm of nickel in terms of weight is applied to the second a-Si film 310 by spin coating. Can be formed. At this time, the concentration of the catalytic element on the surface of the second a-Si film 310 is about 2 ⁇ 10 13 atoms / cm 2 .
  • heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere.
  • an annealing treatment it is preferable to perform an annealing treatment at a temperature of 550 to 620 ° C. for 30 minutes to 4 hours.
  • heat treatment is performed at a temperature of 590 ° C. for 1 hour.
  • nickel added to the surface of the second a-Si film 310 is diffused into the a-Si film 310 and silicidation occurs, and the second a-Si film 310 is crystallized using this as a nucleus. Is done. In this way, a second crystalline silicon film 310a is obtained as shown in FIG.
  • the second crystalline silicon film 310a is patterned to form a semiconductor layer 312 to be a gate electrode of the TFT and an active region (n-type region, p-type region) of the TFD later.
  • the thickness d2 of the island-shaped semiconductor layer 313 is preferably set to be larger than the thickness d1 (here, 50 nm) of the semiconductor layer 307 serving as the active region of the TFT.
  • the thickness is set to be larger than the sum (here, 150 nm) of the thickness d3 (here, 100 nm) of the gate insulating film 309 and the thickness d1 of the semiconductor layer 307.
  • the thickness d2 of the island-shaped semiconductor layer 313 is equal to the thickness of the second crystalline silicon film 310a and is 300 nm.
  • a mask 314 made of resist is formed so as to cover part of the island-shaped semiconductor layer 313 to be an active region of the TFD later.
  • the entire surface of the substrate 301 is ion-doped with n-type impurities (phosphorus) 315.
  • phosphorus 315 is performed through the gate insulating film 309 in the island-shaped semiconductor layer 307 serving as the active region of the TFT, and is bare in the island-shaped semiconductor layer 313 serving as the active region of the TFD. Done in state.
  • phosphorus 315 is formed in a region exposed from the resist mask 314 in the TFD island-shaped semiconductor layer 313 and in a region exposed from the semiconductor layer (later gate electrode) 312 in the semiconductor layer 307 of the TFT. Injected. Further, phosphorus 315 is implanted into the semiconductor layer 312 made of crystalline silicon in a bare state to obtain a gate electrode 317 made of n-type crystalline silicon. The semiconductor layer in the region covered with the resist mask 314 or the gate electrode 317 is not doped with phosphorus 315.
  • regions of the TFT semiconductor layer 307 where phosphorus 315 is implanted become source and drain regions 316 of the later TFT, and regions where phosphorus 315 is not implanted after being masked by the gate electrode 317 This becomes the channel region 319 of the TFT.
  • the region into which phosphorus 315 is implanted becomes an n + region 318 of the later TFD.
  • the thickness d1 of the semiconductor layer 307, the thickness d2 of the semiconductor layer 313, and the thickness d3 of the gate insulating film 309 satisfy the relationship d1 + d3 ⁇ d2. Therefore, even if the doping conditions are optimized for the semiconductor layer 307 serving as the active layer of the TFT and the resistance of the source and drain regions 316 is reduced, the semiconductor layer 313 serving as the active layer of the TFD has a thickness d2.
  • impurities are not implanted to a relatively deep depth. Therefore, in spite of bare doping, doping damage in the vicinity of the lower surface of the semiconductor layer 313 can be suppressed to be lower than that of the semiconductor layer 307 serving as the active layer of the TFT.
  • the gate electrode 317 is also similar to the semiconductor layer 313 serving as the TFD active layer, the doping damage near the lower surface of the gate electrode 317 is caused by the semiconductor layer 307 serving as the TFT active layer despite the bare doping. Can be kept lower.
  • a mask 320 made of resist is formed so as to cover the entire island-shaped semiconductor layer 307.
  • the entire surface of the substrate 301 is ion-doped with p-type impurities (boron) 321.
  • boron 321 is implanted into a region of the TFD island-shaped semiconductor layer 313 exposed from the resist mask 320.
  • the region covered with the resist mask 320 is not doped with boron 321.
  • the region where boron 321 is implanted becomes the p + region 322 of the later TFD, and boron 321 is not implanted among the regions where phosphorus is not implanted in the previous step.
  • the region becomes an intrinsic region 323.
  • this is heat-treated in an inert atmosphere, for example, in a nitrogen atmosphere.
  • an inert atmosphere for example, in a nitrogen atmosphere.
  • Recrystallization occurs from the lower surface side of the semiconductor layer having a small size toward the upper surface.
  • the crystal states of the TFT source / drain region 316, the TFD n + region 318 and p + region 322, and the TFT gate electrode 317 are recovered, and the resistance of these regions can be reduced.
  • phosphorus doped in the source / drain region 316 increases the solid solubility of nickel in the region 316 and the nickel existing in the channel region 319 is present. Is moved from the channel region 319 to the source / drain region 316 in the direction indicated by the arrow 324. As a result, since nickel moves to the source / drain region 316 of the TFT, the nickel concentration in these regions 316 is higher than that of the channel region 319 and becomes 1 ⁇ 10 18 / cm 3 or more. In the TFD semiconductor layer 313, phosphorus doped in the n + region 318 increases the solid solubility of nickel in the region 318, and nickel existing in the intrinsic region 323 is changed from the intrinsic region 323.
  • n + region 318 Move to n + region 318 in the direction indicated by arrow 325.
  • the nickel concentration in these regions is higher than that of the intrinsic region 323 and becomes 1 ⁇ 10 18 / cm 3 or more.
  • interlayer insulating films 326 and 327 are formed.
  • an interlayer insulating film having a two-layer structure of a silicon nitride film 326 and a silicon oxide film 327 is formed.
  • annealing is performed at 350 to 450 ° C. in a nitrogen atmosphere of 1 atm or in a hydrogen mixed atmosphere, and the TFT semiconductor layer 307 and the TFD semiconductor layer 313 are hydrogenated to reduce crystal defects.
  • the silicon nitride film 326 is formed so as to contain hydrogen, it is efficient because hydrogen can be used from the silicon nitride film 326.
  • a TFT electrode / wiring 328 and a TFD electrode / wiring 329 are formed of a metal material.
  • the thin film transistor 330 and the thin film diode 331 are completed.
  • a protective film made of a silicon nitride film or the like may be provided on the thin film transistor 330 and the thin film diode 331 for the purpose of protecting these elements.
  • the semiconductor layers of the TFT and the TFD, and further the channel region of the TFT and the intrinsic region of the optical sensor TFD can be created separately.
  • optimum element characteristics required for each of the TFT and the optical sensor TFD can be realized simultaneously.
  • a TFD light-shielding layer is formed using the same semiconductor film as the TFT semiconductor layer, and a TFT gate insulating film is formed using the same semiconductor film as the TFD semiconductor layer. Therefore, the manufacturing process can be further simplified and the cost can be reduced.
  • a fourth embodiment of the semiconductor device according to the present invention will be described.
  • a display pixel TFT and its auxiliary capacitor (capacitor), a driving CMOS configuration TFT circuit, and a photosensor TFD will be described more specifically as an example on a glass substrate.
  • the semiconductor device of this embodiment can be used for an active matrix liquid crystal display device with a built-in optical sensor, an organic EL display device, or the like.
  • FIG. 9 to 11 show an n-channel thin film transistor 431 and a p-channel thin film transistor 432 for driver circuit described here, an n-channel thin film transistor 433 for driving a pixel electrode, an auxiliary capacitor 434 connected thereto, and a thin film diode 435 for an optical sensor.
  • FIG. 9 is a cross-sectional view showing the manufacturing process of FIG. 9, and the manufacturing process proceeds sequentially in the order of FIG. 9A ⁇ FIG. 11K.
  • a light shielding layer 402 is formed on the surface of the glass substrate 401 on which TFTs and TFDs are to be formed so as to block light from the back side of the substrate in the subsequent TFD.
  • the light shielding layer 402 may be a metal film or a silicon film.
  • a molybdenum (Mo) film is formed by sputtering, and this is patterned to form the light shielding layer 402.
  • the thickness of the light shielding layer 402 is preferably 30 to 300 nm, more preferably 50 to 200 nm.
  • the thickness of the light shielding layer 402 in the present embodiment is, for example, 100 nm.
  • base films 403 and 404 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film and an amorphous semiconductor film 405 are formed in this order on the glass substrate 401 and the light shielding layer 402 by, for example, a plasma CVD method. To do.
  • the base films 403 and 404 are provided to prevent diffusion of impurities from the glass substrate.
  • a silicon nitride film having a thickness of about 100 nm is formed as the lower first base film 403, and subsequently, a silicon oxide film having a thickness of about 200 nm is formed as the second base film 404.
  • an intrinsic (I-type) amorphous silicon film (a-Si film) having a thickness of about 20 to 80 nm, for example, 40 nm is formed by a plasma CVD method or the like.
  • a catalyst element is added to the surface of the a-Si film 405.
  • nickel is used as a catalyst element, and an aqueous solution (nickel acetate aqueous solution) containing, for example, 5 ppm of nickel in terms of weight is applied to the a-Si film 405 by spin coating as in the second and third embodiments.
  • the catalyst element-containing layer 406 is formed.
  • the concentration of the catalyst element on the surface of the a-Si film 405 is about 5 ⁇ 10 12 atoms / cm 2 .
  • heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere.
  • an annealing treatment it is preferable to perform an annealing treatment at a temperature of 550 to 620 ° C. for 30 minutes to 4 hours.
  • heat treatment was performed at a temperature of 600 ° C. for 1 hour.
  • nickel added to the surface of the a-Si film 405 diffuses into the a-Si film 405 and silicidation occurs, and the a-Si film 405 is crystallized using this as a nucleus. In this way, a crystalline silicon film 405a is obtained as shown in FIG. 9B.
  • the crystalline silicon film 405a is further recrystallized by irradiating the crystalline silicon film 405a obtained by the heat treatment with the laser beam 407, thereby improving the crystallinity.
  • a crystalline silicon film 405b is formed.
  • a XeCl excimer laser (wavelength 308 nm) or a KrF excimer laser (wavelength 248 nm) can be applied.
  • the beam size of the laser beam 407 is formed so as to be a long shape on the surface of the substrate 401, and the entire surface of the substrate is irradiated by sequentially scanning in the direction perpendicular to the long direction. At this time, when scanning is performed so that parts of the beams overlap, laser irradiation is performed a plurality of times at any one point of the crystalline silicon film 405a, so that recrystallization can be performed more uniformly.
  • the beam size is formed so as to be a long shape of 300 mm ⁇ 0.4 mm on the surface of the substrate 401, and scanning is sequentially performed with a step width of 0.02 mm in the direction perpendicular to the long direction. . That is, a total of 20 laser irradiations are performed at an arbitrary point on the silicon film.
  • the laser that can be used in this step may be a YAG laser, a YVO 4 laser, or the like in addition to the aforementioned pulse oscillation type or continuous emission type KrF excimer laser and XeCl excimer laser.
  • p is used at a concentration of about 1 ⁇ 10 16 to 5 ⁇ 10 17 / cm 3 for the purpose of controlling the threshold voltage.
  • Boron (B) may be doped as an impurity element imparting a mold. Boron (B) may be added by an ion doping method, or may be doped at the same time when an amorphous silicon film is formed.
  • a gate insulating film 409 is formed so as to cover the semiconductor layers 408n, 408p, 408g, and subsequently, resist masks 410n, 410p, 410g of photoresist are formed. Thereafter, a low concentration impurity (phosphorus) 411 is implanted into the island-like semiconductor layers 408n and 408g using the resist masks 410n, 410p, and 410g as masks.
  • a low concentration impurity (phosphorus) 411 is implanted into the island-like semiconductor layers 408n and 408g using the resist masks 410n, 410p, and 410g as masks.
  • a silicon oxide film having a thickness of 20 to 150 nm, here 70 nm, is formed as the gate insulating film 409.
  • the silicon oxide film is formed by decomposition and deposition by RF plasma CVD method using TEOS (Tetra Ethoxy Ortho Silicate) as a raw material with a substrate temperature of 150 to 600 ° C., preferably 300 to 450 ° C., as a raw material. Also good.
  • TEOS Tetra Ethoxy Ortho Silicate
  • it can also be carried out by depositing TEOS as a raw material together with ozone gas by a low pressure CVD method or an atmospheric pressure CVD method at a substrate temperature of 350 to 600 ° C., preferably 400 to 550 ° C.
  • the temperature is 500 to 600 ° C. for 1 to 4 hours in an inert gas atmosphere. Annealing may be performed.
  • another insulating film containing silicon may be used as the gate insulating film 409.
  • the gate insulating film 409 may be a single layer or may have a stacked structure.
  • Resist masks 410n, 410p, and 410g are provided on the island-shaped semiconductor layers 408n, 408p, and 408g, respectively.
  • a resist mask 410n is disposed so as to cover only the central portion that will later become a channel region. Both end portions that will later become source channel regions are exposed.
  • a resist mask 410g is disposed so as to cover only the portion that will later become the active region of the pixel TFT, and later, This part is exposed.
  • a resist mask 410p is disposed so as to cover the entire semiconductor layer 408p, which later becomes an active region of the p-channel TFT.
  • the implantation of the impurity (phosphorus) 411 can be performed by an ion doping method.
  • the doping gas phosphine (PH 3 ) is used, the acceleration voltage is set to 60 to 90 kV, for example, 70 kV, and the dose amount is set to 5 ⁇ 10 12 to 5 ⁇ 10 14 cm ⁇ 2 , for example, 5 ⁇ 10 13 cm ⁇ 2 .
  • the dose amount is set to 5 ⁇ 10 12 to 5 ⁇ 10 14 cm ⁇ 2 , for example, 5 ⁇ 10 13 cm ⁇ 2 .
  • Phosphorus 411 is not implanted into the regions covered with the resist masks 410n and 410g. Further, since the island-shaped semiconductor layer 408p is masked with the resist mask 410p, phosphorus 411 is not implanted into the island-shaped semiconductor layer 408p at all.
  • gate electrodes 413n, 413p, and 413g are formed on the island-shaped semiconductor layers 408n, 408p, and 408g, respectively, and further, an auxiliary is formed on the island-shaped semiconductor layer 408g.
  • a capacitor upper electrode 413s is formed.
  • a second low-concentration impurity (phosphorus) 414 is implanted into the active region of each TFT by the ion doping method using the gate electrodes 413n, 413p, and 413g and the auxiliary capacitor upper electrode 413s as a mask.
  • the gate electrode 413g of the subsequent pixel TFT is divided into two for the purpose of reducing the leakage current when the pixel TFT is turned off. This is to obtain a so-called dual gate structure in which two TFTs are connected in series.
  • the gate structure of the pixel TFT may be a triple gate structure or a quad gate structure in which the number of gate electrodes 413g (the number of TFTs connected in series) is further increased.
  • the gate electrodes 413n, 413p, 413g and the auxiliary capacitor upper electrode 413s are formed by depositing a metal film by sputtering and patterning it.
  • a metal film As a material for the metal film, Al, Mo, Ta, W, Ti, and the like and alloys containing them as main components may be used. The material used is limited by the heat treatment in the subsequent process.
  • tungsten silicide, titanium silicide, or molybdenum silicide may be used.
  • an Al—Ti alloy (containing 0.2% to 3% Ti) film having a thickness of 300 to 600 nm, for example, 450 nm is used.
  • the second low-concentration phosphorus 414 is implanted into the regions not covered with the gate electrodes 413n, 413p, and 413g and the auxiliary capacitor upper electrode 413s, respectively.
  • the second low-concentration n-type impurity regions 415n, 415p, and 415g are formed.
  • Phosphorus 414 is not implanted into the region masked by the gate electrodes 413n, 413p, 413g and the auxiliary capacitor upper electrode 413s.
  • a second crystalline silicon film is deposited on the gate insulating film 409, and this is patterned to form an active region (n-type region, p-type region) of the later TFD.
  • An island-like semiconductor layer 416 to be an intrinsic region is formed.
  • the second crystalline silicon film can be formed using a plasma CVD method using SiH 4 gas as a material and a substrate heating temperature of 300 to 450 ° C.
  • hydrogen is used as the diluent gas, and the hydrogen dilution rate (SiH 4 / H 2 ) is set to 1/50 or less, so that the crystalline component is included together with the film formation.
  • the hydrogen dilution rate SiH 4 / H 2
  • Ar gas may be added to the dilution gas.
  • the pressure was 1 to 4 Torr, for example 2.5 Torr, and the RF power was 0.2 to 3 kW / m 2 , for example 2 kW / m 2 .
  • the second crystalline silicon film is directly formed by depositing crystalline silicon, and is patterned by a known method to obtain the semiconductor layer 416.
  • the semiconductor layer 416 is formed after the gate electrodes 413n, 413p, 413g, and 413s are formed. However, the semiconductor layer 416 may be formed first.
  • the thickness d2 of the semiconductor layer 416 is preferably set to be larger than the thickness d1 (set to 40 nm in this embodiment) of the semiconductor layers 408n, 408p, and 408g that are the active regions of the TFT.
  • the thickness d2 of the island-shaped semiconductor layer 416 is larger than the sum of the thickness d3 of the gate insulating film 409 and the thickness d1 of the semiconductor layers 408n, 408p, and 408g.
  • the thickness of the gate insulating film 409 immediately after formation is 70 nm.
  • the gate electrodes 413n, 413p, and 413g are etched by dry etching, the gate electrodes 413n, 413p, and 413g are formed.
  • the gate insulating film 409 in a more exposed region is exposed to overetching.
  • the thickness d3 of the region exposed from the gate electrodes 413n, 413p, and 413g in the gate insulating film 409 is 55 nm, for example, about 15 nm smaller than that immediately after the formation. Therefore, in this embodiment, the thickness d2 of the island-shaped semiconductor layer 416 is preferably set to be larger than the sum (95 nm) of the thickness d3 (55 nm) and the thickness d1 (40 nm). Here, the thickness d2 is set to, for example, 300 nm.
  • a doping mask 417g made of a photoresist is provided so as to cover the gate electrode 413g of the later pixel TFT so as to be slightly larger.
  • the gate electrode 413p is further provided.
  • a photoresist mask 417p is provided so as to cover the entire surface and expose the outer edge of the semiconductor layer 408p.
  • a doping mask 417d made of a photoresist is provided so that a part of the semiconductor layer 416 is exposed.
  • a high concentration of impurity (phosphorus) 418 is added to each semiconductor layer by ion doping using the gate electrode 413n of the later n-channel TFT, the upper electrode 413s of the auxiliary capacitor, and the resist masks 417p, 417g, and 417d as masks.
  • the doping gas phosphine (PH 3 ) is used, the acceleration voltage is set to 40 to 80 kV, for example, 60 kV, and the dose amount is set to 1 ⁇ 10 15 to 1 ⁇ 10 16 cm ⁇ 2 , for example, 5 ⁇ 10 15 cm ⁇ 2 .
  • an impurity (phosphorus) 418 is implanted into the region exposed from the gate electrode 413n at a high concentration, and the source / drain region 419n of the later n-channel TFT is It is formed in a self-aligned manner with respect to the gate electrode 413n.
  • a region which is covered with the gate electrode 413n and is not doped with the high concentration phosphorus 418 is a region where phosphorus is implanted at a low concentration in the previous step, an LDD region overlapping the gate electrode 413n, A so-called GOLD (Gate Overlapped Lightly Doped Drain) region 420n is formed, and a region under the gate electrode 413n into which low-concentration phosphorus is not implanted is a channel region 426n.
  • GOLD Gate Overlapped Lightly Doped Drain
  • an impurity (phosphorus) 418 is implanted at a high concentration into a region exposed from the resist mask 417g, and a source / drain region 419g of the subsequent pixel TFT (n-channel type) is formed.
  • the regions covered with the resist mask 417g and not doped with high-concentration phosphorus 418 are LDD regions 421g, and low-concentration phosphorus is also implanted.
  • the region under the gate electrode 413g that does not exist is a channel region 426g.
  • an impurity (phosphorus) 418 is implanted at a high concentration into a region exposed from the resist mask 417p, thereby forming a high-concentration n-type region 419p.
  • the region 421p covered with the resist mask 417p and implanted with the low concentration phosphorus 414 remains as it is.
  • a high concentration n-type region 419d is formed by implanting an impurity (phosphorus) 418 at a high concentration into a region exposed from the resist mask 417d.
  • the n-type impurity element (phosphorus) 411 in the GOLD region 420n of the n-channel TFT has a concentration in the film of 5 ⁇ 10 17 to 1 ⁇ 10 19 / cm 3 , and the n-type in the LDD region 421g of the pixel TFT.
  • the concentration of the impurity element (phosphorus) 414 in the film is preferably 1 ⁇ 10 17 to 5 ⁇ 10 18 / cm 3 . Within such a range, these regions 420n and 421g function more effectively as GOLD regions or LDD regions.
  • the step of doping high concentration phosphorus 418 is performed through the gate insulating film 409 in the island-shaped semiconductor layer 408n of the n-channel TFT and the island-shaped semiconductor layer 408g of the pixel TFT, and becomes an active region of the TFD.
  • the island-shaped semiconductor layer 416 is bare.
  • the thickness d1 of the semiconductor layers 408n and 408g, the thickness d2 of the semiconductor layer 416, and the thickness d3 of the region exposed from the gate electrode of the gate insulating film 409 are set to satisfy d1 + d3 ⁇ d2. .
  • the doping conditions are optimized for the semiconductor layers 408n and 408g of the TFT, and even if the resistance of the source and drain regions 419n and 419g is reduced, the semiconductor layer 416 serving as the active layer of the TFD has a thickness d2 In contrast, impurities are not implanted deeply. Therefore, in spite of bare doping, doping damage near the lower surface of the semiconductor layer 416 can be suppressed to be lower than that of the semiconductor layers 408n and 408g of the TFT.
  • a semiconductor layer 408n of an n-channel TFT, a semiconductor layer constituting a pixel TFT and its auxiliary capacitance are newly added.
  • the photoresist doping masks 422n, 422g, and 422d are provided so as to cover the entire surface of 408g and a part of the TFD semiconductor layer 416.
  • (Boron) 423 is injected.
  • Diborane (B 2 H 6 ) is used as a doping gas, the acceleration voltage is 40 kV to 90 kV, for example 70 kV, and the dose is 1 ⁇ 10 15 to 1 ⁇ 10 16 cm ⁇ 2 , for example 3 ⁇ 10 15 cm ⁇ 2 .
  • boron 423 is implanted at a high concentration into a region of the p-channel TFT semiconductor layer 408p that is not covered with the gate electrode 413p.
  • the region 421p becomes a p-type by inverting the n-type impurity phosphorus 414 implanted at a low concentration in the previous step, and in a self-alignment with the gate electrode 413p, the source / drain region 424p of the later TFT. Is formed.
  • a high concentration boron 423 is implanted into the region 419p to form a gettering region 425.
  • the region under the gate electrode 413p is not implanted with high-concentration boron 423, and becomes a channel region 426p.
  • boron 423 is implanted at a high concentration in a region exposed from the resist mask 422d, and a later TFD p-type region 424d is formed.
  • the region masked with the resist mask 422d and the resist mask 417d in the previous step and into which neither high-concentration phosphorus nor boron is implanted becomes an intrinsic region 426d of the later TFD.
  • the n-channel TFT semiconductor layer 408n and the pixel TFT and the semiconductor layer 408g serving as the lower electrode of the auxiliary capacitor are entirely covered with the resist masks 422n and 422g, so that the boron 423 is not doped.
  • the step of doping high-concentration boron 423 is performed through the gate insulating film 409 in the island-shaped semiconductor layer 408p of the p-channel TFT, and bare in the island-shaped semiconductor layer 416 serving as the active region of the TFD. Done in state.
  • the thickness d1 of the semiconductor layer 408p, the thickness d2 of the semiconductor layer 416, and the thickness d3 of the region exposed from the gate electrode of the gate insulating film 409 are set so as to satisfy d1 + d3 ⁇ d2.
  • the doping condition of boron 423 is optimized for the semiconductor layer 408p of the TFT, and the resistance of the source region and the drain region 424p can be reduced.
  • the resist masks 422n, 422g, and 422d are heat-treated in an inert atmosphere, for example, in a nitrogen atmosphere.
  • the RTA process is used in which the substrate is moved to a high temperature atmosphere one by one and high temperature nitrogen gas is blown to raise and lower the temperature rapidly.
  • temperature raising / lowering was performed at a temperature raising / lowering rate exceeding 200 ° C./min, for example, heat treatment was performed at 650 ° C. for 10 minutes.
  • other methods can be used, and the conditions may be set by the practitioner for convenience.
  • a general diffusion furnace furnace furnace
  • a lamp heating type RTA may be used.
  • the source / drain regions 419n and 419g are doped with phosphorus.
  • the nickel solid solubility is increased, and nickel existing in the channel regions 426n, 426g, the GOLD region 420n, and the LDD region 421g is moved from the channel region to the GOLD region or the LDD region, and the source / drain region by an arrow 427n. And move in the direction indicated by 427g.
  • the semiconductor layer 408p of the later p-channel TFT phosphorus and boron doped at a high concentration in the gettering region 425 formed outside the source / drain region 424p, and a lattice generated at the time of boron doping
  • a defect or the like causes nickel existing in the channel region 426p and the source / drain region 424p to move from the channel region to the source / drain region and the gettering region 425 in the same direction as indicated by an arrow 427p.
  • nickel moves to the source / drain regions 419n and 419g of the n-channel TFT and the pixel TFT and the gettering region 425 of the p-channel TFT. Therefore, the nickel concentration in these regions is 1 ⁇ 10 18 / cm 3 or more.
  • n-channel TFT and pixel TFT source / drain regions 419n and 419g, GOLD region 420n, LDD region 421g, auxiliary capacitance lower electrode region 420g, and n-type region 419d of TFD are doped. Recovering doping damage such as crystal defects caused at the time of doping between the p-type impurity (phosphorus) and the p-type impurity (boron) doped in the source / drain region 424p of the p-channel TFT and the p-type region 424d of the TFD , Activate phosphorus and boron doped in each.
  • the sheet resistance value of the source / drain regions of the n-channel TFT and the pixel TFT is about 0.3 to 0.7 k ⁇ / ⁇
  • the sheet resistance value of the n-type region of the TFD is 0.5 to 1. It is about 0 k ⁇ / ⁇ .
  • the sheet resistance value of the GOLD region and the auxiliary capacitor lower electrode region was about 20 to 60 k ⁇ / ⁇
  • the sheet resistance value of the LDD region was 40 to 100 k ⁇ / ⁇ .
  • the sheet resistance value of the source / drain region of the p-channel TFT is about 0.7 to 1.2 k ⁇ / ⁇ , and the sheet resistance value of the p-type region of the TFD is 1.0 to 1.5 k ⁇ / ⁇ . It was about.
  • the doped n-type impurity element phosphorus and the p-type impurity element boron cancel the carriers (electrons and holes), and the sheet resistance is several tens of k ⁇ / ⁇ .
  • the gettering region in the semiconductor layer of the p-channel TFT is arranged so as not to hinder the movement of carriers, which does not cause a problem in operation.
  • interlayer insulating films (thickness: for example, 400 to 1500 nm, typically 600 to 1000 nm) 428 and 429 are formed.
  • a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film can be used as the interlayer insulating film.
  • an interlayer insulating film having a stacked structure including a silicon nitride film 428 having a thickness of 200 nm and a silicon oxide film 429 having a thickness of 700 nm is formed.
  • the silicon nitride film 428 can be formed using a plasma CVD method using SiH 4 and NH 3 as source gases.
  • the silicon oxide film 429 can be formed using a plasma CVD method using TEOS and O 2 as raw materials.
  • the silicon nitride film 428 and the silicon oxide film 429 are preferably formed in succession.
  • the material and forming method of the interlayer insulating film are not limited to this, and an insulating film containing other silicon may be used.
  • the interlayer insulating film may be a single layer or may have a stacked structure. In the case of a stacked structure, an organic insulating film such as acrylic may be provided as an upper insulating film.
  • a heat treatment is performed at a temperature of 300 to 500 ° C. for about 30 minutes to several hours to hydrogenate the semiconductor layer.
  • This is a process in which hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and dangling bonds (dangling bonds) that degrade the TFT characteristics are terminated with hydrogen to be inactivated.
  • heat treatment was performed at 400 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen.
  • the amount of hydrogen contained in the interlayer insulating film especially the silicon nitride film 326) is sufficient, the same effect can be obtained even if heat treatment is performed in a nitrogen atmosphere.
  • plasma hydrogenation using hydrogen excited by plasma may be performed.
  • contact holes are formed in the interlayer insulating films 428 and 429, and TFT electrodes / wirings 430n, 430p, 430g and 430d are formed.
  • the titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. In this manner, the driver n-channel thin film transistor 431, the p-channel thin film transistor 432, the pixel switching thin film transistor 433, the auxiliary capacitor 434 connected thereto, and the photosensor thin film diode 435 are obtained.
  • a transparent conductive film such as ITO is connected to one of the electrode / wiring 430g of the pixel switching thin film transistor 433 to form a pixel electrode. Further, if necessary, contact holes are provided also on the gate electrodes 413n and 413p, and necessary electrodes are connected by the wiring 430. Furthermore, for the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.
  • the n-channel thin film transistor manufactured by the above method has a field effect mobility of 250 to 300 cm 2 / Vs and a threshold voltage of about 1 V
  • the p-channel thin film transistor 432 has a field effect mobility of 120 to 150 cm 2 / Vs and a threshold value.
  • the voltage was about -1.5V, and it was found that good TFT characteristics were exhibited.
  • a circuit such as an inverter chain or a ring oscillator is formed by a CMOS structure circuit in which an n-channel thin film transistor 431 and a p-channel thin film transistor 432 are complementarily formed, the circuit characteristics are higher and more reliable than the conventional circuit. showed that.
  • the light / dark ratio as the optical sensor element is greatly improved as compared with the case where the same semiconductor layer as the TFT is used as in the conventional method. As described above, it was confirmed that the characteristics for each device can be optimized by forming a semiconductor layer for each element.
  • this embodiment is suitably applied not only to a liquid crystal display device but also to an organic EL display device, for example.
  • a bottom emission type organic EL display device can be manufactured by forming a transparent electrode layer, a light emitting layer, and an upper electrode layer in this order on a substrate provided with a thin film transistor and a thin film diode by the above method. it can.
  • a top emission type organic EL display device may be manufactured by forming a transparent electrode as the upper electrode layer. In that case, the substrate need not be translucent.
  • the configuration and manufacturing method of the semiconductor device of the present embodiment are not limited to the above.
  • the TFD light-shielding layer, the TFT semiconductor layer, the TFD semiconductor layer, and the TFT gate electrode are formed from separate films.
  • the light shielding layer and the TFT semiconductor layer may be formed from the same crystalline semiconductor film, or the gate electrode and the TFD semiconductor layer may be formed from the same crystalline semiconductor film.
  • a method for forming a crystalline semiconductor film for forming a semiconductor layer of a TFT is not limited to a method for crystallizing an amorphous semiconductor film using a catalytic element.
  • the amorphous semiconductor film may be crystallized by irradiating with a laser.
  • a method for forming a crystalline semiconductor film for forming a TFD semiconductor layer is not limited to the plasma CVD method, and a method for crystallizing an amorphous semiconductor film using a catalytic element or by laser irradiation is used. You may apply.
  • the display device having the sensor function is, for example, a liquid crystal display device with a touch sensor, and includes a display region and a frame region located around the display region.
  • the display area has a plurality of display units (pixels) and a plurality of photosensor units.
  • Each display unit includes a pixel electrode and a pixel switching TFT, and each photosensor unit includes a TFD.
  • a display drive circuit for driving each display unit is provided in the frame region, and a drive circuit TFT is used as the drive circuit.
  • the pixel switching TFT, the driving circuit TFT, and the TFD of the optical sensor unit are formed on the same substrate by the method described in the first to fourth embodiments.
  • at least the pixel switching TFT among TFTs used in the display device may be formed on the same substrate as the TFD of the photosensor portion by the above method. Alternatively, it may be separately provided on another substrate.
  • the optical sensor unit is disposed adjacent to a corresponding display unit (for example, primary color pixels).
  • a corresponding display unit for example, primary color pixels.
  • One photosensor unit may be arranged for one display unit, or a plurality of photosensor units may be arranged. Or you may arrange
  • one optical sensor unit can be provided for a color display pixel composed of three primary color (RGB) pixels.
  • RGB primary color
  • the sensitivity of the TFD constituting the optical sensor unit may be reduced. Therefore, no color filter is provided on the observer side of the optical sensor unit. It is preferable.
  • a display device to which an ambient light sensor for controlling display brightness in accordance with the illuminance of external light can be configured by arranging a TFD for an optical sensor in a frame region.
  • the optical sensor unit can also function as a color image sensor.
  • FIG. 12 is a circuit diagram showing an example of the configuration of the optical sensor unit arranged in the display area.
  • the optical sensor unit includes an optical sensor thin film diode 601, a signal storage capacitor 602, and a thin film transistor 603 for extracting a signal stored in the capacitor 602. After the RST signal is input and the RST potential is written into the node 604, when the potential of the node 604 is decreased due to light leakage, the gate potential of the thin film transistor 603 is changed to open and close the TFT gate. Thereby, the signal VDD can be taken out.
  • FIG. 13 is a schematic cross-sectional view showing an example of an active matrix type touch panel liquid crystal display device.
  • one optical touch sensor unit including the optical sensor unit is arranged for each pixel.
  • the liquid crystal display device shown in the figure includes a liquid crystal module 702 and a backlight 701 disposed on the back side of the liquid crystal module 702.
  • the liquid crystal module 702 includes, for example, a light-transmitting back substrate, a front substrate disposed so as to face the back substrate, and a liquid crystal layer provided between these substrates. Composed.
  • the liquid crystal module 702 includes a plurality of display portions (primary color pixels), and each display portion includes a pixel electrode (not shown) and a pixel switching thin film transistor 705 connected to the pixel electrode. Yes.
  • an optical touch sensor unit including a thin film diode 706 is disposed adjacent to each display unit.
  • a color filter is disposed on the viewer side of each display unit, but no color filter is provided on the viewer side of the optical touch sensor unit.
  • a light shielding layer 707 is disposed between the thin film diode 706 and the backlight 701, and light from the backlight 701 is shielded by the light shielding layer 707 and does not enter the thin film diode 706, but only the external light 704 is thin film diode 706. Is incident on. The incident of the external light 704 is sensed by the thin film diode 706 to realize a light sensing touch panel.
  • the light shielding layer 707 may be arranged so that at least light from the backlight 701 does not enter the intrinsic region of the thin film diode 706.
  • FIG. 14 is a schematic plan view showing an example of a rear substrate in an active matrix type touch panel liquid crystal display device.
  • the liquid crystal display device of the present embodiment is composed of a large number of pixels (R, G, B pixels), but only two pixels are shown here for the sake of simplicity.
  • Each of the rear substrates 1000 is disposed adjacent to each of the plurality of display portions (pixels) each including the pixel electrode 22 and the pixel switching thin film transistor 24, and includes a photosensor photodiode 26 and a signal storage capacitor 28. And an optical touch sensor unit including an optical sensor follower thin film transistor 29.
  • the thin film transistor 24 has, for example, the same configuration as the pixel switching TFT described in the fourth embodiment, that is, a dual gate LDD structure having two gate electrodes and an LDD region.
  • the source region of the thin film transistor 24 is connected to the pixel source bus line 34, and the drain region is connected to the pixel electrode 22.
  • the thin film transistor 24 is turned on / off by a signal from the pixel gate bus line 32.
  • display is performed by applying a voltage to the liquid crystal layer by the pixel electrode 22 and the counter electrode formed on the front substrate disposed to face the back substrate 1000 and changing the alignment state of the liquid crystal layer.
  • the photosensor photodiode 26 has the same configuration as the TFD described in the fourth embodiment, for example, and is located between the p + type region 26p, the n + type region 26n, and the regions 26p and 26n. And an intrinsic region 26i.
  • the signal storage capacitor 28 has a gate electrode layer and a Si layer as electrodes, and a capacitance is formed by a gate insulating film.
  • the p + -type region 26p in the photosensor photodiode 26 is connected to the RST signal line 36 for photosensors, and the n + -type region 26n is connected to the lower electrode (Si layer) in the signal storage capacitor 28. 28 is connected to the optical sensor RWS signal line 38.
  • n + -type region 26 n is connected to the gate electrode layer in the photosensor follower thin film transistor 29.
  • the source and drain regions of the photosensor follower thin film transistor 29 are connected to the photosensor VDD signal line 40 and the photosensor COL signal line 42, respectively.
  • the photosensor photodiode 26, the signal storage capacitor 28, and the photosensor follower thin film transistor 29 correspond to the thin film diode 601, the capacitor 602, and the thin film transistor 603 of the drive circuit shown in FIG. It constitutes the drive circuit for the optical sensor. The operation at the time of optical sensing by this drive circuit will be described below.
  • the RWS signal is written into the signal storage capacitor 28 by the RWS signal line 38.
  • a positive electric field is generated on the n + -type region 26 n side of the photosensor photodiode 26, and the photosensor photodiode 26 is in a reverse bias state.
  • the photosensor photodiode 26 present in the region of the substrate surface where light is irradiated light leaks and the charge is released to the RST signal line 36 side.
  • the potential on the n + -type region 26n side is lowered, and the gate voltage applied to the photosensor follower thin film transistor 29 is changed by the potential change.
  • VDD signal is applied from the VDD signal line 40 to the source side of the photosensor follower thin film transistor 29.
  • the gate voltage fluctuates as described above, the value of the current flowing to the COL signal line 42 connected to the drain side changes, so that the electrical signal can be extracted from the COL signal line 42.
  • the RST signal is written from the COL signal line 42 to the photosensor photodiode 26, and the potential of the signal storage capacitor 28 is reset. Optical sensing is possible by repeating the operations (1) to (5) while scanning.
  • the configuration of the back substrate in the touch panel liquid crystal display device of the present embodiment is not limited to the configuration shown in FIG.
  • an auxiliary capacitor (Cs) may be provided in each pixel switching TFT.
  • an optical touch sensor unit is provided adjacent to each of the RGB pixels. However, as described above, one light is supplied to three pixel sets (color display pixels) composed of RGB pixels. A touch sensor unit may be arranged.
  • the thin film diode 706 is arranged in the display area and used as a touch sensor.
  • the thin film diode 706 is formed outside the display area and back It can also be used as an ambient light sensor for controlling the luminance of the light 701 in accordance with the illuminance of the external light 704.
  • FIG. 15 is a perspective view illustrating a liquid crystal display device with an ambient light sensor.
  • the liquid crystal display device 2000 includes an LCD substrate 50 having a display area 52, a gate driver 56, a source driver 58 and an optical sensor unit 54, and a backlight 60 disposed on the back side of the LCD substrate 50.
  • An area of the LCD substrate 50 that is located around the display area 52 and in which the drivers 56 and 58 and the optical sensor unit 54 are provided may be referred to as a “frame area”.
  • the brightness of the backlight 60 is controlled by a backlight control circuit (not shown).
  • TFTs are used for the display area 52 and the drivers 56 and 58, and TFDs are used for the optical sensor unit 54.
  • the optical sensor unit 54 generates an illuminance signal based on the illuminance of external light, and inputs the illuminance signal to the backlight control circuit using a connection using a flexible substrate.
  • the backlight control circuit generates a backlight control signal based on the illuminance signal and outputs it to the backlight 60.
  • an organic EL display device with an ambient light sensor can be configured.
  • Such an organic EL display device can have a configuration in which a display unit and a photosensor unit are arranged on the same substrate as in the liquid crystal display device shown in FIG. There is no need to provide the light 60.
  • the optical sensor unit 54 is connected to the source driver 58 by wiring provided on the substrate 50, and an illuminance signal from the optical sensor unit 54 is input to the source driver 58.
  • the source driver 58 changes the luminance of the display unit 52 based on the illuminance signal.
  • a circuit for performing analog driving and a circuit for performing digital driving can be simultaneously formed on a glass substrate.
  • a source side driving circuit includes a shift register, a buffer, a sampling circuit (transfer gate), and a gate side driving circuit.
  • the source side driving circuit includes a shift register, a buffer, a sampling circuit (transfer gate), and a gate side driving circuit.
  • a level shifter circuit may be provided between the sampling circuit and the shift register.
  • a memory and a microprocessor can be formed.
  • the present invention it is possible to obtain a semiconductor device including TFTs and TFDs having good characteristics on the same substrate by using an optimum semiconductor film for each semiconductor element. Therefore, the TFT used for the drive circuit and the TFT for switching the pixel electrode have a high field effect mobility and an ON / OFF ratio, and the SN ratio for light (current value in light and dark) used as an optical sensor. TFD having a high ratio) can be manufactured in the same manufacturing process. In particular, among these semiconductor layers, by optimizing the thickness and crystal state of the channel region that greatly affects the field effect mobility of the TFT and the intrinsic region that greatly affects the photosensitivity of the TFD, It is possible to realize element characteristics that are optimal for semiconductor elements. Further, such a high-performance semiconductor device can be manufactured by a simpler method, and not only the product can be made compact and high-performance, but also the cost can be reduced.
  • the present invention can be widely applied to semiconductor devices including TFTs and TFDs, or electronic devices in various fields having such semiconductor devices.
  • the present invention may be applied to a CMOS circuit or a pixel portion in an active matrix liquid crystal display device or an organic EL display device.
  • Such a display device can be used for a display screen of a mobile phone or a portable game machine, a monitor of a digital camera, or the like. Therefore, the present invention can be applied to all electronic devices in which a liquid crystal display device or an organic EL display device is incorporated.
  • the present invention can be suitably used particularly for display devices such as active matrix liquid crystal display devices and organic EL display devices, image sensors, photosensors, or electronic devices that combine them.
  • display devices such as active matrix liquid crystal display devices and organic EL display devices, image sensors, photosensors, or electronic devices that combine them.
  • the present invention can be applied to an image sensor including a photosensor using TFD and a driving circuit using TFT.

Abstract

Dans le dispositif semi-conducteur selon l’invention comportant un transistor à couche mince et une diode à couche mince sur un seul substrat, la caractéristique requise pour chacun d’eux peut être réalisée. Le dispositif semi-conducteur comprend : une première couche semi-conductrice cristalline (107) supportée par un substrat (101) et comportant une zone de canal (115), une zone de source, et une zone de drain (113) ; une pellicule d’isolation de gâchette (108) disposée pour recouvrir la première couche semi-conductrice cristalline (107) ; un transistor à couche mince disposé sur la pellicule d’isolation de gâchette (108) et comportant une électrode de gâchette (109) servant à contrôler la conductivité de la zone de canal (115) ; et une diode à couche mince supportée par le substrat (101) et comportant une seconde couche semi-conductrice cristalline (110) contenant au moins une zone de type n (114) et une zone de type p (118).  La seconde couche semi-conductrice cristalline (110) est formée sur la pellicule d’isolation de gâchette (108) de façon à être en contact avec la surface de la pellicule d’isolation de gâchette (108).  La zone de type n (114) ou la zone de type p (118) et la zone de source et la zone de drain (113) contiennent le même élément d’impureté.
PCT/JP2009/005936 2008-11-20 2009-11-09 Dispositif semi-conducteur, son procédé de fabrication, et dispositif d’affichage utilisant le dispositif semi-conducteur WO2010058532A1 (fr)

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JP2016164562A (ja) * 2010-10-07 2016-09-08 株式会社半導体エネルギー研究所 光検出回路
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KR20120042143A (ko) * 2010-10-22 2012-05-03 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 이의 제조 방법
KR20130119614A (ko) * 2012-04-24 2013-11-01 삼성디스플레이 주식회사 센싱 장치 및 이미지 센싱 방법
CN103219391B (zh) * 2013-04-07 2016-03-02 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN104867964B (zh) * 2015-05-18 2019-02-22 京东方科技集团股份有限公司 阵列基板、其制造方法以及有机发光二极管显示装置
CN106356378B (zh) * 2016-09-26 2023-10-27 合肥鑫晟光电科技有限公司 阵列基板及其制作方法
CN107123654A (zh) * 2017-05-26 2017-09-01 京东方科技集团股份有限公司 阵列基板及其制备方法和显示装置
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