WO2010048971A1 - Mécanisme d'essai, broche à effet pogo et procédé pour l'essai d'un dispositif à 'essai - Google Patents

Mécanisme d'essai, broche à effet pogo et procédé pour l'essai d'un dispositif à 'essai Download PDF

Info

Publication number
WO2010048971A1
WO2010048971A1 PCT/EP2008/009178 EP2008009178W WO2010048971A1 WO 2010048971 A1 WO2010048971 A1 WO 2010048971A1 EP 2008009178 W EP2008009178 W EP 2008009178W WO 2010048971 A1 WO2010048971 A1 WO 2010048971A1
Authority
WO
WIPO (PCT)
Prior art keywords
pogo
impedance
pin
test
under test
Prior art date
Application number
PCT/EP2008/009178
Other languages
English (en)
Inventor
Bernd Laquai
Original Assignee
Verigy (Singapore) Pte., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verigy (Singapore) Pte., Ltd. filed Critical Verigy (Singapore) Pte., Ltd.
Priority to PCT/EP2008/009178 priority Critical patent/WO2010048971A1/fr
Priority to TW098136658A priority patent/TWI414791B/zh
Publication of WO2010048971A1 publication Critical patent/WO2010048971A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/06772—High frequency probes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
    • G01R1/06716—Elastic
    • G01R1/06722—Spring-loaded
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56016—Apparatus features
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/06766—Input circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/02—Contact members
    • H01R13/22—Contacts for co-operating by abutting
    • H01R13/24—Contacts for co-operating by abutting resilient; resiliently-mounted
    • H01R13/2407—Contacts for co-operating by abutting resilient; resiliently-mounted characterized by the resilient means
    • H01R13/2421—Contacts for co-operating by abutting resilient; resiliently-mounted characterized by the resilient means using coil springs

Definitions

  • Embodiments of the invention are related to a test arrangement, a pogo-pin and a method for testing a device under test.
  • DUTs device under test
  • DUT specific circuit boards are used to route the signals to/from the DUT from/to the pins of the test head.
  • corresponding inputs of a plurality of devices under test (DUTs) may be connected to a common pin of the test head. All these arrangements pose problems on the test design in that a transition from one impedance domain to the other causes reflections to occur which becomes even more severe with higher test signal data rates. These reflections, in turn, hamper the performance of reliable tests.
  • Fig. 1 shows a beam diagram of light being reflected from or passing an optical material depending on an optical anti-reflection coating of the optical material for illustrating one of the main ideas underlying the embodiments of the present invention described hereinafter;
  • Fig. 2a shows a schematic diagram of the scene of Fig. 1, i.e. light being transmitted through an optical medium having a different reflective index than air surrounding the medium;
  • Fig. 2b shows, in accordance with the optical arrangement shown in Fig. 2a, a schematic diagram of an electrical transmission line connected to a device under test which has an impedance being different from an impedance of the transmission line;
  • Fig. 3a shows an equivalent circuit diagram of an input impedance of a device under test, including a resistive "on-die termination” and a capacitive input capacitance;
  • Fig. 3b shows a Nyquist diagram representing the input impedance of Fig. 3a
  • Fig. 4a shows an equivalent circuit diagram of an input impedance of a device under test comprising a resistive on-die termination and a gate and ESD capacitance with illustrative concrete values for resistance and capacitance;
  • Fig. 4b shows a Nyquist diagram illustrating the input impedance of Fig. 4a
  • Fig. 5 illustratively shows a TDR (Time Domain Reflectometry) diagram of an input impedance of a GDDR5 memory device
  • Fig. 6 shows a sectional view of a circuit pogo-pin according to a comparison embodiment
  • Fig. 7a shows a top view of an inner member of a pogo-pin of another comparison embodiment along with the spring of the pogo-pin for urging the inner member and the outer sleeve of the pogo-pin apart, in a released state;
  • Fig. 7b shows a top view of the arrangement of Fig. 7a in a compressed state
  • Fig. 8 shows a top view of an outer sleeve of the pogo- pin of Fig. 7a and 7b;
  • Fig. 9 shows a time domain reflectometry (TDR) diagram measured at an input pin of a short circuited device under test (DUT) via the pogo-pin of Fig. 7a to 8;
  • Fig. 10 shows a histogram illustrating the repeatability of a pogo-pin measurement using the pogo-pin of
  • Fig. 11 shows a TDR diagram measured with a comparison test arrangement for measuring a device under test (DUT);
  • Fig. 12 shows an eye diagram of a signal received at a TDR receiver of a test arrangement for measuring a device under test with impedance mismatch
  • Fig. 13a shows a schematic sectional view of a SMA (sub- miniature-A) adaptor cable terminated by an on- die termination (ODT) load emulation;
  • SMA sub- miniature-A
  • ODT on- die termination
  • Fig. 13b shows an equivalent circuit diagram of the SMA adaptor cable terminated by the on-°die termination (ODT) load termination as depicted in Fig. 13a;
  • ODT on-°die termination
  • Fig. 14 shows a polar diagram of an input impedance of the SMA adaptor cable terminated by the ODT load termination as depicted in Fig. 13a;
  • Fig. 15 shows a TDR diagram measured with a daisy chain test arrangement having no devices loaded
  • Fig. 16 shows a TDR diagram measured with a daisy chain test arrangement having DDR2 devices loaded in all sites;
  • Fig. 17 shows a circuit diagram of a branch for connecting a tester pin to two devices under test comprising a common line and two branch lines connected via a branching node;
  • Fig. 18 shows a circuit diagram of the branch as depicted in Fig. 17 with specific values for impedances of the branch lines and the input impedance of the DUTs;
  • Fig. 19 shows a circuit diagram of the conventional branch as depicted in Fig. 17 with the reflections occurring being indicated;
  • Fig. 20a shows a circuit diagram of a daisy chain test arrangement for measuring DUTs at a common test channel
  • Fig. 20b shows a TDR diagram measured with the test arrangement of Fig. 20a
  • Fig. 21a shows a step response timing diagram of test signals applied to a daisy chain arrangement
  • Fig. 21b shows an eye diagram of the test signals as depicted in Fig. 21a;
  • Fig. 22a shows a wave diagram of light being transmitted through the optical medium as depicted in Fig. 2a, when the optical medium comprises a optical thin film of anti-reflection coating material;
  • Fig. 22b shows - analogously to Fig. 22a - a signal diagram of the electrical transmission line of Fig. 2b with an anti-reflective circuit
  • impedance matching circuit being connected between the transmission line and the termination impedance, according to an embodiment of the invention
  • Fig. 23a shows a schematic diagram of a test arrangement according to an embodiment of the invention.
  • Fig. 23b shows a schematic diagram of a test arrangement according to another embodiment of the invention.
  • Fig. 23c shows an equivalent circuit diagram of a test arrangement according to an embodiment of the invention.
  • Fig. 23d shows a schematic diagram of a test arrangement comprising a device tester, a test interface and a plurality of interfaces for a plurality of devices under test according to an embodiment of the invention
  • Fig. 23e shows a theoretical Nyquist diagram illustrating the input impedance of the test arrangement as depicted in Fig. 23a;
  • Fig. 24a shows an equivalent circuit diagram of a test arrangement in the illustrative case of a GDDR5 memory device, corresponding to that shown in Fig. 4a, with an impedance matching circuit according to an embodiment of the invention being connected between the transmission line and DUT;
  • Fig. 24b shows a theoretical Nyquist diagram of the test arrangement as depicted in Fig. 24a;
  • Fig. 25 shows a theoretical TDR diagram measured with the test arrangement as depicted in Fig. 24a
  • Fig. 26 shows a step response timing diagram of the voltage at the device under test of the test arrangement as depicted in Fig. 24a, compared to the voltage at the input impedance of the device under test resulting in case of Fig. 4a;
  • Fig. 27 shows a schematic sectional view of a pogo-pin according to an embodiment of the invention
  • Fig. 28 shows a schematic sectional view of a pogo-pin according to another embodiment of the invention.
  • Fig. 29a shows a spatial view of a pogo-pin according to an embodiment of the invention
  • Fig. 29b shows a spatial view of a pogo-pin according to another embodiment of the invention.
  • Fig. 29c shows a top view of a test arrangement according to an embodiment of the invention.
  • Fig. 30 shows an equivalent circuit diagram of a test arrangement comprising an impedance matching circuit, a TDR sender and a TDR receiver according to an embodiment of the invention
  • Fig. 31 shows a TDR diagram measured with the test arrangement as depicted in Fig. 30;
  • Fig. 32 shows an equivalent circuit diagram of a test arrangement comprising an impedance matching circuit, a TDR sender, a microstrip line and a measurement probe according to an embodiment of the invention
  • Fig. 33 shows an eye diagram of a signal received at the TDR receiver of the test arrangement as depicted in Fig. 32;
  • Fig. 34a shows a schematic sectional view of a test arrangement comprising an SMA adaptor cable terminated by a series connection of an ODT load emulation and an impedance matching circuit according to an embodiment of the invention
  • Fig. 34b shows an equivalent circuit diagram of the test arrangement as depicted in Fig. 34a;
  • Fig. 35 shows a Smith diagram of areflection factor measurement of the test arrangement as depicted in Fig. 34a;
  • Fig. 36 shows an equivalent circuit diagram of a test arrangement comprising two impedance matching circuits, each of them associated with a device under test, a Y-branch table with length mismatch, a TDR sender and a measurement probe according to an embodiment of the invention
  • Fig. 37 shows a signal diagram measured with the test arrangement as depicted in Fig. 36;
  • Fig. 38 shows an equivalent circuit diagram of a test arrangement comprising two impedance matching circuits, each of them associated with a device under test, a Y-branch cable with length mismatch, a test signal sender and a test signal receiver according to an embodiment of the invention
  • Fig. 39 shows an eye diagram measured with the test arrangement as depicted in Fig. 38
  • Fig. 40 shows a circuit diagram of a test arrangement comprising the branch as depicted in Fig. 17, and impedance matching circuits connected between respective output lines and respective impedances of the device under test according to an embodiment of the invention
  • Fig. 41 shows an equivalent circuit diagram of a test arrangement comprising two devices under test according to an embodiment of the invention
  • Fig. 42 shows a simulated eye diagram of a first input signal of a simulation of the test arrangement as depicted in Fig. 41;
  • Fig. 43 shows an equivalent circuit diagram of a test arrangement comprising four devices under test according to an embodiment of the invention.
  • Fig. 44 shows a signal diagram of four input signals of a simulation of a test arrangement as depicted in Fig. 43;
  • Fig. 45 shows an eye diagram of the first input signal of the simulation of the test arrangement as depicted in Fig. 44;
  • Fig. 46 shows a schematic diagram of a test arrangement comprising an impedance matching circuit coupled to a first device under test by a first transmission line and coupled to a second device under test by a second transmission line, the first transmission line having a length smaller than a quarter wavelength of a carrier of a test signal and the second transmission line having a length greater than a quarter wavelength of the carrier of the test signal; and Fig. 47 shows a timing diagram of signals measured at the first device under test and measured at the second device under test as depicted in Fig. 46.
  • Fig. 1 shows a beam diagram of light being reflected from or passing an optical material.
  • the ratio between reflection and transmission is dependent on the absence or presence of a conventional anti- reflection coating of the optical material.
  • An upper portion 10 of the optical material is not coated by an anti-reflective coating, whereas a lower portion 12 of the optical material is coated with an anti-reflective coating.
  • the optical material may be a lens 14 and the anti- reflection coating may be applied to the outer surface of the lens 14 facing away from the viewer (not shown) to reduce reflection of incoming light.
  • the reflected light may disturb the viewer. For example, the reflection reduces the transmission yield. Further, the reflected light may reach light sensitive areas where this light is unwanted.
  • the reduction in reflections improves the contrast of the image by elimination of stray light.
  • the primary benefit is the elimination of the reflection itself, thus resulting in a better look of the person and a brighter view.
  • a beam of light 16 may be reflected from the lens 14 for the most part, while only a strongly attenuated part of the upper beam of light 16 passes the lens 14.
  • a beam of light 18 passes the lens 14 for the most part.
  • up to 99% of the beam of light 18 passes the optical material 14, when the optical material 14 comprises an adequately dimensioned anti-reflection coating.
  • Fig. 2a shows a beam diagram of light being transmitted through a conventional optical medium having a different reflective index than the surrounding air.
  • Some portion r of the beam of light 20 is reflected from the surface of the glass 22, while another portion b of the beam of light 20 passes through the glass 22.
  • the strength of the reflection depends on the reflective indices no and ni of the two media as well as the angle of the surface to the beam of light 20. The exact value can be calculated using the Fresnel equations.
  • a thin film anti-reflective coating (ARC) on the surface of glass 22 can reduce the reflectivity.
  • a thin layer of material with refractive index n ftRC between the air with refractive index no and the glass with refractive index ni causes the light beam to reflect twice, namely from the interface between air and the thin ARC layer, and from the interface between the ARC layer to glass interface.
  • Fig. 2b shows a signal diagram of a conventional electrical transmission line terminated with a termination impedance formed by a device under test, which is different from an impedance of the transmission line.
  • An electrical signal 24 passes the transmission line denoted "trace" in Fig. 2b.
  • the transmission line has an impedance Z 0 .
  • the transmission line is terminated by the device under test DUT which, in turn, has an impedance Z 1n . If the impedance Zi n of the device under test DUT is not matched to the impedance Z 0 of the transmission line then a portion r of the electrical wave 24 is reflected from the device under test DUT and another portion b of the electrical wave 24 passes into the device under test DUT.
  • Fig. 2a and Fig. 2b thus, illustrate a correspondence between electrical and optical waves, wherein impedances of electrical lines or devices correspond to refractive indices of optical materials.
  • Fig. 3a shows an equivalent circuit diagram of an input impedance of a conventional device under test DUT comprising resistive "on die termination" R ODT and a capacitive input impedance C IN connected in parallel.
  • the parallel connection of R ODT and C IN is connected between the terminal for connection to the transmission line and potential Vddq which is applied to the DUT from outside.
  • the device under test DUT may correspond to the device under test DUT as depicted in Fig. 2b.
  • the input impedance Z of the DUT of Fig. 3a may correspond to the input impedance Zi n of the device under test DUT as depicted in Fig. 2b.
  • the input impedance Z is formed by the parallel connection of the capacity C IN and resistance R ODT -
  • the resistance R ODT may be formed by an on- die termination implemented on the chip of the DUT, when the device under test DUT comprises a chip.
  • the capacitance CiN may be formed by a gate capacitance or an ESD protection circuitry of the DUT such as the ESD pin circuitry of an integrated circuit if the device under test DUT comprises an integrated circuit.
  • Fig. 3b shows a Nyquist diagram illustrating the input impedance Z of Fig. 3a.
  • the Nyquist diagram shows the impedance Z of the device under test DUT for different frequencies.
  • the impedance Z(f) for the different frequencies is plotted in a coordinate system having a horizontal axis Re(Z) along which the real part of the input impedance Z is plotted and a vertical access In(Z) along which the imaginary part of the input impedance Z plotted.
  • the input impedance Z equals R ODT which may be 120 Ohm.
  • the input impedance Z approximates 0 Ohm, which is caused by the capacitance Ci n .
  • Z(f) describes a curve passing, for a frequency fi, an impedance Z where the imaginary part equals the real part.
  • Fig. 4a shows an equivalent circuit diagram of an input impedance of a device under test DUT comprising a resistive on-die termination ODT and a gate and ESD circuitry forming a capacitance C.
  • the device under test DUT is formed by a parallel connection of the on-die termination resistor showing a resistance R of 60 Ohm on the one hand, and the gate and ESD circuit forming capacitance C of 1.5p on the other hand.
  • the device under test DUT is connected to a transmission line having, exemplarily, an impedance Z 0 of 60 Ohm.
  • the input impedance Zi n corresponds to the input impedance Z as depicted in Fig. 3a, wherein in Fig. 4a the on-die-termination resistor R and the gate and ESD capacitance have discrete values.
  • Fig. 4b shows a Nyquist diagram illustrating the input impedance as depicted in Fig. 4a.
  • r denotes the reflexion coefficient and b the refraction coefficient.
  • the input impedance Zi n of the device under test DUT is equal to 60 Ohm, which matches the impedance Zo of the transmission line being 60 Ohm.
  • the magnitude of the imaginary part of the input impedance Zi n increases.
  • Fig. 5 illustrates that an impedance mismatched interface between a transmission line and a DUT may cause electrical energy of the transmitted signal to reach the transmission source of the transmission line again (like an echo) .
  • Fig. 5 shows a TDR diagram of the input impedance measured with a GDDR5 memory device.
  • GDDR5 graphics double data rate, version 5
  • the time-domain reflectrometry (TDR) is a procedure for determination and analysis of run-time lengths and reflection characteristica of electromagnetic waves and signals.
  • an impulse generator generates a series of very short signal transitions (steps) with a rise time of about 20 nano seconds, for example, which follow in such a time interval that echoes of preceding transitions have completely settled at the time the next transition commences.
  • An oscilloscope may be used for measuring the step responses. The transitions are applied to the device _ _
  • Fig. 5 illustrates a non-matched case.
  • the TDR diagram comprises an amplitude axis A and time axis t.
  • the diagram depicts an amplitude A of a reflected signal transition (step) plotted over time t.
  • the TDR diagram depicts a constant amplitude of the received signal, which illustrates that a part of the signal pulse directly reaching the TDR receiver / oscilloscope being connected to the same end of the transmission line as the impulse generator.
  • Fig. 5 shows that a test measurement with the GDDR5 memory devices used in Fig. 5 should wait at least 750 pico seconds before determining the result of a test signal to make sure that no unwanted distortions have a negative influence on the quality of the measurement .
  • test heads the pins used to electrically contact the pins of the DUT also pose impedance matching problems on the design of the test arrangement.
  • Fig. 6 shows a sectional view of a possible pogo-pin that may be used to interface between a BGA (ball grid array) pad 34 on a socket board and a ball 36 of a ball grid array of the DUT (device under test) 38.
  • a pogo-pin is a device used in electronics to establish a usually temporary connection between two electrical devices such as printed circuit boards or a PCB and an IC or the like.
  • Pogo-pins may be applied in test systems.
  • a test system comprises a test head in which a pin-electronic module and the corresponding driver is located.
  • the pin-electronic module is connected by cables to a pogo-connector, which is arranged at an upper side of the test head.
  • An interface is docked on the test head such that the pogo-pins are contacting the interface by its bottom side.
  • the interface comprises contact pads adapted to contact the pogo-pins, which contact pads are connected by interface cables to the interface. These interface cables are ending at the upper side of the interface for connecting the socket boards.
  • the socket boards may be (small) PCBs (printed circuit boards) , which also comprise contact areas for connecting the DUT sockets 32.
  • the DUT sockets 32 may be screwed (or connected otherwise) to the contact areas of the socket boards.
  • the DUT sockets 32 comprise (small) pogo-pins 30 as shown in Fig. 6. They have a length of about 2-3 mm.
  • the DUTs 38 are pressed in these DUT sockets 32, such that the balls 36 of the Ball-Grid-Array package 38 are contacted by the pogo- pins 30. Such a contacting provides a full signal path connection between DUT and tester driver or tester receiver, respectively.
  • the pogo-pin 30 shown in Fig. 6 may have a relatively short length of about 2-3 mm, while the cable arranged in the interface may have a length of about 40 cm. _ _
  • the pogo-pin shown in Fig. 6 comprises two tubes or shells 40 and 42 made of conductive material among which one 40 is inserted into the other 42 so as to be movable relative to each other in a sliding manner along their common axis. Some interlocking means (not shown in Fig. 6) may be provided in order to prevent shell 40 from escaping shell 42.
  • a spring 44 is located in the inner region housed by the shells 40 and 42 to spring-load the arrangement of shells 40 and 42 from inside so as to urge the shells 40 and 42 apart.
  • the Pogo-pin of Fig. 6 may be arranged along with other pogo-pins in a dense array, connecting together many individual pins of the electrical circuits.
  • one electrical circuit is a DUT 38 while the other is a circuit board dedicated, for example, for interconnecting the DUT with a test head. In the latter case, the pogo-pin of Fig.
  • the spring 6 may electrically interconnect a pin or ball 36 of a ball grid array of the DUT 38 with a respective pad of the circuit or socket board.
  • the electrical contact between the pins 36 and 34 is not only caused by a resistive electrical path formed by the two shells 40 and 42.
  • the spring may be made of a conductive material such as metal. In this case, the spring results in an inductive component being electrically connected between the pins 34 and 36 which is, in the first ⁇ instance, undesirable.
  • this inductance may be positively exploited to from a part of an impedance matching or anti-reflection circuit.
  • Fig. 6 shows the pogo-pin 30 as being comprised by a DUT socket 32. That is, the pogo- pin is supported by the socket 32 so that shell 40 protrudes from one side of the socket 32 while the other shell 42 protrudes from the other side thereof.
  • more than one pogo-pin may, in this manner, be haltered so to result in a lateral array of pogo-pins .
  • the pogo-pin 30 is used to electrically connect a pad on the circuit board 34 with a ball 36 of a ball grid array (BGA) of a device under test package 38.
  • BGA ball grid array
  • the pogo-pin 30 comprises the inner tube 40, the outer tube 42 and the spring 44.
  • Fig. 7a shows an inner tube of a pogo-pin and the spring contacting the inner tube in a released state.
  • the spring 50 may be mechanically attached to the inner tube 52. Alternatively, the spring 50 merely abuts an inner surface of tube 52.
  • the inner tube 52 comprises a contacting portion 56 for abutting a pad of a device under text.
  • the pogo-pin further comprises a piston portion 54 for plunging into the outer tube which is not shown here.
  • the piston portion protrudes out from the outer tube.
  • portion 54 is internal to the outer tube.
  • the pogo-pin comprises a spring resting portion 58 which radially protrudes outward relative to the piston portion in order to interfere with a respective potion of the outer tube in the released state defining a hole through which the piston portion extends in order to avoid an escape of the inner tube 52 out of the outer tube.
  • the spring resting portion 58 is also used to form a resting surface against which spring 50 presses.
  • the spring 50 is stabilized in its radial position inside the inner tube 52 by way of an inner portion 60 of the inner tube 52 extending inwardly from the spring resting portion 58 and having a smaller radial extension than portion 58.
  • spring 50 is _
  • the spring may have a reduced diameter in order to be inserted to the outer tube and in order to serve as a contacting point for the inner portion in the compressed state as described later.
  • the spring resting portion 58 of the pogo-pin corresponds to the fixing point as depicted in Fig. 6 where the spring 44 contacts the inner tube 40.
  • Fig. 7a The outer tube to be put over the inner tube 52 is not depicted in Fig. 7a but an example for same is shown in Fig. 8 which shows an outer tube with the inner tube.
  • the inner portion extends longitudinally in such a way that, in the compressed state shown in Fig. 7b, an end 64 thereof facing away from the spring resting portion 58 contacts the smaller diameter portion of spring 50 and, via same, electrically contacts the outer tube.
  • the inner tube 52 may have a length of 3.7 mm when the spring 50 is in the released state shown in Fig. 7a.
  • spring 50 may be biased even in the state shown in Fig. 7a where the tubes are maximally apart.
  • released should be broadly understood as denoting that the spring is less stressed/biased than in the compressed state depicted in Fig. 7b where the distance between the tubes is minimal.
  • Fig. 7b shows the inner tube 52 of the pogo-pin of Fig. 7a along with spring 50 in the compressed state of the pogo- _ _
  • the inner tube 52 is maximally received within the outer tube and the spring 50 is under maximal tension.
  • the length of the spring 50 is, for example, reduced from 3.7 mm to 3.4 mm in which case the pogo-pin has a variable length being variable by an amount of 0.3 mm. This length is called the contact stroke 62.
  • the end 64 of inner portion 60 mechanically contacts the smaller diameter portion of spring 50 thereby making an electrical contact between the inner tube 52, the spring 50 and the outer tube.
  • the inner portion 60 thus, also serves as a interlocking mechanism preventing the inner tube 52 from dipping into the outer tube by an amount exceeding the contact stroke 62.
  • Fig. 8 shows a possible outer sleeve 66 of the pogo-pin of Fig. 7a and 7b along with the inner tube.
  • the outer sleeve 66 may have dimensions as indicated in the figure.
  • the outer sleeve or tube 66 comprises a small diameter hollow portion 74 accommodating the small diameter portion of spring 50 and serving as an outer contacting portion for mechanically and electrically contacting a pad to which the pad contacted by the contacting portion 56 of the inner tube 52 is to be contacted.
  • sleeve 66 comprises a large diameter portion 72 for accommodating the large diameter portion of spring 50 not depicted in Fig. 8.
  • the sleeve 66 comprises a hole through which the piston portion of the inner tube extends.
  • the large diameter portion 72 comprises a ring protruding inwardly in radial direction (not shown) in order to engage with the spring _ _
  • a pogo-pin similarly constructed is designed such that same forms at least a part of a matching circuit whereby the number of electrical paths may vary as is described below.
  • the path leading through the spring causes a high impedance which has to be accounted for in testing.
  • the point of contact between the spring and the end 64 of inner portion 60 is determined rather inaccurately, thus causing a variance in the resulting impedance between consecutive tests using the pogo-pin of Fig. 7a, 7b and 8, or, at least, a variance of the impedance among a group of constructively identical pogo-pins.
  • Fig. 9 shows a time domain reflectometry (TDR) diagram measured with a pogo-pin contacting a short circuited device under test, the pogo-pin being as depicted in Fig. 7a, 7b and 8.
  • TDR time domain reflectometry
  • the receiver such as, for example, an oscilloscope.
  • the signal which was received at the oscilloscope is depicted in Fig. 9.
  • the signal sent to the device should be, after reflection, received with reverse polarity.
  • the pulse sent to the device had an amplitude of about 70 millivolt which can be seen at the time axis between time 0 and 100 picoseconds.
  • the pulse was reflected after about 1.4 ns +/-400 picoseconds from the short circuited device under test and was received with a reverse polarity.
  • a different delay can be observed.
  • a fixture delay calibration (FXDL cal) is performed before testing the DUT to account for the signal propagation between the test head and the DUT balls.
  • a short circuit device e.g. a gold coated metal piece
  • the short circuit device When the short circuit device is inserted it generates a short to the ground pins.
  • a step signal is send from the tester (like with a TDR) the propagation delay of the echo (appearance of the inverted step) reveals the electrical path length.
  • the path is not an ideal transmission line with a real impedance of e.g. 50ohm but comprises an inductor such as the "bad" socket pogo pin, the impedance becomes complex and adds a parasitic delay. This behaviour is shown in Fig. 9.
  • a first curve 81 illustrates a measurement with a first short circuited device
  • a second curve 82 illustrates a measurement with a second short circuited device.
  • a delay between the first curve 81 and the second curve 82 amounts _ _
  • the delay is about 650 picoseconds for the first curve 81 and about 750 picoseconds for the second curve 82.
  • Fig. 10 shows a histogram illustrating the repeatability of a measurement with a tester using pogo-pins such as that shown in Fig. 7a, 7b and 8.
  • the diagram illustrates the result of a difference between two consecutive FXDL measurements performed on a DDR2 memory device.
  • the time difference between two consecutive FXDL measurements is depicted on a time axis t versus a sample axis (sample) .
  • the sample axis denotes the pin number of the pins of the DDR 2 device which is measured by the FXDL measurement.
  • Difference measurements depict difference times of 0, 80, -40 or -80 picoseconds.
  • the measurement shows a very good repeatability, at most times the difference amounts to 0 seconds, but sometimes an error of 40 or 80 picoseconds incurs.
  • the measurement can be used for calibration purposes of a device tester.
  • Fig. 11 shows a time domain reflectometry (TDR) diagram measured at a device under test terminated by a plane ODT (on die termination) load. A pulse was sent through the transmission line to the device under test which, in turn, was reflected by the ODT load of the device under test.
  • the TDR diagram illustrates the reflection starting at time 2 ns and continuing until a time of about 3.5 ns.
  • Fig. 12 shows an eye diagram of a signal received at in a test arrangement where a device under test is measured at 500Mbps.
  • the digital data signal from the TDR receiver corresponds to the signal measured with the test arrangement as depicted in Fig. 11.
  • the digital data signal was repetitively sampled and applied to the vertical axis input of an oscilloscope which thereby represents the amplitude, while a bit clock was used to trigger the horizontal sweep of the oscilloscope.
  • the resulting oscilloscope output which is called an eye diagram is shown in Fig. 2.
  • the reflections which can be observed by the TDR measurements as depicted in Fig. 11 cause a closure or constriction of the eye pattern.
  • the reflection during the time interval 90 corresponds to distortions of the eye pattern, wherein the duration of one data bit is represented by the time interval 91.
  • the duration 90 of the reflection corresponds to the duration of the reflection as depicted in Fig. 11 and ranges from about 1.7 ns to about 2.3 ns. This is long enough to highly disturb the eye diagram extending about 2 ns . To perform an exact measurement with the test arrangement a lower sampling time, for example 250 Mbps would be necessary, which is no longer relevant for the application.
  • Fig. 13a shows a schematic sectional view of a conventional SMA adaptor 100 terminated by an on die termination (ODT) load emulation 101.
  • the on die termination load emulation 101 comprises a capacitance 102 in parallel connected to a resistance 103.
  • the capacitance 102 in this example has a _ _
  • the value of 11 pF and is realized by a parallel connection of a first capacitor 104 of 10 pF and a second capacitor 105 of 1 pF.
  • the resistance 103 is implemented by a parallel connection of two resistors 106 of 100 ⁇ .
  • the resistors 106 and the capacitors 104, 105 are discrete devices such as, for example, SMD components.
  • the on die termination 101 is attached to the SMA adaptor cable 100 by soldering, for example.
  • Fig. 13b shows an equivalent circuit diagram of the SMA adapter cable 100 terminated by the on die termination (ODT) load termination 101 as depicted in Fig. 13a.
  • the equivalent circuit diagram comprises a parallel connection of the capacitance 102 of 11 pF and the resistance 103 of 50 ⁇ .
  • the SMA adapter cable 100 with the ODT load emulation may be used for demonstration purposes for demonstrating the effects of a resistive on die termination with a parasitic capacitance connected in parallel terminating the device under test.
  • the on die termination load emulation 101 is to show the same electrical properties as for example a memory device terminated by an integrated on die termination.
  • Fig. 14 shows a polar diagram of a reflection factor of the SMA adapter cable 100 terminated by the ODT load termination as depicted in Fig. 13a.
  • the polar diagram illustrates the reflection factor r as absolute value of the S parameter SIl.
  • S-parameters are properties describing the electrical behavior of linear electrical networks when undergoing various steady states stimuli by small signals. Many electrical properties of networks or components may be expressed using S-parameters such as the reflection coefficient r which corresponds to the S-parameter SIl.
  • S- parameters are mostly used for networks operating at radio frequency and microwave frequencies where signal power and energy considerations are more easily quantified than currents and voltages. S-parameters change with the measurement frequency so this must included for any S- _ _
  • SIl is the input port voltage reflection coefficient
  • S12 is the reverse voltage gain
  • S21 is the forward voltage gain
  • S22 is the output port voltage reflection coefficient.
  • the S-parameter SIl is illustrated depending on the measurement frequency.
  • the SIl parameter corresponding to the reflection parameter is zero which depicts a matching of the SMA adaptor cable 100 as depicted in Fig. 13a to the ODT load as depicted in Fig. 13b.
  • an impedance of the SMA adaptor cable 100 being 50 ⁇ corresponds to the DC impedance of the ODT load being 50 ⁇ .
  • the reflection factor increases corresponding to the influence of the capacitor 102 in the ODT load as depicted in Fig. 13b.
  • the following examples illustrate that the measurement problems posed by impedance mismatch increase when more than one DUT is connected to one test head channel or test head pin vie one or several taps such as DUTs connected to a common line at tap points distributed alongside the common transmission line being terminated so as to yield a daisy chain.
  • Fig. 15 shows a TDR diagram measured with a daisy chain test arrangement for memory devices having no devices loaded.
  • the TDR diagram was measured with at an address line which is shared among 4 DUTs. It can be seen that between 1 ns and about 3 ns a lot of echoes result from reflections received from the unloaded ends of the address line branches leading to the individual memory device interfaces. These echoes may disturb an exact measurement.
  • Fig. 16 shows a TDR diagram measured with a daisy chain test arrangement having DDR2 memory devices loaded in all sites of the daisy chain. Compared to the case depicted in Fig. 15, where no memory devices were loaded, the diagram as depicted in Fig. 16 shows an even higher degree of reflections caused by the DDR2 memory devices due to the additional capacitive loading. Reflections occur between a time of 1 ns and a time of about 4.5 ns.
  • Fig. 17 shows a portion of a test arrangement comprising DUTs as well as a circuit board 120 for commonly connecting these DUTs via a branch node to a common test head pin.
  • the board 120 comprises a branch node 121 to which first and second lead lines 122 and 123 are connected, each of which leads to another one of the DUTs 124 and 125, as well as a common (signal feeding) transmission line 127 extending to the interface of a device tester or device tester's test head.
  • the common transmission line 127 typically has an impedance differing from the lead lines 122 and 123.
  • the transmission line 127 comprises, for example, impedance Zi being equal to 50 ⁇ .
  • the first and second devices under test 124 and 125 may have an ODT termination of 60 ⁇ parallel connected to a capacity of, for example, 1.5 pF.
  • the devices under test 124, 125 are, for example, GDDR5 memory devices having a real part impedance of 60 ⁇ .
  • Fig. 18 shows a circuit diagram of the circuit board as depicted in Fig. 17 with a symmetric structure.
  • the first device under test 131 comprises, for example, an resistance of 120 ⁇ in parallel to 1.5 pF.
  • the second device under test 132 also comprises a resistance of 120 ⁇ in parallel to 1.5 pF. Due to the symmetry condition, the branching node 121 is terminated by the two lead lines 122, 123, both having an impedance of 100 ⁇ , which results in an equivalent termination of the branching node 121 of 50 ⁇ .
  • the branching node 121 is matched at its side facing to the tester by 50 ⁇ and at its side facing to the DUTs by 50 ⁇ , such that no reflections occur by the branching node 121. Reflections may only occur by the devices under test 131, 132, having a different impedance than the 100 ⁇ of the branches 122 and 123, such that reflections from the two devices under test 131, 132 are transmitted to the branch point 121. However, the reflection of one DUT e.g. 131 gets cancelled by the reflected signal from the other DUT, e.g 132, refracted into the branch 122 at point 121. This cancellation effect is the reason that no multiple reflections will occur for this arrangement.
  • Fig. 19 shows a circuit diagram of the circuit board 120 as depicted in Fig. 17 illustrating the conditions for the cancellation of the reflections.
  • a lot of reflections occur when a line having a characteristic impedance is connected to another line having another characteristic impedance.
  • the first branch line 122 having the characteristic impedance Z 2 is connected to a first device under test 133 having the characteristic impedance Z. If the characteristic impedance Z 2 is unequal to the characteristic impedance Z, a reflection r X i occurs between the first branch line 122 and the first device under test _
  • the second branch line 123 having the characteristic impedance Z 2 is connected to a second device under test 134 having the characteristic impedance Z which is unequal to the characteristic impedance Z 2 a reflection r Y i occurs between the second branch line 123 and the second device under test 134.
  • the characteristic impedance Z 1 of the signal feeding transmission line 127 is different to the characteristic impedances Z 2 , also reflections at the branching node 121 occur. For example, an electrical wave is send from the tester into transmission line 127, an equal portion of the signal is refracted into the branch lines 122 and 123 and another portion is reflected back to the tester. It is assumed that the tester matches the impedance Zl therefore the reflected portion is totally absorbed in the tester.
  • the refracted portion however, propagates along the branches 122 and 123 towards the DUTs 133 and 134. Since the input impedance Z of the DUTs 133 and 134 can hardly be matched to the branch lines 122 and 123 a reflection occurs with a factor of rxl and ryl respectively. The reflected waves from the DUTs travel towards the branch or fork point 121. The impedance there also does not match the branch line impedance. Therefore in the case of branch line 122 a portion rx2 of the signal is again reflected back towards the DUT 133 and another portion is refracted into the feeding line 127 and into the other branch line 123. However, the same happens on branch 123.
  • Fig. 20a shows a circuit diagram of a daisy chain test arrangement as already mentioned above.
  • the arrangement is for measuring devices under test (DUT) using a daisy chain _ _
  • the daisy chain sharing topology is especially suitable for high-speed memory testing such as for testing a plurality of memory devices in a same testing step.
  • a device tester 140 is connected via a test interface 141 to a transmission line xyl with a characteristic impedance Z (e.g. 50ohm) This transmission line is terminated at its end such that no reflections occur. The termination is achieved with a matching resistor xy2 and a termination supply xy3 connected to ground 155. The transmission line is now tapped at the points xy4, xy5 xy6 and xy7.
  • the devices under test with a characteristic input capacitance 143 are connected via stubs (short transmission lines, e.g. vias) to the taps and therefore distort the ideal transmission of signals on the transmission line xyl. At each tap a reflection occurs because the input capacitance as well as the capacitive behaviour of the stubs act like a short for the first instance of time or very high frequencies respectively.
  • a reflection diagram 156 illustrates reflections at the respective branching nodes 145, 146, 148, 150 which leave the stubs 152 and stem from the parasitic input capacitances 143 of the respective devices under test DUTl - DUT4. At each of the devices under test, a reflection occurs resulting in a distortion of the signal seen by the previous DUT. (The tester is not evaluating the signal, it is used for driving.)
  • Fig. 20b shows a TDR diagram measured with the conventional test arrangement as depicted in Fig. 20a.
  • the time domain reflectometry diagram illustrates the signal which is seen by the first device under test DUTl. This signal comprises three reflections, a first reflection 160 corresponding to a reflection from the second device under test DUT2, a second reflection 161 corresponding to a reflection from the third device under test DUT3 and a third reflection 162 corresponding to reflection from the fourth device under test DUT4.
  • the input impedance of the tester 140 and the terminating impedance 153 are adequately matched to the 50 ⁇ of the input lines, therefore no reflections occur.
  • Fig. 21a shows a timing diagram of test signals.
  • Four test signals v(10), v(ll), v(12), v(13) are received at a test arrangement using a daisy chain sharing topology for testing DDR memory devices with a pseudorandom binary sequence (PRBS) of a sampling rate of 2.5 Gbps.
  • the daisy chain sharing topology is a By-4 sharing topology comprising four devices under test, each having a 1.5 pF load impedance and 30 ps tap stubs. Due to the reflections of the originally sent test signal sent from the device test 140 as depicted in Fig. 20a a received signal at respective devices under test comprises a lot of reflections from neighboring devices under test which can be seen in the timing diagram of Fig. 21a.
  • the received signals v(10), v(ll), v(12), v(13) comprise signal components of the originally sent test signal reflected from the neighboring devices under test. This results in the distortions which are seen at the inputs of the DUTs.
  • the signals seen at the DUTs show a ringing which is decaying to the target programmed value of 0.8 V.
  • Fig. 21b shows an eye diagram corresponding to a test signal as underlying Fig. 21a.
  • the eye diagram illustrates the received test signal v(10) received at the first device under test DUTl according to the test arrangement as depicted in Fig. 20a. Due to the distortions in the received test signal v(10) caused by the reflections of neighboring devices under test the eye of the eye diagram is nearly closed. The overshoots and undershoots of the received test signal v(10) cause a distortion of the eye diagram resulting in closure of the eye.
  • measuring devices under test which comprise specific parasitic capacitances and resistances determining an input impedance of the devices under test cause problems due to reflections which decrease measurement sensitivity.
  • the reflections may stem from a miss-adjustment of the input impedance of the devices under test to the transmission line leading to the device tester.
  • the reflections may also occur from reflections of neighboring devices under test, in case of a test arrangement where more than one device under test in connected to one test channel or one test interface such as in, for example, a daisy chain topology.
  • a precise measurement becomes merely impossible. Solutions are required for canceling the undesired reflections to facilitate a high precision measurement of devices under test.
  • Some embodiments of the invention solve the problem mentioned above by providing a test arrangement comprising an interface for a device under test, the interface comprising an impedance matching circuit comprising a resistance and an inductance connected in parallel.
  • some embodiments of the invention provide a pogo pin comprising a first sleeve of conductive material, a second sleeve of conductive material, a tube of resistive material and a spring of conductive material.
  • the tube of resistive material, the first sleeve and the second sleeve are slidably attached to each other along a common axis with the tube being arranged between the first and the second sleeve.
  • the spring is used for urging the first and the second sleeve apart.
  • the pogo pin forms a parallel connection of an inductance mainly formed by the spring and a resistance mainly formed by the tube.
  • Some embodiments of the invention comprise a pogo pin comprising a first sleeve of conductive material, a second sleeve of conductive material, a tube of insulating material, a spring of conductive material and an elastic and electrically resistive element.
  • the first sleeve, the second sleeve and the tube are slidably attached to each other along a common axis with the tube being arranged between the first and the second sleeve.
  • the spring is used for urging the first and the second sleeve apart.
  • the elastic element comprises a resistive material attached between the first and the second sleeve along the common axis.
  • the pogo pin forms a parallel connection of an inductance mainly formed by the spring acting as inductor and a resistance mainly formed by the elastic element.
  • a further embodiment of the invention comprises a pogo pin comprising an elastomer body having a main longitudinal axis and wires of conductive material embedded in the elastomer body so as to extend between a top and a bottom surface of the elastomer body along the main longitudinal axis.
  • the pogo pin is configured to form a parallel connection of an inductance and a resistance both formed by the wires.
  • a general idea of some embodiments of the invention is to construct a test arrangement comprising a pogo pin such that the input impedance matches the line impedance when it is connected in between the DUT and the connecting transmission line. In such a case no reflections will occur.
  • embodiments of the invention provide an impedance matching circuit comprising a resistance and an inductance connected in parallel to match the generally capacitive input impedance of devices under test.
  • pogo pins comprise a spring providing an inductive spring coil.
  • this inductivity is exploited to from a part of an impedance matching circuit.
  • the pogo pin is thus used to form an inductance and an ohmic resistance to provide an impedance matching circuit which can be placed in immediate vicinity of the DUT.
  • an impedance matching circuit of an improved matching performance may be achieved when the impedance matching circuit has a resistance which is equal to the resistance of the input impedance of the device under test, for example within a tolerance range of ⁇ 10 %, and a inductance which is equal to the squared resistance of the input impedance of the device under test times the capacitance of the input impedance of the device under test such as, for example, within a tolerance range of ⁇ 10 %.
  • Fig. 22a shows a wave diagram of light being transmitted through the optical medium as depicted in Fig. 2a with, however, the optical medium having an optical thin film of antireflection coating material provided thereon.
  • the optical medium is, for example, a highly reflective glass. The coating material minimizes the reflections.
  • a general idea of embodiments of the invention is to transfer this idea from optics to the electrical domain.
  • the optical wave 20 as depicted in Fig. 22a is transmitted through an optical medium such as, for example, glass having a different refraction index ni > no than air and the glass has a thin film of anti-reflective coating material 21, the reflectivity of the glass can be reduced.
  • the thin layer of anti-reflective coating material 21 having a refractive index between the refractive index n 0 of the air and the refractive index ni of the glass the beam of light 20 reflects twice: once from the surface between air and the ARC layer 21, and once from the ARC _ _
  • this optimum refractive index is about n ARC « 1.225.
  • An intermediate coating (anti-reflective coating, ARC) between the air and glass can reduce the reflection loss.
  • Fig. 22b shows a signal diagram of the electrical transmission line Z 0 terminated with the termination impedance Z in of the device under test DUT which is different from the impedance Zo of the transmission line, with an anti-reflective circuit (impedance matching circuit) 200 according to an embodiment of the invention being connected between the transmission line 201 and the device under test 202.
  • the ARC circuit 200 is the analogous element between the two electrical media, i.e. transmission line and termination impedance of the device under test, which is analog to the thin film 21 of anti-reflective coating material between the two optical media, i.e. air and glass in Fig. 22a.
  • the ARC circuit 200 is adapted to comprise a reflection index which is between a reflection index of the transmission line 201 and a reflection index of the device under test termination impedance 202.
  • the ARC circuit 200 is adapted to let an electrical wave 203 travel through the transmission line
  • An adequately adjusted ARC circuit 200 suppresses reflections of the _ _
  • Fig. 23a shows a schematic diagram of a test arrangement
  • the test arrangement 400 comprises an interface 401 for a device under test 404.
  • the interface 401 comprises an impedance matching circuit 402, which impedance matching circuit 402 comprises a resistance R and an inductance L connected in parallel.
  • the interface 402 comprises a pogo-pin 403, which forms the impedance matching circuit 403. This is depicted by the schematic representation 403b of the pogo-pin 403, in which a circuit diagram of the parallel-connection of the resistance R and the inductance L is illustrated.
  • the resistance R and the inductance L of the impedance matching circuit 402 may be formed by discrete electrical components, which are arranged inside the pogo-pin 403 or (closely) outside the pogo-pin 403. Embodiments of the pogo-pin 403 are depicted in Figs. 27, 28, 29a, 29b.
  • the test arrangement 400 further comprises a signal generator 405 for applying a test signal.
  • the test arrangement further comprises the device under test 404, which comprises an input impedance.
  • the resistance R and the inductance L of the impedance matching circuit 402 are configured such that an impedance of the impedance matching circuit 402 matches the input impedance of the device under test 404.
  • Fig. 23b shows a schematic diagram of a test arrangement 400 according to another embodiment of the invention which is equal to the embodiment as depicted in Fig. 23a beside the implementation of the impedance matching circuit 402.
  • the impedance matching circuit 402 comprises a series- connection of the pogo-pin 403 and an external electrical component 420.
  • the external electrical component 420 comprises a discrete resistor R and a discrete inductor L.
  • the discrete resistor R and the discrete inductor L of the external electrical component 420 are configured such that an impedance of the impedance matching circuit 402 (comprising the impedance of the pogo-pin 403 and the impedance of the external electrical component 420) matches an input impedance of the device under test 404.
  • the test arrangement 400 further comprises a signal generator 405 for applying a test signal.
  • the test signal may, for example, have a mean frequency below a maximum frequency to the interface 401.
  • the external electrical component 420 is arranged close to the pogo-pin 403, for example below a quarter of the electrical wavelength corresponding to the maximum frequency. A close distance results in a better matching performance of the impedance matching circuit 402.
  • Fig. 23c shows an equivalent circuit diagram of a test arrangement according to an embodiment of the invention.
  • the test arrangement comprises a device under test DUT having an input impedance Zi n formed by a parallel connection of a resistance R and a capacitance C.
  • the test arrangement further comprises an impedance matching circuit ARC (anti-reflective coating) having an impedance formed by a parallel connection of a resistance R and an inductance L.
  • the impedance matching antireflection circuit ARC and the device under test DUT are connected in series, such that the series connection of impedance matching circuit ARC and device under test DUT has an input impedance of Z .
  • the impedance Z of the circuit comprising the device under test DUT connected in series to the impedance matching circuit becomes a real value corresponding to the resistance R of impedance matching circuit ARC and device under test DUT due to a cancellation of poles and zeros in the equation as shown above.
  • the frequency dependence of the impedance Z is cancelled by a matching condition which is
  • the matching condition has not to be met 100% in order to provide an advantageous arrangement compared to an unmatched situation.
  • the inductance L of the impedance matching circuit may be equal to the squared resistance R of the input impedance times the capacitance C of the input impedance within a tolerance range of +/- 10 percent.
  • the resistance of the impedance matching circuit may be equal to the resistance of the input impedance within a tolerance range of +/- 10 percent.
  • the impedance Zi n of the device under test DUT may be realized by an on die termination ODT and/or by an on die capacitance Ci n , for example a parasitic capacitance, and an external resistor R.
  • Fig. 23d shows a schematic diagram of a test arrangement 400 comprising a device tester, a test interface and a plurality of interfaces for a plurality of devices under test according to an embodiment of the invention.
  • Pogo-pins 403 may be applied in test systems or test arrangements 400, respectively.
  • the test arrangement 400 comprises a test head 407 or a device tester in which a pin-electronic module 410 and the corresponding tester driver 405 is located.
  • the pin- electronic module 410 is connected by cables 412 to a pogo- connector 417, which is arranged at an upper side of the test head 407.
  • a test interface 406 is docked on the test head 407 such that the pogo-connectors 417 are contacting the test interface 406, for example by the bottom side of the test interface 406 or by any other possible contact points.
  • the docking may be performed by a mechanical locking mechanism 416.
  • the test interface 406 comprises contact pads 413 adapted to contact the pogo-connectors 413, which contact pads 413 are connected by test interface cables 418 to the test interface 406. These test interface cables 418 are ending at the upper side of the test interface 406 for connecting a plurality of socket boards
  • the socket boards 408, 408b may be (small) PCBs (printed circuit boards) , which also comprise contact areas 414 for connecting the interfaces 401, 401b (or DUT sockets, respectively) associated with the socket boards 408, 408b.
  • the interface 401 for the DUT 404 is associated with the socket board 408, the second interface 401b for the second DUT 404b is associated with the second socket board 408b.
  • the interfaces (DUT sockets) 401, 401b may be screwed by screws 415 (or connected otherwise by a mechanical arrangement) to the contact areas 414 of the socket boards 408, 408b.
  • the interfaces (DUT sockets) 401, 401b comprise (small) pogo-pins 403, which are small with respect to the pogo-connectors 417 of the test head 407.
  • the pogo-pins 403 may, for example, have a length of about 2-3 mm.
  • the DUTs 404, 404b may be pushed in these interfaces (DUT sockets) 401, 401b, such that the balls 419 of the Ball-Grid-Array package (the devices under test 404, 404b) are contacted by the pogo-pins 403.
  • Such a contacting provides a full signal path connection between a DUT 404, 404b and a tester driver 405 or tester receiver 411, respectively.
  • the pogo-pins 403 shown in Fig. 23d may have a relatively short length of about 2-3 mm, while the cable 418 arranged in the test interface 406 may have a length of about 40 cm.
  • a branch node 120 is formed by an input line 127, a first output line 122 and a second output line 123.
  • the input line 127 is electrically connected between the test interface 406 and a branching node 121.
  • the first output line 122 is electrically connected between the branching node 121 and the interface 401 for the device under test 404 and the second output line 123 is electrically connected between the branching node 121 and the second interface 401b for the second device under test 404b.
  • the branching node 121 may be implemented on one of the (PCB) circuit boards 408, 408b or on the test interface 406.
  • the input line 127, the first output line 122 and the second output line 123 may be implemented as transmission lines, wave guides, micro strip lines, strip conductors of a printed circuit board, via's, connecting (micro-) strip lines, high frequency microwave cables, connectors, interconnectors or assemblies, SMA adaptors or coaxial cables.
  • the lengths of the first 122 and second 123 output lines may be different. Both output lines 122, 123 may be formed in different layers of the circuit boards 408, 408b.
  • Fig. 23e shows a Nyquist diagram illustrating the input impedance Z of the test arrangement as depicted in Fig. 23c.
  • the Nyquist diagram depicts the frequency dependency of the input impedance by a representation of its real part Re(Z) and its imaginary part Im(Z) .
  • the input impedance of the test arrangement Z is constant and real and exactly matches the line impedance. Therefore, no frequency-dependent reflections occur anymore.
  • the constant value corresponds to the resistance R of the device under test DUT and the impedance matching circuit ARC.
  • Fig. 24a shows an equivalent circuit diagram of a test arrangement comprising the GDDR5 memory device as depicted in Fig. 5, with an impedance matching circuit ARC according to an embodiment of the invention being connected between the DUT and the transmission line.
  • the structure of the circuitry corresponds to the structure as depicted in Fig. 23a.
  • a resistance of 60 ⁇ and a capacitance of 1.5 pF form the parallel connection of the input impedance of' the device under test DUT.
  • a transmission line of impedance Zo 60 ⁇ is connected to the other terminal of impedance matching circuit.
  • the impedance matching circuit ARC effects a matching of the impedance Zi n of the device under test DUT to the impedance Z 0 of the transmission line such that reflections are inhibited.
  • Fig. 24b shows a Nyquist diagram of the test arrangement as depicted in Fig. 24a. Due to the impedance matching circuit
  • the input impedance Z of the test arrangement is matched to R such that no reflections occur for all frequencies from DC to nearly infinity.
  • FIG. 25 shows a GDDR time domain reflectometry diagram of an input impedance Z measured with the test arrangement as depicted in Fig. 24a.
  • the signal V(2) corresponds to a measured signal at a TDR receiver. Due to the matching condition, the signal energy is fully absorbed in the series connection of impedance matching circuit ARC and device under test DUT such that no reflections are reflected to the TDR receiver and the received signal V (2) shows no reflections or echoes.
  • the transition between 0 and 100 ns is used to represent the non-ideal rising time of the tester driver.
  • Fig. 26 shows a timing diagram of the voltage at the device under test DUT of the test arrangement as depicted in Fig. 24a compared to a voltage at the input impedance of the conventional device under test as depicted in Fig. 4a.
  • the voltage at the device under test DUT V (40) has a rising time that is larger than the voltage V (4) at a device under test DUT of a test arrangement where no impedance matching circuit ARC is present.
  • the introduction of the matching circuit ARC increases the time constant by a factor of coarsly 1+R/ZO.
  • the voltage V(40) has reached 95 % of the transition voltage being 550 mV after about 500 ps, while the voltage V(4) has reached 95 % of the transition voltage 550 mV after a time of about 450 ps.
  • the voltage V(40) at the device under test comprising the impedance matching circuit needs about 400 ps for a transition, while the voltage V (4) at the device under test without a impedance matching circuit needs about 250 ps for a transition.
  • the difference of 150 ps is effected by the impedance matching circuit ARC due to the signal propagations through the electrical circuit.
  • Fig. 27 shows a sectional diagram of a pogo pin used in a test arrangement according to an embodiment of the invention to connect a DUT 210 to an interface 214 of a test head.
  • the test arrangement comprises a device under test package 210 with a connecting ball 211 which is connected by a pogo pin 212 within a device under test socket 213 to a BGA (ball grid array) pad 214 on a circuit board being especially designed for the device under test and being, itself, connected to or part of a tester.
  • the pogo pin 212 is used for contacting the package ball 211 of the device under test package 210 to the BGA pad 214 of the device under test.
  • An elastic spring 215 of and inside the pogo pin 212 generates the force necessary for securely electrically contacting the ball 211 and pad 214, respectively.
  • the pogo pin 212 comprises a first sleeve 216 of conductive material, a second sleeve 217 of conductive material, a tube 218 of resistive material and the spring 215.
  • the spring 215 is of conductive material and is used for urging the first sleeve 216 and the second sleeve 217 apart.
  • the first sleeve 216, the second sleeve 217 and the tube 218 are slidable attached to each other along a common axis 219 of the tube 218 with the resistive tube 218 being positioned between the first sleeve 216 and the second sleeve 217.
  • the first sleeve 216 and the second sleeve 217 may have, in contrast to the pogo pin as depicted in Fig. 6, a same diameter, such that one of the sleeves is not sliding into the other one of the sleeves - in contrast to the pogo pin as depicted in Fig. 6 and 8, where the inner tube 40 slides into the outer tube 42.
  • the adaptation of the longitudinal size of the pogo pin is effected by the tube 218 which slides into the first sleeve 216 and the second sleeve 217.
  • the spring 215 is attached to the tube 218.
  • the spring 215 may be put on the first sleeve 216 and the second sleeve 217, for example according to a mechanism as depicted in Fig. 7a and Fig. 7b.
  • the pogo pin 212 forms a parallel connection of an inductance mainly formed by the spring 21-5 and a resistance mainly formed by the tube 218.
  • the parallel connection corresponds to the impedance matching circuit ARC as depicted in Fig. 23a and Fig. 24a.
  • the pogo pin 212 may be manufactured in such a way, that the resistance formed by the tube 218 corresponds to a resistance of the device under test and that the inductance formed by the spring 215 corresponds to the squared resistance times the capacitance of the device under test.
  • the pogo pin 212 may be manufactured for the specific needs of a specific device under test such as, for example, for a GDDR5 memory device.
  • a new generation of memory devices may require a new pogo pin 212 which components are adapted to the new memory device.
  • the pogo-pin of Fig. 27 may also be designed such that the spring coil 215 contacts the sleeves and/or the resistive tube merely at locations which keep on being in contact with the spring for all possible compression degrees of the pogo-pin.
  • an ARC circuit as described above may be implemented by use of a pogo-pin as shown in Fig. 27.
  • Fig. 28 shows a sectional diagram of a test arrangement according to another embodiment of the invention.
  • the test arrangement corresponds to the test arrangement as depicted in Fig. 27 except that another pogo pin 222 is used.
  • the pogo pin 222 comprises a first sleeve 226 of conductive material, a second sleeve 227 of conductive material, a spring 225 of conductive material for urging the first sleeve 226 and the second sleeve 227 apart, a tube 228 of _ _
  • the first sleeve 226, the second sleeve 227 and the tube 228 are slide-ably attached to each other along a common axis 229 corresponding to the pogo pin 212 as depicted in Fig. 27 except that the tube 228 is of insulating material instead of conductive material.
  • the pogo pin 222 comprises an elastic element 223 which comprises a resistive material such as, for example a resistive elastomer, attached between the first sleeve 226 and the second sleeve 227 along the common axis 229.
  • the elastomer is insulating in lateral direction und resistive in longitudinal direction. This may be achieved be thin wires extending longitudinally but laterally spaced apart through the elastomer body 223 thereby electrically coupling sleeves 226 and 227 from inside.
  • the pogo pin 222 forms a parallel connection of an inductance mainly formed by the spring 225 and a resistance mainly formed by the elastic element 223. Due to the insulating tube 228 which may be of a material such as e.g. PTFE (Teflon) , an electrical circuit is formed from the first sleeve 226 to the second sleeve 227 via the spring 225 and the elastic element 223, respectively. The electric circuit is not formed by the tube 228. This property differentiates the pogo pin 222 depicted in Fig. 28 from the pogo pin 212 as depicted in Fig. 27.
  • PTFE Teflon
  • embodiments of the invention may comprise a pogo pin 222 having a tube 228 of resistive material and an elastic element 223 of resistive material such that an electrical circuit is formed by the spring 225 and by a resistance of the elastic element 223 in parallel to a resistance of the tube 228.
  • the elastic element 228 may comprise an elastomer body having a main longitudinal axis corresponding to the common axis 229 and wires of conductive material embedded in the Elastomer body, so as to extend between a top to a bottom surface of the Elastomer body along the main longitudinal axis.
  • the wires of conductive material may be wires of carbon or wires of gold, for example.
  • the elastic element 228 may be coated by a coating of insulating material so as to prevent a short circuit between the inductance formed the spring 225 and the resistance mainly formed by the elastic element 223.
  • the spring 225 may have an insulating coating.
  • the spring 225 may be a spiral spring or any different kind of spring for urging the first sleeve 226 and the second sleeve 227 apart.
  • Fig. 29a shows a top view of a test arrangement according to an embodiment of the invention.
  • the test arrangement comprises a pogo pin 232 comprising an elastomer body 233 having a main longitudinal axis 234.
  • the pogo pin 232 further comprises wires of conductive material 235 embedded in the elastomer body 233 so as to extend between a top surface 236 to a bottom surface 237 of the elastomer body 233 along the main longitudinal axis 234.
  • the pogo pin 232 forms a parallel connection of an inductance and a resistance, both formed by the wires 235.
  • a magnetic field of, for example, 5 nH corresponding to the inductance of the pogo pin 232 is formed by the wires 235.
  • the wires 235 are embedded in the body 233 in such a way that the wires 235 are electrically disconnected from each other within the body 233.
  • the top surface 236 and the bottom surface 237 may comprise a conductive material so as to electrically contact the pogo pin 232 to a device under test package 210 and a device under test.
  • the wires 235 may be carbon wires resulting in a total resistance of 50 ⁇ .
  • the pogo pin 232 may be used as a shared pin.
  • the body 233 is cylindrically formed. However, in other embodiments the body 233 may have another kind of form and another cross section such as , for example a form a cuboid. _ _
  • Fig. 29b shows a top view of a test arrangement according to another embodiment of the invention.
  • the test arrangement comprises a pogo pin 242 which is similarly formed to the pogo pin 232 as depicted in Fig. 29a with the difference that the wires 245 are made of gold such that a resistance of 1 ⁇ can be achieved.
  • the low ohmic gold wires 245 provide a low inductance of the pogo pin 242 such that the pogo pin 242 can be used as a power or non-shared pin.
  • the pogo pin 242 is mainly configured for contacting purposes and not for impedance matching purposes in contrast to the pogo pin 242 as depicted in Fig. 29a which is mainly configured for matching purposes.
  • the pogo pin 232 as depicted in Fig. 29a may also be used for the elastic element 225 as depicted in Fig. 28.
  • the pogo pin 242 as depicted in Fig. 29b may be used for the elastic element 225.
  • a main idea of the pogo-pin designs as depicted in Figs. 29a and 29b is to adjust the inductivity of a cylindrically formed pogo-pin 232, 242 by increasing or decreasing its diameter due to a relationship between diameter and inductivity of a cylindrically formed object.
  • the inductivity of a cylinder is a function of its diameter.
  • a thin cylinder has a higher inductivity than a thick cylinder.
  • the gold wires 245 are configured to improve the conductivity of the pogo-pin 242.
  • the pogo-pin 242 comprises gold wires which are arranged along the whole diameter of the elastomer
  • the pogo-pin 232 comprises wires 235 which are arranged only along an inner portion of the diameter (core) of the elastomer. Therefore the pogo-pin 242 as depicted in Fig. 29b has a low inductivity compared to the pogo-pin 232 as depicted in Fig. 29a
  • Fig. 29c shows an array of pogo pins according to the pogo pins 232 and 242 as depicted in Fig. 29a/b.
  • the pogo pins 232, 242 have their bottom surfaces 237 connected to a common electrode 246.
  • the test arrangement may be used for forming a pressure sensitive conductive rubber (PCR) socket.
  • the socket may be used for connecting a printed circuit board or other high performance logic components. Large processors, controllers and other ICs require special sockets.
  • These sockets may be PCR-sockets which offer lower force per pin, higher current carrying capacity and electrical performance up to 20 GHz. Pitches may be as low as 0.25 mm, an AC performance is up to 20 GHz and life cycles are up to 200000.
  • PCR-sockets are designed to be drop in compatible with existing spring pin or stamped contacts and are implemented to increase yield and system up time.
  • the PCR Elastomer contact offers high performance and almost invisible device witness marks.
  • Pogo pins as illustrated in Fig. 29a and Fig. 29b may be used for PCR- sockets.
  • some of the pogo pins 242 may be used for power and non-shared pins, while other of the pogo pins 232 may be used as contacting pins providing the impedance matching circuit for usage as a anti- reflection socket pogo pin.
  • Fig. 30 shows an equivalent circuit diagram of a test arrangement comprising an impedance matching circuit 250, a TDR sender 251 and a TDR receiver 252 according to an embodiment of the invention.
  • the TDR sender 251 and the TDR receiver 252 are connected via a coaxial cable 253 to a circuitry comprising the impedance matching circuit 250 preconnected in series to the device under test DUT having an impedance Zj .n formed of a parallel connection of a capacitance of 11 pF and a resistance of 50 ⁇ .
  • the coaxial cable 253 may have a length of 20 cm and a diameter of 5 mm.
  • the impedance matching circuit 250 is to avoid reflections caused by a mismatch of the impedance of the coaxial cable 253 and the impedance Zi n of the device under test DUT.
  • Fig. 31 shows a TDR diagram measured with the test arrangement as depicted in Fig. 30 comprising the impedance matching circuit 250.
  • the TDR diagram as depicted in Fig. 31 shows nearly no reflections, besides a small reflection after about 2.1 ns which is caused by a parasitic equivalent series inductance (ESL) of the series resistance R of the impedance matching circuit 250.
  • ESL equivalent series inductance
  • a lower value for the inductance of the impedance matching circuit 250 may compensate the parasitic ESL of the resistance R of the impedance matching circuit 250. Due to the less distortions of the TDR signal the test arrangement comprising the impedance matching circuit 250 allows a measurement with higher sampling rates and therefore a high precision measurement of fast memory devices, e.g. GDDR5 memory devices.
  • Fig. 32 shows an equivalent circuit diagram of a test arrangement comprising an impedance matching circuit 250 corresponding to the test arrangement as depicted in Fig. 30, a TDR sender 251 corresponding to the test arrangement as depicted in Fig. 30 and a TDR receiver 254.
  • an RTL (rise time limitation) circuitry is connected for limitation of the rise time of signals generated at the TDR sender 251 to a value of 250 ps.
  • the surface microstrip transmission line 255 is connected to the impedance matching circuit 250 which is serially connected to the device under test DUT having the input impedance Zi n formed of a parallel connection of a capacitance 11 pF and a resistance of 50 ⁇ .
  • Fig. 33 shows an eye diagram of a signal received at the TDR receiver 254 of the test arrangement as depicted in Fig. 32.
  • the eye diagram shows a nearly open eye which is only a little bit disturbed by small reflection 260 due to the parasitic ESL of the resistance R of the impedance matching circuit 250. Compared to the eye diagram as depicted in Fig.
  • FIG. 12 illustrating a test arrangement without an impedance matching circuit 250
  • the distortions in the eye diagram as depicted in Fig. 33 comprising an impedance matching circuit 250 are substantially smaller.
  • a test arrangement comprising an impedance matching circuit 250 or anti-reflective circuit, respectively, allows a precision measurement with an accuracy even at high sampling rates.
  • the test arrangement as depicted in Fig. 32 is well-suited for measuring high rated sampling devices, for example GDDR5 memory devices .
  • Fig. 34a shows a schematic sectional view of a test arrangement comprising an SMA adapter 300 terminating a coaxial cable (not shown) by a series connection of an ODT load emulation 302 and an impedance matching circuit 301 according to an embodiment of the invention.
  • the impedance matching circuit 301 comprises a parallel connection of an inductance 303 of 27 nH and a resistance 304 of 50 ⁇ .
  • the resistance of 50 ⁇ is realized by a parallel connection of two 100 ⁇ resistors to reduce the parasitic ESL.
  • the ODT load emulation 302 is realized by a parallel connection of a capacitance 305 of 11 pF and a resistance 306 of 50 ⁇ .
  • the capacitance 305 of the ODT load emulation 302 is realized by a parallel connection of a 10 pF capacitor and a 1 pF capacitor.
  • the resistance 306 may be realized by a parallel connection of two standard 100 ⁇ resistors.
  • the circuitry of impedance matching circuit 303 and ODT load emulation 302 is connected between a core 307 and a ground connection 308 of the SMA adapter cable 300.
  • the electric components are discrete components such as, for example, SMD components.
  • Fig. 34b shows an equivalent circuit diagram of the test arrangement as depicted in Fig. 34a.
  • the impedance matching circuit 301 is in series connected to the ODT load emulation 302 of the device under test.
  • the inductance 303 is 27 nH, both resistances 304, 306 are 50 ⁇ and the capacitance 305 is 11 pF.
  • the impedance matching circuit 301 is dimensioned such that the resistance 304 of the impedance matching circuit 301 corresponds to the resistance 306 of the ODT load emulation and such that the inductance 303 of the impedance matching circuit 301 corresponds to the squared resistance 306 of the ODT load emulation 302 times the capacitance 305 of the ODT load emulation 302.
  • This matching condition guarantees a suppression of unwanted reflections. Due to the nature of electric components which are tolerance-effected the components 303, 304 of the impedance matching circuit 301 may range within a tolerance region of, for example, 10 % around the optimum values which are determined by the matching condition presented above.
  • Fig. 35 shows a Smith diagram of a reflection factor measurement of the test arrangement as depicted in Fig. 34a.
  • the Smith diagram as depicted in Fig. 35 of a reflection factor of the test arrangement comprising the impedance matching circuit 301 shows a matching property for nearly all frequencies.
  • the measurement is performed from a DC frequency up to a frequency of about 1 GHz. Even at frequencies of about 1 GHz the reflection factor r has only a very small complex value amplitude compared to the reflection factor r as depicted in Fig. 14.
  • the remaining amplitude deviating from zero may be caused by the equivalent series inductance of the resistance 304 of the impedance matching circuit 301 corresponding to the measurements as depicted in Figs. 31 and 33.
  • Fig. 36 shows an equivalent circuit diagram of a test arrangement comprising two impedance matching circuits 320, each of them associated with a device under test 321, a TDR sender 322 and respective TDR receivers 323.
  • the test arrangement further comprises a Y-cable 324 to connect the TDR sender 322 to both of the devices under test 321.
  • the TDR sender 322 comprises a RTL circuitry for rise time limitation to 250 ps of the signal generated by the TDR sender.
  • the Y-branch cable has the structure of a Y comprising a transmission line 325, a first lead line 326 and a second lead line 327.
  • the lead line 325 is connected by a via to the first lead line 326 and the second lead line 327.
  • the transmission line 325 has an impedance of 50 ⁇ and may be realized by a Gore cable of a length of 1 m and a diameter of 5 mm.
  • the first and second lead lines 326, 327 have impedances of 50 ⁇ and may be realized by Rosenberger cables having a length of 20 cm and a diameter of 5 mm.
  • the Y-branch cable further comprises a SMA adapter cable 327 which is connected between the first lead line 326 and an output of the Y-branch cable to produce an intentional length mismatch.
  • the SMA adapter cable has a length of 3 cm.
  • the output of the SMA adapter cable 327 is connected to the impedance matching circuit 320 of the first device under test and the output of the second output cable 327 is connected to the impedance matching circuit 320 of the second device under test.
  • Fig. 37 shows a TDR diagram measured with the test arrangement as depicted in Fig. 36.
  • the TDR measurement shows that although the Y-branch cable 324 has an unsymmetrical structure, no reflections occur at the measurement point where the TDR receiver 323 measures received signals at the device under test 321. Due to the impedance matching circuit 320 which is matched to the impedance of the device under test 321 reflections are cancelled in the circuitry comprising the impedance matching circuit 320 and the device under test 321. Reflections from the Y-branch cable back to the TDR sender 322 are canceled in the TDR sender 322, such that they are not influencing are measurement at the device under test 321.
  • Fig. 38 shows an equivalent circuit diagram of a test arrangement comprising two impedance matching circuits 320, each of them associated with a device under test 321, a Y- branch cable 324 with length mismatch, a test signal sender 330 and a test signal receiver 331.
  • the Y-branch cable 324, the impedance matching circuits 320 and the devices under test 321 correspond to the circuits as depicted in Fig. 36.
  • the test arrangement differs in the type of measurement, the test arrangement as depicted in Fig. 36 is used for a time domain reflectometry measurement, while the test arrangement as depicted in Fig. 38 is used for a signal measurement such as, for example, for measuring an eye diagram at the device under test 321.
  • the test signal sender 330 may be a bit error rate tester (BERT) or a pseudo random binary sequence (PRBS) generator.
  • BERT bit error rate tester
  • PRBS pseudo random binary sequence
  • Fig. 39 shows an eye diagram measured with the test arrangement as depicted in Fig. 38.
  • the eye diagram shows no distortions due to reflections. However, rising times are decreased compared to a test arrangement with a single transmission line as depicted in Fig. 32. Between a 20 % transition point and an 80 % transition point a rising time of about 800 ps can be measured.
  • the eye diagram shows that a symmetrically Y-branch cable is not required for measuring devices under test without reflections.
  • the Y- branch sharing cable may be dimensioned according to the needs of the device under test without considering symmetry conditions. Shorter cables will improve rise times and a droop compensation will give an additional improvement for the rise times.
  • the input line, the first output line and the second output line may comprise transmission lines, wave guides, micro strip lines, strip conductors of a printed circuit board, via's, connecting (micro-) strip lines, high frequency microwave cables, connectors, interconnectors or assemblies, SMA adaptors, coaxial cables and the output lines may deviate from a symmetry condition in that, for example, an impedance of the first output line deviates from an impedance of the second output line by more than 5 percent or such that an impedance of a parallel-connection of the impedance of the first output line and the impedance of the second output line deviates from an impedance of the input line by more than 5 percent.
  • a length of the output lines/ branches may deviate more than 1%
  • the impedances of the devices under test may deviate from each other by more than 1%
  • the first output line may be formed in another layer than the second output line within a circuit board with via connecting thee lines to the common input line being thus asymmetrical.
  • Fig. 40 shows a circuit diagram of a test arrangement comprising the branch circuit board 120 as depicted in Fig. 17 and impedance matching circuits 340 connected between respective output lines 122, 123 and respective impedances of the devices under test DUTl, DUT2 according to an embodiment of the invention.
  • An impedance Z 2 of the output lines can be 60 ⁇ while the impedance Zi of the input line is 60 ⁇ . Symmetry is no longer required, e.g. no length matching is required anymore.
  • the rise times are significantly faster since line impedance is significantly lower.
  • the devices under test DUTl, DUT2 may be GDDR5 memory devices.
  • Fig. 41 shows an equivalent circuit diagram of a test arrangement comprising two devices under test DUTl, DUT2 according to an embodiment of the invention.
  • the test arrangement corresponds to the test arrangement as depicted in Fig. 40 as far as the Y-branch 120, the devices under test DUTl, DUT2 and the impedance matching circuits ARC are concerned.
  • the impedance matching circuits 340 are expressed by a parallel connection of an inductance of 5.4 nH and a resistance of 60 ⁇ .
  • the elements of the impedance matching circuits 340 are dimensioned in accordance with the matching condition: a same resistance of impedance matching circuit 340 and device under test impedance and an inductance being the squared resistance times the capacitance of the device under test.
  • a signal generator 350 is coupled to the test interface 126 and is used for generating test signals for testing the devices under test DUTl, DUT2.
  • Fig. 42 shows a simulated eye diagram of a first input signal v(10) of the test arrangement as depicted in Fig. 41.
  • the sampling time is 2.5 Gbps.
  • the signal generator 350 generates a 2 7 pseudo random binary sequence (PRBS) .
  • PRBS pseudo random binary sequence
  • a rising time t R is reduced to a value of about 130 ps compared to the rising time of 800 ps as depicted in Fig. 39 measured with the arrangement as depicted in Fig. 38.
  • the increase in rising time t R is a consequence of the impedance matching circuitry required to avoid the reflections.
  • Fig. 43 shows an equivalent circuit diagram of a test arrangement comprising four devices under test DUTl, DUT2, DUT3, DUT4 according to an embodiment of the invention.
  • the test arrangement comprises a microstrip line 360 which is connected between a test interface 126 for a device tester 350 and for series connections of impedance matching circuits ARC and devices under test DUTl - DUT4.
  • the microstrip line 360 comprises four branching nodes 361, 362, 363 and 364, such that an impedance of the microstrip line 360 between the test interface 126 and the first branching node 361 is 25 ⁇ , an impedance of the microstrip line 360 between the first branching node 361 and the second branching node 362 is 33 ⁇ , an impedance of the microstrip line 360 between the second branching node 362 and the third branching node 363 is 50 ⁇ and an impedance of the microstrip line 360 between the third branching node 363 and the fourth branching node 364 is 100 ⁇ .
  • the microstrip line 360 is dimensioned such that impedances of output lines between the respective branching nodes 361 - 364 and the impedance matching circuits ARC connecting the respective devices under test DUTl - DUT4 is about 100 ⁇ .
  • the branching nodes 361 to 364 are arranged on the microstrip line 360 and between the test interface 126 such that resistive line elements 365 are formed, wherein each of the resistive line elements 364 has a resistance of 100 ⁇ .
  • the microstrip line 360 comprises four resistive line elements 365 connected in parallel between the test interface 126 and the first branching node 361 amounting to a resistance of 25 ⁇ .
  • first branching node 361 and the second branching node 362 three resistive line elements 365 are connected in parallel amounting to a resistance of 33 ⁇ . Between the second branching node 362 and the third branching node 363 two of the resistive line elements 365 are connected in parallel amounting to a resistance of 50 ⁇ . Between the third branching node 363 and the fourth branching node 364 one of the resistive line elements 365 is connected amounting to a resistance of 100 ⁇ .
  • Fig. 44 shows a signal diagram of four input signals of the test arrangement as depicted in Fig. 43.
  • the signals v(10), v(ll), v(12) and v(13) are measured at the respective devices under test DUTl - DUT4.
  • the microstrip line 360 shows a highly asymmetric structure the signals v(l ⁇ ) - v(13) are free of reflections due to the preconnected impedance matching circuits ARC which cancel out reflections from the devices under test DUTl- DUT4.
  • Fig. 45 shows an eye diagram of the first input signal v(10) of the test arrangement as depicted in Fig. 43.
  • the eye diagram is not distorted by reflections. However, rising times t R of about 200 ps affect the eye diagram such that the eye is not full opened.
  • the eye diagram as depicted in Fig. 45 is more widely opened such that higher precision measurements at, for example, GDDR5 memory devices are possible.
  • the distortions which can be seen in the eye diagram as depicted in Fig. 21b are canceled from the eye diagram as depicted in Fig. 45.
  • Fig. 46 shows a schematic diagram of a test arrangement comprising an impedance matching circuit ARC.
  • Fig. 46 shall show a circuit board provided with an array 371 of pads for being electrically connected to the pads of a DUT.
  • the lateral distrbution of the pads 371 may comply to the footprint and pad distribution of the DUT.
  • each of the pins 371 may by provided with an ARC
  • Fig. 46 shows merely one ARC for a representative pad 372.
  • the ARC is coupled to the contact pad 372 via a first transmission line 381 being, for example, implemented as a signal trace embedded within the circuit board and being connected to the contact pad 372 formed on an outer surface of the circuit board by a via 382.
  • the distance length between he ARC and pad 372 extending via the first transmission line 381 and the via 382 may have a length smaller than a quarter of a mean wavelength ⁇ of a test signal used to test the DUT via the pad 372.
  • the contact pads 371, 372 may be arranged in a symmetrical structure to form a ball grid array (BGA) .
  • the inductor and the resistor device may be stacked one upon the other as shown in Fig. 46. Both may be arranged on top of the outer surface of the circuit board on which the pads 371 are formed.
  • the ARC circuit is formed by SMD parts.
  • a via 383 may connect the ARC with the transmission line 381. At the other terminal of ARC, same may be connected to a lead line which, in turn, connects to a tester or test head.
  • a via 384 and a trace 385 may be connected to the ARC such that the ARC is serially connected between the traces 385 and 381.
  • Trace 385 may be connected to a fork node formed on the circuit board as depicted in the forgoing embodiments.
  • the no fork node may occur between the ARC and a signal generator of the tester.
  • Fig. 47 shows a timing diagram of signals measured with a discrete component ARC impedance matching circuit as depicted in Fig. 46 versus a pogo pin ARC impedance matching circuit as depicted in Fig. 42.
  • the pogo pin ARC measurement signal V (8) has a slightly faster rising time than the discrete component ARC measurement signal V (80) .
  • the inductance L of the impedance matching circuit ARC should be matched to an input impedance of the device under test having a transmission line length smaller than a quarter wavelength of the test signal.
  • a value of 6.2 nH has been found to nearly optimally adjust the impedance matching circuit ARC to the new input impedance of the device under test.
  • the impedance matching circuit ARC acts like a moderate and benign low-pass filter. A droop compensation circuitry in the tester pin electronic card will be able to compensate the low-pass characteristic.
  • Embodiments of the invention comprising an impedance matching circuit ARC are scalable, reflections would not limit the speed anymore.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

La présente invention concerne un mécanisme d'essai (400) comportant une interface (401) pour un dispositif à l'essai (404), l'interface (401) comprenant un circuit d’appariement d'impédances (402) comportant une résistance (R) et une bobine d'induction (L) connectées en parallèle.
PCT/EP2008/009178 2008-10-30 2008-10-30 Mécanisme d'essai, broche à effet pogo et procédé pour l'essai d'un dispositif à 'essai WO2010048971A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/EP2008/009178 WO2010048971A1 (fr) 2008-10-30 2008-10-30 Mécanisme d'essai, broche à effet pogo et procédé pour l'essai d'un dispositif à 'essai
TW098136658A TWI414791B (zh) 2008-10-30 2009-10-29 測試配置裝置、彈簧銷針及用以測試受測元件之方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2008/009178 WO2010048971A1 (fr) 2008-10-30 2008-10-30 Mécanisme d'essai, broche à effet pogo et procédé pour l'essai d'un dispositif à 'essai

Publications (1)

Publication Number Publication Date
WO2010048971A1 true WO2010048971A1 (fr) 2010-05-06

Family

ID=41011371

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/009178 WO2010048971A1 (fr) 2008-10-30 2008-10-30 Mécanisme d'essai, broche à effet pogo et procédé pour l'essai d'un dispositif à 'essai

Country Status (2)

Country Link
TW (1) TWI414791B (fr)
WO (1) WO2010048971A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107577860A (zh) * 2017-08-29 2018-01-12 西安电子科技大学 基于单根金丝键合的微波器件路耦合传输性能预测方法
CN110554346A (zh) * 2019-08-06 2019-12-10 国网四川省电力公司电力科学研究院 用于同轴传输线末端匹配电阻分压器的频率响应测试装置
US11156637B2 (en) 2018-06-14 2021-10-26 Formfactor, Inc. Electrical test probes having decoupled electrical and mechanical design

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110166027B (zh) * 2019-04-30 2023-07-04 华太极光光电技术有限公司 高压脉冲信号产生装置及方法
US11733290B2 (en) 2020-03-31 2023-08-22 Advantest Corporation Flexible sideband support systems and methods
US11619667B2 (en) * 2020-03-31 2023-04-04 Advantest Corporation Enhanced loopback diagnostic systems and methods

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6264476B1 (en) * 1999-12-09 2001-07-24 High Connection Density, Inc. Wire segment based interposer for high frequency electrical connection
US20010035800A1 (en) * 1999-02-25 2001-11-01 Formfactor, Inc. Integrated circuit tester with high bandwidth probe assembly
EP1152425A2 (fr) * 2000-05-02 2001-11-07 Infineon Technologies AG Dispositif de mémoire
US6323667B1 (en) * 1996-12-27 2001-11-27 Nhk Spring Co., Ltd. Contact probe unit
US6442718B1 (en) * 1999-08-23 2002-08-27 Sun Microsystems, Inc. Memory module test system with reduced driver output impedance
EP1248444A1 (fr) * 2001-02-12 2002-10-09 Harris Corporation Appareil téléphonique de test analogue possedant un filtre passe-bas et des resistances couplées avec les lignes de connection pour prévenir l'alteration des signaux de communication numériques
US20030137316A1 (en) * 2000-06-16 2003-07-24 Toshio Kazama Microcontactor probe and electric probe unit
US6642707B1 (en) * 2000-09-13 2003-11-04 Teradyne, Inc. High-speed peaking circuit for characteristic impedance control
US20030210067A1 (en) * 2002-05-08 2003-11-13 Miller Charles A. Test signal distribution system for IC tester
US6785148B1 (en) * 1998-12-21 2004-08-31 Intel Corporation Easy mount socket
US20050227383A1 (en) * 2004-04-09 2005-10-13 Masayoshi Okamoto Manufacturing method of semiconductor integrated circuit device and probe card
EP1648045A1 (fr) * 2004-10-06 2006-04-19 LG Electronics Inc. Système de contact de batterie et terminal sans fil utilisant le mème
EP1686385A1 (fr) * 2003-11-05 2006-08-02 NHK Spring Co., Ltd. Support de contact conducteur et unite de contact conducteur
WO2006116600A1 (fr) * 2005-04-28 2006-11-02 Ardent Concepts, Inc. Ensemble contact electrique flexible
US20070082515A1 (en) * 2005-02-24 2007-04-12 Glenn Goodman Interconnecting electrical devices

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323667B1 (en) * 1996-12-27 2001-11-27 Nhk Spring Co., Ltd. Contact probe unit
US6785148B1 (en) * 1998-12-21 2004-08-31 Intel Corporation Easy mount socket
US20010035800A1 (en) * 1999-02-25 2001-11-01 Formfactor, Inc. Integrated circuit tester with high bandwidth probe assembly
US6442718B1 (en) * 1999-08-23 2002-08-27 Sun Microsystems, Inc. Memory module test system with reduced driver output impedance
US6264476B1 (en) * 1999-12-09 2001-07-24 High Connection Density, Inc. Wire segment based interposer for high frequency electrical connection
EP1152425A2 (fr) * 2000-05-02 2001-11-07 Infineon Technologies AG Dispositif de mémoire
US20030137316A1 (en) * 2000-06-16 2003-07-24 Toshio Kazama Microcontactor probe and electric probe unit
US6642707B1 (en) * 2000-09-13 2003-11-04 Teradyne, Inc. High-speed peaking circuit for characteristic impedance control
EP1248444A1 (fr) * 2001-02-12 2002-10-09 Harris Corporation Appareil téléphonique de test analogue possedant un filtre passe-bas et des resistances couplées avec les lignes de connection pour prévenir l'alteration des signaux de communication numériques
US20030210067A1 (en) * 2002-05-08 2003-11-13 Miller Charles A. Test signal distribution system for IC tester
EP1686385A1 (fr) * 2003-11-05 2006-08-02 NHK Spring Co., Ltd. Support de contact conducteur et unite de contact conducteur
US20050227383A1 (en) * 2004-04-09 2005-10-13 Masayoshi Okamoto Manufacturing method of semiconductor integrated circuit device and probe card
EP1648045A1 (fr) * 2004-10-06 2006-04-19 LG Electronics Inc. Système de contact de batterie et terminal sans fil utilisant le mème
US20070082515A1 (en) * 2005-02-24 2007-04-12 Glenn Goodman Interconnecting electrical devices
WO2006116600A1 (fr) * 2005-04-28 2006-11-02 Ardent Concepts, Inc. Ensemble contact electrique flexible

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107577860A (zh) * 2017-08-29 2018-01-12 西安电子科技大学 基于单根金丝键合的微波器件路耦合传输性能预测方法
CN107577860B (zh) * 2017-08-29 2019-09-10 西安电子科技大学 基于单根金丝键合的微波器件路耦合传输性能预测方法
US11156637B2 (en) 2018-06-14 2021-10-26 Formfactor, Inc. Electrical test probes having decoupled electrical and mechanical design
CN110554346A (zh) * 2019-08-06 2019-12-10 国网四川省电力公司电力科学研究院 用于同轴传输线末端匹配电阻分压器的频率响应测试装置
CN110554346B (zh) * 2019-08-06 2021-06-22 国网四川省电力公司电力科学研究院 用于同轴传输线末端匹配电阻分压器的频率响应测试装置

Also Published As

Publication number Publication date
TWI414791B (zh) 2013-11-11
TW201024739A (en) 2010-07-01

Similar Documents

Publication Publication Date Title
EP1825282B1 (fr) Module de signalisation a reflexions reduites
US4418314A (en) High impedance fast voltage probe
US20120274338A1 (en) High performance time domain reflectometry
WO2010048971A1 (fr) Mécanisme d'essai, broche à effet pogo et procédé pour l'essai d'un dispositif à 'essai
US6501278B1 (en) Test structure apparatus and method
US20030210067A1 (en) Test signal distribution system for IC tester
CN101790690B (zh) 非接触式测量系统
CN112710977B (zh) 基于trm校准的表贴无源器件s参数测量装置及方法
US8098076B2 (en) Method and apparatus for terminating a test signal applied to multiple semiconductor loads under test
Carlton et al. Accurate measurement of high-speed package and interconnect parasitics
US9726707B1 (en) Controlled impedance charged device tester
Resso et al. Signal integrity characterization techniques
Ranieri et al. A novel 24-GHz bandwidth coaxial probe
Chen et al. Electrical characterization of BGA test socket for high-speed applications
van der Merwe et al. S-parameter measurements yielding the characteristic matrices of multiconductor transmission lines
Wang et al. The impact of electrical contact degradation on differential signal transmission of high speed channel
US10267838B1 (en) Current sensor having microwave chip resistors in parallel radial arrangement
Caniggia et al. Full-wave investigation of EFT injection clamp calibration setup
JP2628262B2 (ja) プローブ減衰器
Huang et al. Probe with absorbing materials
Rosas et al. Development of a 1.85 mm coaxial blind mating interconnect for ATE applications
Petersson et al. A New Calibration Kit for VNA Measurements of General Microstrip Line Devices Using Gap Waveguide Technology
Gumparthi Crosstalk in Flat Cables for Transmission of Single Ended Digital Signals Over Medium Distances
Maichen High-Speed Digital Test Interfaces
Goldberg et al. Experimental electrical characterization of high speed interconnects

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08874997

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08874997

Country of ref document: EP

Kind code of ref document: A1