TW201024739A - Test arrangement, pogo-pin and method for testing a device under test - Google Patents

Abstract

A test arrangement comprises an interface for a device under test, the interface comprising an impedance matching circuit comprising a resistance (R) and an inductance (L) connected in parallel.

Description

201024739 VI. Description of the Invention: [Brief of the present invention] Embodiments of the present invention relate to a configuration device, a spring pin, and a method for testing a device under test. In the set state of the wafer test technique, the wheel/pin (pi η) of a device under test (DUT) is connected to the test circuit by a pin of the test head of the tester. Sometimes, the signal is transmitted from the device under test to the pin of the test head or the pin of the test head to the device under test using the device-specific board under test. The corresponding input of the one-step multiple DUTs can be connected to a common pin of the test head; All of these configuration devices introduce problems in the test design because the transmission from one impedance domain to the other is reflected, which becomes more severe at higher test signal rates. These reflections then hinder the performance of reliable testing. [Description of Contents] φ According to an embodiment of the present invention, a test configuration apparatus is specifically provided, comprising: an interface for a device under test, the interface comprising an impedance matching circuit, the impedance matching circuit comprising A resistor (r) and an inductor (L) are connected in parallel. BRIEF DESCRIPTION OF THE DRAWINGS The invention may be described with reference to the accompanying drawings: Figure 1 shows a beam diagram in which light is reflected by or through an optical material, depending on an optical anti-reflective coating of the optical material. The main idea of the basis of the embodiments of the invention described below is one of 3 201024739; Figure 2a shows a schematic view of the scenario of Figure 1 'that the light is transmitted through the raft with ambient air An optical medium having a different index of reflection index; FIG. 2b is a schematic diagram showing an electrical transmission line connected to a device under test according to the optical arrangement device shown in FIG. 2a, the device under test having a transmission line The impedance of the impedance is different; Figure 3a shows an equivalent circuit diagram of the input impedance of a device under test' including a resistive "terminal built into the chip," and a capacitive input capacitor; Figure 3b shows One represents the Nyquist of the input impedance in Figure 3a. · Figure 4a shows an equivalent circuit diagram of an input impedance of a device under test. The input impedance is illustrative. A specific resistance and inductance value is built into the terminal of the wafer and a gate and an ESD (electrostatic discharge) capacitor; Figure 41) shows a Nyquist field illustrating the input impedance in Figure 4a. Figure 5 is a diagram showing a TDR (time domain reflection) of the input impedance of a GDDR5 memory; Figure 6 shows a cross-sectional view of a circuit spring pin according to a comparative embodiment, and Figure 7a shows another comparison. A top view of the inner member of the spring pin of the embodiment and a spring for separating the inner member and the outer sleeve from each other; 201024739 Fig. 7b shows a plan view of a device in a state of compression in Fig. 7a, Figure 8 shows a top view of an outer sleeve of the spring pin shown in Figures 7a and 7b; Figure 9 shows a short-circuited test element through the spring pin of Figures 7a through 8 ( A time domain reflection (TDR) map measured at an input pin of the DUT); FIG. 10 shows a histogram illustrating a spring using the spring pin shown in FIGS. 7a to 8 Repeatability of pin measurement; 11th A TDR map is shown, which is measured by a comparative test configuration device for measuring a DUT; Figure 12 shows a device under test for measuring an impedance mismatch. Testing the eye diagram of a signal received at a TDR receiver in the configuration device, Figure 13a shows an SMA (sub-miniature-A) adapter cable terminated by an ODT load simulation Schematic cross-sectional view; Figure 13b shows an equivalent circuit diagram of the SMA adapter cable terminated by the end-of-wafer terminal (ODT) load terminal as shown in Figure 13a; Figure 14 shows A pole diagram of an input impedance of the SMA adapter cable with the ODT load terminal as the terminal as shown in Fig. 13a; Figure 15 shows a componentless daisy chain test configuration device measured A TDR diagram; Figure 16 shows a TDR diagram measured using the Chrysanthemum 5 201024739 chain test configuration device that has loaded DDR2 components at all locations; Figure 17 shows the connection of one test pin to two a circuit diagram of a branch on the component under test, the branch containing - a shared line And two branches connected through a branch node; Figure 18 shows a circuit diagram of the branch as shown in Figure π, wherein the impedance of the branch lines and the input impedance of the DUTs are specific values; Figure 19 shows - a conventional branch circuit diagram as shown in Figure 17, which indicates the reflection that occurs; Figure 20a shows a circuit diagram of a daisy chain test configuration device for measuring dut in a shared test channel; The figure shows a TDR diagram measured using the test configuration device shown in item 2; the figure shows a step response timing diagram of the test signal applied to a daisy chain configuration device; the 2 lb diagram shows An eye diagram of the test signal shown in Figure 21a &21a; Figure 22a shows a transmission through an optical medium as shown in the & Figure when the optical medium is made of an anti-reverse (four) layer material - a wave pattern of the optical film time; Figure 22b shows a signal diagram similar to Figure 22a, in accordance with one embodiment of the present invention, the (four) picture is a first electrical transmission line and has a connection between the transmission line and the impedance of the terminal Resistance a circuit (impedance matching circuit); FIG. 23a shows a schematic diagram of a test configuration package 201024739 according to an embodiment of the present invention; and FIG. 23b shows a test configuration device according to another embodiment of the present invention. FIG. 23c is a diagram showing an equivalent circuit diagram of a test configuration apparatus according to an embodiment of the present invention; and FIG. 23d is a schematic diagram showing a test configuration apparatus according to an embodiment of the present invention, the test configuration apparatus Includes a device tester, a test interface, and a number of interfaces for most of the components under test; ® Figure 2 3 e shows the theoretical input impedance of the test configuration device as shown in Figure 2 3 a a Nyquist diagram; Figure 24a shows an equivalent circuit diagram of one of the illustrative configurations of the GDDR5 memory component shown in Figure 4a, having an embodiment in accordance with an embodiment of the present invention An impedance matching circuit between the transmission line and the device under test; Figure 24b shows a theoretical Nyquist of the test configuration device as shown in Figure 24a Figure 25 shows a theoretical TDR diagram measured using the test configuration device as shown in Figure 24a; Figure 26 shows the measured component of the test configuration device as shown in Figure 24a A step response timing diagram comparing the voltage at the voltage to the voltage at the input impedance of the device under test generated in the case of Figure 4a; Figure 27 shows a spring pin in accordance with an embodiment of the present invention A schematic cross-sectional view of the needle; Figure 28 shows a schematic cross-sectional view of a spring pin 7 201024739 in accordance with another embodiment of the present invention; Figure 29a shows an embodiment in accordance with the present invention A spatial view of a spring pin; Figure 29b shows a spatial view of a spring pin in accordance with another embodiment of the present invention; Figure 29c shows a test in accordance with an embodiment of the present invention A top view of a configuration device; FIG. 30 shows an equivalent circuit diagram of a test configuration device according to an embodiment of the present invention, the test configuration device comprising an impedance matching circuit, a TDR transmitter and a TDR receiver; 31 shows A TDR diagram measured using the test configuration device as shown in FIG. 30; FIG. 32 is an equivalent circuit diagram showing a test configuration device according to an embodiment of the present invention, the test configuration device including a An impedance matching circuit, a TDR transmitter, a microstrip line, and a measuring probe; FIG. 3 3 shows an eye diagram of a signal received by the TD R receiver of the test configuration device as shown in FIG. Figure 34a shows a schematic cross-sectional view of a test configuration device including an SMA adapter cable emulated with an ODT load and an impedance matching circuit, in accordance with an embodiment of the present invention Connected as a terminal; Figure 34b shows an equivalent circuit diagram of the test configuration device as shown in Figure 34a; Figure 35 shows a 201024739 reflection coefficient measurement of the test configuration device as shown in Figure 34a A Smith chart; Figure 36 shows an equivalent circuit diagram of a test configuration device according to an embodiment of the present invention, the test configuration device comprising two impedance matching circuits, each impedance matching circuit and a The device under test, a length mismatched Y-branch cable, a TDR transmitter, and a measurement probe are associated; Figure 37 shows the measurement using the test configuration device as shown in Figure 36. A signal diagram; Figure 38 shows an equivalent circuit diagram of a test configuration apparatus according to an embodiment of the present invention, the test configuration apparatus comprising two impedance matching circuits, each impedance matching circuit and a device under test a length mismatched Y-branch cable, a test signal transmitter, and a test signal receiver; % Figure 39 shows an eye measured using the test configuration device as shown in Figure 38 Figure 40 is a circuit diagram showing a test configuration device including the branch as shown in Figure 17 and connected to respective output lines and the device under test, in accordance with an embodiment of the present invention. An impedance matching circuit between respective impedances; Figure 41 shows an equivalent circuit diagram of a test configuration device comprising two components under test in accordance with an embodiment of the present invention; Figure 42 shows 41 picture A simulated eye diagram of a simulated first input signal of the test configuration device; FIG. 43 shows an equivalent circuit diagram of a test configuration device in accordance with an embodiment of the present invention, the test configuration device comprising four The device under test; Fig. 44 shows a signal diagram of four input signals of a model 9 201024739 of a test configuration device as shown in Fig. 43; Fig. 45 shows the image as shown in Fig. 44. Testing an eye diagram of the simulated first input signal of the configuration device; Figure 46 shows a schematic diagram of a test configuration %罝 device, the test configuration device including an impedance matching circuit called the impedance matching circuit through a first transmission line Receiving a first device under test and coupling to a second transmission line via a second transmission line: the second device under test having a carrier of the ratio test signal

a length of the skin length and the second transmission line has a length greater than a quarter wavelength of the carrier of the test signal; and FIG. 47 shows the first acceptance in the first image as shown in FIG. The measurement component is measured and the second component under test is a timing diagram of the signal obtained by the thousand retest. [Poverty Mode 3] Next, a main idea existing in the present invention is explained by the reflection problem in the reference optics, which shows that (4) is similar to _

The occurrence of the electrical measurement test configuration introduced the role of the reflection problem in optics and then converted these measures into the electrical measurement test configuration device in the form of most of the embodiments of the present invention. Figure 1 shows the optical phase, which is reflected by the optical material or passed through the optical material. As shown in Figure 1, the ratio between reflection and transmission depends on the optical material - the conventional anti-reflective coating is a turn. The upper portion 10 of the optical material is not coated with an anti-reflective coating and the lower portion 12 of the optical material is coated with an anti-reflective coating. The optical material can be a lens 14 and an anti-reflective coating can be applied to the outer surface of the lens 14 remote from the viewer (not shown) to reduce reflection of the transmitted light. This reflected light may interfere with the observer. For example, the inverse 10 201024739 shot reduces transmission. Further, the reflected light may reach an area where light is not desired to be sensitive to light. In complex systems such as a telescope, for example, the drop in reflection can increase the contrast of the image by eliminating stray light. In other applications, such as, for example, applying an anti-reflective coating to an eyeglass lens, the primary benefit is to eliminate its own reflections, thus resulting in a better vision and a brighter view. In Fig. 1, for example, the optical material 14 does not include an upper portion of the anti-reflective coating, a beam of light 16 is mostly reflected back by the lens 14, and only a portion of the upper light 16 that has been strongly attenuated passes through the lens 14. At the lower portion of the optical material 14 coated with an anti-reflective coating, a beam of light 18 passes mostly through the lens 14. When the optical material 14 comprises an appropriately sized anti-reflective coating, up to 99% of the beam 18 in Figure 1 passes through the optical material 14. Figure 2a shows a conventional optical medium in which light is transmitted through a reflection index having a different index of reflection than ambient air. The beam 2 is moved by an optical medium such as air into another optical medium glass 22 such as glass, wherein the glass 22 has a reflection index ηι greater than the reflection index of the air, where η() = ι η, ie ηι > η0. A portion r of the beam 2 is reflected by the surface of the glass 22, and another portion b of the beam 20 passes through the glass 22. The intensity of this reflection depends on the reflection index of the two media as (1) and the angle between the surface and the beam 20. The exact value can be calculated using Fresnel equations. The simplest form of anti-reflective coating was discovered by L〇rd Rayleigh in 1886. A thin film anti-reflective coating (ARC) on the surface of the glass 22 reduces reflection. A film having a refractive index ~ team material between the air having a refractive index nQ and the glass having a refractive index ~ can cause the light 11 201024739 beam to be reflected twice, that is, from the interface between the air and the thin ARC layer. And reflecting from the interface of the thin ARC layer and the glass. Figure 2b shows a signal diagram which is a conventional electrical transmission line 'with a terminal impedance formed by a device under test, the terminal impedance being different from the impedance of the transmission line. An electrical signal 24 passes through the transmission line labeled "trace" in Figure 2b. The transmission line has an impedance z0. The transmission line is terminated by the device under test DUT, which in turn has an impedance Zin. If the impedance Zin of the device under test does not match the impedance ZQ' of the transmission line, a portion r of the wave 24 is reflected by the device under test DUT and another portion b of the wave 24 is transmitted to the device under test DUT. The case of "matching" occurs if the impedance Zin of the DUT under test is equal to the impedance of the transmission line 2, i.e., Zin = Z, which is, for example, 5 ohms. In this matching state, the radio wave 24 is all transmitted to the device under test dut. The reflected portion 该 of the electric wave 24 will reach 0%, and the transmitting portion b of the electric wave 24 will reach 1%. 2a and 2b, therefore, the similarity of the electric wave and the optical wave is explained, wherein the impedance of the electric wire or the element corresponds to the refractive index of the optical material. Figure 3a shows an equivalent circuit diagram of one of the input impedances of a conventional device under test, which includes a resistive "〇n-die termination" RODT and a capacitive input. Capacitor & parallel. In the case of Fig. 3a, the parallel connection of the Rodt & Cin is between the terminal for connecting the transfer line and the potential Vddq applied to the DUT from the outside.梵 The Vatican component DUT can correspond to the device under test described in Figure 2b. The input impedance Z of the device under test in the first figure may correspond to the input impedance zin of the device under test DUT as described in Fig. 21). The input impedance z is formed by the parallel connection of the capacitor Cm and the 201024739 resistor RODT. When the device under test DUT includes a wafer, the resistor R 〇 dt can be formed by a termination resistor built into the wafer implemented on the wafer of the DUT. The capacitor CIN may be formed by a gate capacitor or an ESD protection circuit of the DUT, such as an integrated circuit ESD pin circuit, if the device under test DUT includes an integrated circuit. Figure 3b shows a Nyquist plot illustrating the input impedance z in Figure 3a. The Nyquist plot shows the impedance Z of the device under test for different frequencies. The impedance z(f) for different frequencies is plotted in a coordinate system having a horizontal axis of Re(Z) and a vertical axis of Im(Z), along which the real part of the input impedance Z is plotted. The imaginary part of the input impedance Z is plotted along the vertical axis. For zero frequency or DC conditions, the input impedance Z is equal to R 〇 DT, which can be 120 Ohm. For the case where the frequency is close to infinity, the input impedance z is close to 〇 〇hm due to the Cin valley. For the case where the frequency is between zero frequency and infinity, Z(f) describes a curved transition... for a given frequency, for a frequency fl, the imaginary part of the impedance z is equal to the real part. φ Figure 4a shows an equivalent circuit diagram of an input impedance of a DUT under test, the device under test comprising a resistive built-in terminal DT of the chip and a gate and ESD circuit forming capacitor C. The device under test DUT is formed by connecting the terminal resistor of the chip, which is a resistor R of 6 〇 Ohm, in parallel with the gate and ESD circuit forming the capacitor c of 1 。. The device under test dut is connected to a transmission line exemplarily having an impedance z — of - (8) 〇hm. Therefore, the input impedance Zin corresponds to the impedance z as described in the %th figure, wherein the terminal resistor R built in the wafer and the closed-pole and ESD electric valley have discrete values in the 4a. 13 201024739 Figure 4b shows a Nyquist diagram illustrating the input impedance as shown in Figure 4a. r represents the reflection coefficient and b represents the refractive index. At the DC frequency, the impedances Z〇 and Zin match, i.e., r = 0% and b = 100%. In other words, the input impedance Zin of the DUT at the DC frequency is equal to 6 〇 〇hm, matching the impedance of the transmission line to 6 〇 〇hm. For higher frequencies, the magnitude of the imaginary part of the input impedance zin increases. For example, for a frequency between 1〇1^ and 2〇1^, the input impedance corresponds to Zin=(3〇_3〇j)〇hm. For frequencies close to infinity, a wave is completely reflected by the DUT under test, i.e., r = 100% and b = 〇%. For frequencies close to infinity, the electrical action such as the same masking circuit completely reflects the energy of the electric wave flowing through the transmission line. Similar to the case of optics described above, such electrical reflections can cause problems. This will be outlined below. ‘ For example, Figure 5 illustrates an impedance mismatch interface between a transmission line and a DUT that causes the power in the transmitted signal to reach the transmission source (like an echo) again. In particular, Figure 5 shows a time domain reflectance (TDR) plot of the input impedance measured using the -GDDR5 memory component.

GDDR5 (Graphic Double Data Rate 'Version 5) is a high speed dynamic random access code Q

It body 'wf· is used in applications requiring high bandwidth. The time domain reflectometer (D (10)) is a program used to determine and analyze the duration and reflection characteristics of electromagnetic waves and electromagnetic signals. In the TDR test, the pulse generator generates a series of short signal transitions with a rise time of, for example, 2G nanoseconds (step (Qing), which waits for a time interval such as f shield to make the next turn At the beginning of the state, the echoes that have not changed state are completely settled. An oscilloscope can be used to measure the step responses. The transition states are applied to the device under test, and the device under test is based on 14 201024739 The pulses are reflected at its input impedance. If the input impedance of the device under test matches the impedance of the transmission line, then no pulses are reflected and no echoes can be observed by the oscilloscope. Figure 5 illustrates a mismatch. The case diagram includes an amplitude axis A and a time axis t. The figure shows an amplitude A of a reflected signal transition (step) plotted at time t. t=Os indicates the beginning of a transition state. Time. Between Ren (9) and 100 ps (picoseconds), a transient occurs in relation to the rise time of the square wave signal pulses. Between l ps and 400 ps, the TDR map represents the received h One of the strange amplitudes, which illustrates a part of the signal pulse Directly reaching the TDR receiver/oscilloscope connected to the same end of the transmission line as the pulse generator. After 400 ps, the reflection of the signal pulse reaches the receiver, whereby the energy of the received signal is initially reduced. In Figure 5, the reduction Illustratively from 500 millivolts to 345 millivolts. Thereafter, the received voltage rises again between 5 ps and 750 ps, rising from 345 millivolts to a full amplitude of 550 millivolts. The negative effect of reflection is terminated after 750 ps. The 750 ps is a time indicating the transient time of the device under test connected to the impedance line and is a characteristic value of the DUT. Figure 5 shows a test using the GDDR5 memory component for the fifth figure. The measurement should wait at least 750 ps before deciding a test signal result to ensure that there are no unwanted distortions that have a negative impact on the quality of the measurement. Until now, the above discussion focused only on the input impedance of the DUT, adapting the impedance. The line impedance of the transmission. However, in the case of a test head, the pin used to electrically contact the pin of the DUT also constitutes an impedance match in the design of the test configuration device. Problem 15 201024739 Figure 6 shows a cross-sectional view of a possible spring pin that can be used as a BGA (spherical grid array) pad 34 on a socket board and the DUT (device under test) The interface between a ball 36 in one of the arrays of 3-8. The spring pin is used in a device in an electronic circuit for between two electronic devices, such as between printed circuit boards (PCBs) or A normally temporary connection is established between a PCB and a 1C or similar device. The spring pin can be used in a test system. A test system includes a test head 'a pin-electronic module and corresponding The drive is located in the test head. The pin-electronic module is connected to a spring-connector via a cable, and the spring-connector is arranged on the upper side of the test head. An interface is mated to the test head such that the spring pin contacts the interface through the low side. The interface includes contact pads adapted to contact the pins of the pins, wherein the contacts are connected to the interface through the interface. These interface thin wires end on the upper side of the interface to connect the socket boards. The socket boards can be (small) PCBs (printed circuit boards) and also contain contact areas for connecting the DUT sockets 32. The DUT sockets 32 can be screwed to (or connected to) the contact areas of the socket boards. The DUT sockets 32 contain (small) spring pins 3〇 as shown in Fig. 6. They have a length of approximately 2_3 ® nun. The DUTs 38 are pressed into the DUT sockets 32 whereby the balls 36 of the ball grid array package 38 are contacted by the spring pins 30. Such a contact provides a one-way signal path connection between the DUT and the test driver or DUT and the test receiver, respectively. The spring pin 3'' shown in the second figure may have a relatively short length of about 2-3 mm, and the ridge line disposed on the interface has a length of about 40 cm. The spring pin shown in Figure 6 comprises two tubes 16 of electrically conductive material: 201024739 cartridges or housings 40 and 42, of which 40 are inserted in the other 42 so as to slide along their common axis The way relative is relatively movable. Some interlocking (not shown in the sixth figure) can be provided to prevent the outer casing 40 from falling out of the outer casing 42. - the spring 44 is placed in the inner region enclosed by the sections (4) and 42 to The mounting means for carrying the outer shell lions 42 separate the outer casings 40 and 42. Along the longitudinal axis of the spring lock pin, such as after the two electrical circuits, the spring lock pin causes the outer casing to be pushed relative to the electrical circuit by force Do 42, the magnitude of the force depends on the degree of compression 'and thus establish a safe electrical contact between the two circuits. The spring pin in Figure 6 can be placed on a dense array with other bullet pins. A plurality of individual pins of the electrical circuits are connected. In the middle, one electrical circuit is a job 38 and the other is, for example, a circuit board for interconnecting the DUT with the test head. In the latter case, the spring pin in Fig. 6 can electrically interconnect the pin or ball 36 of a ball grid array of the DUT with the respective pads of the circuit board or the socket board. The electrical contact between 36 and 34 is not only due to the two outer casings 40 and A resistive electrical path is formed 42. Further, the elastomer can be made of a conductive material such as a metal. In this case, the spring produces a function of electrically connecting the material between the % of the material, In the first example, 'it is not required. However, the following bribes relating to some embodiments of the present invention will show a positive effect on this «in-service-partial impedance matching or anti-reflection circuit. For the sake of completeness, Figure 6 is further described below. In particular, Figure 6 shows the spring pin 3〇 contained by the -DUT socket 32. 17 201024739 That is, the spring pin is supported by the socket 32. The outer casing 40 projects from one side of the socket 32 and the other outer casing 42 projects from the other side of the socket 32. Although not shown in Fig. 6, more than one spring pin can be combined in this manner to obtain a lateral direction of a spring pin. The spring pin 30 is used to electrically connect a pad 34 on a circuit board to a ball 36 of a ball grid array (BGA) of a device under test package 38. As described above, the spring Pin 3〇 includes the inner tube 40 The outer tube 42 and the spring 44. Figure 7a shows an inner tube of a spring pin and a spring in contact with the inner tube in a loosened state. The spring 50 can be mechanically attached The inner tube 52. Alternatively, the spring 50 abuts only the inner surface of the tube 52. The 'inner tube 52 includes a contact portion 56 for abutting - a tab of the device under test. Further included is a piston portion 54 for inserting the outer tube of the figure - shown. In the released state as shown in Figure 7a, the piston portion protrudes beyond the outer tube. In the compressed state shown, the portion 54 is inside the outer tube. At the opposite end of the piston portion opposite the contact portion, the spring pin includes a spring retaining portion 58 relative to the diameter of the piston portion. Projecting outwardly to interfere with the respective portions of the outer tube in the relaxed state of the spring defines a bore through which the piston portion extends to prevent the inner tube 52 from disengaging out of the outer tube. The elastic cyanine fixing portion 58 is also used to form a fixed surface against which the spring is compressed. The spring 50 is stabilized in the inner tube 52 in its radial position by the inner portion 6 of the inner tube 52, and the inner portion 6〇 has an inward extension from the elastic portion 58 Portion 58 has a smaller radial extent. In other words, the spring 50 is fitted over the inner portion 60. At the end of the spring opposite the fixed end of the spring fixed portion of the spring 18 201024739, the spring may have a reduced direct service to be inserted into the outer tube and serve as the inner portion in the compressed state. One of the contact points, as described later. The spring fixing portion 58 of the spring pin corresponds to the fixing point as shown in Fig. 6, wherein the spring 44 contacts the inner tube 40. The outer tube sleeved over the inner tube 52 is not drawn in Figure 7a but an example is shown in Figure 8, which shows an outer tube and the inner tube. The inner portion extends longitudinally in such a manner that, in the compressed state shown in Fig. 7b, an end portion 64 facing away from the spring fixing portion 58 contacts the small diameter portion of the spring 50, and by the small diameter Partially electrically contacting the outer tube. As shown in Fig. 7a, the inner tube 52 can have a length of 3.7 mm when the spring 5 is in the released state shown in Fig. 7a. It is to be noted that the spring 50 can be biased even in the state in which the separation of the tubes shown in Fig. 7a is maximized. To this extent, the term "released" is to be interpreted broadly to mean that the spring is compressed/biased in a compressed state that minimizes the distance between the tubes as shown in the figures. The pressure is small. Fig. 7b shows the inner tube 52 of the spring pin in Fig. 7a and the spring 50 of the spring pin in the compressed state. In this state, the inner tube 52 is maximally received into the outer tube and the spring 5 is under maximum compression. The length of the spring 50 is reduced, for example, from 3.7 mm to 3.4 mm, in which case the spring pin has a variable length with a variable of 〇3 mm. This length is referred to as the contact stroke 62. When the spring 5 is maximally compressed, the end 64 of the inner portion 60 is in mechanical contact with the small diameter portion of the spring 50. 19 201024739 thus forming an electrical connection between the inner tube 52, the spring 50 and the outer tube contact. Thus, the inner portion 60 also acts as a interlocking mechanism to prevent the portion of the inner tube 52 from entering the outer tube beyond the contact stroke 62. Figure 8 shows a possible outer sleeve 66 of the spring pin of Figures 7a and 7b and the inner tube. The outer tube 66 can have dimensions as indicated in the figures. The outer sleeve or tube 66 includes a small diameter hollow portion 74 adapted to one of the small diameter portions of the spring 50 and the hollow portion 74 serves as an external contact portion for mechanically and electrically contacting a gasket, the gasket being The gasket contacting the contact portion 56 of the inner tube 52 contacts. Further, the sleeve 66 includes a large diameter portion 72 to accommodate the large diameter portion of the spring 50, not shown in Fig. 8. At the end of the large diameter portion 72 opposite the small diameter portion 74, the sleeve 66 includes a bore through which the piston portion of the inner tube extends. At the hole, the large diameter portion 72 includes a ring (not shown) projecting inward in the radial direction to engage the spring fixing portion of the inner tube 52 to prevent the inner tube from coming out of the outer tube. It can be clearly seen from the discussion of the above-mentioned 7a, 7b and 8 that there are three possible electrical paths through which the ends of the spring pin are electrically connected through the spring pin: a path through the spring 50, a path through the inner portion of the inner sleeve, and a path through the mechanical contact between the piston and the cylindrical portion via the sleeve itself. In accordance with some of the following embodiments, a spring pin having a similar configuration is designed to form at least a portion of a matching circuit whereby the number of electrical paths can vary as described below. In any case, the spring-traveled path results in a high impedance that must be considered during testing. Further, the point of contact between the spring and the end 64 of the inner portion 60 201024739 is determined to be rather inaccurate due to the use of the spring pin shown in Figures 7a, 7b and 8 to cause The resulting impedance will change, or at least, a set of junctions will continue to test the impedance change between the pins. 5 The same bullet-like figure 9 shows a time-domain reflection (TDR) map measured by the contact of a short-circuited one thousand ~ elastic needle, the spring pin tribute diagram, the brother 7b diagram and the 8th The figure shows. The above-mentioned pinion pin:,,, - the third inductor produces the need for measurement by the spring pin. Figure 9 illustrates this delay. A TDR pulse is generated by a signal. delay. The spring pin is delivered to the shorted device. The pulse is reflected by the spring and received by a signal receiver such as, for example, a ballast. The signal received by the oscilloscope is shown in Figure 9. In the case of a short circuit, the signal of the ❹m device should be reversed to the extreme (4). The pulse sent to the device has a large (four) millivolt amplitude. ^ The time axis is observed between 〇m〇0ps. The pulse is reflected by the shorted test element after L-Gps and received in reverse polarity. Depending on the details of the short circuit, such as the resistance of the inductive nature of the path, a different delay can be observed. In order to calibrate the test instrument, an instrument is extended by η ττττ ---, and the t-index (FXDL cal) is executed after the test s-DUT to take into account the relationship between the "heart-style head and the DUT balls. The signal propagation process. For this purpose, insert a short-circuit device (such as a gold metal plate) instead of a real Dut ^ Gan Li 4 . 4 When the shorting device is inserted, it generates a short circuit to the ground pin. If a hopping signal is sent by the tester (like using a TDR), the propagation delay of the echo (in the presence of a retrace) is revealed. The length of the electrical path is shown in 201024739. '_, if the material is not—(4) the actual impedance is, for example, an ideal transmission line of 50 ohms but contains - an inductor such as the "have & damage, the socket spring ride, the resistance becomes Wei and the addition - sent later. This. The characteristics are shown in Figure 9.

A first curve 81 illustrates the measurement using a first short circuit device and a second curve 82 illustrates the measurement using a second short circuit. A delay between the first curve w and the second curve 82 reaches approximately 1 〇〇 1) 8, which can be observed by the two points at which the first curve 81 and the two curve 82 intersect the time axis 1. The delay is approximately 650 ps for the first curve 81 and approximately 75 对于 for the second curve.

Figure 10 shows a histogram illustrating the & repeatability of the -tester using the spring pins as shown in Figures 7a, 7b and 8. The figure illustrates the results of the difference between the two consecutive FXDL measurements performed on the -2 memory component. The time difference of a continuous Fxdl measurement is plotted on a time axis t and a sampling axis. The sampling axis represents the scale needle of the pin of the DDR2 device measured by the FXDL measurement. The 曰 difference value measurement shows the difference time 0, 80, -40 or _8 〇 ps. The amount is left to dry up - very good repeatability, the county value of the big recording seam is up to seconds ^ sometimes there will be a 40 or 8 〇 Ps error. This measurement can be used for the purpose of the test device. μ, the problem shown in Figure 10 above shows that there may be a + inductive part of the pin and can be used for purposes with a specific intent, such as an anti-reflection circuit. The short display of the spring pins for providing a connection interface between the DUT and the test head increases the complexity of the matching problem. The second step 201024739 is generated by the impedance mismatch between the DUT and the transmission line. The issue will be explained. Figure 11 shows a time domain reflectometry (TDR) map measured at one of the components under test for a planar ODT (terminal built into the wafer). A pulse is transmitted through the transmission line to the device under test and is then reflected by the ODT load of the device under test. The TDR map illustrates that the reflection starts at 2118 and lasts until approximately 3.5 ns. Figure 12 shows an eye diagram of a signal received by a test configuration device that measures one of the components under test at 5 Mbps. The digital signal from the TDR receiver corresponds to the signal measured using the test configuration device as shown in FIG. However, the digital signal is oversampled and applied to the vertical axis input of an oscilloscope such that the signal represents amplitude and the one-bit clock signal is used to trigger horizontal scanning of the oscilloscope. The resulting oscilloscope output is referred to as an eye diagram as shown in Figure 12. It can be seen that the reflection as shown in Fig. 11 observed by the tdr measurement causes the closure or contraction of the eye pattern. During time interval 90, the reflection corresponds to the distortion of the eye pattern, wherein the duration of a data bit is represented by time interval 91. The duration 90 of the reflection corresponds to the duration of the reflection shown in Figure 且 and ranges from about 1.7 ns to about 2.3 ns. This is long enough for the eye diagram to be severely disturbed for a duration of approximately 2 ns. In order to perform an accurate measurement using the test configuration device, a shorter sampling time is required, for example 250 Mbps may be required, and is no longer relevant to the application. Figure 13a shows a schematic cross-sectional view of a conventional SMA adapter 100 with one terminal built into the wafer (〇 DT) load simulation 101 as a terminal. The 23 201024739 terminal load emulation ιοί built into the chip includes a capacitor 102 connected in parallel with a resistor i〇3. The value of the capacitor 1 〇 2 in this example is llpF and is realized by a parallel connection of a 10 pF first capacitor 104 and an lpF second capacitor 105. This resistor 103 is implemented by connecting two 100 Ω resistors 106 in parallel. The resistors 106 and the capacitors 104, 105 are discrete devices such as, for example, SMD components. The terminal 101 built into the wafer is attached to the SMA adapter 100 by, for example, soldering. Fig. 13b shows an equivalent circuit diagram of the SMA adapter cable 100 terminated with the end-of-wafer terminal (ODT) load terminal 1 〇 1 as shown in Fig. 13a. The equivalent circuit diagram includes a 11 pF capacitor 102 in parallel with a 50 Ω resistor 103. The SMA adapter cable 100 with ODT load emulation can be used for illustrative purposes to illustrate the result of a resistive built-in termination of the wafer in parallel with a parasitic capacitance as a termination of the device under test. The terminal load emulation 101 built into the chip is used to display the same electrical characteristics as, for example, a memory component terminated by an integrated terminal built into the chip. Figure 14 shows a pole view of a reflection factor of the SMA adapter cable 100 with the DT load terminal as shown in Figure i3a. The pole map illustrates the reflection factor r with the absolute value of the S parameter S11. The S parameter is a characteristic that describes the electrical behavior of a linear electrical network when subjected to various small signal steady state excitations. Many of the electrical characteristics of the network or component can be represented by S-parameters such as the reflection coefficient r corresponding to the S-parameter S11. Most of the 5 parameters are applied to networks operating at RF and microwave frequencies, where the power and energy of the signal are easier to quantify than current and voltage. Since the s-parameter varies with the frequency of the measurement 201024739, the measurement frequency must be included in addition to the characteristic impedance or system impedance for any of the s-parameter measurements. These four s parameters can be measured using a network analyzer. S11 is the voltage reflection coefficient of the input ,, S12 is the reverse voltage gain, S21 is the forward voltage gain, and S22 is the voltage reflection coefficient of the output 玮. In the pole diagram according to Fig. 14, the S parameter S11 is displayed in accordance with the measurement frequency. Starting with a direct current (DC) frequency, the S11 parameter corresponds to a reflection parameter of 〇, which indicates that the SMA adapter line 1〇〇 as shown in Fig. 13a matches the ODT as shown in Fig. 13b. load. For DC frequencies, the impedance of the SMA adapter cable 100 is 50 Ω, and the DC impedance of the ODT load is 50 Ω. This reflection parameter increases for higher frequency/rates up to 1 GHz, corresponding to the effect of capacitor 102 in the ODT load as shown in Figure 13b. For non-zero frequency conditions, such reflections from the 〇dt load may not be ignored. Multiple connector points are connected to the common line. The following examples illustrate when more than one DUT is connected to a test head channel or the test head pins compete for one or more joints, such as the DUT When the joint point of a common transmission line of the terminal is connected to the common transmission line to obtain a daisy chain, the measurement problem caused by the increase of the impedance mismatch is shown in FIG. 15 showing the component-free loading for the memory element. A daisy-key test configuration device measured - coffee chart. The TDR map is measured on the - address line shared between the four duTs. A number of echoes between lns and 3 ns are seen which are generated by the received reflections from the unloaded ends of the branches of the address lines connected to the individual memory element interfaces. These echoes can interfere with an accurate measurement. 25 201024739 Figure 16 shows a TDR plot measured using a daisy chain test configuration device that has loaded DDR2 memory components at all sites of the daisy chain. Compared to the example of the no-memory component load shown in Fig. 15, the pattern shown in Fig. 16 shows a higher degree of reflection due to the DDR2 memory components due to the additional capacitive load. . Reflection occurs between Ins and approximately 4.5 ns. Figure 17 shows a portion of a test configuration device that includes a plurality of DUTs and a circuit board 120 that commonly connects the DUTs to a common test pin pin through a branch node. In particular, the board 120 includes a branch node 121 to which the first and second conductors 122 and 123 are connected, each of the conductors 122 and 123 being coupled to the other of the devices under test 124 and 125. And the board 120 includes a common (signal fed) transmission line 127 that extends to the interface of a device tester or to the test head of a device tester. The common transmission line 127 typically has a different impedance than the conductors 122 and 123. The transmission line 127 contains, for example, an impedance Z! equal to 50 Ω. The first and second devices under test 124 and 125 can have a 60 Ω ODT termination in parallel with a capacitance of, for example, 1.5 pF. As described, the circuit board 120 provides a test interface 126 for a device tester. Due to the 60 Ω of the elements under test, even if the impedance of the output lines 122, 123 is Z2 = 60 Ω, the elimination requirement is no longer satisfied. The devices 12 and 125 to be tested are, for example, GDDR5 memory elements having a 60 Ω real impedance. The problem of how to set the impedance values of the wires 122 and 123 is answered in Fig. 18. Fig. 18 shows a circuit diagram of the circuit board as shown in Fig. 17 having a symmetrical structure. The first wire 122 and the second wire 123 201024739 comprise an impedance Zz=100 Ω. The first device under test 131 comprises, for example, a 120 Ω resistor in parallel with 15 pF. The second device under test 132 also includes a 120 Ω resistor in parallel with 1.5 pF. Due to the symmetry condition, the branch node 121 terminates with the two wires 122, 123 each having an impedance of 100 Ω, which is equivalent to the equivalent terminal of the branch node 121 of 50 Ω. The branch node 121 is matched with 50 Ω on one side of the tester and 50 Ω on the side facing the DUT, whereby the branch node 121 does not reflect. The reflections will only occur by the elements 14 and 132 having an impedance different from the impedance of the branches 122 and 123 by 100 Ω, whereby reflections from the two elements under test 131, 132 are transmitted to the branch node 121. However, this reflection of a DUT, e.g., 131, is cancelled by the reflected signal of another DUT, such as 132, which is refracted into the branch 122 at node 121. This erasing effect is the reason why the configuration device does not have multiple reflections. But it generally requires that the value of Z2 be twice the value of Zl. Due to the symmetrical structure of the circuit board 120 and the impedance matching between the transmission line 127 and the test interface 126, only one reflection occurs and it is eliminated in both branches without generating a plurality of reflected echoes. Thus, the board 120 allows for high measurement accuracy measurements of GDDR5 memory components. However, the elimination of reflection is not easy to achieve. Fig. 19 shows a circuit diagram of the circuit board 120 as shown in Fig. 17, which illustrates the conditions of reflection cancellation. Multiple reflections occur when a wire having a characteristic impedance is connected to another wire having another characteristic impedance. The first branch line 122 has a characteristic impedance Z2' coupled to a first device under test 133 having a characteristic impedance Z. If the characteristic impedance & is not equal to the characteristic impedance z, a reflection rx1 occurs between the first branch line 122 and the first device under test 133. If the 27 201024739 has a special impedance b 2, the second branch line 123 is connected to the second measured component m having the characteristic impedance z, and the impurity impedance 2 is not the special impedance & A reflection Γγ1 occurs between the branch line 12 3 and the second device under test 13 4 . If the characteristic impedance Z1 of the signal transmission line 127 is different from the characteristic impedance center, reflection also occurs at the branch node 121. For example, a wave is sent by the tester to transmission line 127 where an equal portion is refracted into the branch lines 122 and 123 and another portion is reflected back to the tester. Assuming that the tester matches the impedance Z1, the reflected portion is completely absorbed by the tester. However, the refracting portion propagates along the branches 122 and 123 toward the 133 Φ and 134. Since the input impedances 2 of the DUTs 133 and 134 are almost impossible to match the branch lines 122 and 123, the reflections of the coefficients rxl and ryl* occur, respectively. Reflected waves from the DUTs are propagated to the branch or fork node 121. The impedance here does not match the branch line impedance. Thus, for the case of branch line 122, a portion of the signal rx2 is reflected to the DUT 133 and another portion is refracted into the feed line 127 and the other branch line 123. However, the same situation occurs on the branch line 123. Here, the portion by2 is refracted into another branch line and the portion by2 is refracted into the feed line 127. It can be shown that if the value of Z2 is twice the value of Z1, then rx2 has the same magnitude as byl but has different signs and therefore cancels each other. This means that no more reflections will occur. However, this requires two branches to be perfectly symmetric in terms of impedance and length. Figure 20a shows a circuit diagram of the daisy chain test configuration device already mentioned above. The device uses a daisy-chain shared topology to measure the measured component. This daisy chain sharing topology is particularly suitable for testing high speed memory, such as for measuring a plurality of memory elements in the same test step. 28 201024739 A component tester 140 is coupled through a test interface 141 to a transmission line 117. The transmission line 71 has a characteristic impedance 2 (e.g., 50 〇 11111). This transmission line is terminated with its end so that no reflection occurs. The terminal is implemented by a matching resistor xy2 and a terminal power supply xy3 of a ground 155. The transmission line now performs joint measurement at xy4, xy5, xy6, and xy7 points. The devices under test having a characteristic input capacitance 143 are connected to the connectors via stubs (short transmission lines, such as vias) and thereby distort the desired signal transmission on the transmission line xyl. Reflection occurs at each joint because the input capacitance and the capacitive behavior of the short lines produce a short-circuit effect at the first time or at a very high frequency, respectively. A reflection 156 illustrates the reflections from the respective branch nodes 145, 146, 148, 150 from the short lines 152 and the parasitic input capacitances 143 from the respective device under test DUT1-DUT4. At each of the tested components, a reflection occurs, resulting in a distortion of the signal experienced by the previous DUT. (The tester is not used to evaluate the signal for driving.) Figure 20b shows a TDR map measured using the conventional test configuration device as shown in Figure 20a. This TDR diagram illustrates the signal experienced by the first device under test DUT1. This signal contains three reflections. A first reflection 160 corresponds to a reflection from the second device under test DUT2. A second reflection 161 corresponds to a reflection from the third device under test DUT3 and a third reflection 162 corresponds to The reflection from the fourth device under test DUT4. The input impedance of the tester 140 and the termination impedance 153 are suitably matched to 50 Ω of the input lines, so no reflection occurs. Figure 21a shows a timing diagram of the test signal. Four test signals 29 201024739 v(10), v(ll), V(12), V(13) are received at a test configuration device that uses a daisy chain sharing topology to use a sampling frequency of 2.5. A pseudo-random binary sequence (PRBS) of Gbps is used to test DDR memory components. The daisy chain sharing topology is a By-4 shared topology comprising four elements under test, each of the tested components having a load impedance of 1.5 pF and a stub of 30 ps. Due to the reflection of the test 彳§ number originally sent by the component tester 140 shown in Fig. 20a, it can be seen in the timing diagram of Fig. 21a that the signals received at the respective devices under test contain many phases. Reflection of adjacent test elements. Due to reflections from adjacent test elements, the received signals v(10), v(ll), v(i2), v(13) contain reflections from adjacent test elements in the originally transmitted test signal. Signal component. This results in distortion experienced at the input of the DUTs. The signals experienced by the DUTs show a ringing that decays to a target planning value of 0.8V. Fig. 21b shows an eye diagram corresponding to a test signal which is the basis of Fig. 21a. The eye diagram illustrates the test signal v(l〇) received at the first device under test DUT1 in accordance with the test configuration device as shown in Fig. 2a. The eye in the eye is almost closed due to distortion of the received test signal ν (10) due to reflection from adjacent elements under test. The excess (oversh〇〇t) and undershoot of the received test signal ν(1〇) causes the eye pattern to be distorted resulting in eye closure. As can be seen from the above figure, measuring the measurement element including the specific parasitic capacitance and resistance which determine the input impedance of the device under test may cause a problem due to reflection and reduce the sensitivity of the measurement. The reflections may be due to a loss-adjustment of the input impedance of the tested elements to the transmission line connected to the component tester. In the case where more than one of the devices under test is connected to one of the test channels or one of the test interfaces (such as, for example, a daisy-chain topology), the reflections may also occur from reflections of adjacent test elements. . Especially for the higher sampling frequencies required for new generation memory components such as, for example, GDDR5 memory components, accurate measurement becomes almost impossible. A solution is needed to eliminate unwanted reflections to make high-accuracy measurements of the device under test easier. Some embodiments of the present invention address the above mentioned problems by providing a test configuration apparatus including an interface for a device under test, the interface including an impedance matching circuit and the impedance matching circuit including A resistor is connected in parallel with an inductor. Further, some embodiments of the present invention provide a spring pin comprising a first sleeve of a conductive material, a second sleeve of a conductive material, a tube of a resistive material, and a conductive material. Hey. The tube of the resistive material, the first sleeve and the second sleeve are slidably attached to each other along a common axis, wherein the tube is disposed between the first and second sleeves. The spring is used to separate the first and second tubes outwardly. The spring pin forms an inductance formed primarily by the spring in parallel with one of the resistors formed primarily by the barrel. Some embodiments of the present invention comprise a spring pin comprising a first sleeve of electrically conductive material, a second sleeve of electrically conductive material, a tube of insulating material, a spring of electrically conductive material, and an elastic Resistive component. The first sleeve, the second sleeve, and the barrel are slidably attached to each other along a common shaft, wherein the tube is disposed between the first and second sleeves. The 31 201024739 spring is used to separate the first and second tubes outward. The resilient member includes a resistive material attached between the first and second sleeves along the common axis. The spring pin forms a parallel connection of an inductor formed primarily by the spring to create an inductor and a resistor formed primarily by the elastomeric member. A further embodiment of the invention includes a spring pin comprising an elastomer body having a main longitudinal axis; and a conductive material embedded in the elastomer body for the elastomer A line extending between the top surface and the bottom surface of the body along the main longitudinal axis. The spring pins are assembled to form a parallel connection of an inductor formed by the lines to a capacitor. The general idea of some embodiments of the present invention is to construct a test configuration device including a spring pin such that the input impedance matches the line impedance when the spring pin is coupled between the DUT and the connection transmission line. In such a case, no reflection occurs. Since the input impedance of a device under test is typically capacitive, embodiments of the present invention provide an impedance matching circuit that includes a resistor-inductor in parallel to match the generally capacitive input of the device under test. impedance. Therefore, based on these realities, the characteristics of these spring pins, which are generally considered to be harmful, become advantages and are utilized. More precisely, the 6-inclusive spring-loaded pin provides an inductive elastomeric coil. Typically, it is interpreted as a parasitic element. However, according to these embodiments, the money is composed of poems - part of the impedance matching circuit. Thus the spring pin is cut to form an inductor and - the ohmic resistor to provide an impedance matching circuit. The hybrid impedance matching circuit can be placed in close proximity to the turn. 32 201024739 Some embodiments of the present invention are based on the idea that an impedance matching circuit with improved matching performance can be obtained when the impedance matching circuit has an electrical % 等于 equal to the resistance value of the input impedance of the device under test, For example, within a tolerance of ± 10%, and a square of the electrical enthalpy value equal to the wheel-in resistance of the device under test multiplied by the capacitance of the input impedance of the device under test, such as, for example, ±10% When the tolerance is within the range. Figure 22a shows a wave diagram of light transmitted through an optical medium as shown in Figure 2a, however, wherein the optical medium has an optical film of an anti-reflective coating material thereon. The optical medium is, for example, a highly reflective glass. This coating material minimizes reflection. The general idea of one of the embodiments of the present invention is to transfer this idea from the field of optics to the field of electricity. When the light wave 2〇 as shown in Fig. 22a is transmitted through an optical medium such as, for example, a glass having a refractive index (1) different from an air refractive index, such as ηι > n〇 and the glass has an anti-reflective layer When the thin layer 21 of material is used, the reflectance of the glass can be lowered. Passing through the thin layer 21 of the anti-reflective coating material, wherein the thin layer 21 ® of the anti-reflective coating material has a refractive index between the air refractive index n 〇 and the glass refractive index 〜, the light beam 20 reflects Twice: that is, one reflection from the surface between the air and the eight-ion layer 21, and one reflection from the interface of the ARC layer 21 to the glass 22. It can be shown that when the refractive index of the ARC layer 21 is a certain optimum value, the transmittances of the two interfaces are equal, and this corresponds to the maximum total transmittance of the glass. This optimal value is given by the geometric mean of the two surrounding indices:

Vvi 0 For example, glass has a refractive index of approximately (1) = L5 and air 33 201024739 has a refractive index n 〇 = 1, and this optimum refractive index is approximately nARc = 丨 225. An intermediate dielectric coating (anti-reflective coating, Arc) between air and glass reduces reflection losses. The idea of transferring an optical anti-reflective coating to the field of electricity is shown in Figure 22b. Figure 22b shows a signal diagram of the electrical transmission line Z〇 with the terminal impedance Zin of the device under test Din as the terminal, Zin and the impedance Z〇 of the transmission line being unequal, according to an embodiment of the invention, having An anti-reflection circuit (impedance matching circuit) 200 is connected between the transmission line 2〇1 and the device under test 2〇2. The ARC circuit 200 is an analog component between the two electrical media, that is, the transmission line and the terminal impedance of the device under test, and is analogous to the anti-reflective coating between the two optical media, that is, the air and the glass in FIG. 22a. A thin layer 21 of material. The anti-reflective coating circuit 2 can be designed to include a reflectance index between the reflectance index of the passer wire 201 and the reflectance index of the terminal impedance 202 of the device under test. The ARC circuit 200 can be designed to pass the reflection of the radio wave 203 to cause the electric wave 203 to flow through the transmission line 201 to reach the terminal impedance 202. An appropriately adjusted ARC circuit 200 suppresses the reflection of the electric wave 203 by about 99% whereby the energy of the electric wave 203 is transmitted to the terminal impedance 202 of the device under test. Figure 23a shows a schematic diagram of a test configuration device 400 in accordance with an embodiment of the present invention. The test configuration device 4A includes an interface 401 for a device under test 404. The interface 4〇1 includes an impedance matching circuit 402. The impedance matching circuit 402 includes a resistor r and an inductor 1 connected in parallel. The interface 402 includes a spring pin 403 that forms the impedance matching circuit 403. This is described by the schematic representation 4〇3b of the spring pin 4〇3, which is illustrated in 201024739 in parallel with the resistor R and the inductance L. The resistor R and the inductor L in the impedance matching circuit 402 may be formed by discrete electronic components that are arranged inside or (close to) the spring pin 4〇3 outside. The embodiment of the spring pin 4〇3 is depicted in Figures 27, 28, 29a and 29b. The shai test configuration device 400 further includes a signal generator 405 for applying a test signal. The sin test configuration device further includes the device under test, which includes a ~ input impedance. The interface 4〇1 is used to provide electrical coupling between the impedance matching circuit 4〇2 and the input impedance of the device under test 404. The resistor R of the impedance matching circuit 402 and the inductor 1 are combined such that one impedance of the impedance matching circuit 4〇2 matches the input impedance of the device under test 404. Figure 23b shows a schematic diagram of a test configuration device 400 in accordance with another embodiment of the present invention, which embodiment is identical to the embodiment shown in Figure 23a except that the implementation of the impedance matching circuit 402 is different. The impedance matching circuit 402 includes a series connection of the spring pin 403 and an external electrical component 420. The external electrical component 420 includes a discrete resistor r and a discrete inductor L. The discrete resistor r and the discrete inductor L of the external electrical component 420 are assembled such that an impedance of the impedance matching circuit 4〇2 (including the impedance of the spring pin 403 and the impedance of the external electrical component 420) An input impedance of the device under test 404 is matched. The test configuration device 400 further includes a signal generator 405 for applying a test signal. For example, the test signal can have a mean frequency that is lower than the maximum frequency of the interface 4〇1. The external electrical component 35 201024739 420 is arranged against the spring pin 403, for example, less than a quarter of the electrical wavelength corresponding to the maximum frequency. The close distance produces better matching performance of the impedance matching circuit 402.

Figure 23c shows an equivalent circuit diagram of a test configuration device in accordance with an embodiment of the present invention. The test configuration device includes a device under test DUT' having a input impedance Zin formed by a parallel connection of a resistor R and a capacitor C. The test configuration device further includes an impedance matching circuit ARC (anti-reflective coating) having an impedance formed by the parallel connection of the resistor R and the inductor L. The impedance matching anti-reflection circuit ARC is connected in series with the device under test DUT, whereby the series connection of the impedance matching circuit ARC and the device under test DUT has an input impedance Z. The calculation result of the input impedance Z is 2 + will + ±)

A resistor A of the input impedance Zi n of the device under test corresponds to the impedance ZARC^-resistor R of the impedance matching circuit ARC. If the condition l = r2c is satisfied, the result of the impedance Z of the circuit is

=R Due to the elimination of the pole and the zero in the equation shown above, the impedance Z of the circuit including the DUT contiguously connected to the impedance matching circuit becomes the resistance of the impedance matching circuit ARC and the device under test dut R corresponds to a real value. Thereby, the frequency dependence of the impedance Z is eliminated by the following matching conditions. 36 201024739

L = R2 C Of course, the matching condition does not need to be 100% satisfied to provide a configuration that is advantageous over the mismatch. For example, the inductance of the impedance matching circuit can be equal to the square of the resistance R of the input impedance multiplied by the capacitance C' of the input impedance within a tolerance of +/- 10%. Additionally, the impedance of the impedance matching circuit can be equal to the resistance of the input impedance, within a tolerance of +/- 10%. If the resistance R is equal to the impedance Zq of the transmission line connected to the circuit, then no reflection at all occurs. The impedance Zin of the device under test DUT can be realized by a terminal ODT built in the chip and/or by a capacitor Qn (for example, a capacitor) built in the chip and an external resistor R. Figure 23d shows a schematic diagram of a test configuration device 400 including a component tester, a test interface, and a plurality of interfaces for a plurality of devices under test, in accordance with an embodiment of the present invention. . Spring pin 403 can be applied to test system or test configuration device 400, respectively. In this embodiment, the test configuration device 4A includes a test φ test head 407 or a component tester in which a pin-electronic module 410 and a corresponding tester driver 405 are located. The pin-electronic module 41 is connected by a cable 412 to a spring-connector 417' which is arranged on the upper side of the test head 407. A test interface 4〇6 is mated to the test head 4〇7 to bring the spring connectors 417 into contact with the test interface 4〇6, such as at the bottom edge of the test interface 406 or any other possible point of contact. The mating can be implemented using a mechanical lock mechanism 416. The test interface 4〇6 includes contact pads 413 that are adapted to contact the spring connectors 413, wherein the contact pads 413 are connected to the test interface 4〇6 via a test interface cable 418. These test interfaces 37 201024739 cable 418 terminates above the test interface 406 to connect a plurality of socket boards (or boards) 4 〇 8, 408b. The socket boards 4〇8, 408b may be (small) PCBs (printed circuit boards)' also include (respectively) connecting the interfaces 401, 401b associated with the socket boards 408, 408b (or Contact area 414 of the component socket). The interface 401 for the device under test 404 is associated with the socket plate 408. The second interface 4b for the second device under test 4〇4b is associated with the socket plate 408b. The interfaces (device sockets under test) 4, ib can be screwed (or connected by a mechanical arrangement) to the contact areas 414 of the socket plates 408, 408b using screws 415. The interfaces (device under test sockets) 4〇1, Ο 401b include (small) spring pin 403, which is smaller than the spring-connector 417 of the test head 4〇7. The spring pins 4〇3 can for example have a length of approximately 2_3 mm. The test elements 404, 404b can be pushed into the interfaces (measured - component sockets) 401, 401b, whereby the ball 419 of the ball grid array package (the test elements 404, 404b) is replaced by the spring pins The needle 403 is in contact. Such contact provides a complete signal path connection between the device under test 404, 404b and a tester drive 4〇5 or tester receiver 411, respectively. The spring pin 403 shown in Figure 23d can have a relatively short length of about 23 Ο mm, and the cable 418 disposed within the test interface 406 has a length of about 4 〇 εη. A branch node 120 is formed by an input line 127, a first output line 122, and a second output line 123. The input line 127 is electrically connected between the test interface 4〇6 and a branch node 121. The first output line 122 is electrically connected between the branch node 121 and the interface 4〇1 for the device under test 404, and the second output line 123 is electrically connected to the branch node 121 and used for the second Between the second interface 40lb of the measuring element 38 201024739 404b. The branch node 12i can be implemented on one of the (pCB) boards 408, 408b or the test interface 4〇6. The input line 127, the first output line 122, and the second output line 123 may be a transmission line, a waveguide, a microstrip line, a strip conductor of a printed circuit board, a via hole, a connection (micro) strip line, and a high frequency microwave. Implemented with a line, connector, interconnect or component, SMA mating or coaxial slow line. The lengths of the first 122 and second 123 output lines may be different. Output lines 122 and 123 can each be implemented on different layers of the boards 408, 408b. Figure 23e shows a Nyquist plot of the input impedance z of the test configuration device as shown in Figure 23c. The Nyquist diagram shows the frequency dependence of the input impedance through the representation of the real part Re(z) and its imaginary part Im(Z). The test configuration device has an input impedance Z that is constant and is a real amount and is perfectly matched to the line impedance. Therefore, no frequency dependent reflections occur. The set value corresponds to the resistance R of the device under test DUT and the impedance matching circuit ARC. Figure 24a shows an equivalent circuit diagram corresponding to a test configuration device including a GDDR5 memory device as shown in Figure 5, having an embodiment connected to the device under test and the transmission line in accordance with an embodiment of the present invention. Inter-impedance matching circuit ARC. The structure of this circuit corresponds to the structure as described in Fig. 23a. Corresponding to the GDDR5 memory component, a 6 Ω Ω resistor and an i.5 pF capacitor form a parallel connection of the input impedance of the DUT under test. The equal 60 Ω resistor is connected in parallel with an L = R2C = 5.4 nH inductor to form the impedance matching circuit ARC, whereby the impedance z of the test configuration device becomes z = R. A transmission line with an impedance of Z 〇 = 60 Ω is connected to the other terminal of the impedance matching circuit. The impedance matching circuit ARC realizes the impedance of the DUT of the device under test 39 201024739

Zin is matched to the impedance Z〇 of the transmission line, whereby reflection is suppressed. Figure 24b shows a Nyquist plot of the test configuration device as shown in Figure 24a. Due to the impedance matching circuit ARC, the input impedance Z of the test configuration device is matched to R, whereby no reflection occurs for all frequencies from DC to almost infinite. This match point = R is the same point for all frequencies. A large reflection of about 0% r and a large transmission of about 1% of b can be obtained. Fig. 25 shows a GDDR time domain reflection map for measuring an input impedance Z using the test configuration device as shown in Fig. 2. The signal v(2) corresponds to a measured signal at a TDR receiver. Due to the matching condition, the energy of the signal is completely absorbed in the series connection of the impedance matching circuit ARC and the device under test DUT whereby no reflection is reflected to the TDR receiver and the received signal V(2) shows no reflection. Or echo. The transition between 0 and 10 ns is used to indicate the non-ideal rise time of the tester driver. Figure 26 shows a comparison of the voltage at the DUT of the test configuration device as shown in Figure 24a with the voltage at the input impedance of the conventional device under test shown in Figure 4a. Sequence diagram. The voltage V(40) at the DUT under test has a rise time which is greater than the voltage V(4) at a DUT of a test device which does not exist in the impedance matching circuit ARC. In general, the step response of a configuration device having and without a matching circuit ARC can be roughly described using an exponential function f(t) = alpha * (l-exp(-t/tau)). The introduction of the matching circuit ARC increases the time constant by a factor of roughly 1 + R / Z0. This voltage V(40) reaches 95% of the 550 mV transition voltage after approximately 500 ps, while the voltage 201024739 V(4) reaches 95% of the 550 mV transition voltage after approximately 450 ps At the office. Considering that a transition state of the voltage starts at a time of about 200 ps, the voltage V(40) at the device under test including the impedance matching circuit requires about 400 ps to transition, and the impedance matching circuit is not included. The voltage V(4) at the device under test requires approximately 250 ps to transition. The difference 15 〇 ps is a result of the matching of the matching circuit ARC due to signal transmission through the electrical circuit. There are different alternative ways to implement the ARC circuit between the DUT and the transmission line within the test device as outlined above. Some embodiments are described below. Figure 27 is a side elevational view of a spring pin for connecting a device under test 210 to a interface 214 of a test head in a test configuration apparatus in accordance with one embodiment of the present invention. Specifically, the test configuration device includes a device under test enclosure 21 having a connection ball 211 connected to a spring pin 212 in a socket 213 under test connected to a circuit board. A BGA (Plate Array) pad 214 that is specifically designed for the device under test and that is itself connected to a tester or a portion thereof. The spring pin 212 is used to contact the package ball 21 of the device under test 21 丨 to the BGA pad 214 of the device under test. A retractable spring 215 belonging to and within the spring pin 212 produces the force required to securely contact the ball 211 and pad 214, respectively. The spring pin 212 includes a first sleeve 216 of electrically conductive material, a second sleeve 217 of electrically conductive material, a tube 218 of resistive material, and the spring 215. The spring 215 is made of a conductive material and is used to separate the first sleeve 41 201024739 cartridge 216 and the second sleeve 217. The first sleeve 216, the second sleeve 217 and the tube 218 are slidably attached to each other along a common axis 219 of the tube 218, wherein the resistive tube 218 is positioned in the first sleeve Between the barrel 216 and the second sleeve 217. The first sleeve 216 and the second sleeve 217 may have the same diameter as compared with the spring pin shown in FIG. 6, whereby one of the sleeves does not slide into the other sleeve. In contrast to the spring pins shown in Figures 6 and 8, the inner tube 40 slides into the outer tube 42 in the spring pins shown in Figures 6 and 8. The adaptability of the longitudinal extent of the spring pin is achieved by the barrel 218 which slides into the first sleeve 216 and the second sleeve 217. The spring 215 is attached to the tube 218 at a contact field 220. The spring 215 can be placed over the first sleeve 216 and the second sleeve 2, for example in accordance with the mechanisms shown in Figures 7a and 7b. The spring pin 212 forms a parallel connection of the inductance formed primarily by the spring 215 with a resistor formed primarily by the barrel 218. This parallel connection corresponds to the impedance matching circuit ARC as shown in Figs. 23a and 24a. The spring pin 212 can be obtained by making the resistance formed by the tube 218 correspond to a resistance of the device under test and the inductance formed by the spring 215 is corresponding to the square of the resistance multiplied by the capacitance of the device under test. To manufacture. The spring pin 212 can be fabricated for these particular needs of a particular device under test, such as for a GDDR5 memory component. A new generation of memory elements may require a new spring pin 212 with components suitable for the new memory component. It should be noted that the spring pin in Fig. 27 can also be designed such that the tactile coil 215 takes over only at the position where it maintains contact with the spring for all possible compressions of the spring pin 201024739. Equal sleeve and / or s sinuous resistive phase. By appropriately selecting the size and material, the ARC circuit as described above can be implemented by using the spring lock pin shown in Fig. 27 & Figure 28 is a cross-sectional view showing a test configuration apparatus in accordance with another embodiment of the present invention. The test configuration device corresponds to the test configuration device 'as shown in Fig. 27' except that another spring pin 222 is used. The spring pin 222 includes a first sleeve 226 of a conductive material, a second sleeve 227 of a conductive material, and a spring 225 of a conductive material for separating the first sleeve 226 and the second sleeve 227. A tube 228 of insulating material and an elastic member 223. The first sleeve 226, the second sleeve 227 and the tube 228 are slidably attached to each other along a common shaft 229, corresponding to the spring pin 212' as shown in Fig. 27 except for the tube 228. Made of insulating material instead of conductive material. Further, the spring pin 222 includes a resilient member 223 that includes a resistive material such as, for example, a resistive elastomer attached between the first sleeve 226 and the second sleeve 227 along a common axis 229. . The elastomer is laterally insulated and longitudinally resistive. This can be accomplished with thin wires extending longitudinally and laterally through the elastomeric member 223, thereby electrically coupling the sleeves 226 and 227 from the interior. The spring pin 222 forms an inductance formed primarily by the spring 225 in parallel with one of the resistors formed primarily by the elastomeric member 223. Since the insulating barrel 228 can be made of a material such as, for example, PTFE (Teflon), an electrical circuit is transmitted from the first sleeve 226 through the spring 225 and the elastic member 223 to the second The sleeve 227 is formed. The electrical circuit is not formed by the tube 228. This feature distinguishes the spring pin 222 shown in the figure (4) from the spring pin 212 shown in Fig. 27. In addition, other embodiments of the present invention may include a spring pin 222 having a tube 228 of a resistive material and a resilient member 223 of a resistive material, whereby an electrical circuit is used by the spring 225 and the resistor of the elastic element μ are formed in parallel with the resistance of the barrel 228. As described above, the elastic member 228 can include an elastomer having a main longitudinal axis corresponding to the common shaft 229 and a top surface of the elastomer along the main longitudinal axis. To the line of the bottom surface of the hybrid conductive material. The electrically conductive (4) wires may be, for example, <line or gold wire 126. The elastic member 228 may be coated with a coating of insulating material to prevent snagging in the inductance formed by the spring 225 and primarily by the elastomeric member 223. Short circuit between ''resistance'. Alternatively, the spring 225 can have an insulating coating. The spring 225 can be a helical spring or any of a variety of elastomers to separate the first sleeve 226 and the second sleeve 227.

Figure 29a shows a top view of a test configuration device in accordance with an embodiment of the present invention. The test configuration device includes a magazine pin 232 that includes an elastomer body 233 having a main longitudinal axis 234 that includes electrical conductivity embedded in the elastomer body, such as A line 235 of material extends between the top surface 236 and the bottom surface 237 of the elastomer body 233 along the main longitudinal axis 234. The spring pin 232 forms a parallel connection of an inductor and a resistor, both formed by a wire 235. A magnetic field of, for example, 5 nH corresponding to the inductance of the spring pin 232 is formed by the lines. The lines 235 are embedded in the body 233 in such a manner that the lines 235 are electrically interrupted between the bodies 233 44 201024739. The top surface 236 and the bottom surface 237 can include a conductive material to electrically contact the spring pin 232 to a device under test 210 and a device under test. The line 235 can be a carbon wire resulting in a total resistance of 50 ohms. The spring pin 232 can be used as a common pin. In this embodiment of the invention, the body 233 is a cylindrical body. However, in other embodiments, the body 233 can have another form and another cross section, such as, for example, a cube shape. Figure 29b shows a top view of a test configuration device in accordance with another embodiment of the present invention. The test configuration device includes a spring pin 242 that is similar in construction to the spring pin 232 as shown in Figure 29a, except that the wires 245 are made of gold to obtain The resistance of an i port. The low resistance gold wires 245 provide a low inductance of the spring pin 242 whereby the spring pin 242 can be used as a power source or a non-share pin. The spring pin 242 is compared to the 忒 spring pin 242, which is primarily assembled for matching purposes as shown in Fig. 29a, and is primarily intended for contact purposes and 迤 φ is not used for matching purposes. The spring pin 232 as shown in Fig. 29a is also used for the elastic member 225 as shown in Fig. 28. Similarly, the spring pin 242 can be used for the resilient member 225 as shown in Figure 29b. A main idea of the design of the spring pin as shown in Figures 29a and 29b is to adjust the cylindrical spring pin by increasing or decreasing the diameter of the cylindrical body by the relationship between the diameter and the inductance of the cylindrical object. The inductance of the pins 232, 242 is the function of the diameter of the cylinder. A thin cylinder has a higher inductance than a thick cylinder. The gold wires 245 are assembled to adjust the electrical conductivity of the "spring" pin 242. The spring pin 242 includes the gold wires 45 201024739 arranged along the overall diameter of the elastomer, and the spring pin 232 The inclusion line 235 is only arranged in the inner portion (core) along the diameter of the elastomer. Thus the spring pin 242 as shown in Fig. 29b, such as the spring pin 232 shown in Fig. 29a, has a low inductance. Figure 29c shows an array of spring pin pins of the spring pins 232 and 242 as shown in Figure 29a/b. The spring pins 232, 242 have a bottom surface 237 that is coupled to a common electrode 246. The test device can be used to form a pressure sensitive conductive rubber (PCR) socket that can be used to connect - printed circuit boards or other high performance logic components. Large processors, controllers, and other integrated circuits (1C) Specific sockets are required. These sockets can be PCR sockets that provide less force per pin, higher current delivery capacity and electrical performance up to 20 GHz. Pitch can be as low as 0.25 mm, an AC (AC) performance reaches 20 GHz and is born The cycle reaches 200,000. The PCR socket is designed to be compatible with existing spring pins or stamped contacts and implemented to increase yield and system up time. The PCR elastomer contacts provide high Performance and almost invisible component marks. Spring pins as illustrated in Figures 29a and 29b can be used in PCR sockets. Some spring pins 242 can be used as needed. The power supply and the non-shared pin, and the other spring pin 232 can be used as a contact pin, which is provided to the impedance matching circuit as an anti-reflection socket spring pin. Figure 30 is an embodiment of the present invention, An equivalent circuit diagram of a test configuration apparatus is shown. The test configuration apparatus includes an impedance matching circuit 250, a TDR transmitter 251, and a TDR receiver 252. The TDR transmitter 201024739 251 and the TDR receiver 252 are coupled through a coaxial The cable 253 is connected to a circuit including the impedance matching circuit 25 〇 pre-connected to the DUT under test, the DUT having a capacitance of 丨丨pp and a 5 〇Ω resistor connected in parallel An impedance Zin. The coaxial cable 253 can have a length of 20 cm and a diameter of 5 mm. The impedance matching circuit 25 is used to avoid the impedance of the coaxial cable 253 and the DUT under test. The reflection caused by the impedance Zin mismatch. Fig. 31 shows a TDR diagram measured using the test configuration device as shown in Fig. 3, the test configuration device including the impedance matching circuit 25A. If not, a comparison of the magnitudes of the impedance matching circuit 25A is not included, and the TDR pattern shown in Fig. 31 shows almost no reflection except for the series connection by the impedance matching circuit 25 after about 2.1 ns. A small reflection caused by a parasitic · inductor series inductance (ESL) of the resistor R. However, the reflection caused by the parasitic ESL is negligible compared to a circuit that does not include a resistive matching circuit 250. A lower value for the inductance of the impedance matching circuit 25A compensates for the parasitic ESL of the resistance R of the impedance matching circuit 250. Due to the small distortion of the TDR彳s number, the test configuration device including the impedance matching circuit 25〇 allows measurement with higher sampling frequency and thus high precision for fast memory components such as GDDR5 Measurement. Figure 32 is a diagram showing an equivalent circuit diagram of a test configuration device, the test configuration device comprising - corresponding to the impedance matching circuit 25G of the test configuration device as shown in the second, - corresponding to the test configuration device as shown in the second TDR transmitter 251 and - TDR receiver 254. An RTL (rise time limit) circuit is coupled between the TDR _251 and the surface microstrip transmission line 47 201024739 to limit the rise time of the signal generated at the TDR transmitter 251 to a value of 250 ps. The surface microstrip transmission line 255 is coupled to the impedance matching circuit 250 in series with the device DUT having the input impedance Zin formed by a 11 PF capacitor and a 50 Ω resistor in parallel. This configuration device is used when the fast TDR measurement (30 ps rise time) as shown in Fig. 30 is applied but the slower TDR measurement (250 ps rise time) as shown in Fig. 32 The performance of the impedance matching circuit 250 and the DUT under test is tested, and the rise time of the slower TDR measurement is more suitable for the rise time of the tester (about 200 ps). Figure 33 shows an eye diagram of a signal received by the TDR receiver 254 of the test configuration device as shown in Figure 32. The eye diagram shows an almost open eye that is minimally disturbed only by the small reflection 260 caused by the parasitic ESL of the impedance R of the impedance matching circuit 250. The distortion in the eye diagram including an impedance matching circuit 250 as shown in Fig. 33 is substantially smaller as compared with the eye diagram of the test configuration device having no impedance matching circuit 250 as shown in Fig. 12. . A test configuration device comprising an impedance matching circuit 250 or an anti-reflection circuit respectively allows for an accurate measurement with accuracy, even at high sampling rates. The test configuration device as shown in Figure 32 is well suited for measuring high rate sampling devices, such as GDDR5 memory components. Figure 34a shows a schematic cross-sectional view of a test configuration apparatus including an SMA adapter 300' for transmitting an OD load simulation 302 and an impedance matching circuit 301, in accordance with an embodiment of the present invention. A coaxial cable (not shown) is terminated in series. The impedance matching circuit 〇1 includes a 27nH inductor 303 in parallel with a 50Ω resistor 304. The 50Ω resistor is implemented in parallel with one of two 201024739 100 Ω resistors to reduce this parasitic ESL. The ODT load simulation 302 is implemented by a parallel connection of a 11 pF capacitor 305 and a 50 Ω resistor 306. The capacitance 305 of the ODT load simulation 302 is implemented by a parallel connection of a 10 pF capacitor and an lpF capacitor. The resistor 306 is implemented in a parallel connection of two standard 100 ohm resistors. The circuit of the impedance matching circuit 303 and the ODT load emulation 302 are coupled between a core 307 and a ground connection 308 of the SMA adapter cable 300. The electronic components are discrete components such as, for example, SMD components. Figure 34b shows an equivalent circuit diagram of one of the test configuration devices as shown in Figure 34a. The impedance matching circuit 301 is coupled in series with the ODT load simulation 302 of the device under test. The inductor 303 is 27 nH, both resistors 304, 306 are 50 Ω and the capacitor 305 is 11 pF. The impedance matching circuit 301 is sized such that the resistance 304 of the impedance matching circuit 301 corresponds to the resistance 306 of the ODT load simulation and the inductance 303 of the impedance matching circuit 301 corresponds to the square of the resistance 306 of the ODT load simulation 302. The ODT load simulates the capacitance 305 of 302. This matching condition guarantees suppression of unwanted reflections. Due to the tolerance-effect properties of the electrical components, the components 303, 304 of the impedance matching circuit 301 can be varied within an allowable region, such as 'optimally determined by the matching conditions shown above. The value is around 10%. Figure 35 shows a Smith chart of a reflection coefficient measurement of the test configuration device as shown in Figure 34a. Compared to the Smith chart of the reflection coefficient of the SMA adapter cable that does not include the impedance matching circuit, the Smith chart of the coefficient of the test configuration device including the impedance matching circuit 301 shown in FIG. 35 shows the coefficient of 201024739. For a few halves there are frequency matching characteristics.兮 Measurements are performed from the frequency of up to about 1 post. Even if the Hai f1GI7 solves the 'slave (four) number whistle, as shown in the 14th, the reflection coefficient 只有 is only - very small complex value. The degree of deviation of _ may be generated by an equivalent series inductance of the resistor 304 of the impedance matching circuit 30! corresponding to the amount shown in Fig. 31 and the paste.

Figure 36 shows an equivalent circuit diagram of the test configuration device, the test configuration device comprising two impedance matching circuits 32(), each of the impedance matching circuit and the re-measuring component 32-TDR transmitter 322 and each (four) TDR Receiver 323 is associated. The test configuration device further includes a gamma line to connect the TDR transmitter 322 to the two devices under test 321 . The TDR transmitter 322 includes an RTL circuit for limiting the rise time of the signal generated by the TDR transmitter to 250 ps. The gamma-branch cable has a meandering structure including a transmission line 325, a first conductor 326 and a second conductor 327. The wire 325 is connected to the first wire 326 and the second wire through a via hole.

327. The transmission line 325 has a 50 Ω impedance and can be implemented with a Gore cable having a length of 1 m and a diameter of 5 mm. The first and second conductors 326, 327 have an impedance of 50 Ω and can be realized with a Rosenberger winding having a length of 20 cm and a diameter of 5 mm. The Y-branch cable further includes an SMA adapter cable 327 coupled between the first conductor 326 and an output of the Y-branch cable to produce a desired length lost pair. The SMA adapter cable has a length of 3 cm. The output of the SMA adapter cable 327 is coupled to the impedance matching circuit 320 of the first device under test and the output of the second output buffer 327 is coupled to the impedance matching circuit 320 of the second device under test. 50 201024739 Through the asymmetric structure of the Y-branch line 324, the results due to the asymmetrical line length can be measured. Figure 37 shows a TDR map measured using a test configuration device as shown in Figure 36. The TDR measurement shows that although the γ-branch cable 324 has an asymmetrical structure, no reflection occurs at the measurement point at which the TDR receiver 323 measures the received signal at the device under test 321 . Due to the impedance matching circuit 320 matching the impedance of the device under test 321, the reflection is cancelled in the circuit including the impedance matching circuit 320 and the device under test 321 . The reflections returned from the Υ-branch cable to the TDR transmitter 322 are eliminated in the TDR transmitter 322, whereby they do not affect the measurement at the device under test 321 . Figure 38 shows an equivalent circuit diagram of a test configuration device comprising two impedance matching circuits 320, each impedance matching circuit and a device under test 321, a length mismatched Υ-branch cable 324 A test signal transmitter 330 and a test signal receiver 331 are associated. The Υ-branch cable 324, the impedance matching circuit 320, and the device under test 321 correspond to the circuits as shown in Fig. 36. The test configuration device differs in the type of measurement, such as the test configuration device shown in FIG. 36 for a time domain reflectometry, and the test configuration device as shown in FIG. 38 for signal measurement such as For example, it is used to measure an eye diagram at the device under test 321 . The test signal transmitter 330 can be a one bit error rate tester (BERT) or a pseudo random binary sequence (PRBS) generator. Fig. 39 shows an eye diagram measured using the test configuration device as shown in Fig. 38. This eye diagram shows no distortion due to reflection. However, 51 201024739

The rise time is reduced as compared to the job configuration device having the signal transmission line of the 32_(4). Between the 20% transition point and the 8〇% transition point, it is measurable—about face_rise time. This eye_ shows that it is not necessary for measuring the component to be measured without reflection - the _ γ branch. The respective impedances of the erase condition Z2 = 2.H towel fine lines 326 and 327 are no longer required and Z1 describes the impedance of the transmission line 325 in the γ_branch_. Therefore, due to the matching of the impedance matching circuit 32, it is not necessary to consider the length of the wire, and the fiber of the burr can be sized according to the needs of the device under test without considering the symmetry condition. A shorter _ line will increase the rise time and a drop in the amount of compensation. The compensation will give the time of the field - an additional increase.

This then means that a test configuration device in accordance with the present invention requires less design constraints for the branch nodes. The first output line and the second output line of the input line may include a transmission line, a waveguide, a microstrip line, a strip conductor of a printed circuit board, a via hole, a connection (micro) strip line, and a high frequency microwave line connector. , an interconnect or component, an SMA adapter, a coaxial thin wire, and the output line may deviate from a symmetrical condition, ie, for example, the impedance of the first output line deviates from the impedance of the first output line by more than 5% or The impedance of the impedance of the first output line in parallel with the second output line is less than 5% of the impedance of the input line. Alternatively or additionally, the length of the scale outlet/branch may be offset by more than 1%, the impedances of the tested components may be offset from each other by more than 1%, and/or the first output line is on the circuit board Formed on another layer different from the second output line, the three lines are connected to the common input line through the via holes and thus are asymmetrical. Figure 40 is a circuit diagram showing a test configuration package 52 201024739 in accordance with an embodiment of the present invention. The test configuration device includes the branch circuit board 120 as shown in Figure 17 and is connected to respective output lines 122, An impedance matching circuit 34 is formed between 123 and the respective impedances of the devices DUT1, DUT2. Through the impedance matching circuit 340, no reflection occurs at the branch end thereby eliminating the condition (Z2 = 2ZD becomes no longer needed. When the impedance of the input line & 60 Ω is 'one of the output lines' Impedance Z2 can be 6 〇Ω. Symmetry is no longer required. 'For example, length matching is no longer required. These rise times are significantly faster because the line impedance is significantly lower. For example, the impedance through these output lines ζ 2 = 6 〇 Ω The rise time can be increased by an equivalent line impedance of 30 Ω. The devices DUT1, DUT2 can be GDDR5 memory elements. Figure 41 shows a test configuration device in accordance with an embodiment of the present invention. An equivalent circuit diagram, the test configuration device includes two components Dim, DUT2. For the Υ-branch 120, the DUTs DUT1, DUT2 and the impedance matching circuit ARC, the test configuration device corresponds to The test configuration device shown in Fig. 40. The impedance matching circuit 340 is represented by a parallel connection of a 5.4 nH inductor and a 60 Ω resistor. The components of the impedance matching circuit 340 are sized according to the following matching conditions: impedance matching An equal resistance of the impedance of the path 340 and the device under test and an inductance of the capacitance of the device under test for the square of the resistance. A signal generator 350 is coupled to the test interface 126 and used to generate the test. The test signals of the tested components DUT1, DUT2. Figure 42 shows a simulated eye diagram of a first input signal v(10) of the test configuration device as shown in Fig. 41. The sampling time is 2.5. Gbps. The signal generator 350 generates a 27 pseudo-random binary sequence 53 201024739 (PRBS). A rise time tR and 8 〇〇 ps measured using the test configuration device as shown in Fig. 38 as shown in Fig. 39 The rise time is reduced to approximately 130 ps compared to its value. The increase in rise time is to avoid the results of the impedance matching circuit required for such reflections. Figure 43 shows a test configuration in accordance with an embodiment of the present invention. An equivalent circuit diagram of the device, the test configuration device comprising four devices DUT1, DUT2, DUT3, DUT4. The test configuration device includes a microstrip line 360' connected to a device tester 350 One test The test interface 126 and the impedance matching circuit ARC and the connected components DUT1 - DUT4 瘳 are connected in series. The microstrip line 360 includes four branch nodes 361, - 362, 363 and 364, whereby the test interface 126 and The impedance of the microstrip line 360 between the first branch node 361 is 25 Ω, and the impedance of the microstrip line 360 between the first branch node point 3 61 and the second branch node 3 62 is 33 Ω, the impedance of the microstrip line 360 between the second branch node 362 and the third branch node 363 is 50 Ω and the microstrip between the third branch node 363 and the fourth branch node 364 The impedance of line 360 is 1 〇〇Ω. The microstrip line 360 can be sized such that the impedance of the output line between the respective branch nodes 361 - 364 and the impedance matching circuits ARC of the respective sense elements DUT1 - DUT4 connected to Θ is approximately 100 Ω. The branch nodes 361 to 364 are arranged on the microstrip line 3 60 and between the test interfaces 12 6 thereby forming a resistive line element 365, wherein each resistive line element 364 has a resistance of 100 Ω. The microstrip line 360 includes four resistive line elements 365 connected in parallel between the test interface 126 and the first branch node 361 for a total of 25 Ω. Between the first branch node 361 and the second branch node 362, three 54 201024739 resistive line elements 365 are connected in parallel, for a total of 33 Ω. The two resistive line elements 365 are connected in parallel between the second branch node 362 and the third branch node 363, for a total of 50 Ω. A resistive line element 365 is connected between the third branch node 363 and the fourth branch node 364 for a total of 100 Ω. Figure 44 shows a signal diagram of the four input signals of the test configuration device as shown in Figure 43. The signals ν(1〇), ν(11), ν(12), and ν(13) are measured at the respective devices DUT1 - DUT4. Although the microstrip line 360 exhibits a highly asymmetrical structure, the signals v(l〇)-v (the signals v(l〇)-v) are removed due to the pre-connected impedance matching circuits ARC that cancel the reflections from the DUT1 - DUT4. 13) No reflection. It is to be noted that the reflection that occurs when there is no impedance matching circuit ARC is generated by the inputs of the devices DUT1 - DUT4 rather than by the asymmetric microstrip line 360. This bus-like structure (not to the microstrip line 360) requires an impedance matching circuit ARC for a desired function. Therefore, in contrast to a Y-structure (such as the Y-branch 120 shown in Fig. 41), no elimination condition is defined for the bus-like bus structure (asymmetric microstrip line 360). Figure 45 shows an eye diagram of the first input signal v(10) of the test configuration device as shown in Figure 43. This eye diagram is not distorted by reflection. However, a rise time of approximately 200 ps affects the eye pattern such that the eye is not fully open. Compared with the measurement without the impedance matching circuit as shown in Fig. 22b, the eye pattern as shown in Fig. 45 is opened wider, thereby measuring the higher precision in, for example, the GDDR5 memory element. It is possible. These 55 201024739 are eliminated in the eye diagram shown in Figure 21b, which is visible in the eye diagram. The distortion is as shown in Fig. 45. The test configuration device has a test circle. The test configuration device W impedance matching circuit is a vertical ship, and the first display-with-chip array 3 is used to cut the circuit board. These cymbals on the DUT. To this end, the slabs 37 = follow the area occupied by the lee and the distribution of the shims. Although the pins 371 == - can have - tear, Figure 46 shows only - representative cymbals:

-ARC. The ARC is discharged to the contact port 372 via a first transmission line 381. The first transmission line 381 is implemented, for example, as a signal trace embedded in the circuit board and connected by the via hole 382 to the outside of the circuit board. The contact 塾 372 formed on the surface. The distance between the ARC and the spacer 372 is long extended via the first transmission line 381 and the via 382 may have a quarter of the average wavelength λ of the test (four) used to measure the D υ τ via the potential 37 2 A small length. The contact pads 371, 372 can be arranged in a symmetrical configuration to form a ball array (BGA).

The impedance matching circuit ARC includes a parallel such as an inductor (such as a line art inductor having, for example, L = 6.2 nH) and a resistor (for example, a discrete element of 6 。. The inductor and the resistor element can be as The one shown in Fig. 46 is stacked one on top of the other. Both can be arranged on top of the outer surface of the circuit board forming the slabs 371. For example, the ARc circuit is formed by the SMD portion. A via 383 The ARC can be connected to the transmission line 381. The other terminal of the ARC can also be connected to a conductor, which is then connected to a tester or test head. For example, a via 384 and a walk 56 201024739 line 385 Can be connected to the ARC such that the ARC is connected in series between the traces 385 and 381. The trace 385 can be connected to a bifurcation node, as described in the foregoing embodiments. Formed on the circuit board. Alternatively, the non-forked node may appear between the ARC and one of the signal generators of the tester. Figure 47 shows the ARC impedance of a discrete component as shown in Fig. 46. Matching circuit measurement A timing diagram of the comparison of the signals measured by a spring pin ARC impedance matching circuit as shown in Fig. 42. The spring pin ARC measurement signal V(8) has a measured signal V(V) compared to the discrete component. 80) a slightly faster rise time. Since the length of the transmission line 381 contacting the contact pad of the device under test to the ARC impedance matching circuit is less than a quarter wavelength of the wavelength of the test signal, the mismatch condition is no longer Effective. The inductance L of the impedance matching circuit ARC should be matched to an input impedance of the device under test having a transmission line having a length less than a quarter wavelength of the test signal. A value of 6.2 nH is found. The impedance matching circuit ARC is adjusted to be nearly optimally adapted to the new input impedance of the device under test. The impedance matching circuit ARC produces a function as a moderate and benign low pass filter. A drop compensation circuit in the card will be able to compensate for the low-pass characteristic, whereby a significant eye opening can be obtained. Since the input capacitance Cin of the device under test is a limiting factor for the rise time, The new generation of memory components results in a reduction in the proportion of Cin which increases the edge rise time. The embodiments of the present invention comprising an impedance matching circuit ARC are scalable 'reflections no longer limit the speed. 57 201024739 Figure 1 shows a beam diagram in which light is reflected by an optical material or through an optical material, depending on an optical anti-reflective coating of the optical material, to illustrate the implementation of the invention described below. One of the main ideas of the basis of the example; Figure 2a shows a schematic diagram of the scene of Figure 1, that is, the optical transmission of an optical medium having a different reflection index than the reflection index of the surrounding air; Figure 2b is based on the second The optical arrangement shown in the figure shows a schematic diagram of an electrical transmission line connected to a device under test having an impedance different from the impedance of the transmission line; Figure 3a shows the input of a component under test An equivalent circuit diagram of impedance, including a resistive "terminal built into the chip" and a capacitive input capacitor; Figure 3b shows a representation of Figure 3a a Nyquist diagram of the input impedance; Figure 4a shows an equivalent circuit diagram of an input impedance of a device under test, the input impedance comprising a resistive specific resistance and inductance value embedded in the terminal of the wafer And a gate and an ESD (electrostatic discharge) capacitor; Figure 4b shows a Nyquist diagram illustrating the input impedance in Figure 4a; Figure 5 illustratively shows the input impedance of a GDDR5 memory a TDR (Time Domain Reflected) diagram; Figure 6 shows a cross-sectional view of a circuit spring pin according to a comparative embodiment; 58 201024739 Figure 7a shows the internal components of a spring pin of another comparative embodiment and for A top view of the spring in which the inner member and the outer sleeve are separated from each other; FIG. 7b shows a plan view of a device in a compressed state in FIG. 7a, and FIG. 8 shows a spring pin shown in FIGS. 7a and 7b. a top view of one of the outer sleeves of the needle; Figure 9 shows a time domain measured by an input pin of a shorted test element (DUT) through the spring pin of Figures 7a through 8 Reflection (TDR) map Figure 10 shows a histogram illustrating the repeatability of a spring pin measurement using the spring pins shown in Figures 7a through 8; Figure 11 shows a TDR map showing the TDR The figure is measured by a comparative test configuration device for measuring a DUT; Figure 12 shows a TDR reception in a test configuration device for measuring an impedance component of an impedance mismatch. An eye diagram of a signal received at the device, Figure 13a shows a schematic cross-sectional view of an SMA (sub-miniature-A) adapter cable terminated with an ODT load simulation; Figure 13b An equivalent circuit diagram showing the SMA adapter cable terminated by the end terminal (ODT) loaded terminal of the wafer as shown in Fig. 13a is shown; Fig. 14 is shown as shown in Fig. 13a A pole map of an input impedance of the SMA adapter cable with the ODT load terminal as a terminal; 59 201024739 Figure 15 shows a TDR diagram measured by a componentless loaded daisy chain test configuration device; Figure 16 shows a daisy chain test configuration device using DDR2 components loaded at all locations. a measured TDR diagram; Figure 17 shows a circuit diagram for connecting a test pin to a branch on two elements under test, the branch comprising a common line and two lines connected by a branch node; Figure 18 shows a circuit diagram of the branch as shown in Figure 17, wherein the impedance of the branch lines and the input impedance of the DUTs are specific values; Figure 19 shows a conventional example as shown in Figure 17. Branch circuit diagram, which indicates the reflection that occurs; Figure 20a shows a circuit diagram of a daisy-chain test configuration device for measuring the DUT in a shared test channel; Figure 20b shows the test configuration shown in Figure 20a. a TDR map obtained by the device; FIG. 21a shows a step response timing diagram of a test signal applied to a daisy chain configuration device; and FIG. 21b shows an eye of the test signal as shown in FIG. 21a Figure 22a shows a wave pattern of light transmitted through an optical medium as shown in Figure 2a when the optical medium comprises an optical film made of an anti-reflective coating material; Figure 22b shows the same as Figure 22b. akin Signal diagram, according to an embodiment of the present invention, the signal diagram is the electrical transmission line of Figure 2b and has an anti-reflection circuit (impedance matching circuit) connected to the transmission line and the impedance of the terminal of 201024739; One embodiment of the invention shows a schematic diagram of a test configuration apparatus; FIG. 23b shows a schematic diagram of a test configuration apparatus according to another embodiment of the present invention; and FIG. 23c shows an embodiment according to an embodiment of the present invention. An equivalent circuit diagram of a test configuration device; FIG. 23d is a schematic diagram showing a test configuration device including a device tester, a test interface, and a majority for receiving a test configuration device according to an embodiment of the present invention. Measuring a plurality of interfaces of the component; Figure 23e shows a theoretical Nyquist plot illustrating the input impedance of the test configuration device as shown in Figure 23a; Figure 24a shows the corresponding Figure 4a An equivalent circuit diagram of a test configuration device, one of the illustrative examples of a GDDR5 memory component, having an embodiment connected to the transmission in accordance with an embodiment of the present invention And an impedance matching circuit between the tested components; Figure 24b shows a theoretical Nyquist diagram of the test configuration device as shown in Figure 24a; Figure 25 shows the use as shown in Figure 24a The test configuration device measures a theoretical TDR map; Figure 26 shows the voltage at the device under test of the test configuration device as shown in Fig. 24a and the case generated in the case of Fig. 4a A step response timing diagram comparing the voltages at the input impedance of the device under test; 61 201024739 Figure 27 shows a schematic cross-sectional view of a spring pin in accordance with an embodiment of the present invention; A schematic cross-sectional view of a spring pin in accordance with another embodiment of the present invention is shown; Figure 29a shows a spatial view of a spring pin in accordance with an embodiment of the present invention; A space view of a spring pin according to another embodiment of the present invention; FIG. 29c shows a top view of a test configuration device in accordance with an embodiment of the present invention; FIG. 30 is an embodiment of the present invention Showing a test configuration An equivalent circuit diagram of the device, the test configuration device comprising an impedance matching circuit, a TDR transmitter and a TDR receiver; and FIG. 31 shows a TDR measured using the test configuration device as shown in FIG. Figure 32 is a diagram showing an equivalent circuit diagram of a test configuration apparatus including an impedance matching circuit, a TDR transmitter, a microstrip line, and a measuring probe, in accordance with an embodiment of the present invention. Figure 3 3 shows an eye diagram of a signal received by the TDR receiver of the test configuration device as shown in Figure 32; Figure 34a shows one of the test configuration devices in accordance with an embodiment of the present invention In a schematic cross-sectional view, the test configuration apparatus includes an SMA adapter cable that is terminated by an ODT load simulation and a series connection of an impedance matching circuit; 201024739 Figure 3 4 b shows a diagram as shown in Figure 34 An equivalent circuit diagram of one of the test configuration devices; FIG. 35 shows a Smith chart of a reflection coefficient measurement of the test configuration device as shown in FIG. 34a; FIG. 36 shows an embodiment of the present invention An equivalent circuit diagram of a test configuration device, the test configuration device comprising two impedance matching circuits, each impedance matching circuit and a device under test, a length mismatched Y-branch cable, a TDR transmitter and a The measurement probe is associated; Figure 37 shows a signal diagram measured using the test configuration device as shown in Figure 36; Figure 38 shows a test configuration device in accordance with an embodiment of the present invention An equivalent circuit diagram, the test configuration device includes two impedance matching circuits, each impedance matching circuit and a device under test, a length mismatched Y-branch cable, a test signal transmitter, and a test signal receiver Corresponding; FIG. 39 shows an eye diagram measured using the test configuration device as shown in FIG. 38; FIG. 40 is a circuit diagram showing a test configuration device according to an embodiment of the present invention, the test configuration device Included in the branch as shown in FIG. 17, and an impedance matching circuit connected between respective output lines and respective impedances of the device under test; FIG. 41 is an embodiment of the present invention An equivalent circuit diagram of a test configuration device is shown, the test configuration device comprising two components under test; and Figure 42 is a simulation of a first input signal of the simulation of the test configuration device as shown in Fig. 41 Eye diagram; 63 201024739 Figure 43 shows an equivalent circuit diagram of a test configuration device comprising four components under test in accordance with an embodiment of the invention; Figure 4 4 shows a diagram as in Figure 4 A test signal of a simulated four input signals of a test configuration device; FIG. 45 shows an eye diagram of the simulated first input signal of the test configuration device as shown in FIG. 4; The figure shows a schematic diagram of a test configuration device. The test configuration device includes an impedance matching circuit coupled to a first device under test via a first transmission line and coupled to a first transmission line through a second transmission line. a second component to be tested, the first transmission line having a length smaller than a quarter wavelength of a carrier of the test signal and the second transmission line having a quarter wave of the carrier of the test signal The length of the growth; and Fig. 47 shows a timing chart of the signal measured by the first device under test and measured by the second device under test as shown in Fig. 46. [Description of main component symbols] 10...upper part of optical material 30·.·spring pin 12...lower part 32 of optical material...device socket 14 under test...lens 34...shield/pin Needle 16/18...light 36...ball 20...beam 38...test component package 21...thin layer of anti-reflective coating material 40···outer/inner tube/ARC layer 42... Housing/outer tube 22...glass 44/50...spring 24...electric signal 52...inner tube 201024739

54.. piston part 56.. contact part 58.. spring fixed part 60.. internal part 62.. contact stroke 64... end 66.. outer sleeve 72.. large diameter part 74. .. Small diameter hollow portion 81.. Measuring curve 82.. Measuring curve 90... Time interval 91 for reflection of eye shape distortion... Time interval of data bit 100.. .5.A adapter 101...Signal terminal load simulation 102...capacitor 103.. ·resistor 104,105·.·capacitor 106..resistor 120..circuit board 121...branch node 122...first lead/first round outgoing line 123... Second wire/second wheel outlet 124, 125... Tested component 126.. Test interface 127.. Transmission line 131~134... Tested component 140... Device tester 141.. Test interface 143.. Input Capacitors 145, 146, 147, 148, 150.. Branch Nodes 152... Short Lines 153... Terminal Impedances 155... Grounds 156... Reflections 160... Reflections from DUT 2 161... Reflections from DUT 3 ...... Reflections from DUT 4 200.. Impedance Matching Circuits 201... Transmission line 202...Terminal impedance of the device under test/measured element 203...Electric wave 210··. Device under test 211··. 212.. . Spring Pin 213. · Tested Component Socket 65 201024739 214... Grid Array Pad 215 on the Socket Plate... Spring 216.. First Sleeve 217.. Second Sleeve 218.. Tube 219.. .Shared shaft 220.. Contact field 222.. Spring pin 223... Elastic element 225.. Spring 226... First sleeve 227... Second sleeve 228.. Tube 229.. Common shaft 232.. Spring pin 233.. Elastomer body 234.. Main longitudinal axis 235.. Carbon wire 236.. Top surface 237.. Bottom surface 247. .. kernel 242.. spring pin 245.. gold wire 246.. electrode 250.. impedance matching circuit 251..TDR transmitter 252..TDR receiver 253.. coaxial cable 254 .. .TDR Transmitter 255.. Surface Microstrip Transmission Line 260.. Small Reflection 300.. .5.A Adapter 301.. Impedance Matching Circuit 302..0.T Load Simulation 303.. Inductor 304...resistor 305..capacitor 306..resistance 307..core 308.. Ground connection 320.. impedance matching circuit 321.. Measured component 322..TDR transmitter 323.. TDR Receiver 324.. . Y-Branch Cable 325.. . Coaxial Cable / Transmission Line 326.. . Coaxial Electric Winding / First Conductor

66 201024739

327...Second wire/SMA adapter thin wire/second output cable 330.. Bit error rate tester/pseudo-random binary sequence/signal source 331.. test signal receiver 340.. impedance matching circuit 350.. .Signal generator 360.. . microstrip line 361/362/363/364. ·. Branch node 365.. resistive line element 371.. spacer array 372.. spacer 381... A transmission line 382~384... via hole 385.. signal line 400.. test configuration device 401.. interface 402.. impedance matching circuit 403.. spring pin 403b... schematic of spring pin Indicates 404.. Test element 405.. Signal generator 420.. External electrical component 401b... Interface 404b... Tested component 406.. Test interface 407.. Test head 408/408b. .. socket board 410.. pin-electronic module 411.. tester receiver 412.. cable 413.. contact pad 414.. contact area 415.. screw 416.. mechanical Lock mechanism 417.. Spring connector 418.. Test interface cable 419". Ball R/R〇 DT... Resistance C/Cin... Capacitance L... Inductance Z/Zin/Zarc/Zi/Z2 ... Impedance fl...frequency r...reflection coefficient b...refractive index no/i^/nARc...refractive index S 11/S12/S21/S22...S parameters tR...rise time 67

Claims (1)

201024739 VII. Patent application scope: 1. A test configuration device comprising: an interface for a device under test, the interface comprising an impedance matching circuit, the impedance matching circuit comprising a resistor (R) and an inductor connected in parallel (L). 2. The test configuration device of claim 1, wherein the interface comprises a spring pin that forms the impedance matching circuit. 3. The test configuration device of claim 1 or 2, wherein the resistance (R) of the impedance matching circuit and the inductance (L) are formed by discrete electrical components. 4. The test configuration device of any of the preceding claims, further comprising a signal generator for applying a test signal having an intermediate frequency below a maximum frequency to the interface, wherein the impedance matching circuit is The electrical distance between the device under test and the impedance matching circuit is configured to be less than a quarter of an electrical wavelength corresponding to the highest frequency. 5. The test configuration device of any of the preceding claims, further comprising the device under test, the device under test comprising an input impedance (Zin), the interface being adapted to be in the impedance matching circuit and the input An electrical coupling is provided between the impedances (Zin) such that one impedance of the impedance matching circuit (ZaRC) matches the input impedance (Zin). 6. The test configuration device of claim 5, wherein the input impedance comprises a resistor (R) and a capacitor (C) connected in parallel, wherein the resistor (R) of the impedance matching circuit is equal to the input The resistance (R)' of the impedance 68 201024739 (Zin) is within a tolerance of +/_1〇%, and the inductance (L) of the impedance matching circuit is equal to the resistance (R) of the input impedance (Zin) The square of this input impedance (Zin) is the capacitance (C) within +/- 10% of the tolerance. The test configuration device according to any one of the preceding claims, further comprising: a second interface for a second device under test, the second interface comprising an impedance matching circuit The circuit includes a resistor (R) and an inductor (L) in parallel. The resistor (R) and the inductor (L) are equal to the resistor (R) and the inductor (L) for the interface of the device under test; a test interface for a component tester; and a branch point formed by an input line, a first output line, and a second output line. The input line is electrically connected to the test interface and a branch node The first output line is electrically connected between the branch node and the interface for the 70 pieces of the document, the second output line is electrically connected to the branch point and the portion for the second device under test Between the second interface. 8. The test configuration device of claim 7, wherein the input line, the first output line, and the second output line comprise a transmission line, a waveguide, a microstrip line, a strip conductor of a printed circuit board, Via, connection (microwire, directional microwave cable, connector, interconnect or component, SMA adapter or coaxial cable. 9. The test configuration device of claim 7 wherein The first and second output lines are offset from a symmetrical condition such that the impedance of the first output line deviates from the impedance of the second output line by more than 5% or 69. 201024739 such that the impedance of the first output line is different from the first The parallel impedance of the impedance of the two output lines deviates from the impedance of the input line by more than 5%. 10. The test configuration device of claim 7 or 8, wherein the first and second output lines The length of the test device according to any one of claims 7 to 10, wherein the impedances of the devices under test deviate from each other by more than 1%. Apply for patent scope item 7 to The test configuration device of any of the items 11, wherein the first output line is formed on another layer in a circuit board different from the second output line. 13. A spring pin comprising: a conductive a first sleeve of material; a second sleeve of electrically conductive material; a tube of resistive material, the first sleeve, the second sleeve and the tube are slidably attached to each other along a common axis Wherein the tube is disposed between the first and the second sleeve; and a spring of electrically conductive material for separating the first and the second sleeve, wherein the spring pin forms a primary The spring pin formed by the spring is connected in parallel with a resistor formed mainly by the tube. The spring pin according to claim 13, wherein the first and second sleeves have the same diameter. , the tolerance of the first and second sleeves, wherein the tube has a smaller one than the first and second sleeves, wherein the tolerance is in the range of +/- 5%. The diameter is such that the tube can slide in the first and second sleeves in 201024739. 16. The spring pin of any of claims 13 to 15 wherein the spring is disposed within the first and second sleeves. 17. As claimed in claim 16 a spring pin, wherein the spring is arranged in the tube. 18. A spring pin comprising: a first sleeve of electrically conductive material; a second sleeve of electrically conductive material; a tube, the first sleeve, the second sleeve and the tube are slidably attached to each other along a common shaft, wherein the tube is arranged between the first and the second sleeve; a spring of electrically conductive material for separating the first and second sleeves; and an elastic member comprising a resistive material attached between the first and second sleeves along the common axis, wherein The spring pin forms a parallel connection of an inductance formed primarily by the spring and a resistor formed primarily by the resilient element. 19. The spring pin of claim 18, wherein the resilient member is attached to the configuration of the first and second sleeves and the barrel. 20. The spring pin of claim 18, wherein the spring is a helical spring and the resilient element is disposed within the helical spring. The spring pin of any one of claims 18 to 20, wherein the elastic element is a resistive elastomer. The spring pin of any one of clauses 18 to 21, wherein the elastic element is coated with a coating of insulating material to prevent the inductance and the main formed mainly by the spring. A short circuit between the resistors formed by the resilient element. The spring pin of any one of claims 18 to 20, wherein the elastic member comprises an elastomer body having a main longitudinal axis; and the body member is embedded in the body of the elastomer a wire of electrically conductive material extending along a major longitudinal axis between a top surface and a bottom surface of the elastomer body, wherein the resilient member is attached between the first and second sleeves such that The main longitudinal axis is aligned with the common axis. 24. A spring pin comprising: an elastomer body having a main longitudinal axis; and a line of conductive material intended to be inserted into the body of the elastomer such that a top surface of the body of the elastomer is to The bottom surfaces extend along the main longitudinal axis, wherein the spring pins form a parallel connection of an inductor (L) and a resistor (R) each formed by the lines. 25. The spring pin of claim 24, wherein the wires are embedded in the body such that the wires are electrically interrupted from each other within the body. 26. The spring pin of claim 24 or claim 25, wherein the wires are carbon or gold wires. 27. The spring 201024739 pin of any one of claims 24 to 26, wherein the body is cylindrical in shape and wherein the wires are embedded in a cylindrical shaped core of the cylindrical body, The diameter of the core determines the value of the inductance (L). An array of spring pins as claimed in any one of claims 24 to 27, wherein their bottom surfaces are connected to a common electrode. 29. A method for testing a device under test, comprising the steps of: connecting the device under test through an impedance matching circuit comprising a resistor (R) and an inductor (L) in parallel. 73