WO2010032866A1

WO2010032866A1 - Semiconductor programmable device and signal transferring method in semiconductor programmable device

Info

Publication number: WO2010032866A1
Application number: PCT/JP2009/066581
Authority: WO
Inventors: 斎藤英彰
Original assignee: 日本電気株式会社
Priority date: 2008-09-16
Filing date: 2009-09-15
Publication date: 2010-03-25
Also published as: JP5365639B2; JPWO2010032866A1

Abstract

A semiconductor programmable device with low cost and high performance is obtained. Thus, the semiconductor programmable device is provided with a plurality of row wiring and a plurality of column wiring which are arranged on a chip, switch fabrics provided at the intersection points between the row wiring and the column wiring so as to transfer data signals, and a circuit block connected to each of the switch fabrics, wherein one of the row wiring or the column wiring is configured so as to transfer either a first data signal group or a second data signal group which constitutes the data signals, and the other one of the column wiring or the row wiring is configured so as to transfer both of the first data signal group and the second data signal group.

Description

Semiconductor programmable device and signal transfer method in semiconductor programmable device

The present invention relates to a semiconductor programmable device and a signal transfer method capable of changing a circuit configuration.

2. Description of the Related Art In recent years, semiconductor programmable devices capable of changing the configuration of a circuit after the manufacture of the semiconductor integrated circuit device have been actively developed in order to reduce the cost of the semiconductor integrated circuit device and reduce the turnaround time (TAT). Here, TAT refers to the time from receipt of an order to completion of delivery.
Semiconductor programmable devices range from FPGAs (Field Programmable Gate Array) that reconfigure by combining circuits at the gate level to those that reconfigure by combining circuit blocks (for example, processors and memories) that are larger circuit units. There is something.
As a semiconductor programmable device that reconfigures by combining circuit blocks, for example, Non-Patent Document 1 discloses a technique of arranging circuit blocks in a two-dimensional array on a chip and connecting the circuit blocks by mesh wiring. ing.
FIG. 13 is a block diagram showing an example of a related semiconductor programmable device in which circuit blocks are arranged in a two-dimensional array and the circuit blocks are connected by mesh wiring.
In the related semiconductor programmable device shown in FIG. 13, circuit blocks 111 are arranged in a two-dimensional array. The circuit block 111 includes a processor, a memory, a custom hardware circuit, and the like.
Further, as shown in FIG. 13, each of the circuit blocks 111 arranged in a two-dimensional array is connected to the switch fabric 113. The switch fabric 113 inputs and outputs signals between itself and the circuit block 111 that is directly connected. Further, it transfers a signal output from the switch fabric 113 adjacent to itself.
Further, as shown in FIG. 13, in order to transfer the signal output from the circuit block 111 to the outside of the other circuit block 111 or the semiconductor programmable device, the switch fabrics 113 are connected to each other by a mesh-like column wiring 115 and row wiring 117. It is connected.
That is, the switch fabric 113 is connected to the other switch fabric 113 adjacent in the vertical direction in the figure by the column wiring 115 and is connected to the other switch fabric 113 adjacent in the horizontal direction in the figure by the row wiring 117. It is also connected to the circuit block 111, and the switch fabric 113 has inputs and outputs in a total of five directions.
FIG. 14 is a block diagram showing a configuration of the switch fabric 113 of the related semiconductor programmable device shown in FIG.
As shown in FIG. 14, the switch fabric 113 shown in FIG. 13 includes five selectors 113-1 and a selection logic circuit 113-2 connected to each selector 113-1. This is because the switch fabric 113 has inputs and outputs in five directions as described above.
The selector 113-1 selects and outputs one of the signals input from four directions other than the direction in which the selector 113-1 outputs. The selection logic circuit 113-2 determines which direction the signal is selected from. Note that the selection logic circuit 113-2 includes, for example, a decoding circuit for decoding the addressed data transfer direction.
"Proceedings of the IEEE Computer Society Annual Symposium on VLSI", 2002, p. 40, Proceedings of the IE Computer Society Annual Symposium on VLSI (Proceedings of the IEEE Computer Society Annual VLSI). 105-112

If a semiconductor programmable device as disclosed in Non-Patent Document 1 is used, the circuit configuration can be changed even after the manufacture of the semiconductor integrated circuit device by switching the connection between the circuit blocks. The cost can be reduced and the TAT can be shortened.
The semiconductor programmable device as disclosed in Non-Patent Document 1 is compared with a normal semiconductor integrated circuit device in which the circuit configuration cannot be changed, and wiring for connecting circuit blocks as shown in FIG. The difference is that it has a switch fabric for switching connections. In a semiconductor programmable device as disclosed in Non-Patent Document 1, these wirings and switch fabric occupy a large area on the chip.
As a result, depending on the area occupied by the circuit block, a necessary and sufficient number of wires and switch fabrics cannot be accommodated on the chip.
In fact, in an FPGA, which is one of semiconductor programmable devices, half of the chip area is occupied by wiring and switch fabric. Similarly, in a semiconductor programmable device in which processors are arranged in a two-dimensional array, about ¼ of the chip area is occupied by wiring and switch fabric.
In addition, although it is conceivable to add a wiring layer in order to secure a necessary and sufficient number of wires with a limited chip area, there is a problem that the mask cost for manufacturing the added wiring layer increases. .
An object of the present invention is to provide a semiconductor programmable device and a signal transfer method that solve the above-described problem that it is difficult to obtain a low-cost and high-performance semiconductor programmable device.

A semiconductor programmable device of the present invention includes a plurality of row wirings and a plurality of column wirings arranged on a chip, and a plurality of switch fabrics provided at intersections of the row wirings and the column wirings and transferring input data signals. A plurality of circuit blocks that are directly connected to each of the plurality of switch fabrics and that input and output data signals through the plurality of switch fabrics, and either the row wiring or the column wiring constitutes a data signal Only one of the first data signal group and the second data signal group is transferred, and the other of the column wiring and the row wiring is the first data signal group. And the second data signal group are transferred.
A signal transfer method in a semiconductor programmable device according to the present invention includes a plurality of row wirings and a plurality of column wirings arranged on a chip, and a plurality of signal lines for transferring input data signals provided at intersections of the row wirings and the column wirings A signal transfer method in a semiconductor programmable device having a switch fabric and a plurality of circuit blocks that are directly connected to each of the plurality of switch fabrics and that input / output data signals via the plurality of switch fabrics, Alternatively, either one of the column wirings transfers only one data signal group of the first data signal group and the second data signal group constituting the data signal, and the column wiring and the row wiring. The other transfers both the first data signal group and the second data signal group.

According to the present invention, a low-cost and high-performance semiconductor programmable device can be obtained.

FIG. 1A is a block diagram showing a configuration of a semiconductor programmable device according to the first embodiment of the present invention.
FIG. 1B is a block diagram showing a configuration of a semiconductor integrated circuit device including a semiconductor programmable device according to the second embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a memory macro of a semiconductor programmable device according to the second embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of the memory input / output unit of the semiconductor programmable device according to the second embodiment of the present invention.
FIG. 4 is a block diagram showing the configuration of the upper bit switch fabric according to the second embodiment of the present invention.
FIG. 5 is a block diagram showing the configuration of the upper bit switch section in the upper bit switch fabric according to the second embodiment of the present invention.
FIG. 6 is a block diagram showing the configuration of the lower bit switch section in the upper bit switch fabric according to the second embodiment of the present invention.
FIG. 7 is a block diagram showing the configuration of the lower bit switch fabric according to the second embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a lower bit switch section in the lower bit switch fabric according to the second embodiment of the present invention.
FIG. 9 is a block diagram showing the configuration of the upper bit switch section in the lower bit switch fabric according to the second embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration of another switch fabric according to the second exemplary embodiment of the present invention.
FIG. 11 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the third embodiment including the semiconductor programmable device of the present invention.
FIG. 12 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the fourth embodiment including the semiconductor programmable device of the present invention.
FIG. 13 is a block diagram showing an example of a related semiconductor programmable device.
FIG. 14 is a block diagram showing a configuration of a switch fabric of a related semiconductor programmable device.

10, 50, 80 Semiconductor

programmable device

11, 51 Memory macro

11a Control unit

11b Address decoder 11c Word line driver

11d Sense amplifier

11e Write buffer 11f Read buffer 11g

Memory cell array

12, 52, 82, 112 Memory input /

output unit

13, 53, 83 Upper

bit switch fabric

13a, 14a Upper

bit switch section

13b, 14b Lower bit switch section 13a-1, 13b-1, 14a-1, 14b-1, 33c, 113-1 selector 13a-2, 13b- 2, 14a-2, 14b-2, 113-2

Select logic circuit

14, 54, 84 Lower

bit switch fabric

15, 55, 85 Upper

bit column wiring

16, 56, 86 Lower

bit column wiring

17, 57 87, 117

Row wiring

20, 60, 90

Logic device

21, 61, 91

Logic macro

33, 113 Switch fabric 33a Switch unit without column wiring 33b Switch unit with column wiring 62 Logic input / output unit 81 Processor 111 Circuit block 115 columns wiring

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1A is a block diagram showing a configuration of a semiconductor programmable device according to the first embodiment of the present invention. The semiconductor programmable device 10 includes a plurality of row wirings and a plurality of column wirings arranged on a chip, and a plurality of switch fabrics that transfer input data signals at intersections of the row wirings and the column wirings. A circuit block is directly connected to each switch fabric, and each circuit block inputs and outputs data signals via the switch fabric.
Here, either the row wiring or the column wiring is configured to transfer only one data signal group of the first data signal group and the second data signal group constituting the data signal. ing. The other of the column wiring and the row wiring is configured to transfer both the first data signal group and the second data signal group.
In the present embodiment, the memory macro 11 is used as the circuit block, the upper bits of the data signal are used as the first data signal group, and the lower bits of the data signal are used as the second data signal group. Further, in the present embodiment, as shown in FIG. 1A, the column wiring is composed of the upper bit column wiring 15 for transferring only the upper bit and the lower bit column wiring 16 for transferring only the lower bit, and the row wiring 17 Is configured to transfer both upper and lower bits. At this time, the upper bit switch fabric 13 is arranged on the upper bit column wiring 15 and the lower bit switch fabric 14 is arranged on the lower bit column wiring 16.
In the semiconductor programmable device 10 according to the present embodiment, the data signal read from the memory macro 11 is divided into upper bits and lower bits by the upper bit switch fabric 13 and the lower bit switch fabric 14. The upper bits are transferred by the upper bit column wiring 15 and the row wiring 17, and the lower bits are transferred by the lower bit column wiring 16 and the row wiring 17, respectively.
Therefore, according to the present embodiment, the number of bits of the column wiring can be halved, and the configuration of the upper bit switch fabric 13 and the lower bit switch fabric 14 can be simplified. As a result, the area overhead caused by the switch fabric and the column wiring can be reduced, and a high-performance semiconductor programmable device can be obtained at low cost.
[Second Embodiment]
FIG. 1B is a block diagram showing a configuration of a semiconductor integrated circuit device including the semiconductor programmable device according to the first embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 1B includes a semiconductor programmable device 10 and a logic device 20.
The semiconductor programmable device 10 includes a memory macro 11, which is a circuit block, a memory input / output unit 12, a switch fabric 13 for upper bits, and a switch fabric 14 for lower bits.
In the semiconductor programmable device 10 shown in FIG. 1B, 16 memory macros 11 are arranged in a 4 × 4 two-dimensional array. Each of the memory macros 11 is directly connected to the upper bit switch fabric 13 or the lower bit switch fabric 14.
Further, in the semiconductor programmable device 10 shown in FIG. 1B, a plurality of wirings are laid in the row direction and the column direction. Specifically, upper bit column wirings 15 and lower bit column wirings 16 are alternately laid in the vertical direction in the figure, and row wirings 17 are laid in the horizontal direction in the figure.
The upper bit column wiring 15 is a wiring for transferring higher bits of a signal transferred in the semiconductor integrated circuit device of the present embodiment, and the lower bit column wiring 16 is a semiconductor integrated circuit of the present embodiment. It is a wiring for transferring lower bits of a signal transferred in the apparatus.
The memory macro 11 includes, for example, a 1 k word SRAM (Static Random Access Memory) macro, and writes a write data signal output from the logic device 20 to a memory cell or outputs a read data signal to the logic device 20. .
FIG. 2 is a block diagram showing a configuration of the memory macro 11 of the semiconductor programmable device 10 shown in FIG. 1B.
As shown in FIG. 2, the memory macro 11 shown in FIG. 1B includes a control unit 11a, a memory cell array 11g, an address decoder 11b, a word line driver 11c, a sense amplifier 11d, a write buffer 11e, and a read buffer 11f. And. Here, the address decoder 11b controls access to the corresponding memory cell in the write and read operations of the memory cell in the memory cell array 11g. The word line driver 11c controls the word line connected to each of the memory cells in the memory cell array 11g, and the sense amplifier 11d amplifies the signal. The operation of the control unit 11a will be described later.
The memory input / output unit 12 illustrated in FIG. 1B mediates signal input / output between the memory macro 11 and the logic device 20. FIG. 3 is a block diagram showing a configuration of the memory input / output unit 12 of the semiconductor programmable device 10 shown in FIG. 1B.
As shown in FIG. 3, the memory input / output unit 12 receives a 16-bit read data signal from the memory macro 11 via the upper bit switch fabric 13 and the lower bit switch fabric 14 and outputs the data to the logic device 20. Is done. Further, a 16-bit write data signal, a 14-bit address signal, and a 2-bit command signal from the logic device 20 are input and output to the

switch fabrics

13 and 14.
Here, as an example of signal input / output between the logic device 20 and the semiconductor programmable device 10, a case of instructing reading of a data signal from the logic device 20 to the semiconductor programmable device 10 is described with reference to FIGS. 1B to 3. explain.
The logic device 20 instructing to read data outputs a command signal and an address signal to the memory input / output unit 12 as shown in FIG. The command signal and the address signal are input to all the memory macros 11 in the semiconductor programmable device 10 (see FIG. 1B) via the memory input / output unit 12. Here, the command signal indicates a data read instruction.
The control unit 11a (see FIG. 2) of the memory macro 11 to which the command signal and the address signal are input, stores its own address stored in advance, and the address of the memory macro 11 to be read from the data indicated by the address signal. Compare Here, the address signal is composed of a total of 14 bits including a 4-bit memory macro address for designating the memory macro 11 and a 10-bit word address for designating the word address in the memory macro 11. ing.
When the memory macro address of the address signal matches its own address stored in advance by the control unit 11a, the control unit 11a reads data from the memory cell indicated by the word address in the memory cell array 11g. This is because the command signal indicates a data read instruction here. Then, the control unit 11a outputs the read data as a read data signal from the read buffer 11f.
The read data signal output from the memory macro 11 is transferred by the upper bit switch fabric 13 and the lower bit switch fabric 14 and output to the logic device 20 via the memory input / output unit 12. The signal transfer method by the upper bit switch fabric 13 and the lower bit switch fabric 14 will be described later.
The above is an example of signal input / output between the logic device 20 and the semiconductor programmable device 10. Hereinafter, the write data signal input to the memory macro 11 and the read data signal output from the memory macro 11 are collectively referred to as “input / output data signal of the memory macro 11”.
The upper bit switch fabric 13 is provided at the intersection of the upper bit column wiring 15 and the row wiring 17. The upper bit switch fabric 13 controls the transfer direction of a plurality of signals input from the adjacent upper bit switch fabric 13, the adjacent lower bit switch fabric 14, and the directly connected memory macro 11.
The lower bit switch fabric 14 is provided at the intersection of the lower bit column wiring 16 and the row wiring 17. The lower bit switch fabric 14 controls the transfer direction of a plurality of signals input from the adjacent upper bit switch fabric 13, the adjacent lower bit switch fabric 14, and the directly connected memory macro 11.
FIG. 4 is a block diagram showing a configuration of the upper bit switch fabric 13 shown in FIG. 1B. As shown in FIG. 4, the upper bit switch fabric 13 includes an upper bit switch unit 13a that is a first upper bit switch unit and a lower bit switch unit 13b that is a first lower bit switch unit. I have.
In the upper bit switch fabric 13, when the input / output data signal of the memory macro 11 is input, the upper bits of the input / output data signal of the memory macro 11 are input to the upper bit switch unit 13 a. Are input to the lower bit switch unit 13b.
For example, in the upper bit switch fabric 13, when a 16-bit read data signal from the memory macro 11 is input as shown in FIG. 4, the upper 8 bits of the input read data signal are converted into the upper bit switch unit. 13a. On the other hand, the lower 8 bits of the input read data signal are input to the lower bit switch unit 13b. Further, as shown in FIG. 4, the 8-bit signal output from the upper bit switch unit 13a and the 8-bit signal output from the lower bit switch unit 13b are merged, and the memory macro is used as a write data signal. 11 is input.
The upper bit switch unit 13a controls the output destination of the upper bits of the input / output data signal of the memory macro 11 input to the upper bit switch fabric 13 by the selection logic circuit.
The lower bit switch unit 13b controls the output destination of the lower bits of the input / output data signal of the memory macro 11 input to the upper bit switch fabric 13 by the selection logic circuit. A selection logic circuit for controlling the output destination of the upper bit or the lower bit will be described later.
FIG. 5 is a block diagram showing a configuration of the upper bit switch section 13a in the upper bit switch fabric 13 shown in FIG. As described above, the upper bits of the input / output data signal of the memory macro 11 input to the upper bit switch fabric 13 are input to the upper bit switch unit 13a.
As shown in FIG. 5, the upper bit switch unit 13a shown in FIG. 4 includes a selector 13a-1 and a selection logic circuit 13a-2 connected to the selector 13a-1. The selector 13a-1 is provided in each signal input / output direction, and a selection logic circuit 13a-2 is connected to each selector 13a-1.
As shown in FIG. 5, the upper bit switch unit 13a has inputs and outputs in a total of five directions. As shown in FIG. 4, in addition to the connection with the memory macro 11, the upper bit switch unit 13a is connected with the upper bit switch fabric 13 and the upper bit column wiring 15 in the vertical direction in the figure. This is because, in the left-right direction in the figure, it is connected to the adjacent lower bit switch fabric 14 by the row wiring 17. Therefore, the upper bit switch unit 13a includes five selectors 13a-1 and selection logic circuits 13a-2, which are the same as the number of signals in the input / output direction.
The selector 13a-1 outputs one signal selected by the selection logic circuit 13a-2 among the signals input from four directions other than the direction in which the signal is output.
The selection logic circuit 13a-2 determines one signal to be output from signals input to the selector 13a-1 from four directions by a certain logic.
Here, when the upper bits of the read data signal output from any memory macro 11 are input to the upper bit switch unit 13a from four directions, the selection logic circuit 13a-2 selects one read data signal to be output. An example of logic to be determined will be described.
The selection logic circuit 13a-2 stores the address on the chip of the upper bit switch fabric 13 to which the selection logic circuit 13a-2 belongs. Here, the left-right address in FIG. 1B of the upper bit switch fabric 13 is represented as SX, and the up-down address in FIG. 1B is represented as SY.
The selection logic circuit 13a-2 also recognizes the address on the chip of the memory macro 11 that outputs the read data signal. This is because the upper bit switch fabric 13 receives an address signal output from the logic device 20 when instructing the output of the read data signal, and the memory macro that causes the address signal to read data. This is because a macro address indicating an address on 11 chips is included.
Here, the horizontal address in FIG. 1B of the memory macro 11 that outputs the read data signal is represented as MX, and the vertical address in FIG. 1B is represented as MY. Note that when the upper bit switch fabric 13 to which it belongs is directly connected to the memory macro 11 that outputs the read data signal, MX = SX and MY = SY. Here, M represents a memory macro, S represents an upper bit switch fabric, X represents a left-right direction in FIG. 1B, and Y is a subscript representing a vertical direction in FIG. 1B. Further, the addresses MX, SX, MY, and SY in FIG. 1B are integers.
The selection logic circuit 13a-2 compares SX and SY indicating the address of the upper bit switch fabric 13 to which the selection logic circuit 13a-2 belongs with MX and MY indicating the address of the memory macro 11 that outputs the read data signal. Of the read data signals input from the four directions, one read data signal to be output is determined.
Actually, when a read data signal is input from four directions, the selection logic circuit 13a-2 constructs a logic so as to perform selection as shown in the following (1) to (8).
(1) If SX <MX-1, the input from the lower bit switch fabric 14 on the right side of the figure is selected.
(2) If SX> MX, select input from switch fabric 14 for lower bits on the left side of the figure
(3) If SX = MX and SY <MY, the input from the upper bit switch fabric 13 is selected.
(4) If SX = MX and SY> MY, the input from the lower bit switch fabric 13 in the figure is selected.
(5) If SX = MX and SY = MY, select input from memory macro 11
(6) If SX = MX-1 and SY <MY, the input from the upper bit switch fabric 13 is selected.
(7) If SX = MX-1 and SY> MY, select the input from the upper bit switch fabric 13 in the lower part of the figure.
(8) If SX = MX-1 and SY = MY, select input from switch fabric 14 for lower bits on the right side of the figure
The above is an example of logic for selecting one read data signal to be output from read data signals input from four directions. The present invention is not limited to this, and any logic can be used in the present embodiment as long as it is a logic that transfers data signals within a matrix in a matrix in which column wirings for transferring data in the vertical direction in the matrix are arranged at predetermined intervals. .
FIG. 6 is a block diagram showing a configuration of the lower bit switch unit 13b in the upper bit switch fabric 13 shown in FIG. In the lower bit switch unit 13b, as described above, the lower bits of the input / output data signal of the memory macro 11 input to the upper bit switch fabric 13 are input.
As shown in FIG. 6, the lower-bit switch unit 13b shown in FIG. 4 includes a selector 13b-1 and a selection logic circuit 13b-2 connected to the selector 13b-1. The selector 13b-1 is provided for each signal input / output direction, and a selection logic circuit 13b-2 is connected to each selector 13b-1.
As shown in FIG. 6, the lower bit switch unit 13b has inputs and outputs in a total of three directions. As shown in FIG. 4, in addition to the connection with the memory macro 11, the lower bit switch unit 13 b is connected to the lower bit switch fabric 14 adjacent in the left and right directions in the figure by the row wiring 17. Because. Therefore, the lower-bit switch unit 13b includes the same three selectors 13b-1 and selection logic circuits 13b-2 as the number of signals in the input / output direction.
The selector 13b-1 outputs one signal selected by the selection logic circuit 13b-2 among the signals input from two directions other than the direction in which the signal is output.
The selection logic circuit 13b-2 determines one signal to be output from signals input to the selector 13b-1 from two directions by a certain logic.
Here, when the lower bit of the read data signal output from the arbitrary memory macro 11 is input to the lower bit switch unit 13b from two directions, the selection logic circuit 13b-2 selects one read data signal to be output. An example of logic to be determined will be described.
In the same manner as described in the case of determining one signal output from the selection logic circuit 13a-1 of the upper bit switch unit 13a, the upper bit switch fabric 13 to which the selection logic circuit 13b-2 belongs is described. The address in the left-right direction in FIG. 1B is represented as SX, and the address in the vertical direction in FIG. 1B is represented as SY. In addition, the horizontal address in FIG. 1B of the memory macro 11 that outputs the read data signal is represented as MX, and the vertical address in FIG. 1B is represented as MY.
The selection logic circuit 13b-2 compares SX and SY indicating the address of the upper bit switch fabric 13 to which the selection logic circuit 13b-2 belongs with MX and MY indicating the address of the memory macro 11 that outputs the read data signal. One read data signal to be output is selected from read data signals input from two directions.
Specifically, when read data signals are input from two directions, a logic is constructed in the selection logic circuit 13b-2 so as to perform selection as shown in the following (1) to (6).
(1) If SX <MX-1, the input from the lower bit switch fabric 14 on the right side of the figure is selected.
(2) If SX> MX, select input from switch fabric 14 for lower bits on the left side of the figure
(3) If SX = MX and SY <MY, select the input from the lower bit switch fabric 14 on the left side of the figure.
(4) If SX = MX and SY> MY, select the input from the lower bit switch fabric 14 on the left side of the figure.
(5) If SX = MY and SY = MY, select input from memory macro 11
(6) If SX = MX-1, select input from lower bit switch fabric 14 on the right side of the figure
The above is an example of logic for selecting one read data signal to be output from read data signals input from two directions.
As described above, the upper bit switch fabric 13 transfers both the upper bit and the lower bit of the input / output data signal of the memory macro 11 in the horizontal direction in FIG. 1B. Only the upper bits of the input / output data signal of the memory macro 11 are transferred in the middle and up and down directions.
FIG. 7 is a block diagram showing the configuration of the lower-bit switch fabric 14 shown in FIG. 1B. As shown in FIG. 7, the lower bit switch fabric 14 includes an upper bit switch unit 14a that is a second upper bit switch unit and a lower bit switch unit 14b that is a second lower bit switch unit. I have.
In the lower bit switch fabric 14, when an input / output data signal of the memory macro 11 is input, an upper bit of the input / output data signal of the memory macro 11 is input to the upper bit switch unit 14a. Are input to the lower bit switch section 14b.
For example, in the lower bit switch fabric 14, when a 16-bit read data signal is input from the memory macro 11 as shown in FIG. 7, the upper 8 bits of the input read data signal are used as the upper bit switch unit. The lower 8 bits are input to the lower bit switch unit 14b. Further, as shown in FIG. 7, the 8-bit signal output from the upper bit switch unit 14a and the 8-bit signal output from the lower bit switch unit 14b are merged to generate a memory macro as a write data signal. 11 is output.
The upper bit switch unit 14 a controls the output destination of the upper bits of the input / output data signal of the memory macro 11 input to the lower bit switch fabric 14 by the selection logic circuit.
The lower bit switch unit 14b controls the output destination of the lower bits of the input / output data signal of the memory macro 11 input to the lower bit switch fabric 14 by the selection logic circuit. A selection logic circuit for controlling the output destination of the upper bit or the lower bit will be described later.
FIG. 8 is a block diagram showing a configuration of the lower-bit switch unit 14b in the lower-bit switch fabric 14 shown in FIG. As described above, the lower bit of the input / output data signal of the memory macro 11 input to the lower bit switch fabric 14 is input to the lower bit switch unit 14b.
As shown in FIG. 8, the lower-bit switch unit 14b shown in FIG. 7 includes a selector 14b-1 and a selection logic circuit 14b-2 connected to the selector 14b-1. The selector 14b-1 is provided for each signal input / output direction, and a selection logic circuit 14b-2 is connected to each selector 14b-1.
As shown in FIG. 8, the lower-bit switch unit 14b has inputs and outputs in a total of five directions. As shown in FIG. 7, in addition to the connection with the memory macro 11, the lower bit switch section 14b is connected with the lower bit switch fabric 14 and the lower bit column wiring 16 in the vertical direction in the figure. . Further, the lower bit switch section 14b is connected to the adjacent upper bit switch fabric 13 by the row wiring 17 in the left-right direction in the figure. Therefore, the lower-bit switch unit 14b includes five selectors 14b-1 and selection logic circuits 14b-2, which are the same as the number of signals in the input / output direction.
The selector 14b-1 outputs one signal selected by the selection logic circuit 14b-2 among the signals input from four directions other than the direction in which the selector 14b outputs a signal.
The selection logic circuit 14b-2 determines one signal to be output among signals input to the selector 14b-1 from four directions by a certain logic.
When the lower bits of the read data signal output from any memory macro 11 are input to the lower bit switch unit 14b from four directions, the selection logic circuit 14b-2 selects one read data signal to be output. An example of logic to be determined will be described.
The selection logic circuit 14b-2 stores the address on the chip of the lower-bit switch fabric 14 to which the selection logic circuit 14b-2 belongs. Here, the address in the left-right direction in FIG. 1B of the switch fabric 14 for lower bits is represented as SX, and the address in the up-down direction in the figure is represented as SY.
The selection logic circuit 14b-2 also recognizes the address on the chip of the memory macro 11 that outputs the read data signal. This is because the lower bit switch fabric 14 is supplied with the address signal output from the logic device 20 when instructing the output of the read data signal, and the address macro reads the data from the memory macro. This is because a macro address indicating an address on 11 chips is included.
Here, the horizontal address in FIG. 1B of the memory macro 11 that outputs the read data signal is represented as MX, and the vertical address in FIG. 1B is represented as MY. When the lower-bit switch fabric 14 to which it belongs is directly connected to the memory macro 11 that outputs the read data signal, MX = SX and MY = SY. Here, X is a subscript representing the left-right direction in FIG. 1B, and Y is a subscript representing the vertical direction in FIG. 1B. Further, the addresses MX, SX, MY, and SY in FIG. 1B are integers.
The selection logic circuit 14b-2 compares SX and SY indicating the address of the lower-bit switch fabric 14 to which the selection logic circuit 14b-2 belongs and MX and MY indicating the address of the memory macro 11 that outputs the read data signal. Based on the comparison result, one read data signal to be output is selected from the read data signals input from the four directions.
Actually, when read data signals are input from four directions, a logic is constructed in the selection logic circuit 14b-2 so as to perform selection as shown in the following (1) to (8).
(1) If SX <MX-1, the input from the upper bit switch fabric 13 on the right side of the figure is selected.
(2) If SX> MX, select input from switch fabric 13 for upper bits on the left side of the figure
(3) If SX = MX and SY <MY, the input from the lower bit switch fabric 14 in the upper part of the figure is selected.
(4) If SX = MX and SY> MY, the input from the lower-order bit switch fabric 14 is selected.
(5) If SX = MX and SY = MY, select input from memory macro 11
(6) If SX = MX-1 and SY <MY, the input from the lower bit switch fabric 14 in the upper part of the figure is selected.
(7) If SX = MX-1 and SY> MY, the input from the lower-order bit switch fabric 14 in the figure is selected.
(8) If SX = MX-1 and SY = MY, select the input from the upper bit switch fabric 13 on the right side of the figure.
The above is an example of logic for selecting one read data signal to be output from read data signals input from four directions.
FIG. 9 is a block diagram showing a configuration of the upper bit switch section 14a in the lower bit switch fabric 14 shown in FIG. In the upper bit switch section 14a, the upper bits of the input / output data signal of the memory macro 11 input to the lower bit switch fabric 14 are input as described above.
As shown in FIG. 9, the upper bit switch unit 14a shown in FIG. 7 includes a selector 14a-1 and a selection logic circuit 14a-2 connected to the selector 14a-1. The selector 14a-1 is provided in each signal input / output direction, and a selection logic circuit 14a-2 is connected to each selector 14a-1.
As shown in FIG. 9, the upper bit switch unit 14a has inputs and outputs in a total of three directions. As shown in FIG. 7, in addition to the connection with the memory macro 11, the upper bit switch unit 14a is connected to the upper bit switch fabric 13 adjacent in the left and right direction in the figure by the row wiring 17. Because. Therefore, the upper bit switch unit 14a includes the same three selectors 14a-1 and selection logic circuits 14a-2 as the number of signals in the input / output direction.
The selector 14a-1 outputs one signal selected by the selection logic circuit 14a-2 among the signals input from two directions other than the direction in which the signal is output.
The selection logic circuit 14a-2 determines one signal to be output from signals input to the selector 14a-1 from two directions by a certain logic.
Here, when the upper bit of the read data signal output from the arbitrary memory macro 11 is input to the upper bit switch unit 14a from two directions, the selection logic circuit 14a-2 selects one read data signal to be output. An example of logic to be determined will be described. In the description, the same notation as described in the case of determining one signal output from the selection logic circuit 14b-1 of the lower-bit switch unit 14b is used. That is, the left-right address in FIG. 1B of the lower-bit switch fabric 14 to which the selection logic circuit 14a-2 belongs is represented as SX, and the up-down address in FIG. 18 is represented as SY.
In addition, the horizontal address in FIG. 1B of the memory macro 11 that outputs the read data signal is represented as MX, and the vertical address in FIG. 1B is represented as MY.
The selection logic circuit 14a-2 compares SX and SY indicating the address of the lower bit switch fabric 14 to which it belongs and MX and MY indicating the address of the memory macro 11 that outputs the read data signal. From this comparison result, one read data signal to be output is selected from the read data signals input from two directions.
Specifically, when read data signals are input from two directions, a logic is constructed in the selection logic circuit 14a-2 so as to perform selection as shown in the following (1) to (6).
(1) If SX <MX-1, the input from the upper bit switch fabric 13 on the right side of the figure is selected.
(2) If SX> MX, select input from switch fabric 13 for upper bits on the left side of the figure
(3) If SX = MX and SY <MY, the input from the upper bit switch fabric 13 on the left side of the figure is selected.
(4) If SX = MX and SY> MY, the input from the upper bit switch fabric 13 on the left side of the figure is selected.
(5) If SX = MY and SY = MY, select input from memory macro 11
(6) If SX = MX-1, the input from the upper bit switch fabric 13 on the right side of the figure is selected.
The above is an example of logic for selecting one read data signal to be output from read data signals input from two directions.
As described above, the lower bit switch fabric 14 transfers both the upper bit and the lower bit of the input / output data signal of the memory macro 11 in the horizontal direction in FIG. 1B. On the other hand, in the vertical direction in FIG. 1B, the lower bit switch fabric 14 transfers only the lower bits of the input / output data signal of the memory macro 11.
In the upper bit switch fabric 13 and the lower bit switch fabric 14, the circuit for controlling the transfer direction of the address signal and the circuit for controlling the output direction of the command signal also operate in the same manner as the above-described switch unit. That is, the circuit for controlling the transfer direction of the address signal and the circuit for controlling the output direction of the command signal transfer only the upper bit or the lower bit of the signal in the vertical direction of FIG. 1B. Here, the address signal and the command signal may be output from the logic device 20 to the memory macro 11 of the semiconductor programmable device 10, and output from the memory macro 11 is not necessary. Therefore, in the upper bit switch fabric 13 and the lower bit switch fabric 14, the circuit that controls the transfer direction of the address signal and the circuit that controls the transfer direction of the command signal can only output the signal to the memory macro 11. Just do it.
In the above-described embodiment, the memory macro 11 is an SRAM memory macro having 1 k words and 16 bits. However, the memory macro 11 may have an arbitrary word and bit configuration.
In the present embodiment described above, the memory in the memory macro 11 is an SRAM. However, this may be a DRAM (Dynamic Random Access Memory). Since DRAM has a small circuit area, a larger capacity memory can be mounted. Moreover, it is good also as non-volatile memories, such as flash memory, MRAM (Magnetorescent Random Access Memory), and ReRAM (Resistance Random Access Memory). By using the non-volatile memory, it is possible to stop the power supply of the memory area that is not used temporarily and enter the power saving mode.
In the above-described embodiment, the case where the memory macro 11 is a 4 × 4 two-dimensional array has been described. However, the size of the two-dimensional array is not limited to the 4 × 4 two-dimensional array.
In the embodiment described above, the column wiring in the vertical direction in FIG. 1B is the column wiring 15 for upper bits or the column wiring 16 for lower bits in FIG. 1B. The same effect can be obtained by separating the upper bit wiring and the lower bit wiring.
In this case, the row wiring 17 is either the upper bit row wiring or the lower bit row wiring. The switch fabric on the upper bit row wiring includes a third upper bit switch unit and a third lower bit switch unit.
The third upper bit switch unit transfers upper bits to the switch fabric adjacent on the column wiring, the switch fabric adjacent on the upper bit row wiring, and the directly connected circuit block.
The third lower bit switch unit transfers the lower bits to the switch fabric adjacent on the column wiring and the directly connected circuit block.
The switch fabric on the lower bit row wiring includes a fourth upper bit switch unit and a fourth lower bit switch unit.
The fourth lower bit switch unit transfers the lower bits to the switch fabric adjacent on the column wiring, the switch fabric adjacent on the lower bit row wiring, and the directly connected circuit block.
The fourth upper bit switch unit transfers the upper bits to the switch fabric adjacent on the column wiring and the directly connected circuit block.
In the above-described embodiment, the input / output data signal has been described as being divided into half of the upper bits and the lower bits. However, the signal division ratio is not limited to half, and other ratios are possible. You may divide by.
In the above-described embodiment, the case where the switch fabric is fixed to the upper bit or the lower bit as in the upper bit switch fabric 13 and the lower bit switch fabric 14 has been described. However, the switch fabric is used for the upper bit. Alternatively, it is possible not to fix for the lower bits.
FIG. 10 is a block diagram illustrating a configuration of a switch fabric that is an example of another switch fabric according to the present embodiment and is not fixed for upper bits or lower bits.
The switch fabric 33 shown in FIG. 10 includes a switch unit 33a for no column wiring that receives only signals from the row wiring, a switch unit 33b for column wiring that receives signals from the row wiring and the column wiring, and a selector 33c. And.
The switch fabric 33 shown in FIG. 10 includes the selector 33c, so that the upper bit wiring and the lower bit wiring can be switched in the switch fabric 33. Therefore, it is possible to transfer in the vertical direction in the figure while switching between the upper bit and the lower bit. That is, the switch fabric 33 can operate as both a high-order bit switch fabric and a low-order bit switch fabric.
As described above, in this embodiment, the upper bits of the input / output data signal of the memory macro 11 are transferred by the upper bit column wiring 15 and the lower bits are transferred by the lower bit column wiring 16. Thereby, the number of bits transferred by each wiring is reduced, and the area of the wiring can be reduced. As a result, a necessary and sufficient number of wires can be secured on the chip, so that it is not necessary to add a separate wiring layer, and an increase in manufacturing cost due to the addition of the wiring layer can be avoided.
In addition, since the upper bit or lower bit is not transferred in the column direction in the upper bit switch fabric 13 and the lower bit switch fabric 14, the number of selectors for outputting a signal in the column direction can be reduced. Thereby, the areas of the upper bit switch fabric 13 and the lower bit switch fabric 14 can be reduced.
[Second Embodiment]
Next, a second embodiment of the present invention will be described. In the first embodiment, the semiconductor integrated circuit device in which the semiconductor programmable device and the logic device of the present invention are integrated on the same chip has been described. In this embodiment, the semiconductor programmable device and the logic device of the present invention are integrated on different chips, and the semiconductor integrated circuit device is configured by stacking these chips.
FIG. 11 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the second embodiment including the semiconductor programmable device of the present invention. In the semiconductor integrated circuit device of this embodiment, the semiconductor programmable device 50 and the logic device 60 are stacked.
In the semiconductor integrated circuit device described in the first embodiment, as shown in FIG. 1B, the semiconductor programmable device 10 and the logic device 20 are integrated on the same chip. Was arranged around.
On the other hand, in the present embodiment, as shown in FIG. 11, the semiconductor programmable device 50 and the logic device 60 are integrated on different chips, and these chips are stacked. In addition, the memory input / output unit 52 can be arranged for each memory macro 51.
In this case, the transfer of input / output data signals between the semiconductor programmable device 50 and the logic device 60 is performed via the memory input / output unit 52 and the logic input / output unit 62 provided for each memory macro 51. That is, since the memory input / output unit 52 is not shared between the plurality of memory macros 51, the memory input / output unit 52 is not shared between the semiconductor programmable device 50 and the logic device 60 as compared with the semiconductor integrated circuit device described in the first embodiment. It is possible to increase the transfer amount of the input / output data signal.
[Third Embodiment]
Next, a third embodiment of the present invention will be described. In the first embodiment and the second embodiment, the case where the semiconductor programmable device of the present invention is configured by a memory macro has been described. In the third embodiment, a case where the semiconductor programmable device of the present invention is configured by a processor will be described. That is, in this embodiment, the processor is a circuit block.
FIG. 12 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the third embodiment including the semiconductor programmable device 80 of the present invention. The semiconductor integrated circuit device shown in FIG. 12 differs from the semiconductor integrated circuit device shown in FIG. 1B in that the memory macro 11 of the semiconductor programmable device 10 shown in FIG. A memory device 90 including a memory macro 91 is arranged around the semiconductor programmable device 80 and connected to each other via a processor input / output unit 82. The processor 81 is, for example, a 16-bit RISC (Reduced Instruction Set Computer) processor.
Even if the circuit block is changed from the memory to the processor as in the present embodiment, the upper bits of the input / output data signal of the processor 81 are transferred by the upper bit column wiring 85 as described in the first embodiment. The lower bits are transferred by the lower bit column wiring 86. Thereby, the number of bits transferred by each wiring is reduced, and the area of the wiring can be reduced. As a result, a necessary and sufficient number of wires can be secured on the chip, so that it is not necessary to add a separate wiring layer, and an increase in manufacturing cost due to the addition of the wiring layer can be avoided.
Further, since the upper bits or the lower bits are not transferred in the column direction in the upper bit switch fabric 83 and the lower bit switch fabric 84, the number of selectors for outputting a signal in the column direction can be reduced. As a result, the areas of the upper bit switch fabric 83 and the lower bit switch fabric 84 can be reduced.
[Fourth Embodiment]
A semiconductor programmable device according to a fourth embodiment of the present invention includes a plurality of switch fabrics that are provided at intersections of a plurality of row wirings and a plurality of column wirings laid on a chip and transfer input data signals. A semiconductor programmable device directly connected to each of the plurality of switch fabrics and having a plurality of circuit blocks for inputting / outputting data signals via the plurality of switch fabrics, wherein the column wiring is input / output by the circuit blocks The upper bit column wiring for transferring the upper bits or the lower bit column wiring for transferring the lower bits of the data signal divided into the upper bits and the lower bits. The switch fabric on the wiring is the adjacent switch fabric on the row wiring, and the column arrangement for the upper bits. First upper bit switch unit for transferring upper bits to adjacent switch fabric and directly connected circuit block, and lower bit to adjacent switch fabric and directly connected circuit block on row wiring A switch fabric on the lower bit column wiring, a switch fabric adjacent on the row wiring, a switch fabric adjacent on the lower bit column wiring, and a direct connection Second lower bit switch unit for transferring lower bits to the connected circuit block, switch fabric adjacent on the row wiring, and second upper bit switch unit for transferring upper bits to the directly connected circuit block And have.
[Fifth Embodiment]
A signal transfer method in a semiconductor programmable device according to the fifth embodiment of the present invention is a plurality of methods for transferring input data signals provided at intersections of a plurality of row wirings and a plurality of column wirings laid on a chip. And a plurality of circuit blocks that are directly connected to each of the plurality of switch fabrics and perform input / output of data signals via the plurality of switch fabrics, and a column wiring method The data signal input / output in the circuit block is divided into upper bits and lower bits, the upper bit column wiring for transferring the upper bits, or the lower bit column wiring for transferring the lower bits. Either, and the switch fabric on the column wiring for the upper bits is adjacent on the row wiring. Switch fabric, switch fabric adjacent on upper bit column wiring, and processing for transferring upper bit to directly connected circuit block, and switch fabric on upper bit column wiring are adjacent on row wiring , And a process of transferring lower bits to a directly connected circuit block, and a switch fabric on the lower bit column wiring is adjacent on the row wiring, a switch fabric adjacent on the lower bit column wiring, and A process of transferring lower bits to a directly connected circuit block, and a process of transferring upper bits to a switch fabric adjacent on the row wiring and a directly connected circuit block by the switch fabric on the column wiring for the lower bits. Have
The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the invention described in the claims, and it is also included within the scope of the present invention. Not too long.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-236782 for which it applied on September 16, 2008, and takes in those the indications of all here.

The present invention can be applied to a semiconductor programmable device in which a plurality of circuit blocks including processors and memories are integrated.

Claims

A plurality of row wirings and a plurality of column wirings arranged on a chip; a plurality of switch fabrics provided at intersections of the row wirings and the column wirings; and transferring the input data signal; and the plurality of switch fabrics A plurality of circuit blocks that are directly connected to each other and that perform input and output of the data signals through the plurality of switch fabrics,
Either the row wiring or the column wiring is configured to transfer only one data signal group of the first data signal group and the second data signal group constituting the data signal. ,
The other of the column wiring and the row wiring is configured to transfer both the first data signal group and the second data signal group. Semiconductor programmable device.
The semiconductor programmable device according to claim 1,
The column wiring is configured to transfer only one data signal group of the first data signal group and the second data signal group,
The row wiring is configured to transfer both the first data signal group and the second data signal group. A semiconductor programmable device.
The semiconductor programmable device according to claim 2,
The column wiring is composed of upper bit column wiring for transferring upper bits as the first data signal group and lower bit column wiring for transferring lower bits as the second data signal group,
The switch fabric on the upper bit column wiring is:
The switch fabric adjacent on the row wiring, the switch fabric adjacent on the upper bit column wiring, and a first upper bit switch unit for transferring the upper bits to the directly connected circuit block;
The switch fabric adjacent on the row wiring, and a first lower bit switch unit for transferring the lower bit to the directly connected circuit block,
The switch fabric on the lower bit column wiring is:
The switch fabric adjacent on the row wiring, the switch fabric adjacent on the lower bit column wiring, and a second lower bit switch unit for transferring the lower bits to the directly connected circuit block;
A semiconductor programmable device comprising: the switch fabric adjacent on the row wiring; and a second upper bit switch unit that transfers the upper bit to the directly connected circuit block.
The semiconductor programmable device according to claim 3,
The switch fabric on the upper bit column wiring is:
When the circuit block that outputs the data signal is located on the same upper bit column wiring as the switch fabric,
The upper bits are input from the switch fabric adjacent to the side where the circuit block is located on the same column wiring as the switch fabric,
The lower bit is input from a switch fabric adjacent to the left side of the switch fabric on the same row wiring as the switch fabric,
When the circuit block that outputs the data signal is located on the same upper bit column wiring as the switch fabric and on the same row wiring as the switch fabric, the circuit block is connected to the switch fabric. Data signal from the specified circuit block,
When the circuit block for outputting the data signal is not located on the same upper bit column wiring as the switch fabric and is not located on the upper bit column wiring adjacent to the switch fabric, The data signal from the switch fabric adjacent on the side where the circuit block is located on the same row wiring as the switch fabric is input,
When the circuit block that outputs the data signal is located on the upper bit column wiring adjacent to the switch fabric,
The upper bits are input from the switch fabric adjacent to the side where the circuit block is located on the same column wiring as the switch fabric,
The lower order bit is input from a switch fabric adjacent to the right side of the switch fabric on the same row wiring as the switch fabric.
The semiconductor programmable device according to claim 3,
A semiconductor programmable device in which the upper bit column wiring and the lower bit column wiring are alternately laid.
The semiconductor programmable device according to claim 3,
The switch fabric is a semiconductor programmable device that transfers the upper bit and the lower bit while switching to the adjacent switch fabric on the column wiring.
The semiconductor programmable device according to claim 1,
The row wiring is configured to transfer only one of the first data signal group and the second data signal group,
The column wiring is configured to transfer both the first data signal group and the second data signal group. A semiconductor programmable device.
The semiconductor programmable device according to claim 7,
The row wiring is composed of upper bit row wiring for transferring upper bits as the first data signal group and lower bit row wiring for transferring lower bits as the second data signal group,
The switch fabric on the upper bit row wiring is:
The switch fabric adjacent on the column wiring, the switch fabric adjacent on the upper bit row wiring, and a third upper bit switch unit for transferring the upper bits to the directly connected circuit block;
The switch fabric adjacent on the column wiring, and a third lower bit switch unit for transferring the lower bit to the directly connected circuit block,
The switch fabric on the lower bit row wiring is:
The switch fabric adjacent on the column wiring, the switch fabric adjacent on the lower bit row wiring, and a fourth lower bit switch unit for transferring the lower bits to the directly connected circuit block;
A semiconductor programmable device comprising: the switch fabric adjacent on the column wiring; and a fourth upper bit switch unit for transferring the upper bit to the directly connected circuit block.
The semiconductor programmable device according to claim 8,
A semiconductor programmable device in which the upper bit row wiring and the lower bit row wiring are alternately laid.
The semiconductor programmable device according to claim 8,
The switch fabric is a semiconductor programmable device that transfers the upper bit and the lower bit while switching to the adjacent switch fabric on the row wiring.
The semiconductor programmable device according to claim 1,
A semiconductor programmable device in which the circuit block is a memory macro.
The semiconductor programmable device according to claim 1,
A semiconductor programmable device in which the circuit block is a processor.
A plurality of row wirings and a plurality of column wirings arranged on a chip; a plurality of switch fabrics provided at intersections of the row wirings and the column wirings; and transferring the input data signal; and the plurality of switch fabrics A signal transfer method in a semiconductor programmable device having a plurality of circuit blocks that are directly connected to each of the plurality of circuit blocks and that input and output the data signal through the plurality of switch fabrics,
Either the row wiring or the column wiring transfers only one data signal group of the first data signal group and the second data signal group constituting the data signal,
The other of the column wiring and the row wiring transfers both the first data signal group and the second data signal group. A signal transfer method in a semiconductor programmable device.
The signal transfer method in the semiconductor programmable device according to claim 13,
The column wiring transfers only one data signal group of the first data signal group and the second data signal group,
The row wiring is a signal transfer method in a semiconductor programmable device that transfers both the first data signal group and the second data signal group.
The signal transfer method in the semiconductor programmable device according to claim 14,
The upper bit column wiring constituting the column wiring transfers higher bits as the first data signal group, and the lower bit column wiring constituting the column wiring is transferred as the second data signal group. Transfer the lower bits,
The switch fabric on the upper bit column wiring is:
Transferring the upper bits to the switch fabric adjacent on the row wiring, the switch fabric adjacent on the column wiring for upper bits, and the directly connected circuit block;
Transferring the lower bit to the switch fabric adjacent on the row wiring and the directly connected circuit block;
The switch fabric on the lower bit column wiring is:
Transferring the lower bits to the switch fabric adjacent on the row wiring, the switch fabric adjacent on the lower bit column wiring, and the directly connected circuit block;
A signal transfer method in a semiconductor programmable device that transfers the upper bit to the switch fabric adjacent on the row wiring and the directly connected circuit block.
The signal transfer method in the semiconductor programmable device according to claim 15,
The switch fabric on the upper bit column wiring is:
When the circuit block that outputs the data signal is located on the same upper bit column wiring as the switch fabric,
The upper bits are input from the switch fabric adjacent to the side where the circuit block is located on the same column wiring as the switch fabric,
The lower bit is input from a switch fabric adjacent to the left side of the switch fabric on the same row wiring as the switch fabric,
When the circuit block that outputs the data signal is located on the same upper bit column wiring as the switch fabric and on the same row wiring as the switch fabric, the circuit block is connected to the switch fabric. Data signal from the specified circuit block,
When the circuit block for outputting the data signal is not located on the same upper bit column wiring as the switch fabric and is not located on the upper bit column wiring adjacent to the switch fabric, The data signal from the switch fabric adjacent on the side where the circuit block is located on the same row wiring as the switch fabric is input,
When the circuit block that outputs the data signal is located on the upper bit column wiring adjacent to the switch fabric,
The upper bits are input from the switch fabric adjacent to the side where the circuit block is located on the same column wiring as the switch fabric,
The lower bit is input from a switch fabric adjacent to the right side of the switch fabric on the same row wiring as the switch fabric. A signal transfer method in a semiconductor programmable device.
The signal transfer method in the semiconductor programmable device according to claim 15,
A signal transfer method in a semiconductor programmable device in which the upper bit column wiring and the lower bit column wiring laid alternately transfer the upper bit or the lower bit.
The signal transfer method in the semiconductor programmable device according to claim 15,
The signal transfer method in the semiconductor programmable device, wherein the switch fabric transfers the upper bit and the lower bit while switching to the adjacent switch fabric on the column wiring.
The signal transfer method in the semiconductor programmable device according to claim 13,
The row wiring transfers only one data signal group of the first data signal group and the second data signal group,
The column wiring is a signal transfer method in a semiconductor programmable device that transfers both the first data signal group and the second data signal group.
In the signal transfer method in the semiconductor programmable device according to claim 19,
The upper bit row wiring constituting the row wiring transfers upper bits as the first data signal group, and the lower bit row wiring constituting the row wiring is transferred as the second data signal group. Transfer the lower bits,
The switch fabric on the upper bit row wiring is:
Transferring the upper bit to the switch fabric adjacent on the column wiring, the switch fabric adjacent on the upper bit row wiring, and the directly connected circuit block;
Transferring the lower bit to the switch fabric adjacent on the column wiring and the directly connected circuit block;
The switch fabric on the lower bit row wiring is:
Transferring the lower bits to the switch fabric adjacent on the column wiring, the switch fabric adjacent on the lower bit row wiring, and the directly connected circuit block;
A signal transfer method in a semiconductor programmable device, wherein the upper bits are transferred to the switch fabric adjacent on the column wiring and the directly connected circuit block.
The signal transfer method in the semiconductor programmable device according to claim 20,
A signal transfer method in a semiconductor programmable device in which the upper bit row wiring and the lower bit row wiring laid alternately transfer the upper bit or the lower bit.
The signal transfer method in the semiconductor programmable device according to claim 20,
The signal transfer method in a semiconductor programmable device, wherein the switch fabric transfers the upper bit and the lower bit while switching to an adjacent switch fabric on the row wiring.
The signal transfer method in the semiconductor programmable device according to claim 13,
A signal transfer method in a semiconductor programmable device, wherein the circuit block is a memory macro and a data signal inputted / outputted by the memory macro is transferred.
The signal transfer method in the semiconductor programmable device according to claim 13,
A signal transfer method in a semiconductor programmable device, wherein the circuit block is a processor and transfers a data signal input / output by the processor.