JP4418655B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a multi-port semiconductor memory device that is particularly suitable for use in video signal processing.

  In the conventional semiconductor memory device, for example, as described in Patent Document 1, each port has a decoder, a bit line, and a sense amplifier circuit, and an arbitrary address can be independently accessed between the ports. .

  FIG. 6 shows a configuration diagram of a memory having a 2-port configuration as such a conventional multi-port configuration. In the figure, 1 is an address signal and control signal of port 1, 2 is an address signal and control signal of port 2, and 6 and 11 are memory cell arrays divided into two.

  3 is a port 1 decoder, 23 is a port 2 decoder, 4 is a port 1 memory cell array 6 decoder, 24 is a port 2 memory cell array 6 decoder, 28 is a memory cell array 6 memory cell, and 9 is a port port. 1 is a sense amplifier circuit of the memory cell array 6, 29 is a sense amplifier circuit of the memory cell array 6 of the port 2, 7 is a precharge circuit of the port 1, and 27 is a precharge circuit of the port 2.

  Similarly, the memory cell array 11 includes a port 5 decoder 5 and a port 2 decoder 25. Although not shown, the memory cell array 11 includes a plurality of memory cells as well as the memory cell array 6 and has a sense amplifier circuit and a precharge circuit for each port.

  Further, 12 is a selector, which receives the output Dr11 of the memory cell array 6 and the output Dr21 of the memory cell array 11, and selects either one of them based on the signal from the decoder 3 and outputs it as read data 30 of the port 1 To do. Reference numeral 13 denotes a selector which inputs the output Dr12 of the memory cell array 6 and the output Dr22 of the memory cell array 11, selects one of the outputs based on a signal from the decoder 3, and outputs it as read data 32 of the port 2. Reference numeral 26 denotes port 1 write data which is input to the memory cell array 6 and the memory cell array 11 via the signal line Dw1. Reference numeral 28 denotes port 2 write data which is input to the memory cell array 6 and the memory cell array 11 via the signal line Dw2.

  7A is a configuration diagram of the memory cell 28, FIG. 7B is a configuration diagram of the precharge circuit 7 (and 27), and FIG. 7C is a configuration diagram of the sense amplifier circuit 9 (and 29). The memory cell 28 in FIG. 7A is connected to the bit lines b11 and b12 of the port 1 and the bit lines b21 and b22 of the port 2 by a pair of transistors 601 and 602, respectively, for each port. The decoder 104 is connected to word lines w1 and w2 for each port. The precharge circuit of FIG. 7B precharges each bit line (b11, b12), (b21, b22) at the time of access, and three P's are supplied by a control signal c1 input from the decoder 4. The type transistor 604 is turned on and the bit lines b1 and b2 are precharged. The sense amplifier circuit 9 shown in FIG. 7C sends write data Dw to the bit lines b1 and b2 by a control signal c2 at the time of writing, and a bit by the sense amplifier SA exclusively at the time of reading from the control signal c2 at the time of writing. The potential difference between the lines b1 and b2 is amplified and output as read data Dr.

  Such a two-port semiconductor memory device has a decoder, a bit line, a precharge circuit, and a sense amplifier circuit for each port, and can perform a write or read operation independently.

  Also, in recent years, for high-speed access, the memory is physically divided into a plurality of memory blocks, and then, for example, each memory block is accessed with an upper address, and the data of the accessed memory block is selected with a lower address. However, in the case of the multi-port type, a decoder or the like is provided for each port as described above.

Japanese Patent Laid-Open No. 7-182852

  However, the semiconductor memory device as described above has a decoder or the like for each port in order to enable independent access for each port. For this reason, there exists a subject that a circuit area increases.

  An object of the present invention is to reduce the size of a multi-port semiconductor memory device by sharing an address decoder, a precharge circuit, a sense amplifier circuit, and the like between ports.

  In order to achieve the above object, the present invention pays particular attention to a multi-port semiconductor memory device used for video signal processing. In this video signal processing, line delay, field delay, and frame delay data are created. In this case, access from each port to the memory is not completely independent, and the access addresses of each port are separated. There is a feature.

  The present invention pays attention to these characteristic points, divides the memory cell array into a plurality of memory cell blocks, and performs simultaneous access to different memory blocks at the time of simultaneous access from each port. In this case, only one address decoder, precharge circuit, sense amplifier circuit, etc. can be arranged.

In other words, the semiconductor memory device according to the first aspect of the present invention is a semiconductor memory device having a plurality of ports, each port being capable of accessing a memory cell at a different address for each port, and having a plurality of memory cells. A single-port memory block, and a selection means for inputting an address signal and a control signal for each port, and selecting and outputting an address signal and a control signal for different ports to the plurality of single-port memory blocks And each of the single port memory blocks makes an access request for each different port and reads data from each different port from each memory block.

  According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the selection unit inputs an address signal and a control signal for each port, and from the address signal and the control signal for each port, A control signal generation circuit is provided that generates a control signal for controlling which address signal and control signal of any port is selected and output to which memory block.

  According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, the selection unit includes a plurality of first selectors corresponding to the plurality of memory blocks, and the plurality of first selectors is , Each of which receives a control signal of the control signal generation circuit, and based on the control signal, selects an address signal and a control signal for any one of the port-specific address signals and control signals, An address signal and a control signal of one port selected by each first selector are an address signal and a control signal having different ports.

  According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the selection unit includes a plurality of second selectors corresponding to the plurality of memory blocks, and the plurality of second selectors is The external write data for each port and the control signal for the control signal generation circuit are input, and the write data for any one of the write data for each port based on the control signal. And the operation of writing the write data of different ports to each of the plurality of memory blocks is performed.

  According to a fifth aspect of the present invention, in the semiconductor memory device according to the first or fourth aspect, each of the plurality of memory blocks has a precharge circuit, a sense amplifier circuit, and an address decoder common to the respective ports. Features.

  According to a sixth aspect of the present invention, in the semiconductor memory device according to the second aspect, the control signal generation circuit inputs an address signal of each port and a most significant bit of each address included in the control signal. Based on the most significant bit, a control signal for selecting an address signal and a control signal of which port is selected for the plurality of memory blocks is generated.

  According to a seventh aspect of the present invention, in the semiconductor memory device according to the second aspect, the control signal generation circuit inputs at least the upper 2 bits of each address included in the address signal and the control signal of each port, and Based on each upper 2 bits, a control signal for selecting an address signal and a control signal of which port is selected for the plurality of memory blocks is generated.

  According to an eighth aspect of the present invention, in the semiconductor memory device according to the second aspect, the control signal generation circuit inputs an address signal of each port and a least significant bit of each address included in the control signal, Based on the least significant bit, a control signal for selecting an address signal and a control signal of which port is selected for the plurality of memory blocks is generated.

  According to a ninth aspect of the present invention, in the semiconductor memory device according to the second aspect, the control signal generation circuit inputs a predetermined upper bit and lower bit of each address included in the address signal and control signal of each port. Then, a control signal for selecting which port address signal and control signal is selected for the plurality of memory blocks is generated based on each of the predetermined upper bits and lower bits.

  According to a tenth aspect of the present invention, in the semiconductor memory device according to the second aspect, the control signal generation circuit inputs at least a predetermined 1 bit of each address included in the address signal and the control signal of each port, A control signal for selecting an address signal and a control signal of which port is selected for the plurality of memory blocks is generated based on each 1 bit.

  As described above, in the semiconductor memory device according to any one of claims 1 to 10, the selecting unit assigns the address signal and the control signal of each port to each memory block so that accesses from a plurality of ports do not overlap in the same memory block. Each memory block has only one address decoder, one sense amplifier circuit, and the like.

  As described above, according to the semiconductor memory device of the present invention, there is no need to have an address decoder, a sense amplifier circuit, a bit line, etc. for each port even in a multi-port semiconductor memory device. There is an effect that significant reduction is possible.

  FIG. 1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention, and exemplifies a 2-port memory configuration.

  In FIG. 1, 101 is an address signal and control signal for port 1 input from the outside, and 102 is an address signal and control signal for port 2 input from the outside. A memory cell array (memory block) 106 includes a plurality of memory cells 110. Reference numeral 108 denotes another memory cell array (memory block) having the same configuration as the memory cell array 106. A is a selection circuit (selection means) for inputting the address signals and control signals 101 and 102 of the ports 1 and 2, and based on the address signals and control signals 101 and 102 of the ports 1 and 2, An access request for one port (for example, 1) is made to either one of the memory cell arrays 106 or 108 (for example, the memory cell array 106), and at the same time, the other port to the other memory cell array (for example, 108). (2), for example, the data of the ports 1 and 2 are read from the different memory cell arrays 106 and 108, and the write data from the ports 1 and 2 are written to the different memory cell arrays 106 and 108, respectively. To. Details thereof will be described later.

  Reference numeral 103 denotes a decoder (control signal generation) that receives the address signals of the ports 1 and 2 and a part of the control signals 101 and 102 (for example, the most significant bit of the address signal as will be described later) and generates the control signal cnt. Circuit). Reference numerals 104 and 105 denote decoders (address decoders) for inputting and decoding a part of the address signals of the ports 1 and 2 and part of the control signals 101 and 102 (for example, all bits except the most significant bit of the address signal). A precharge circuit 107 precharges the bit lines b 1 and b 2 and is provided in the memory cell array 106. Reference numeral 109 denotes a sense amplifier circuit that amplifies the signals of the bit lines b 1 and b 2 and is provided in the memory cell array 106. Reference numeral 110 denotes a memory cell for storing data, and a plurality of memory cells 110 are provided in the memory cell array 106. Since the internal configuration of the memory cell array 108 is the same as that of the memory cell array 106, its illustration and description are omitted.

  In FIG. 1, reference numeral 114 inputs the address signals of both the ports 1 and 2 and a part of the control signals 101 and 102 (for example, all bits except the most significant bit of the address signal), and either one of them is input. The first selector is selected based on the control signal cnt from the decoder 103 and output to the decoder 104 for the one memory cell array 106. 116 is also a first selector, which receives the address signals of both the ports 1 and 2 and a part of the control signals 101 and 102, and selects one of them based on the control signal cnt from the decoder 103. To the decoder 105 for the other memory cell array 108.

  Further, 115 receives external write data 120 of port 1 and external write data 122 of port 2, selects one of the write data by the control signal cnt from the decoder 103, A second selector that outputs to the sense amplifier circuit 109 via the line Dw1. Reference numeral 117 denotes a second selector which inputs external port 1 write data 120 and external port 2 write data 122, and outputs one of the write data to the control signal cnt from the decoder 103. And output to the memory cell array 108 via the signal line Dw2.

  A third selector 118 receives data from the two memory cell arrays 106 and 108 via the signal lines Dr1 and Dr2, and selects one of the data by the control signal cnt from the decoder 103. Thus, the data is output to the outside as read data 121 of port 1. Reference numeral 119 denotes a third selector, which inputs data from the two memory cell arrays 106 and 108 via the signal lines Dr1 and Dr2, and receives one of the data according to the control signal cnt from the decoder 103. Select and output to the outside as read data 123 of port 2.

  The precharge circuit 107 and the sense amplifier circuit 109 have an internal configuration shown in FIGS. These circuits have the same configuration as that of FIG. 7 showing the conventional example, but as shown in comparison with the semiconductor memory device of FIG. 6 showing the conventional example, even if two ports 1 and 2 are provided, one memory cell array Only one of each is arranged for 106 and is shared between both ports 1 and 2. As a result of this sharing, each memory cell 110 in the memory cell array 106 has a pair of latch circuits 203 shared by both ports 1 and 2 via a pair of transistors 201 and 202, as shown in FIG. Connected to bit lines b1 and b2. The gates of the pair of transistors 201 and 202 are connected to a word line W1 shared by both ports 1 and 2.

  Next, the operation will be described. In the present embodiment, the most significant bit is used as part of the 8-bit address signal of each of the address signals of the ports 1 and 2 and the control signals 101 and 102, and one of the memory cell arrays 106 and 108 is connected to the most significant bit. An example will be described in which the memory cell array 106 is selected when the most significant bit is 0 and the memory cell array 108 is selected when the most significant bit is 1.

  First, in the write operation, the address signals and control signals 101 and 102 of the ports 1 and 2 are input from the outside. Among these, the control signals are a write enable signal and a clock signal. Of the address signal and control signal 101 of port 1, the most significant bit of the address signal and the control signal are input to the decoder 103. When the most significant bit of the input address signal is 0, the first selector 114 selects the address signal and control signal of the lower 7 bits of the address signal and control signal 101 by the control signal cnt of the decoder 103, and Output to the decoder 104. The decoder 104 decodes the address signal and drives the word line w1. As shown in FIG. 2A, the word line w1 is connected to the memory cell 110, and turns on the transistors 201 and 202 of the memory cell 110.

  On the other hand, the write data 120 of the port 1 is selected by the second selector 115 by the control signal cnt of the decoder 103, and is output to the sense amplifier circuit 109 via the signal line Dw1. As shown in FIG. 2 (c), when the control signal c2 from the decoder 104 is 1, the sense amplifier circuit 109 transmits the write data 120 of the port 1 of the signal line Dw1 through the inverter and the buffer. The positive and negative logic signals are output to the bit lines b1 and b2, respectively. As a result, the write data 120 of the port 1 is written and held in the latch circuit 203 via the transistors 201 and 202 shown in FIG. A write operation is performed by such an operation.

  Contrary to the above, when the most significant bit of the input address signal among the address signal and control signal 101 of port 1 is 1, the first selector 116 receives the control signal cnt of the decoder 103, The address signal and control signal 101 are selected, and the lower 7-bit address signal and control signal are output to the decoder 105. Further, the write data 120 of the port 1 is selected by the second selector 117 by the control signal cnt of the decoder 103 and output to the memory cell array 108, and the write operation of the write data 120 of the port 1 is performed as described above. Is done.

  Such an operation is the same for the port 2, and the address signal and control signal 102 of the port 2 indicate that the most significant bit of the address signal is 0 or 1, and the lower 7 bits of the address signal are the first selector. The port 2 write data 122 is selected by the second selector 115 or 117 and written to the memory cell array 106 or 108.

  Next, the reading operation will be described. Of the address signal and control signal 101 of port 1, the most significant bit of the address signal and the control signal are input to the decoder 103. When the most significant bit of the input address signal is 0, the first selector 114 outputs the address signal and the lower 7 bits of the address signal out of the control signal 101 to the decoder 104 according to the control signal cnt of the decoder 103. To do. The decoder 104 decodes the address signal and drives the word line w1. When the word line w1 is driven, the transistors 201 and 202 of the memory cell 110 are turned on as shown in FIG.

  The bit lines b1 and b2 are precharged based on the control signal c1 from the decoder 104 by the precharge circuit 107 including the transistor 204 shown in FIG. As described above, when the transistors 201 and 202 in FIG. 2A are turned on, a potential difference is generated between the bit lines b1 and b2 depending on the data of the latch circuit 203. This potential difference is amplified by the sense amplifier SA in FIG. 2C in the sense amplifier circuit 109, and is output as read data to the third selector 118 via the signal line Dr1. The third selector 118 selects the read data of the signal line Dr1 according to the control signal cnt from the decoder 103, and outputs it to the outside as the read data 121 of the port 1.

  On the other hand, when the most significant bit of the input address signal of the port 1 is 1, the first selector 116 uses the control signal cnt of the decoder 103 and the lower 7 of the address signal out of the address signal and the control signal 101. The bits are output to the decoder 105. The decoder 105 decodes the address signal, outputs it to the memory cell array 108, and outputs it to the third selector 118 via the signal line Dr2 as described above. The third selector 118 selects the data of the signal line Dr2 according to the control signal cnt from the decoder 103, and outputs it as read data 121 of the port 1 to the outside.

  For port 2 as well, the memory cell array 106 or 108 is operated by the most significant bit of the address signal, the read data is selected by the third selector 119, and the read data 123 of port 2 is sent to the outside. Output. A read operation is performed by such an operation.

  In the write operation and the read operation, as shown in FIG. 3A, when creating field delay data in video signal processing, the data of the port 1 is the field 1 area at a certain arbitrary time. If the data of port 2 is an area of field 2, if the memory capacity is set to two fields, the highest address of the address signals of port 1 and port 2 and the address signals of control signals 101 and 102 By assigning and controlling so that the values of are different from each other, it becomes possible to operate the memory cell arrays 106 and 108 in parallel for access to the port 1 and the port 2, respectively. As a result, it is possible to operate in parallel without providing an address decoder and a sense amplifier circuit for each port as in the prior art, and the circuit area can be reduced.

  Further, for example, when the data of one field of port 1 is less than one field of the memory capacity, the data of field 2 of port 1 is written in the field 1 area. After writing, it is possible to operate in the same manner as described above by correcting the address so that it comes to the beginning of the next field as in the address correction 301 and 302 shown in FIG.

  FIG. 3B shows another example of address assignment. In FIG. 2B, the memory is divided into four memory blocks, and one field of data is assigned to each memory block. In this case, the allocation to the four memory blocks is performed using the upper 2 bits of the address signal of each port and the address signals of the control signals 101 and 102. In this configuration, when operating as a 2-port memory, when generating 2-field delay data, if field 1 data is assigned to port 1 and field 3 data is assigned to port 2, each port accesses one memory block to each other. Only done away. As a result, even if the port 1 and the port 2 are asynchronous, the memory block can be operated in parallel as described above as long as it does not exceed the area of one field between them. It is possible to share an amplifier circuit or the like.

  Further, if one memory block is set to 1/2 field, a delay of 1 field can be generated within a range in which each port does not exceed a 1/2 field area.

  FIG. 4A shows an example applied when the memory capacity of a line memory or the like is small. In a line memory or the like, the allocation of FIGS. 3A and 3B subdivides the size of one memory block, resulting in poor memory area efficiency. For this reason, as shown in FIG. 4A, the memory block is switched using the least significant bit. As a result, the memory cell array 106 and the memory cell array 108 can be switched between the even address and the odd address, and the port 1 and the port 2 can be switched to odd, even, even, and odd, respectively. Can be operated without being subdivided.

  Further, FIG. 4B shows an example in which the memory block is divided into four, and the four memory blocks are selected by the most significant bit and the least significant bit of the address signal. As a result, asynchronous data cannot be handled in FIG. 4A, but since the memory block is selected by the most significant bit in FIG. 4B, port 1 and port 2 are accessed by the same memory block. Can be assigned so that they do not overlap.

  FIG. 5 is a diagram illustrating address allocation when the present invention is applied to DCT processing (Discrete Cosine Transform). In the DCT process, for example, data access is performed in the order shown by the arrows in FIG. 5 for an 8 × 8 pixel data block. In such a case, if the pixel data is 8 bits and the memory port is 8 bits, the 6th bit of the address signal becomes the boundary of the 8 × 8 pixel data block. Therefore, as shown in FIG. 5A, by dividing the memory block depending on whether the sixth bit of the address signal is 1 or 0, it is possible to access the 8 × 8 pixel data block so that the two ports do not overlap. It becomes. Further, as shown in FIG. 5B, by dividing the memory block by the 6th and 7th bits of the address signal, it becomes possible to access one pixel data block apart, so that it can also be applied to asynchronous processing. It becomes.

  Although the present embodiment has been described using an SRAM, it is needless to say that the present invention can be similarly realized with other memory configurations such as a DRAM. In the ROM, the same operation is possible although only reading is performed.

  In the present embodiment, the case where the memory cell array is divided into two is illustrated. However, even if the memory cell array is divided into a larger number of memory blocks, if each port is set so as not to use the same memory cell array, a plurality of memory cell arrays can be used. In the case of division (for example, three divisions), it is possible to configure up to the same number of ports as the division number (for example, up to three ports).

  Furthermore, if any one bit of the address signal of each port and the address signal included in the control signal is controlled so that it does not overlap the same memory cell array region in each port, it can be used as in this embodiment. Is possible. For example, as shown in FIG. 4, if the least significant bit of the address signal is switched, the memory cell array can be switched between the odd address and the even address, and the switching can be performed not in units of fields but in units of pixels. .

  As described above, the semiconductor memory device of the present invention does not require an address decoder, a sense amplifier circuit, and a bit line for each port, so that the circuit area can be greatly reduced. It is useful as a semiconductor memory device having a multi-port configuration to be used.

1 is a diagram showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention. (A) is a diagram showing a configuration of a memory cell provided in the semiconductor memory device, (b) is a diagram showing a configuration of the precharge circuit, and (c) is a diagram showing a configuration of the sense amplifier circuit. FIG. 5A is a diagram showing memory address allocation with the most significant bit when the memory cell array is divided into two memory blocks in the embodiment, and FIG. 5B is a diagram illustrating the memory cell array in four memory blocks in the embodiment. It is a figure which shows the memory address allocation by the most significant bit at the time of dividing | segmenting. FIG. 5A is a diagram showing memory address allocation with the least significant bit when the memory cell array is divided into two memory blocks in the embodiment, and FIG. 5B is a diagram illustrating the memory cell array in four memory blocks in the embodiment. It is a figure which shows the memory address allocation by the most significant bit and the least significant bit at the time of dividing | segmenting. (A) is a figure which shows memory address assignment at the time of dividing | segmenting into two memory blocks, when this invention is applied to DCT processing, (b) is a figure which shows memory address assignment at the time of dividing | segmenting into the same four memory blocks. It is. 1 is a diagram illustrating an overall configuration of a conventional semiconductor memory device having a multi-port configuration. (A) is a figure which shows the structure of the memory cell with which the conventional semiconductor memory device is equipped, (b) is a figure which shows the structure of the same precharge circuit, (c) is a figure which shows the structure of the same sense amplifier circuit.

Explanation of symbols

101 Port 1 Address Signal and Control Signal 102 Port 2 Address Signal and Control Signal 103 Decoder (Control Signal Generation Circuit)
104, 105 decoder (address decoder)
106, 108 Memory cell array (memory block)
107 Precharge circuit 109 Sense amplifier circuit 110 Memory cells 114 and 116 First selector 115 and 117 Second selector 120 Port 1 write data 121 Port 1 read data 122 Port 2 write data 123 Port 2 read data A Selection circuit (selection means)
cnt control signal

Claims (10)

A semiconductor memory device having a plurality of ports, each port being capable of accessing a memory cell at a different address for each port,
A plurality of single-port memory blocks having a plurality of memory cells;
Selection means for inputting an address signal and a control signal for each port, and selecting and outputting an address signal and a control signal for different ports to the plurality of single-port memory blocks ,
A semiconductor memory device, wherein access requests for different ports are made for each single-port memory block, and data for different ports are read from each memory block. The selection means includes
The address signal and control signal for each port are input, and the address signal and control signal for any port is selected from the address signal and control signal for each port, and the output to which memory block is controlled. The semiconductor memory device according to claim 1, further comprising a control signal generation circuit that generates a control signal to be transmitted. The selection means includes
A plurality of first selectors corresponding to the plurality of memory blocks;
Each of the plurality of first selectors inputs a control signal of the control signal generation circuit, and based on the control signal, an address signal of any one of the port-specific address signals and control signals 3. The semiconductor device according to claim 2, wherein the address signal and control signal of one port selected by each first selector are address signals and control signals having different ports. Storage device. The selection means includes
A plurality of second selectors corresponding to the plurality of memory blocks;
Each of the plurality of second selectors receives external write data for each port and a control signal for the control signal generation circuit, and based on the control signal, out of the write data for each port. Select write data for any one port,
The semiconductor memory device according to claim 3, wherein an operation of writing write data of different ports to each of the plurality of memory blocks is performed. Each of the plurality of memory blocks is
5. The semiconductor memory device according to claim 1, wherein each port has a common precharge circuit, a sense amplifier circuit, and an address decoder. The control signal generation circuit includes:
The most significant bit of each address included in the address signal and control signal of each port is input, and the address signal and control signal of any port is selected for the plurality of memory blocks based on the most significant bit The semiconductor memory device according to claim 2, wherein a control signal is generated. The control signal generation circuit includes:
At least the upper 2 bits of each address included in the address signal and control signal of each port are input, and the address signal and control signal of any port are input to the plurality of memory blocks based on the upper 2 bits. The semiconductor memory device according to claim 2, wherein a control signal for selection is generated. The control signal generation circuit includes:
The least significant bit of each address included in the address signal and control signal of each port is input, and the address signal and control signal of any port is selected for the plurality of memory blocks based on each least significant bit The semiconductor memory device according to claim 2, wherein a control signal is generated. The control signal generation circuit includes:
A predetermined upper bit and lower bit of each address included in the address signal and control signal of each port are input, and any port for the plurality of memory blocks is input based on the predetermined upper bit and lower bit. 3. The semiconductor memory device according to claim 2, wherein a control signal for selecting the address signal and the control signal is generated. The control signal generation circuit includes:
At least a predetermined 1 bit of each address included in the address signal and control signal of each port is input, and the address signal and control signal of any port is input to the plurality of memory blocks based on the 1 bit. The semiconductor memory device according to claim 2, wherein a control signal for selection is generated.

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