CN103914429A - Multi-mode data transmission interconnection device for coarseness dynamic reconfigurable array - Google Patents
Multi-mode data transmission interconnection device for coarseness dynamic reconfigurable array Download PDFInfo
- Publication number
- CN103914429A CN103914429A CN201410157349.6A CN201410157349A CN103914429A CN 103914429 A CN103914429 A CN 103914429A CN 201410157349 A CN201410157349 A CN 201410157349A CN 103914429 A CN103914429 A CN 103914429A
- Authority
- CN
- China
- Prior art keywords
- computing unit
- interconnection
- interconnection structure
- array
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a multi-mode data transmission interconnection device for a coarseness dynamic reconfigurable array. The interconnection device comprises a multi-mode interconnection controller and a multi-mode interconnection structure module. The multi-mode interconnection controller is used for storing different interconnection structure selection information and sending the same to the multi-mode interconnection structure module. The multi-mode interconnection structure module is used for selecting one or more interconnection structures from the array according to the interconnection structure selection information of the multi-mode interconnection controller to realize computing element interconnection in the reconfigurable array. By the interconnection device, an interconnection structure meeting multiple computing needs and with good computing performance can be realized on the reconfigurable array; moreover, the interconnection structure has the advantages of easiness in extension, low power consumption and small area.
Description
Technical field
The present invention relates to integrated circuit fields, relate in particular to a kind of transmission of the multimode data for coarseness dynamic reconfigurable array connectors.
Background technology
At present, reconfigurable structures originates from FPGA(field programmable gate array, Field-Programmable Gate Array), as emerging hardware processor structure, it has the dirigibility of general processor software execution and the high efficiency of special IC concurrently.Be widely used in the fields such as the communications field, media application, password, its R&D cycle is short, low in energy consumption, is accepted by increasing field at present, has wide development space.
Due in FPGA, interconnect resource takies 70% chip area nearly, and interconnect delay takies at 50%-60%.Coarse-grained reconfigurable architecture, as the class in reconfigurable structures, owing to calculating, granularity is large, and the information that need to reconfigure is few, the short good interconnection problems in FPGA that solved of reconstitution time.
Coarse-grained reconfigurable architecture not only can change controls stream, can also change fast data path, meets array and realize fast the demand of many algorithms.Make array can realize fast the calculating of many algorithms, furtheing investigate so interconnection structure design is requisite content in design process.
Routing infrastructure is most important to the data flowing water efficiency of reconfigureable computing array, and the interconnected expense of routing infrastructure is huge on the impact of reconfigureable computing array resource overhead.Traditional reconfigureable computing array routing infrastructure comprises following three kinds of citation forms: overall shared routing infrastructure, local shared routing infrastructure and complete interconnected routing infrastructure.
In the shared routing infrastructure of the overall situation, computing units all in reconfigureable computing array are shared data register file by unique access interface, and data register file can be accessed by any computing unit.This routing infrastructure can provide sufficiently high flexibility ratio, and the hardware spending of interconnection is also very low, but can not support well the above-mentioned optimization method for array pipelining performance.Because in the time that multiple computing units need the multiple data of buffer memory, these computing units can produce access conflict to the read operation of data register file, produce two class problems.First, cannot guarantee that data read the time, may cannot obtain desired data in expeced time, cause computing to make mistakes; Secondly, bring extra latency delays in order to process access conflict meeting, must in streamline, introduce extra data access and wait for beat, original flowing water performance is worsened.
In the shared routing infrastructure in part, certain several computing unit in computing array are shared one (or several) data register, each data register can be accessed by several computing units around, its interconnection expense will be much smaller than complete interconnected routing infrastructure, and hardware spending is relevant with concrete interconnection scale;
Full interconnect architecture is actually an extreme case of local shared structure, and arbitrary data register can be shared by computing units all in array, but interconnected hardware expense is very big.
The present invention, on the basis of the shared routing infrastructure of the overall situation, has proposed a kind of transmission of the multimode data for coarseness dynamic reconfigurable array connectors, has solved the problem that meets multiple computation requirement and calculated performance deterioration.
Summary of the invention
The object of the invention is for one or more of prior art not enoughly and a kind of transmission of the multimode data for coarseness dynamic reconfigurable array connectors is provided, described connectors realizes and meets multiple computation requirement and the good interconnection structure of calculated performance on reconfigurable arrays.
In order to realize goal of the invention, the invention discloses a kind of transmission of the multimode data for coarseness dynamic reconfigurable array connectors, described connectors comprises multi-mode interconnect controller and multi-mode interconnection structure module;
Described multi-mode interconnect controller is selected information for storing different interconnection structures, and interconnection structure selection information is sent to multi-mode interconnection structure module;
Described multi-mode interconnection structure module is for selecting information to select one or more interconnection structures on array according to the interconnection structure of multi-mode interconnect controller, calculates cell interconnection thereby realize in reconfigurable arrays.
As preferably, in order to strengthen the parallel managerial ability for data route in multitask, described multi-mode interconnect controller comprises broadcast type interconnect registers, many organization networks interconnect registers, computing unit self feed back interconnect registers and cumulative formula interconnect registers;
The broadcast type interconnection structure selection information that described broadcast type interconnect registers receives for storing multi-mode interconnect controller, and in the time that multi-mode interconnect controller receives broadcast type interconnection instruction, broadcast type interconnection structure selection information is sent to reconfigurable arrays;
Many organization networks interconnection structure selection information that described many organization networks interconnect registers receives for storing multi-mode interconnect controller, and in the time that multi-mode interconnect controller receives many organization networks interconnection instructions, many organization networks interconnection structure selection information is sent to reconfigurable arrays;
The computing unit self feed back interconnection structure selection information that described computing unit self feed back interconnect registers receives for storing multi-mode interconnect controller, and in the time that multi-mode interconnect controller receives computing unit self feed back interconnection instruction, computing unit self feed back interconnection structure selection information is sent to reconfigurable arrays;
The cumulative formula interconnection structure selection information that described cumulative formula interconnect registers receives for storing multi-mode interconnect controller, and the formula interconnection structure selection information that will add up in the time that multi-mode interconnect controller receives cumulative formula interconnection instruction is sent to reconfigurable arrays.
As preferably, in order to strengthen for the efficient task pipeline interconnection structure of isomery computing, described multi-mode interconnection structure module comprises broadcast type interconnecting modules, computing unit self feed back interconnecting modules, many organization networks interconnecting modules, cumulative formula interconnecting modules;
Described broadcast type interconnecting modules is used for the result of calculation of division array computation unit to be broadcast to the computing unit of basic calculating array, and the result of calculation of predetermined computation unit in basic calculating array is fed back to division array computation unit;
Described computing unit self feed back interconnecting modules, for the output terminal of computing unit is connected with the input end of self, will be exported data and again operate as input data;
Described many organization networks interconnecting modules is for the data transmission of computing unit between adjacent layer, the data interaction of computing unit between adjacent column;
The successively accumulation calculating of described cumulative formula interconnection for relating in computings such as FIR, by inverted triangle array format, is successively added data, finally calculates data accumulation result.
As preferably, arrive the efficiency of many distributions in order to strengthen data one in different computing unit array interconnect processes, described broadcast type interconnecting modules comprises interlayer route box, column register and globally interconnected line; Described interlayer route box, for the operation result of division array computation unit is outputed to route box, is dispersed to each column register by route box, realizes most according to input and most according to output; Described globally interconnected line is for coupling together computing unit and interlayer route box, interlayer route box and register, register and computing unit on formation streamline; Described column register is connected with the computing unit of route box and object row respectively by globally interconnected line input/output port.
As preferably, for in controlling interconnect hardware expense and interconnection line transmission delay, realize efficient, extendible data transmission between isomorphism computing unit array, described many organization networks interconnecting modules comprises adjacent bed computing unit interconnecting modules, adjacent column count cell interconnection module, border column computing unit interconnecting modules;
Described adjacent bed computing unit interconnecting modules is for the transmission of data between adjacent upper and lower two-layer computing unit, and interconnection composition comprises inter-level interconnects box and vertical, lower-left, three of bottom rights direction line;
Described adjacent column count cell interconnection module is for coupling together every layer of rightmost side inter-level interconnects box and leftmost side inter-level interconnects box is connected with orlop right side computing unit with orlop left side computing unit;
Described adjacent side circle column count cell interconnection module interconnects is for the transmission of data between two column count unit, adjacent left and right, from leftmost column, the computing unit that bottom computing unit is adjacent to right side top layer is connected, and successively left-hand line bottom computing unit is adjacent to right side top layer computing unit and is connected;
Wherein, described inter-level interconnects box is for selecting the output data transmission of upper strata computing unit to lower floor's same column or left and right sides computing unit; Bottom right line, row circulation line;
Described lower-left line is for interconnection box between articulamentum and its same column lower floor left side computing unit;
Described vertical join line is used for connecting inter-level interconnects and upper and lower two computing units of its same column;
Described bottom right line is used for connecting inter-level interconnects and its same column lower floor right side computing unit.
Compared with prior art, described connectors realizes and meets multiple computation requirement and the good interconnection structure of calculated performance on reconfigurable arrays in the present invention, and interconnection structure also has advantages of the expansion of being easy in addition, low in energy consumption, area is little.
Accompanying drawing explanation
Fig. 1 is multimode data transmission connectors structural representation of the present invention;
Fig. 2 is embodiment of the present invention broadcast type interconnection structure schematic diagram;
Fig. 3 is many organization networks of embodiment of the present invention interconnection structure schematic diagram;
Fig. 4 is the cumulative formula interconnection structure schematic diagram of the embodiment of the present invention;
Fig. 5 is embodiment of the present invention computing unit self feed back interconnection structure schematic diagram;
Fig. 6 is the interconnection structure schematic diagram of interconnector shown in Fig. 1 of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
Fig. 1 is multimode data transmission connectors structural representation of the present invention.As shown in Figure 1, a kind of transmission of the multimode data for coarseness dynamic reconfigurable array connectors is provided, and it comprises that multi-mode interconnect controller is made up of broadcast type interconnect registers, many organization networks interconnect registers, computing unit self feed back interconnect registers and cumulative formula interconnect registers.Multi-mode interconnection structure module is made up of broadcast type interconnecting modules, many organization networks interconnecting modules, computing unit self feed back interconnecting modules and cumulative formula interconnecting modules.
In concrete implementation, multi-mode interconnect controller is respectively used to the selection information of the interconnection of stored broadcast formula, the interconnection of many organization networks, computing unit self feed back interconnection and the formula interconnection that adds up.When control information enters after multi-mode interconnect controller, multi-mode interconnect controller will be sent to multi-mode interconnection structure module by the interconnection selection information in corresponding interconnect registers according to control information, and multi-mode interconnection structure module interconnects computing unit on array according to the selection information of multi-mode interconnect controller.For example, broadcast type interconnecting modules is also for being broadcast to the result of calculation of division array computation unit isomorphism computing unit and the accumulation calculating unit of basic calculating array, and the result of calculation of predetermined computation unit in basic calculating array is fed back to division calculation cell array, wherein, basic calculating unit permutation and division calculation cell array form reconfigurable arrays, and basic calculating cell array comprises isomorphism computing unit array and accumulation calculating cell array.
In accompanying drawing 1, be exactly these two of division calculation cell array and basic calculating cell arrays.
Fig. 2 is embodiment of the present invention broadcast type interconnection structure schematic diagram.As shown in Figure 2, provide a kind of broadcast type interconnection structure, it comprises: division calculation cell array, has 1*8 operand and be the division calculation unit of 32; Column register, has 8 registers, and storage data are 32; Isomorphism computing unit array, has the isomorphism computing unit of 6*8, and operand is 32; Two route boxes, between division calculation cell array and isomorphism computing unit array.
In broadcast type interconnection, basic calculating unit forms column unit by interconnection line, and every column count unit is connected with corresponding column register, forms data one to multicast transmission interconnection.Column register forms row unit by interconnection line, is connected with the output terminal of the route box of division calculation unit output terminal, forms the broadcast interconnection of division calculation unit to isomorphism computing unit.Data, from the output of division calculation unit, are passed through two periodic transfer to isomorphism computing unit by the globally interconnected line of 32 bit wides.The route box of division calculation cell array input end is broadcast to each the division calculation unit in row division calculation cell array by outer input data or isomorphism computing unit feedback data by 32 interconnection lines.
Fig. 3 is many organization networks of embodiment of the present invention interconnection structure schematic diagram.As shown in Figure 3, many organization networks interconnection structure comprises: isomorphism computing unit array, has 6*8 isomorphism computing unit, wherein, isomorphism computing unit operand is 32, and the interconnected interconnection of many organization networks comprises the interconnection of isomorphism computing unit adjacent bed, adjacent row interconnection, border column interconnection.
The interconnection of isomorphism computing unit between adjacent layer, by interlayer Route Selection, can be by the Output rusults of upper isomorphism of sheaves computing unit, be sent in lower vertical, lower-left, three of bottom rights computing unit by 32 interconnection lines, in one-period, realize the data transmission of isomorphism computing unit between adjacent layer.
Border column interconnection, be used for every layer of mutual route box of rightmost side interlayer and orlop left side computing unit, couple together by 32 interconnection lines, and leftmost side interlayer route box is connected with orlop right side computing unit, realizes data and between the isomorphism computing unit of array avris, transmit in one-period.
Adjacent row interconnection, by the head and the tail computing unit of adjacent column, couples together by the interconnection line of 32.From the first row of left side, successively the output terminal of the computing unit of the bottommost of left-hand line is connected with the input of adjacent right-hand column top isomorphism computing unit, realize the transmission of data between row in the monocycle.
Fig. 4 is the cumulative formula interconnection structure schematic diagram of the embodiment of the present invention.As shown in Figure 4, cumulative formula interconnection structure comprises five layers of accumulation calculating unit, for example, ground floor has 8 accumulation calculating unit, the second layer has four accumulation calculating unit, the 3rd layer has 2 accumulation calculating unit, the 4th layer, layer 5 respectively by 1 accumulation calculating unit its for relating to successively cumulative calculating.Wherein, five layers of accumulation calculating unit are for example inverted triangle layout, and the accumulation calculating unit of three vicinities was communicated with to 32 interconnection lines, connect into inverted triangle structure.
Through interconnection line, the output terminal of adjacent two accumulation calculating unit is in the ranks connected with the input end of the same accumulation calculating of next line unit, in descending accumulation calculating unit, complete the addition of two accumulation calculating unit numerical value of lastrow, the like the cumulative interconnection of composition, complete the interconnection of accumulation calculating unit.
Fig. 5 is embodiment of the present invention computing unit self feed back interconnection structure schematic diagram.As shown in Figure 5, computing unit self feed back interconnection structure is provided, and it,, by 32 interconnection lines, is connected the output terminal of self feed back computing unit with the input end of self, to export data and again operate as input data, be applicable to add up, tired take advantage of etc. repeatedly repetitive operation from computing.
Fig. 6 is the interconnection structure schematic diagram of interconnector shown in Fig. 1 of the present invention.As shown in Figure 6, on array, select many organization networks interconnection structure, cumulative interconnection and computing unit self feed back interconnection structure simultaneously, form FIR(wave filter, Finite Impulse Response) interconnection structure that calculates.
In concrete implementation, interconnection structure comprises: isomorphism computing unit array, there is 6*8 isomorphism computing unit, and wherein, isomorphism computing unit operand is 32, in array, between adjacent bed, adjacent row isomorphism computing unit, data transmission is the monocycle.Accumulation calculating cell array is 5 row accumulation calculating unit compositions, for example, ground floor has 8 accumulation calculating unit, the second layer has four accumulation calculating unit, the 3rd layer has 2 accumulation calculating unit, the 4th layer, layer 5 respectively by 1 accumulation calculating unit its for relating to successively cumulative calculating.Wherein, five layers of accumulation calculating unit are for example inverted triangle layout, and service data is 32, and interlayer data transmission is the monocycle.A self feed back computing unit, operand bit is 32.Service data, by route box, is distributed in the each isomorphism computing unit being listed as of isomorphism computing unit array and takes advantage of operation.Take advantage of result by interconnection line, in one-period, be transferred to successively in cumulative formula interconnection accumulation calculating cell array, the product that will split calculating is added.Afterwards by the interconnected cumulative sum of all calculating products of self feed back computing unit self feed back, the numerical value that the FIR asking calculates.By with globally interconnected structure, based on bunch bus interconnection test findings compare, adopt the interconnection structure performance of interconnected, the cumulative formula interconnection of many organization networks, self feed back computing unit interconnection combination to promote respectively 23% and 37%.
More than describe the preferred embodiment of the present invention in detail; but the present invention is not limited to the detail in above-mentioned embodiment, within the scope of technical conceive of the present invention; can carry out multiple equivalents to technical scheme of the present invention, these equivalents all belong to protection scope of the present invention.
It should be noted that in addition each the concrete technical characterictic described in above-mentioned embodiment, in reconcilable situation, can combine by any suitable mode.For fear of unnecessary repetition, the present invention is to the explanation no longer separately of various possible array modes.
Claims (5)
1. for a multimode data transmission connectors for coarseness dynamic reconfigurable array, it comprises:
Multi-mode interconnect controller, selects information for storing different interconnection structures;
Multi-mode interconnection structure module, for selecting information to select one or more interconnection structure modules on array according to the interconnection structure of multi-mode interconnect controller, described interconnection structure selection information is sent to multi-mode interconnection structure module by described multi-mode interconnect controller, calculates cell interconnection thereby realize in reconfigurable arrays.
2. the transmission of the multimode data for coarseness dynamic reconfigurable array connectors as claimed in claim 1, wherein, described multi-mode interconnect controller also comprises:
Broadcast type interconnect registers, the broadcast type interconnection structure selection information receiving for storing described multi-mode interconnect controller, and in the time that described multi-mode interconnect controller receives broadcast type interconnection instruction, described broadcast type interconnection structure selection information is sent to described reconfigurable arrays;
Many organization networks interconnect registers, the many organization networks interconnection structure selection information receiving for storing described multi-mode interconnect controller, and in the time that described multi-mode interconnect controller receives many organization network interconnection instructions, described many organization networks interconnection structure selection information is sent to described reconfigurable arrays;
Computing unit interconnect registers, the self feed back computing unit self feed back interconnection structure selection information receiving for storing described multi-mode interconnect controller, and in the time that described multi-mode interconnect controller receives self feed back computing unit self feed back interconnection instruction, self feed back computing unit self feed back interconnection structure selection information is sent to reconfigurable arrays;
Cumulative formula interconnect registers, the cumulative formula interconnection structure selection information receiving for storing described multi-mode interconnect controller, and in the time that described multi-mode interconnect controller receives cumulative formula interconnection instruction, the formula that will add up interconnection structure selection information is sent to reconfigurable arrays.
3. the transmission of the multimode data for coarseness dynamic reconfigurable array connectors as claimed in claim 2, wherein, described multi-mode interconnection structure module comprises:
Broadcast type interconnecting modules, for the result of calculation of division array computation unit being sent to the computing unit of basic calculating array, and feeds back to described division array computation unit by the result of calculation of predetermined computation unit in described basic calculating array;
Computing unit self feed back interconnecting modules, for the output terminal of computing unit is connected with the input end of described computing unit, using output data as input data again operate from computing;
Many organization networks interconnecting modules, for the data transmission of computing unit between adjacent layer, the data interaction of the described computing unit between adjacent column;
Cumulative formula interconnecting modules, for accumulation calculating successively, by inverted triangle array format, is successively added data, calculates data accumulation result.
4. the transmission of the multimode data for coarseness dynamic reconfigurable array connectors as claimed in claim 3, wherein, described broadcast type interconnecting modules also comprises:
Interlayer route box, for outputing to described route box by the operation result of described division array computation unit;
Column register, is dispersed to each column register by described route box, realizes most according to input and most according to output;
Globally interconnected line, for coupling together described computing unit and described interlayer route box, described interlayer route box and described register, described column register and described computing unit on formation streamline;
Described column register is connected with the computing unit of described route box and object row respectively by input, the output port of globally interconnected line.
5. the transmission of the multimode data for coarseness dynamic reconfigurable array connectors as claimed in claim 3, wherein, described many organization networks interconnecting modules also comprises:
Adjacent bed computing unit interconnecting modules, for the transmission of data between adjacent upper and lower two isomorphism of sheaves computing units, interconnection composition comprises the described isomorphism computing unit line of described inter-level interconnects box and vertical, lower-left, three directions in bottom right;
Adjacent column count cell interconnection module, for coupling together inter-level interconnects box described in every layer of rightmost side and inter-level interconnects box described in the leftmost side is connected with isomorphism computing unit described in orlop right side with the described isomorphism computing unit in orlop left side;
Border column computing unit interconnecting modules, for the transmission of data between the described isomorphism computing unit of adjacent left and right two row, from leftmost column, the described isomorphism computing unit that isomorphism computing unit described in the bottom is adjacent to right side top layer is connected, and successively isomorphism computing unit described in the left-hand line bottom is adjacent to isomorphism computing unit described in the top layer of right side and is connected;
Described inter-level interconnects box is for selecting the output data transmission of isomorphism computing unit described in upper strata to isomorphism computing unit, bottom right line, row circulation line described in lower floor's same column or arranged on left and right sides;
Described lower-left line is for interconnection box between articulamentum and its same column lower floor described isomorphism computing unit in left side;
Described vertical join line is used for connecting inter-level interconnects and upper and lower two the described isomorphism computing units of its same column;
Described bottom right line is used for connecting inter-level interconnects and its same column lower floor right side computing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410157349.6A CN103914429B (en) | 2014-04-18 | 2014-04-18 | Multimode data for coarseness dynamic reconfigurable array transmits connectors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410157349.6A CN103914429B (en) | 2014-04-18 | 2014-04-18 | Multimode data for coarseness dynamic reconfigurable array transmits connectors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103914429A true CN103914429A (en) | 2014-07-09 |
| CN103914429B CN103914429B (en) | 2016-11-23 |
Family
ID=51040124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410157349.6A Active CN103914429B (en) | 2014-04-18 | 2014-04-18 | Multimode data for coarseness dynamic reconfigurable array transmits connectors |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103914429B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104391819A (en) * | 2014-11-17 | 2015-03-04 | 天津大学 | Network interconnection architecture of multi-level and multi-processing unit reconfigurable array |
| CN112306500A (en) * | 2020-11-30 | 2021-02-02 | 上海交通大学 | Compiling method for reducing multi-class access conflict aiming at coarse-grained reconfigurable structure |
| WO2022068148A1 (en) * | 2020-09-30 | 2022-04-07 | 北京清微智能科技有限公司 | Processor array and multi-core processor |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004104904A2 (en) * | 2003-05-20 | 2004-12-02 | Axis Systems, Inc. | Multi-user server system and method for simulation |
| CN101782893A (en) * | 2009-01-21 | 2010-07-21 | 上海芯豪微电子有限公司 | Reconfigurable data processing platform |
| CN102253920A (en) * | 2011-06-08 | 2011-11-23 | 清华大学 | Fully-interconnected route structure dynamically-reconfigurable data processing method and processor |
| CN102508816A (en) * | 2011-11-15 | 2012-06-20 | 东南大学 | Configuration method applied to coarse-grained reconfigurable array |
| CN103218345A (en) * | 2013-03-15 | 2013-07-24 | 上海安路信息科技有限公司 | Dynamic reconfigurable system adaptable to plurality of dataflow computation modes and operating method |
| CN203982379U (en) * | 2014-04-18 | 2014-12-03 | 东南大学 | For the multimode data transmission connectors of coarseness dynamic reconfigurable array |
-
2014
- 2014-04-18 CN CN201410157349.6A patent/CN103914429B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004104904A2 (en) * | 2003-05-20 | 2004-12-02 | Axis Systems, Inc. | Multi-user server system and method for simulation |
| WO2004104904A3 (en) * | 2003-05-20 | 2005-03-24 | Axis Systems Inc | Multi-user server system and method for simulation |
| CN101782893A (en) * | 2009-01-21 | 2010-07-21 | 上海芯豪微电子有限公司 | Reconfigurable data processing platform |
| CN102253920A (en) * | 2011-06-08 | 2011-11-23 | 清华大学 | Fully-interconnected route structure dynamically-reconfigurable data processing method and processor |
| CN102508816A (en) * | 2011-11-15 | 2012-06-20 | 东南大学 | Configuration method applied to coarse-grained reconfigurable array |
| CN103218345A (en) * | 2013-03-15 | 2013-07-24 | 上海安路信息科技有限公司 | Dynamic reconfigurable system adaptable to plurality of dataflow computation modes and operating method |
| CN203982379U (en) * | 2014-04-18 | 2014-12-03 | 东南大学 | For the multimode data transmission connectors of coarseness dynamic reconfigurable array |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104391819A (en) * | 2014-11-17 | 2015-03-04 | 天津大学 | Network interconnection architecture of multi-level and multi-processing unit reconfigurable array |
| WO2022068148A1 (en) * | 2020-09-30 | 2022-04-07 | 北京清微智能科技有限公司 | Processor array and multi-core processor |
| CN112306500A (en) * | 2020-11-30 | 2021-02-02 | 上海交通大学 | Compiling method for reducing multi-class access conflict aiming at coarse-grained reconfigurable structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103914429B (en) | 2016-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9674114B2 (en) | Modular decoupled crossbar for on-chip router | |
| US8819611B2 (en) | Asymmetric mesh NoC topologies | |
| US11296705B2 (en) | Stacked programmable integrated circuitry with smart memory | |
| US8045546B1 (en) | Configuring routing in mesh networks | |
| US8737392B1 (en) | Configuring routing in mesh networks | |
| US8058899B2 (en) | Logic cell array and bus system | |
| US8265070B2 (en) | System and method for implementing a multistage network using a two-dimensional array of tiles | |
| US11580056B2 (en) | Control barrier network for reconfigurable data processors | |
| CN112395819A (en) | Unified programmable computing memory and configuration network | |
| JP2004326799A (en) | Processor book for constructing large-scale and scalable processor system | |
| CN102063408B (en) | Data bus in multi-kernel processor chip | |
| US20090237113A1 (en) | Semiconductor integrated circuit, program transformation apparatus, and mapping apparatus | |
| CN101808032A (en) | Static XY routing algorithm-oriented two-dimensional grid NoC router optimization design method | |
| JP4907521B2 (en) | Reconfigurable semiconductor integrated circuit and process allocation method thereof | |
| Ahn et al. | Network within a network approach to create a scalable high-radix router microarchitecture | |
| CN103914429A (en) | Multi-mode data transmission interconnection device for coarseness dynamic reconfigurable array | |
| CN203982379U (en) | For the multimode data transmission connectors of coarseness dynamic reconfigurable array | |
| CN107807901A (en) | A kind of expansible restructural polycaryon processor connection method | |
| KR20080106129A (en) | Method and apparatus for connecting multiple multimode processors | |
| CN102508797B (en) | Flash memory control expanding module, controller, storage system and data transmission method thereof | |
| CN104750659A (en) | Array circuit with reconfigurable coarsness on the basis of automatic wiring interconnection network | |
| CN112486905A (en) | Reconfigurable isomerization PEA interconnection method | |
| US8593818B2 (en) | Network on chip building bricks | |
| CN204256740U (en) | The network interconnection architecture of the reconfigurable arrays of multistage multiplied unit | |
| Zheng et al. | Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |