WO2010032699A1 - Circuit et procede de reproduction d'horloge - Google Patents

Circuit et procede de reproduction d'horloge Download PDF

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Publication number
WO2010032699A1
WO2010032699A1 PCT/JP2009/065962 JP2009065962W WO2010032699A1 WO 2010032699 A1 WO2010032699 A1 WO 2010032699A1 JP 2009065962 W JP2009065962 W JP 2009065962W WO 2010032699 A1 WO2010032699 A1 WO 2010032699A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
circuit
phase comparison
result
symbol rate
Prior art date
Application number
PCT/JP2009/065962
Other languages
English (en)
Japanese (ja)
Inventor
晃一 山口
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2010529745A priority Critical patent/JP5447385B2/ja
Publication of WO2010032699A1 publication Critical patent/WO2010032699A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/067—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability

Abstract

Selon l'invention, un signal d'entrée présentant une forme d'onde binaire est reproduit à haute vitesse et avec une faible consommation d'énergie. L'invention concerne un circuit de reproduction d'horloge comprenant : un circuit d'égalisation destiné à égaliser le signal d'entrée présentant la forme d'onde binaire en un signal duobinaire, à évaluer le niveau du signal duobinaire par rapport à une pluralité de seuils à la temporisation d'un signal d'horloge à débit de symboles et à émettre le résultat de cette évaluation; un circuit de comparaison de phase destiné à émettre le résultat de comparaison de phase indiquant le décalage de phase du signal d'horloge à débit de symboles en fonction du résultat de cette évaluation; et un circuit d'ajustement de phase destiné à augmenter ou réduire la période du signal d'horloge à débit de symboles en fonction du résultat de la comparaison de phase.
PCT/JP2009/065962 2008-09-17 2009-09-11 Circuit et procede de reproduction d'horloge WO2010032699A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010529745A JP5447385B2 (ja) 2008-09-17 2009-09-11 クロック再生回路およびクロック再生方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008-238200 2008-09-17
JP2008238200 2008-09-17

Publications (1)

Publication Number Publication Date
WO2010032699A1 true WO2010032699A1 (fr) 2010-03-25

Family

ID=42039523

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/065962 WO2010032699A1 (fr) 2008-09-17 2009-09-11 Circuit et procede de reproduction d'horloge

Country Status (2)

Country Link
JP (1) JP5447385B2 (fr)
WO (1) WO2010032699A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012029597A1 (fr) * 2010-09-01 2012-03-08 日本電気株式会社 Circuit et procédé de reproduction d'horloge
JP2013162147A (ja) * 2012-02-01 2013-08-19 Fujitsu Ltd 送信回路、通信システム、及び送信方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007037312A1 (fr) * 2005-09-28 2007-04-05 Nec Corporation Dispositif et procede de reproduction d'horloge
WO2009113462A1 (fr) * 2008-03-11 2009-09-17 日本電気株式会社 Circuit d'égalisation de forme d'onde et procédé d'égalisation de forme d'onde

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007037312A1 (fr) * 2005-09-28 2007-04-05 Nec Corporation Dispositif et procede de reproduction d'horloge
WO2009113462A1 (fr) * 2008-03-11 2009-09-17 日本電気株式会社 Circuit d'égalisation de forme d'onde et procédé d'égalisation de forme d'onde

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012029597A1 (fr) * 2010-09-01 2012-03-08 日本電気株式会社 Circuit et procédé de reproduction d'horloge
JP2013162147A (ja) * 2012-02-01 2013-08-19 Fujitsu Ltd 送信回路、通信システム、及び送信方法
US9160380B2 (en) 2012-02-01 2015-10-13 Fujitsu Limited Transmission circuit, communication system and transmission method

Also Published As

Publication number Publication date
JP5447385B2 (ja) 2014-03-19
JPWO2010032699A1 (ja) 2012-02-09

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