WO2010018072A1 - Procede de protection du decryptage des fichiers de configuration de circuits logiques programmables et circuit mettant en oeuvre le procede - Google Patents
Procede de protection du decryptage des fichiers de configuration de circuits logiques programmables et circuit mettant en oeuvre le procede Download PDFInfo
- Publication number
- WO2010018072A1 WO2010018072A1 PCT/EP2009/059891 EP2009059891W WO2010018072A1 WO 2010018072 A1 WO2010018072 A1 WO 2010018072A1 EP 2009059891 W EP2009059891 W EP 2009059891W WO 2010018072 A1 WO2010018072 A1 WO 2010018072A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- decryption
- programmable logic
- logic circuit
- attacks
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
- G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
Definitions
- the invention relates to a method for protecting the decryption of programmable logic circuit configuration files of the FPGA type as well as a circuit implementing the method.
- the invention applies in particular to the fields of electronics and the security of programmable logic circuits.
- circuits embed secret implementations. This is the case for content distribution market segments such as satellite television or the military with confidential protocols and algorithms.
- the information to be protected is available in the form of a configuration file usually qualified by the English term "bitstream".
- this configuration file is stored in a non-volatile memory, a PROM for example, easily extractable because soldered and therefore fully readable. Since this memory is not on the value chain of FPGA product designers, it is imperative that its cost be as low as possible. As a result, these components are generally lacking secure protection.
- the configuration file is saved directly within the FPGA matrix making it more complex to access.
- reading configuration files is made difficult by encrypting them with symmetric methods, such as with 3DES and AES algorithms.
- the communication between said memory and the programmable logic circuit is also protected, since the decryption is usually performed on the chip of said circuit.
- the logical decryption operation meanwhile, is not protected against attacks on its physical implementation. Thus an intelligent attack can potentially find the encryption key and then access the data in the configuration file.
- the first family of attacks that is to say the observation attacks, exploits the fact that the instantaneous power consumption of the circuit performing the encryption depends in particular on the data processed.
- Simple Power Analysis attempts to differentiate operations performed by a unit from a measure of its electrical consumption measured during a cryptographic operation.
- DPA Differential Power Analysis
- Differential Power Analysis uses statistical operations on many power consumption measurements, performed during cryptographic operations on random messages and with a constant key to validate or invalidate a hypothesis made on a part limited key.
- Tempolate attacks use in a first phase a device identical to the attacked device, except that this identical device contains no secrets, to build consumption models indexed by the value of a limited part of the key and use in a second phase some consumption measurements of the device attacked to determine the model whose measured consumptions are the closest and thus determine the value of this sub-key. Furthermore, any electric current flowing in a conductor generates an electromagnetic field whose measurement can give rise to attacks identical in principle to the attacks on the power consumption, including DPA.
- the second family of attacks that is to say the attacks by disturbance or fault injection, introduce a disturbance in the system thanks, for example, to a variation of temperature or voltage, a strong parasitic signal on the power supply or electromagnetic field, laser firing, etc.
- the faults generated have the consequence of modifying the value of a node of the attacked circuit. They can be single or multiple, permanent or transient depending on the impact on silicon. The flexibility of transient failure injections gives rise to more powerful attacks by doing multiple trials and increases the chances of success. Attacks with simple faults simplify the attack procedure. Fault attacks are based on the differential analysis between the non-errored encrypted output and the faulted output.
- the security model for programmable component configuration files is faulty: physical attacks on the non-volatile memory on which the file is located are countered by encryption, but the decryption circuit on the programmable component is not protected and can be subject to physical attack. It is so possible to potentially isolate the encryption of data blocks from the configuration file, for example by triggering on the configuration clock and measuring the instantaneous magnetic signature. This analysis makes it possible to go back to the encryption key, and thus to the decrypted configuration file.
- An object of the invention is in particular to overcome the aforementioned drawbacks.
- the invention relates to a method for protecting a programmable logic circuit.
- the data file or files used for the configuration of the programmable resources of the circuit are stored in a non-volatile memory after having been encrypted, a decryption module internal to the circuit being in charge of decrypting the file or files by using a secret key stored in the circuit, the decryption module being protected against hidden channel attacks or fault attacks aimed at obtaining the key during the decryption operation by implementing at least one countermeasure technique among which: differential logic protection, protection by masking and protection by fault detection.
- the programmable logic circuit is for example FPGA type.
- the decryption module may for example be a dedicated logic circuit internal to the programmable logic circuit or else instantiated by programming the configurable resources of the programmable logic circuit.
- the subject of the invention is also a programmable logic circuit of the FPGA type characterized in that it comprises at least one internal decryption module to the circuit responsible for decrypting the configuration file or files of the programmable resources of said circuit by using a secret key stored in the circuit, the decryption module being protected against attacks by observation and / or fault injection during the decryption operation using the method according to one of the preceding claims.
- FIG. 1 illustrates an example of a procedure for configuring a programmable logic circuit of the FPGA type
- FIG. 2 illustrates an example of a procedure for initializing a programmable logic circuit of the FPGA type and the way in which the decryption circuit according to the invention is protected.
- FIG. 1 illustrates an example of a procedure for configuring a programmable logic circuit of the FPGA type.
- the FPGA 100 is composed of a programmable resource area 101. Once programmed, it makes it possible to perform the functions required for the application targeted by the designer.
- the programmable resource zone is composed in particular of configurable logic blocks and interconnection resources between these blocks.
- the programmable resource area also includes input / output blocks, usually referred to as Input / Output Blocks (IOB). These blocks are interconnected by programming, the IOBs making it possible to define the use of the input and output ports 1 18 of the FPGA.
- the FPGA 100 comprises a volatile memory RAM 104 used in particular for storing the configuration file.
- a configuration logic module 105 is used to connect the logic blocks and the IOBs together according to the program contained in volatile memory 104 in the configuration file.
- the FPGA 100 includes a decryption module 103 for decrypting the configuration file as well as a non-volatile memory area 102 in which the key needed for decryption is located.
- a non-volatile memory 107 of PROM type for example, is used to store the encrypted configuration file.
- the FPGA circuit is programmed to perform one or more functions depending on the targeted application.
- the designer uses for example a computer 108 comprising computer-aided design (CAD) software.
- the designer programs the one or more functions 1 10 using a high level hardware description language, such as VHDL.
- the corresponding programs and data 11 1 lead to a configuration file stored in the memory of the computer.
- the designer has the option of setting an encryption key K 109 to protect said configuration data. This key is entered in parameter 1 13.
- the configuration data 11 1 grouped in the configuration file are encrypted using an encryption algorithm 1 12 such as AES or 3DES using the key K 1 13.
- the encrypted configuration file is then placed 116 in the nonvolatile memory 107.
- Another way of doing is to directly place the encrypted configuration file directly 1 17 in the volatile memory 104 internal to the FPGA via an input port 1 14, and this for objectives of system test, for example.
- the configuration file it is necessary for the configuration file to be decrypted by the FPGA.
- the key K is stored internally of the component and is transmitted during the design phase via port 106 of the FPGA.
- FIG. 2 illustrates an example of a procedure for initializing a programmable logic circuit of the FPGA type and the way in which the decryption circuit according to the invention is protected.
- the encrypted configuration file is usually stored in an external nonvolatile memory 207 to the FPGA 200.
- the encrypted configuration file is downloaded 208 and is input to the internal decryption module 203. to the FPGA via, for example, an input port 213.
- the key K 202 is used 209 by the module 203 to decrypt the file and it is transmitted 210 to the internal volatile memory 205.
- the configuration file is then used 212 by the configuration logic module 206 to configure 211 the programmable resource area 201.
- the initialization procedure described above is triggered systematically each time the system is powered up.
- An attacker whose goal is to identify the key K stored 202 in the FPGA and then to decrypt the configuration file can choose to study the functioning of the decryption module 203 during system initialization.
- This initialization is controlled by the attacker by, for example, the use of the synchronization clock used by the communication protocol between the ROM 207 and the FPGA 200.
- the decryption module is then attacked 204 by observation or injection disturbances.
- the decryption module 203 can implement various methods of countermeasures.
- the decryption module is protected against observation attacks, in particular of the DPA type, using differential logic.
- differential logic is protected against observation attacks, in particular of the DPA type, using differential logic.
- the decryption module is in this case composed of two dual logical networks operating in complementary logic so as to make the consumption of the module almost constant; SECLIB (Secured Llbrary) described in the article by S. Guilley,
- DyMCL described in the article by MW Allam and MI Elmasry entitled “Dynamic Current Logic Mode (DyMCL), a new low- power / hight-performance logic family ",
- This mask has random values and can be used at a function as a logic gate.
- the decryption circuit can be protected by using the fault detection technologies described for example in: - the article by Y. Kim, R. Karri and K Wu titled "Competitor
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP09806409A EP2316096A1 (fr) | 2008-08-12 | 2009-07-30 | Procédé de protection du décryptage des fichiers de configuration de circuits logiques programmables et circuit mettant en oeuvre le procédé |
CA2733546A CA2733546A1 (fr) | 2008-08-12 | 2009-07-30 | Procede de protection du decryptage des fichiers de configuration de circuits logiques programmables et circuit mettant en oeuvre le procede |
JP2011522469A JP2012505442A (ja) | 2008-08-12 | 2009-07-30 | プログラマブル論理回路の設定ファイルの解読を保護する方法およびそれを実施する論理回路 |
US13/058,548 US20110258459A1 (en) | 2008-08-12 | 2009-07-30 | Method for protecting the decrypting of the configuration files for programmable logic circuits and circuit implementing the method |
CN2009801313284A CN102119390A (zh) | 2008-08-12 | 2009-07-30 | 防止可编程逻辑电路的配置文件被解密的方法以及实现该方法的电路 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0855536A FR2935078B1 (fr) | 2008-08-12 | 2008-08-12 | Procede de protection du decryptage des fichiers de configuration de circuits logiques programmables et circuit mettant en oeuvre le procede |
FR0855536 | 2008-08-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010018072A1 true WO2010018072A1 (fr) | 2010-02-18 |
Family
ID=40377212
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2009/059891 WO2010018072A1 (fr) | 2008-08-12 | 2009-07-30 | Procede de protection du decryptage des fichiers de configuration de circuits logiques programmables et circuit mettant en oeuvre le procede |
Country Status (8)
Country | Link |
---|---|
US (1) | US20110258459A1 (fr) |
EP (1) | EP2316096A1 (fr) |
JP (1) | JP2012505442A (fr) |
KR (1) | KR20110083592A (fr) |
CN (1) | CN102119390A (fr) |
CA (1) | CA2733546A1 (fr) |
FR (1) | FR2935078B1 (fr) |
WO (1) | WO2010018072A1 (fr) |
Families Citing this family (14)
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US7587044B2 (en) | 1998-01-02 | 2009-09-08 | Cryptography Research, Inc. | Differential power analysis method and apparatus |
JP5552541B2 (ja) | 2009-12-04 | 2014-07-16 | クリプトグラフィ リサーチ, インコーポレイテッド | 検証可能な耐漏洩性暗号化および復号化 |
KR101695251B1 (ko) | 2012-05-22 | 2017-01-12 | 한화테크윈 주식회사 | 원격으로 카메라 fpga 배열을 변경하기 위한 시스템 및 카메라 제어 방법 |
US9424019B2 (en) | 2012-06-20 | 2016-08-23 | Microsoft Technology Licensing, Llc | Updating hardware libraries for use by applications on a computer system with an FPGA coprocessor |
US9298438B2 (en) | 2012-06-20 | 2016-03-29 | Microsoft Technology Licensing, Llc | Profiling application code to identify code portions for FPGA implementation |
US9230091B2 (en) | 2012-06-20 | 2016-01-05 | Microsoft Technology Licensing, Llc | Managing use of a field programmable gate array with isolated components |
CN103873227A (zh) * | 2012-12-13 | 2014-06-18 | 艺伦半导体技术股份有限公司 | 一种fpga加密数据流的解密电路及解密方法 |
JP6026324B2 (ja) * | 2013-03-14 | 2016-11-16 | 株式会社富士通アドバンストエンジニアリング | 電子機器、回路データ保護装置、及び回路データ保護方法 |
CN104484615B (zh) * | 2014-12-31 | 2017-08-08 | 清华大学无锡应用技术研究院 | 适用于可重构阵列架构的基于空间随机化抗故障攻击方法 |
US10708073B2 (en) * | 2016-11-08 | 2020-07-07 | Honeywell International Inc. | Configuration based cryptographic key generation |
FR3059447A1 (fr) * | 2016-11-28 | 2018-06-01 | Proton World International N.V. | Brouillage du fonctionnement d'un circuit integre |
US10741997B2 (en) | 2018-10-31 | 2020-08-11 | Jennifer Lynn Dworak | Powering an electronic system with an optical source to defeat power analysis attacks |
CN109614826B (zh) * | 2018-11-23 | 2021-05-07 | 宁波大学科学技术学院 | 一种基于tdpl逻辑的译码器 |
CN111339544B (zh) * | 2019-04-24 | 2023-03-14 | 上海安路信息科技股份有限公司 | 离线下载装置及离线下载方法 |
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US6654889B1 (en) * | 1999-02-19 | 2003-11-25 | Xilinx, Inc. | Method and apparatus for protecting proprietary configuration data for programmable logic devices |
GB9930145D0 (en) * | 1999-12-22 | 2000-02-09 | Kean Thomas A | Method and apparatus for secure configuration of a field programmable gate array |
JP2001325153A (ja) * | 2000-05-15 | 2001-11-22 | Toyo Commun Equip Co Ltd | フィールドプログラマブルゲートアレイの回路情報保護方法 |
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2009
- 2009-07-30 US US13/058,548 patent/US20110258459A1/en not_active Abandoned
- 2009-07-30 CN CN2009801313284A patent/CN102119390A/zh active Pending
- 2009-07-30 KR KR1020117003338A patent/KR20110083592A/ko not_active Application Discontinuation
- 2009-07-30 WO PCT/EP2009/059891 patent/WO2010018072A1/fr active Application Filing
- 2009-07-30 JP JP2011522469A patent/JP2012505442A/ja active Pending
- 2009-07-30 EP EP09806409A patent/EP2316096A1/fr not_active Withdrawn
- 2009-07-30 CA CA2733546A patent/CA2733546A1/fr not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
CN102119390A (zh) | 2011-07-06 |
CA2733546A1 (fr) | 2010-02-18 |
KR20110083592A (ko) | 2011-07-20 |
US20110258459A1 (en) | 2011-10-20 |
FR2935078A1 (fr) | 2010-02-19 |
JP2012505442A (ja) | 2012-03-01 |
EP2316096A1 (fr) | 2011-05-04 |
FR2935078B1 (fr) | 2012-11-16 |
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