WO2010013683A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2010013683A1
WO2010013683A1 PCT/JP2009/063361 JP2009063361W WO2010013683A1 WO 2010013683 A1 WO2010013683 A1 WO 2010013683A1 JP 2009063361 W JP2009063361 W JP 2009063361W WO 2010013683 A1 WO2010013683 A1 WO 2010013683A1
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Prior art keywords
insulating film
region
element isolation
isolation insulating
semiconductor device
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PCT/JP2009/063361
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French (fr)
Japanese (ja)
Inventor
信 宮村
潔 竹内
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日本電気株式会社
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Priority to JP2010522715A priority Critical patent/JP5486498B2/en
Publication of WO2010013683A1 publication Critical patent/WO2010013683A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • MISFET Metal-Insulator-Semiconductor-Field-Effect-Transistor
  • the gate dimension means an area given by the product of the length and width of the channel portion controlled by the gate electrode.
  • Cell transistors used in SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are designed near the minimum dimensions in the process. Therefore, the influence of random variation as described above is the largest.
  • the gate width is increased. Then, since the area occupied by one memory element (hereinafter referred to as cell size) increases, the merit of scaling cannot be enjoyed.
  • Japanese Patent Laid-Open No. 2007-27502 discloses the following example of a semiconductor device.
  • the surface of the STI (Shallow Trench Isolation) insulating film differs between the logic part and the memory part, and the STI insulating film surface is formed lower than the semiconductor surface in the memory part.
  • FIG. 9 shows a cross-sectional view of the channel region of the MISFET.
  • FIG. 9 is a cross-sectional view of the semiconductor device 50 cut perpendicularly to the direction in which the source / drain current passes.
  • the semiconductor device 50 includes a semiconductor element (MISFET) 50a in a logic part and a semiconductor element (MISFET) 50b in a memory part.
  • the respective semiconductor elements 50a and 50b have substantially the same structure.
  • the semiconductor elements 50a and 50b are respectively shallow trenches 504a and 504b, gate insulating films 502a and 502b, and gate electrodes 503a and 503b filled with insulating films (STI insulating films and element isolation insulating films) 501a and 501b on the semiconductor substrate 500. Active regions 505a and 505b and sidewalls 506a and 506b. As shown in FIG.
  • the surface of the insulating film 501b is dug down lower than the surface of the semiconductor substrate 500.
  • a channel can be formed also on the side surface of the element isolation region.
  • the gate width increases by the length 2 ⁇ W of the side region. Therefore, the effective gate width can be increased without increasing the planar area of the MISFET.
  • the conventional planar MISFET has a problem that random variation increases due to scaling, and it is difficult to further improve the integration degree of SRAM and DRAM. Also, considering the use of the side surface region in the gate width direction of the MISFET as a channel, the influence of random variation is improved.
  • the method of changing the height of the STI insulating film surface between the logic portion and the memory portion has a problem that the processing accuracy of lithography is deteriorated and it becomes difficult to process the gate electrode into a desired shape.
  • An object of the present invention is to provide a semiconductor device capable of increasing the effective channel width of a field emission transistor and a method for manufacturing the same.
  • a semiconductor device includes a semiconductor substrate having a first region and a second region, and a first formed in the first region of the semiconductor substrate.
  • a recess is formed in a portion adjacent to the second active region, and a bottom of the recess is formed in the second element isolation insulating film. And formed at a position lower than a portion adjacent to the first active region of the first element isolation insulating film. And which is characterized in that.
  • a method of manufacturing a semiconductor device defines a step of preparing a semiconductor substrate having a first region and a second region, and a first active region.
  • Forming a first groove portion in the first region of the semiconductor substrate and a second groove portion defining a second active region in the second region of the semiconductor substrate; and Forming a first element isolation insulating film in the groove portion and a second element isolation insulating film in the second groove portion, respectively, and the step of forming the element isolation insulating film comprises the step of: A recess is formed in a portion of the second element isolation insulating film adjacent to the second active region so as to be lower than a portion of the first element isolation insulating film adjacent to the first active region. Including the step of forming.
  • the side region of the active region of the field emission transistor can be used as a channel by providing a recess in the element isolation insulating film in the region adjacent to the active region. Accordingly, it is possible to provide a semiconductor device and a method for manufacturing the same that can increase the effective channel width of the field emission transistor without changing the height of the surface of the element isolation insulating film.
  • FIG. 1 is a plan view schematically showing a semiconductor device according to a first embodiment. It is a figure which shows the other structural example of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment.
  • a semiconductor device and a method for manufacturing the semiconductor device according to the first embodiment will be described below.
  • a semiconductor device in which the pullback amount is changed between a logic unit and an SRAM (Static Random Access Memory) unit will be described as an example.
  • the final STI (Shallow Trench Isolation) insulating film recess shape is reduced in the SRAM portion by reducing the pull back amount of the SRAM portion (memory portion) compared to the pull back amount of the logic portion. It is possible to dig deeper.
  • the semiconductor device 10 includes a logic unit that is a first region, a memory unit (SRAM unit) that is a second region, and two regions.
  • a logic circuit is formed in the logic portion.
  • the semiconductor element 10a is a MISFET (Metal
  • a plurality of semiconductor elements 10b are formed in the memory portion, and a memory circuit is formed.
  • the semiconductor element 10b is a MISFET. 1 is a cross-sectional view of the MISFET of the semiconductor device 10 cut in the gate width W direction shown in FIG. 3, and FIG.
  • FIG. 2 is a cross-sectional view of the MISFET of the semiconductor device 10 cut in the gate length L direction shown in FIG. FIG. Further, in order to distinguish between the structures of the logic unit and the memory unit, a is added to the end of the code related to the component of the logic unit and b is added to the end of the code related to the component of the memory unit for convenience.
  • the semiconductor element 10a includes a semiconductor substrate (silicon substrate) 100, a trench (groove) 104a, a thermal oxide film 105a, an element isolation insulating film (buried insulating film) 107a, an active region 108a, A gate insulating film 109a, a depression (depression) 110a, a gate electrode 111a, and a sidewall 112a are provided.
  • the semiconductor element 10a includes a drain region 113a, a drain electrode 114a, a source region 115a, a source electrode 116a, a silicide layer 117a, an Extension / Halo diffusion layer 118a, and the like.
  • the semiconductor substrate 100 is a silicon substrate, and includes a trench 104a, an active region 108a, a gate insulating film 109a, and a thermal oxide film 105a on the upper surface of the semiconductor substrate 100.
  • the trench 104a formed in the semiconductor substrate 100 partitions the semiconductor element 10a and is separated from other adjacent semiconductor elements as shown in FIG.
  • the trench 104a includes an element isolation insulating film 107a inside thereof.
  • the thermal oxide film 105a is made of a silicon oxide film and is provided on the surface of the trench 104a.
  • the element isolation insulating film (buried insulating film) 107a is made of a silicon oxide film and fills the trench 104a.
  • a region of the element isolation insulating film 107a that is in contact with the thermal oxide film 105a has a recess (depression) 110a.
  • the recessed portion 110a exposes the thermal oxide film 105a in a region corresponding to the opening of the trench 104a.
  • the semiconductor element 10a shown in FIG. 1 the case where the depression 110a is formed is described as an example. However, the semiconductor element 10a does not need to have the depression 110a as shown in FIG. . Further, as shown in FIG. 4, the semiconductor element 10a may not include the thermal oxide film 105a.
  • the active region 108a is a region on the upper side of the silicon substrate 100 where impurities are diffused, and is defined by the trench 104a.
  • the active region 108a functions as a channel region when a voltage is applied to the gate electrode 111a.
  • the gate insulating film 109a is made of a silicon oxide film and is formed on the active region 108a.
  • the gate electrode 111a is made of, for example, polysilicon. As shown in FIG. 1, a sidewall 112a made of an insulating material such as a silicon nitride film is formed around the gate electrode 111a.
  • the semiconductor element 10b has substantially the same configuration as the semiconductor element 10a, and includes a semiconductor substrate (silicon substrate) 100, a trench (groove) 104b, a thermal oxide film 105b, an element isolation insulating film (buried insulating film) 107b, and an active element. A region 108b, a gate insulating film 109b, a depression (depression) 110b, a gate electrode 111b, and a sidewall 112b are provided. Further, as shown in FIG. 2, the semiconductor element 10b includes a drain region 113b, a drain electrode 114b, a source region 115b, a source electrode 116b, a silicide layer 117b, an Extension / Halo diffusion layer 118b, and the like.
  • the difference between the semiconductor element 10a in the logic part and the semiconductor element 10b in the memory part is that the recessed part 110a formed in the element isolation insulating film 107a of the semiconductor element 10a is different from the recessed part 110b formed in the element isolation insulating film 107b. In other words, it is shallow, or the recess 110a is not formed.
  • the element isolation insulating films 107a and 107b have substantially the same height.
  • the horizontal length of the recess 110a is preferably 30 nm or less, and preferably 20 nm or less.
  • the recess 110a of the element isolation insulating film 107a is shallower than the recess 110b of the element isolation insulating film 107b or does not include the recess 110a.
  • the effective channel width of the semiconductor element in the memory portion can be increased without changing the height of the element isolation insulating films 107a and 107b between the logic portion and the memory portion.
  • FIGS. 5A to 5I are cross-sectional views of the MISFET of the semiconductor device cut in the gate width W direction.
  • cross-sectional views of the logic portion and the memory portion are sequentially shown.
  • a sacrificial oxide film 101 (first insulating film) having a thickness of, eg, about 10 nm is formed on a silicon substrate 100 by a thermal oxidation method.
  • the sacrificial oxide film 101 is made of a silicon oxide film.
  • a silicon nitride film (second insulating film) 102 is formed to a thickness of, for example, 100 nm by low pressure CVD (Chemical Vapor Deposition). Note that the thickness of the silicon nitride film 102 is preferably about 50 nm to 150 nm.
  • resist patterns 103 a and 103 b having openings corresponding to the trenches 104 are formed on the silicon nitride film 102.
  • a part of the silicon nitride film 102 is removed by anisotropic plasma etching using an etching gas mainly composed of a fluorine-based gas (CHF 3 , C 2 F 6, etc.) using the resist patterns 103 a and 103 b as a mask.
  • the silicon nitride films 102a and 102b remain in accordance with the resist patterns 103a and 103b.
  • the resist pattern is washed with SPM (sulfuric acid / hydrogen peroxide mixture) and APM (ammonia / hydrogen peroxide mixture). Thereby, the resist pattern is peeled off.
  • the sacrificial oxide film 101 on the silicon substrate 100 is removed by wet etching mainly using a hydrofluoric acid buffer solution.
  • the silicon substrate 100 is etched by anisotropic plasma etching using an etching gas mainly composed of a chlorine-based gas (CCl 4 or Cl 2 ) (trench etching).
  • the etching depth is preferably 200 nm to 400 nm, for example, about 300 nm.
  • thin thermal oxide films 105a and 105b having a thickness of, for example, several nm are formed on the exposed surfaces of the trenches 104a and 104b, as shown in FIG. 5B.
  • a high temperature annealing of, for example, 1000 ° C.
  • thermal oxide films 105a and 105b are not formed or become extremely thin as natural oxide films.
  • oxide films 106a and 106b are preferably formed with a thickness of about 50 nm or less, for example, about 10 nm, by low pressure CVD. Thereafter, a resist pattern (not shown) is formed only in the memory portion by a lithography process. By etching the oxide film 106a in the logic portion by etching using dilute hydrofluoric acid, the oxide film 106b remains only in the memory portion as shown in FIG. 5C. In this etching step, dry etching that can take a selectivity with the silicon nitride film may be used.
  • the etching rate of the oxide film 106b is extremely fast (for example, about 10 times) compared to the thermal oxide films 105a and 105b, the thermal oxide films 105a and 105b are hardly etched.
  • a part of the silicon nitride film 102a exposed only in the logic portion is isotropically etched by wet etching with phosphoric acid at about 160 ° C. (this process is referred to as a first pullback).
  • the first pullback causes the end portion of the silicon nitride film 102a in the logic portion to recede from the corner of the trench 104a by a length W11.
  • the resist pattern formed in the memory portion is washed with SPM or the like and peeled off. Further, the oxide film 106b remaining in the memory portion is etched using dilute hydrofluoric acid. At this stage, the silicon nitride films 102a and 102b in the logic part and the memory part are both exposed. Therefore, for example, a part of the silicon nitride films 102a and 102b is additionally etched isotropically by wet etching with phosphoric acid at about 160 ° C. (this process is referred to as a second pull back). By the second pullback, as shown in FIG.
  • the end portion of the silicon nitride film 102b in the memory portion recedes from the corner of the trench 104b by a length W12. Further, the end portion of the silicon nitride film 102a in the logic portion recedes from the corner of the trench 104a by a length W11 + W12.
  • element isolation insulating films 107a and 107b are formed with a thickness of, for example, about 450 nm so as to fill the trenches 104a and 104b by high-density plasma (HDP) CVD.
  • HDP high-density plasma
  • baking for modifying the element isolation insulating films 107a and 107b is performed under conditions of, for example, 800 ° C. and about 10 minutes. By baking, the properties of the element isolation insulating films 107a and 107b approach that of the thermal oxide film, and the quality is improved.
  • the element isolation insulating films 107a and 107b excluding the trench portions are removed by CMP (Chemical-Mechanical Polishing) method using the silicon nitride films 102a and 102b as etching stoppers.
  • CMP Chemical-Mechanical Polishing
  • the silicon nitride films 102a and 102b are removed by wet etching using phosphoric acid at about 160 ° C., for example.
  • the element isolation insulating film 107a in the logic portion extends outward from the element isolation region by W11 longer than the corner portion of the trench 104a as compared with the element isolation insulating film 107b in the memory portion.
  • impurities are implanted into the well and channel region through the sacrificial oxide film 101.
  • the implantation conditions vary depending on the transistor design, but the well depth is controlled to be, for example, about 150 nm and the channel impurity concentration is about 1 ⁇ 10 17 atm / cm 3 to 1 ⁇ 10 19 atm / cm 3 .
  • activation and crystal recovery are performed by lamp annealing at about 1000 ° C., for example. As a result, active regions 108a and 108b are formed.
  • the sacrificial oxide film 101 is removed by wet etching using a buffered hydrofluoric acid solution.
  • the element isolation insulating films 107a and 107b are also etched.
  • gate insulating films (oxide films) 109a and 109b are formed by wet annealing at, eg, about 850 ° C., as shown in FIG. 5I.
  • the gate insulating films 109 a and 109 b are formed in order from the high breakdown voltage transistor among the plurality of semiconductor elements 10 a and 10 b constituting the semiconductor device 10.
  • the oxide film thickness of the high voltage transistor is, for example, about 7 nm at the time of 3.3V design.
  • the previously formed thick gate insulating films 109a and 109b are etched once with a hydrofluoric acid solution, and then the thin gate insulating films 109a and 109b of 3 nm or less are again formed. Form.
  • the element isolation insulating films 107a and 107b are further etched to have a final shape.
  • the pull back amount of the silicon nitride film 102b in the memory portion is smaller than that in the silicon nitride film 102a in the logic portion, as shown in FIG. 5I, the STI insulating film in the vicinity of the active region 108b in the memory portion.
  • the depression 110b is formed deeper than the depression 110a of the logic part.
  • gate electrodes 111a and 111b are formed by a known method, and Extension / Halo ions are implanted to form Extension / Halo diffusion layers 118a and 118b. Further, sidewalls 112a and 112b are formed. Next, ions are implanted into the source / drain regions 113a, 113b, 115a, and 115b, and activation annealing is performed to activate the implanted ions. Further, silicide layers 117a and 117b are formed, and drain electrodes 114a and 114b and source electrodes 116a and 116b are provided.
  • the gate insulating films 109a and 109b and the gate electrodes 111a and 111b are formed to extend to the side surfaces of the active regions 108a and 108b exposed by the depressions 110a and 110b. Through these steps, the semiconductor elements 10a and 10b are formed.
  • a logic circuit is formed in the logic part, and a memory circuit is formed in the memory part.
  • These circuits may be formed simultaneously or separately. In the case of forming separately, for example, after the memory portion is masked and the logic circuit is formed, the mask of the memory portion is removed and the logic portion is masked to form the memory circuit. Or you may form in the reverse order.
  • These circuits can be formed by methods known to those skilled in the art. By such a process, the semiconductor device 10 is formed.
  • the oxide film 106b is formed only in the memory portion, and the silicon nitride film 102a is etched only in the logic portion. Further, after removing the oxide film 106b in the memory portion, the silicon nitride film 102a in the logic portion and the silicon nitride film 102b in the memory portion are etched. Thereby, the recess 110a of the element isolation insulating film 107a in the logic part can be formed shallower than the recess 110b in the element isolation insulating film 107b of the memory part.
  • the recess 110a can be formed only in the element isolation insulating film 107b of the memory portion without providing the recess 110a in the element isolation insulating film 107a of the logic portion. Therefore, it is possible to provide a semiconductor device in which only the element isolation region adjacent to the active region 108b of the memory portion is dug and the side region of the trench 104b can be used as a channel.
  • the steps on the surfaces of the gate electrodes 111a and 111b formed thereafter are reduced. Therefore, processing of the gate electrodes 111a and 111b is easy, and the gate processing accuracy can be maintained.
  • the gate width can be increased while preventing the cell size from increasing, and the driving capability of the cell transistor can be increased accordingly. Furthermore, random variations of cell transistors can be improved.
  • the semiconductor device of this embodiment is different from the semiconductor device of the first embodiment.
  • the element isolation insulating film embedded in the trench is composed of the first embedded insulating film and the second embedded insulating film.
  • the final recess shape of the element isolation insulating film can be deeply digged in the memory portion. There is in point to do.
  • the semiconductor device 20 includes two areas, a logic section that is a first area and a memory section (SRAM section) that is a second area.
  • a plurality of semiconductor elements 20a are formed in the logic portion.
  • the semiconductor element 20a is a MISFET (Metal
  • a plurality of semiconductor elements 20b are formed in the memory portion, and the semiconductor elements 20b are MISFETs.
  • a is added to the end of the code related to the component of the logic part and b is added to the end of the code related to the component of the memory part for convenience.
  • the semiconductor element 20a includes a semiconductor substrate (silicon substrate) 200, a trench 204a, a thermal oxide film 205a, a first element isolation insulating film (buried insulating film) 206a, and a second element isolation.
  • An insulating film (buried insulating film) 207a, an active region 209a, a gate insulating film 210a, a depression (depression) 211a, a gate electrode 212a, and a sidewall 213a are provided. Further, as shown in FIG.
  • the semiconductor element 20a includes a drain region 214a, a drain electrode 215a, a source region 216a, a source electrode 217a, a silicide layer 218a, an extension / halo diffusion layer 219a, and the like.
  • the element isolation insulating film includes a first element isolation insulating film (buried insulating film) 206a and a second element isolation insulating film (buried insulating film) 207a.
  • the recess 211a is formed in the first buried insulating film 206a and / or the second buried insulating film 207a.
  • the semiconductor substrate 200 is a silicon substrate, and a trench 204a, an active region 209a, and a gate insulating film 210a are formed on the upper surface of the semiconductor substrate 200.
  • the trench 204a is formed in the semiconductor substrate 200, surrounds the semiconductor element 20a, and is formed so as to be separated from the adjacent semiconductor element.
  • a first element isolation insulating film 206a and a second element isolation insulating film 207a are formed in the trench 204a.
  • the thermal oxide film 205a is formed of, for example, a silicon oxide film, and is formed on the surface of the trench 204a.
  • the first element isolation insulating film (buried insulating film) 206a is formed of, for example, a silicon oxynitride film. Note that the first element isolation insulating film 206a may be an oxide film into which an element other than nitrogen, for example, carbon or fluorine is introduced. As shown in FIG. 6, the first element isolation insulating film 206a is formed so as to cover the surface of the thermal oxide film 205a formed on the surface of the trench 204a.
  • the second element isolation insulating film (buried insulating film) 207a is formed of, for example, a silicon oxide film and fills the trench 204a.
  • a recess (depression) 211a is formed in the region where the first element isolation insulating film 206a and the second element isolation insulating film 207a are adjacent to the thermal oxide film 205a.
  • the recess 211a is formed across the first element isolation insulating film 206a and the second element isolation insulating film 207a or in the first element isolation insulating film 206a.
  • the semiconductor element 20a shown in FIG. 6 the case where the recess 211a is formed is described as an example. However, the semiconductor element 20a may not include the recess 211a.
  • the active region 209a is a region formed on the upper surface of the silicon substrate 200 and in which impurities are diffused.
  • the active region 209a functions as a channel region when a voltage is applied to the gate electrode 210a.
  • the gate insulating film 210a is made of, for example, a silicon oxide film, and is formed on the active region 209a surrounded by the trench 204a.
  • the gate electrode 212a is made of, for example, polysilicon. As shown in FIG. 6, a sidewall 213a made of an insulating material such as a silicon nitride film is formed around the gate electrode 212a.
  • the semiconductor element 20b has substantially the same configuration as the semiconductor element 20a, and includes a semiconductor substrate (silicon substrate) 200, a trench 204b, a thermal oxide film 205b, a first element isolation insulating film 206b, and a second element isolation insulation.
  • a film 207b, an active region 209b, a gate insulating film 210b, a depression (depression) 211b, a gate electrode 212b, and a sidewall 213b are provided.
  • the semiconductor element 20b includes a drain region 214b, a drain electrode 215b, a source region 216b, a source electrode 217b, a silicide layer 218b, an Extension / Halo diffusion layer 219b, and the like.
  • the recess 211b is formed across the first element isolation insulating film 206b and the second element isolation insulating film 207b.
  • the difference between the semiconductor element 20a in the logic portion and the semiconductor element 20b in the memory portion is that the depth of the recessed portion 211a of the semiconductor element 20a is the recessed portion 211b formed in the second element isolation insulating film 207b of the semiconductor element 20b. This is in that the depth is less than the depth or the recess 211a is not formed. Note that the heights of the second element isolation insulating films 207a and 207b are substantially the same. Thus, by forming the recessed portion 211b of the memory portion deeper than the recessed portion 211a of the logic portion, the region near the opening of the trench 204b can be dug down.
  • the gate insulating film 210b can be formed in a region surrounded by the trench 204b on the semiconductor substrate 200 and a region near the opening of the trench 204b, and the effective channel width of the semiconductor element 20b is increased. Can do. Further, in this embodiment, the effective channel width of the semiconductor element in the memory unit is increased without changing the height of the insulating films of the second element isolation insulating films 207a and 207b between the logic unit and the memory unit. be able to.
  • FIGS. 8A to 8J are cross-sectional views in which the MISFET of the semiconductor device is cut in the gate width direction. For comparison, cross-sectional views of the logic portion and the memory portion are sequentially shown.
  • a sacrificial oxide film (first insulating film) 201 having a thickness of, for example, about 10 nm is formed on a silicon substrate 200 by a thermal oxidation method.
  • a silicon nitride film (second insulating film) 202 is formed on the sacrificial oxide film 201 by low pressure CVD.
  • the thickness of the silicon nitride film 202 is preferably about 50 nm to 150 nm, and is formed to a thickness of about 100 nm, for example.
  • resist patterns 203 a and 203 b having openings corresponding to the element isolation regions are formed on the silicon nitride film 202.
  • a part of the silicon nitride film 202 is removed by anisotropic plasma etching using an etching gas mainly containing a fluorine-based gas (CHF 3 , C 2 F 6, etc.) using the resist patterns 203 a and 203 b as a mask. .
  • the silicon nitride films 202a and 202b remain according to the resist patterns 203a and 203b.
  • the resist patterns 203a and 203b are peeled off by cleaning using SPM (sulfuric acid / hydrogen peroxide solution) and APM (ammonia / hydrogen peroxide solution).
  • the sacrificial oxide film 201 is removed by wet etching mainly using a hydrofluoric acid buffer solution.
  • the silicon substrate 200 is etched (trench etching) by anisotropic plasma etching using an etching gas mainly composed of a chlorine-based gas (CCl 4 or Cl 2 ) to form trenches 204a and 204b.
  • the etching depth is preferably about 200 nm to 400 nm, for example, about 300 nm.
  • thin thermal oxide films 205a and 205b having a thickness of about several nm are formed on the exposed surfaces of the trenches 204a and 204b, as shown in FIG. 8B.
  • a high temperature annealing at 1000 ° C. or higher is additionally performed in an oxidizing atmosphere.
  • a method of forming a thermal oxide film there is a method of annealing at about 800 ° C. in a hydrogen atmosphere after washing with a hydrofluoric acid solution.
  • reconfiguration of silicon atoms occurs, and it is possible to obtain effects such as recovery of crystallinity and rounding of the corners of the trench.
  • the thermal oxide films 205a and 205b are not formed, or a film extremely thin to the extent of the natural oxide film thickness is formed. The steps so far are almost the same as those in the first embodiment.
  • the pullback process is performed after this, but in the present embodiment, the pullback process may not be performed.
  • the first element isolation insulating films 206a and 206b are thinly and isotropically formed to a thickness of about 10 nm, for example, by plasma CVD.
  • a silicon oxynitride film may be used as the first element isolation insulating films 206a and 206b, or an insulating film into which an element other than nitrogen, for example, carbon or fluorine is introduced may be used.
  • second element isolation insulating films 207a and 207b are formed by high density plasma (HDP) CVD so as to fill the trenches 204a and 204b.
  • the second element isolation insulating films 207a and 207b are formed to a thickness of 450 nm, for example.
  • baking for modifying the second element isolation insulating films 207a and 207b is performed at 800 ° C. for about 10 minutes.
  • the properties of the second element isolation insulating films 207a and 207b are close to those of the thermal oxide film, and the quality is improved.
  • the etching rate of the first element isolation insulating films 206a and 206b is preferably at least twice that of the second element isolation insulating films 207a and 207b.
  • Each insulating film is formed so that
  • the second element isolation insulating films 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207b and the first element isolation insulating films 206a and 206b are removed.
  • a resist is applied and developed to form a resist pattern 208a having an opening corresponding to the memory portion and exposing the memory portion.
  • a part of the first element isolation insulating film 206b of the memory portion is selectively etched as shown in FIG. 8G.
  • the etching may be performed by wet etching using a hydrofluoric acid solution, and dry etching may be used as long as the first element isolation insulating film 206b can be selectively etched.
  • the resist pattern 208a is removed by cleaning using SPM and APM. Further, the silicon nitride films 202a and 202b are removed by wet etching using phosphoric acid at about 160 ° C. as shown in FIG. 8H.
  • ions are implanted into the well region and the channel region through the sacrificial oxide film 201.
  • the implantation conditions vary depending on the transistor design.
  • the well depth is controlled to be about 150 nm
  • the channel impurity concentration is controlled to be about 1 ⁇ 10 17 atm / cm 3 to 1 ⁇ 10 19 atm / cm 3 .
  • activation and crystal recovery are performed by lamp annealing at about 1000 ° C. Thereby, the active regions 209a and 209b are formed.
  • the sacrificial oxide film 201 is removed by wet etching using a buffered hydrofluoric acid solution.
  • the first element isolation insulating films 206a and 206b and the second element isolation insulating films 207a and 207b are also etched.
  • gate insulating films (oxide films) 210a and 210b are formed.
  • the gate insulating films 210 a and 210 b are formed in order from the high breakdown voltage transistor among the plurality of semiconductor elements 20 a and 20 b constituting the semiconductor device 20.
  • the oxide film thickness of the high voltage transistor is, for example, about 7 nm at the time of 3.3V design.
  • the previously formed thick gate insulating films 210a and 210b are once etched with a hydrofluoric acid solution, and then the thin gate insulating films 210a and 210b of 3 nm or less are formed again. To do.
  • the first element isolation insulating films 206a and 206b and the second element isolation insulating films 207a and 207b are further etched to have a final shape.
  • the first element isolation insulating film 206b in the memory portion is etched more than the first element isolation insulating film 206a in the logic portion.
  • the dent part (dent part) 211b near the active region 209b in the memory part is formed deeper than the dent part (dent part) 211a of the logic part.
  • thermal oxide films 205a and 205b are thin, when the first element isolation insulating films 206a and 206b are recessed and etched, the thermal oxide films 205a and 205b are the same as the first element isolation insulating films 206a and 206b. It is simultaneously etched to a certain height.
  • gate electrodes 212a and 212b are formed by a known method, and Extension / Halo ions are implanted to form Extension / Halo diffusion layers 219a and 219b.
  • sidewalls 213a and 213b are formed.
  • ions are implanted into the source / drain regions 214a, 214b, 216a, and 216b, and activation annealing is performed to activate the implanted ions.
  • silicide layers 218a and 218b are formed, and drain electrodes 215a and 215b and source electrodes 217a and 217b are provided.
  • semiconductor elements 20a and 20b are formed as shown in FIGS.
  • a logic circuit is formed in the logic part, and a memory circuit is formed in the memory part.
  • These circuits may be formed simultaneously or separately. In the case of forming separately, for example, after the memory portion is masked and the logic circuit is formed, the mask of the memory portion is removed and the logic portion is masked to form the memory circuit. Or you may form in the reverse order.
  • These circuits can be formed by methods known to those skilled in the art. By such a process, the semiconductor device 20 is formed.
  • first buried insulating films 206a and 206b and second buried insulating films 207a and 207b are formed in the trenches 204a and 204b, and the first buried insulating films 207a and 207b are formed.
  • the upper part of the buried insulating film 206b is selectively etched.
  • the recess 211a of the logic part can be formed to be shallower than the recess 211b of the memory part or not to provide the recess 211a. Accordingly, it is possible to provide a semiconductor device in which only the element isolation region adjacent to the active region 209b of the memory portion is dug and the side region of the trench 204b can be used as a channel.
  • the step on the surface of the semiconductor element is reduced, the processing of the gate electrodes 212a and 212b is facilitated, and the gate processing accuracy can be maintained.
  • the gate processing accuracy can be maintained.
  • each part disclosed in the above embodiment exemplifies only essential parts, and an actual semiconductor device includes a part that is not explicitly shown in this embodiment.
  • the present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
  • the order of the steps disclosed in the above-described embodiments can be changed as appropriate, for example, the order can be changed.
  • some or all of the configurations of the above-described embodiments may be appropriately combined with each other.
  • a thin thermal oxide film may exist between the silicon substrate 200 and the first buried insulating films 206a and 206b.

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Abstract

A semiconductor device (10) comprises a semiconductor element (10a) in a logic unit and a semiconductor element (10b) in a memory unit.  Each semiconductor element (10a, 10b) has an element isolation insulating film (107a, 107b) embedded in a trench (104a, 104b).  The element isolation insulating film (107b) of the semiconductor element (10b) in the memory unit has a recessed portion (recess) (110b) in a region adjacent to an active region (108b).  The element isolation insulating film (107a) in the logic unit has a recess (110a) in a region adjacent to an active region (108a), said recess (110a) being shallower than the recess (110b) of the semiconductor element (10b), or alternatively, the element isolation insulating film (107a) does not have the recess (110a).

Description

半導体装置及び半導体装置の製造方法Semiconductor device and manufacturing method of semiconductor device
　本発明は、半導体装置及び半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
　ＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）は微細化に伴って、その電気的な特性のばらつきが増大する傾向がある。トランジスタに所望の性能を与えるために注入する不純物には、微視的なばらつきがある。そのため、特にＭＩＳＦＥＴのゲート寸法を縮小すると、トランジスタのランダムばらつきが増大してしまうことが知られている。ここで、ゲート寸法とは、ゲート電極に制御されるチャネル部の長さと幅の積で与えられる面積を言う。 MISFET (Metal-Insulator-Semiconductor-Field-Effect-Transistor) tends to increase the variation in its electrical characteristics with miniaturization. There are microscopic variations in impurities implanted to give the transistor desired performance. For this reason, it is known that the random variation of the transistors increases especially when the gate size of the MISFET is reduced. Here, the gate dimension means an area given by the product of the length and width of the channel portion controlled by the gate electrode.
　ＳＲＡＭ（Static Random Access Memory）やＤＲＡＭ（Dynamic Random Access Memory）に使用されるセルトランジスタは、そのプロセスにおける最小寸法付近に設計される。そのため、上に述べたようなランダムばらつきの影響は最も大きくなる。ばらつきもしくはトランジスタの駆動能力を改善するためには、ゲート幅を大きくすることになる。そうすると、１つのメモリ素子が占有する面積（以降、セルサイズと呼ぶ）が増加してしまうため、スケーリングのメリットが享受できなくなる。 Cell transistors used in SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are designed near the minimum dimensions in the process. Therefore, the influence of random variation as described above is the largest. In order to improve the variation or the driving capability of the transistor, the gate width is increased. Then, since the area occupied by one memory element (hereinafter referred to as cell size) increases, the merit of scaling cannot be enjoyed.
　このように、半導体基板平面上に形成する平面ＭＩＳＦＥＴを用いたのでは、ＳＲＡＭやＤＲＡＭの集積度を更に向上することが難しくなっている。 As described above, when the planar MISFET formed on the semiconductor substrate plane is used, it is difficult to further improve the integration degree of the SRAM and the DRAM.
　このような問題に対応する１つの方法として、実効的なチャネル部の面積を増加することが考えられる。例えば、特開２００７－２７５０２号公報では、次の半導体装置の例が開示されている。この半導体装置は、ロジック部とメモリ部でＳＴＩ（Shallow Trench Isolation）絶縁膜の表面の高さが異なり、メモリ部で半導体表面よりもＳＴＩ絶縁膜表面が低く形成されている。図９にＭＩＳＦＥＴのチャネル領域の断面図を示す。図９は、半導体装置５０を、ソース・ドレイン電流の通過方向に垂直に切った断面図である。半導体装置５０はロジック部に半導体素子（ＭＩＳＦＥＴ）５０ａと、メモリ部に半導体素子（ＭＩＳＦＥＴ）５０ｂと、を備える。それぞれの半導体素子５０ａ，５０ｂは、ほぼ同じ構造である。半導体素子５０ａ，５０ｂは、それぞれ半導体基板５００上に絶縁膜（ＳＴＩ絶縁膜，素子分離絶縁膜）５０１ａ，５０１ｂが充填された浅いトレンチ５０４ａ，５０４ｂ、ゲート絶縁膜５０２ａ，５０２ｂ、ゲート電極５０３ａ，５０３ｂ、活性領域５０５ａ，５０５ｂ及びサイドウォール５０６ａ，５０６ｂを有している。図９に示すように、メモリ部のＭＩＳＦＥＴ５０ｂでは、絶縁膜５０１ｂ表面が半導体基板５００表面よりも低く掘り下げられている。その領域にゲート絶縁膜５０２ｂおよびゲート電極５０３ｂを延在させることで、チャネルを素子分離領域の側面にも形成することができる。このようにすれば、元のゲート幅Ｗに加えて、側面領域の長さ２ΔＷだけゲート幅が増加する。従って、ＭＩＳＦＥＴの平面的な面積を増加させずに、実効的なゲート幅を増加させることができる。 One method for dealing with such a problem is to increase the effective channel area. For example, Japanese Patent Laid-Open No. 2007-27502 discloses the following example of a semiconductor device. In this semiconductor device, the surface of the STI (Shallow Trench Isolation) insulating film differs between the logic part and the memory part, and the STI insulating film surface is formed lower than the semiconductor surface in the memory part. FIG. 9 shows a cross-sectional view of the channel region of the MISFET. FIG. 9 is a cross-sectional view of the semiconductor device 50 cut perpendicularly to the direction in which the source / drain current passes. The semiconductor device 50 includes a semiconductor element (MISFET) 50a in a logic part and a semiconductor element (MISFET) 50b in a memory part. The respective semiconductor elements 50a and 50b have substantially the same structure. The semiconductor elements 50a and 50b are respectively shallow trenches 504a and 504b, gate insulating films 502a and 502b, and gate electrodes 503a and 503b filled with insulating films (STI insulating films and element isolation insulating films) 501a and 501b on the semiconductor substrate 500. Active regions 505a and 505b and sidewalls 506a and 506b. As shown in FIG. 9, in the MISFET 50b of the memory part, the surface of the insulating film 501b is dug down lower than the surface of the semiconductor substrate 500. By extending the gate insulating film 502b and the gate electrode 503b in that region, a channel can be formed also on the side surface of the element isolation region. In this way, in addition to the original gate width W, the gate width increases by the length 2ΔW of the side region. Therefore, the effective gate width can be increased without increasing the planar area of the MISFET.
特開２００７－２７５０２号公報JP 2007-27502 A
　しかしながら、図９に示すようにＳＴＩ絶縁膜５０１ｂを掘り下げると、ＳＴＩ絶縁膜５０１ｂを形成した後に形成したゲート電極５０３ｂの表面に凸凹が生じる。そのため、本工程の後に続くリソグラフィ工程におけるフォーカスマージンを減少させるという問題がある。このように、メモリ部とロジック部でＳＴＩ絶縁膜表面が異なる高さを持つ場合、同一のリソグラフィ工程によってメモリ部とロジック部の両者のゲート電極の形状をそれぞれ所望の形状に加工することはきわめて難しい。 However, when the STI insulating film 501b is dug down as shown in FIG. 9, the surface of the gate electrode 503b formed after the STI insulating film 501b is formed becomes uneven. Therefore, there is a problem that the focus margin in the lithography process following this process is reduced. Thus, when the STI insulating film surfaces have different heights in the memory portion and the logic portion, it is extremely difficult to process the gate electrodes of the memory portion and the logic portion into desired shapes by the same lithography process. difficult.
　このように、従来の平面ＭＩＳＦＥＴでは、スケーリングによってランダムばらつきが増加し、ＳＲＡＭやＤＲＡＭの集積度をさらに向上させることが難しくなってきているという問題があった。また、ＭＩＳＦＥＴのゲート幅方向の側面領域をチャネルとして利用することを考えれば、ランダムばらつきの影響は改善される。しかしながら、ＳＴＩ絶縁膜表面の高さをロジック部とメモリ部で変化させるといった方法では、リソグラフィの加工精度を劣化させ、所望の形状にゲート電極を加工することが困難になるという問題があった。 As described above, the conventional planar MISFET has a problem that random variation increases due to scaling, and it is difficult to further improve the integration degree of SRAM and DRAM. Also, considering the use of the side surface region in the gate width direction of the MISFET as a channel, the influence of random variation is improved. However, the method of changing the height of the STI insulating film surface between the logic portion and the memory portion has a problem that the processing accuracy of lithography is deteriorated and it becomes difficult to process the gate electrode into a desired shape.
　本発明はこのような問題に鑑みてなされたものであり、埋め込み絶縁膜表面の高さを変化させることなく、素子分離絶縁膜で区画された活性領域の側面領域をチャネルとして利用することにより、電界放出トランジスタの実効的なチャネル幅を増加させることが可能な半導体装置およびその製造方法を提供することを目的とする。 The present invention has been made in view of such problems, and by using the side region of the active region partitioned by the element isolation insulating film as a channel without changing the height of the surface of the embedded insulating film, An object of the present invention is to provide a semiconductor device capable of increasing the effective channel width of a field emission transistor and a method for manufacturing the same.
　上記目的を達成するため、本発明の第１の観点に係る半導体装置は、第１の領域及び第２の領域を有する半導体基板と、前記半導体基板の前記第１の領域に形成された第１の活性領域と、前記半導体基板の前記第２の領域に形成された第２の活性領域と、前記第１の領域に形成され、前記第１の活性領域を定義する第１の溝部と、前記第２の領域に形成され、前記第２の活性領域を定義する第２の溝部と、前記第１の溝部に埋め込まれた第１の素子分離絶縁膜と、前記第２の溝部に埋め込まれた第２の素子分離絶縁膜と、を有し、前記第２の素子分離絶縁膜には、前記第２の活性領域に隣接した部分に、凹み部が形成されており、該凹み部の底部は、前記第１の素子分離絶縁膜の前記第１の活性領域に隣接した部分よりも低い位置に形成されている、ことを特徴とする。 To achieve the above object, a semiconductor device according to a first aspect of the present invention includes a semiconductor substrate having a first region and a second region, and a first formed in the first region of the semiconductor substrate. An active region of the semiconductor substrate, a second active region formed in the second region of the semiconductor substrate, a first groove formed in the first region and defining the first active region, A second groove defined in the second region and defining the second active region; a first element isolation insulating film embedded in the first groove; and embedded in the second groove A recess is formed in a portion adjacent to the second active region, and a bottom of the recess is formed in the second element isolation insulating film. And formed at a position lower than a portion adjacent to the first active region of the first element isolation insulating film. And which is characterized in that.
　上記目的を達成するため、本発明の第２の観点に係る半導体装置の製造方法は、第１の領域及び第２の領域を有する半導体基板を用意するステップと、第１の活性領域を定義する第１の溝部を前記半導体基板の前記第１の領域に、第２の活性領域を定義する第２の溝部を前記半導体基板の前記第２の領域に、それぞれ形成するステップと、前記第１の溝部に第１の素子分離絶縁膜を、前記第２の溝部に第２の素子分離絶縁膜を、それぞれ形成するステップと、を備え、前記素子分離絶縁膜を形成するステップは、底部が、前記第１の素子分離絶縁膜の前記第１の活性領域に隣接した部分よりも低い位置となるように、前記第２の素子分離絶縁膜の前記第２の活性領域に隣接する部分に凹み部を形成するステップを含む、ことを特徴とする。 In order to achieve the above object, a method of manufacturing a semiconductor device according to a second aspect of the present invention defines a step of preparing a semiconductor substrate having a first region and a second region, and a first active region. Forming a first groove portion in the first region of the semiconductor substrate and a second groove portion defining a second active region in the second region of the semiconductor substrate; and Forming a first element isolation insulating film in the groove portion and a second element isolation insulating film in the second groove portion, respectively, and the step of forming the element isolation insulating film comprises the step of: A recess is formed in a portion of the second element isolation insulating film adjacent to the second active region so as to be lower than a portion of the first element isolation insulating film adjacent to the first active region. Including the step of forming.
　本発明によれば、活性領域に隣接する領域の素子分離絶縁膜に凹み部を設けることにより、電界放出トランジスタの活性領域の側面領域をチャネルとして利用できる。これにより、素子分離絶縁膜の表面の高さを変化させることなく、電界放出トランジスタの実効的なチャネル幅を増加させることが可能な半導体装置およびその製造方法を提供することができる。 According to the present invention, the side region of the active region of the field emission transistor can be used as a channel by providing a recess in the element isolation insulating film in the region adjacent to the active region. Accordingly, it is possible to provide a semiconductor device and a method for manufacturing the same that can increase the effective channel width of the field emission transistor without changing the height of the surface of the element isolation insulating film.
第１実施形態に係る半導体装置をゲート幅方向に切断した断面図である。It is sectional drawing which cut | disconnected the semiconductor device which concerns on 1st Embodiment in the gate width direction. 第１実施形態に係る半導体装置をゲート長方向に切断した断面図である。It is sectional drawing which cut | disconnected the semiconductor device which concerns on 1st Embodiment in the gate length direction. 第１実施形態に係る半導体装置を模式的に示した平面図である。1 is a plan view schematically showing a semiconductor device according to a first embodiment. 第１実施形態に係る半導体装置の他の構成例を示す図である。It is a figure which shows the other structural example of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 第２実施形態に係る半導体装置をゲート幅方向に切断した断面図である。It is sectional drawing which cut | disconnected the semiconductor device which concerns on 2nd Embodiment in the gate width direction. 第２実施形態に係る半導体装置をゲート長方向に切断した断面図である。It is sectional drawing which cut | disconnected the semiconductor device which concerns on 2nd Embodiment in the gate length direction. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 比較例を示す図である。It is a figure which shows a comparative example.
　本発明の実施形態に係る半導体装置及び半導体装置の製造方法を、図を用いて説明する。 A semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
　（第１実施形態）
　第１実施形態に係る半導体装置及び半導体装置の製造方法について、以下説明する。なお、本実施形態では、プルバック量をロジック部とＳＲＡＭ（Static Random Access Memory）部とで変化させた半導体装置を例に挙げて説明する。本実施形態では、後述するようにＳＲＡＭ部（メモリ部）のプルバック量をロジック部のプルバック量に比べて小さくすることで、最終的なＳＴＩ（Shallow Trench Isolation）絶縁膜の窪み形状をＳＲＡＭ部において深く掘り下げられるようにすることが可能である。 (First embodiment)
A semiconductor device and a method for manufacturing the semiconductor device according to the first embodiment will be described below. In the present embodiment, a semiconductor device in which the pullback amount is changed between a logic unit and an SRAM (Static Random Access Memory) unit will be described as an example. In the present embodiment, as will be described later, the final STI (Shallow Trench Isolation) insulating film recess shape is reduced in the SRAM portion by reducing the pull back amount of the SRAM portion (memory portion) compared to the pull back amount of the logic portion. It is possible to dig deeper.
　半導体装置１０は、図１～３に示すように第１の領域であるロジック部と、第２の領域であるメモリ部（ＳＲＡＭ部）と、２つの領域を備える。ロジック部には、複数の半導体素子１０ａが形成され、ロジック回路が形成されている。ここで半導体素子１０ａはＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）である。メモリ部にも同様に複数の半導体素子１０ｂが形成され、メモリ回路が形成されている。ここで半導体素子１０ｂは、ＭＩＳＦＥＴである。図１は、半導体装置１０のＭＩＳＦＥＴを、図３に示すゲート幅Ｗ方向に切断した断面図であり、図２は、半導体装置１０のＭＩＳＦＥＴを、図３に示すゲート長Ｌ方向に切断した断面図である。また、ロジック部とメモリ部の構造を区別するため、便宜的にロジック部の構成要素に係る符号の末尾にはａを、メモリ部の構成要素に係る符号の末尾にはｂをそれぞれ付加する。 As shown in FIGS. 1 to 3, the semiconductor device 10 includes a logic unit that is a first region, a memory unit (SRAM unit) that is a second region, and two regions. In the logic portion, a plurality of semiconductor elements 10a are formed, and a logic circuit is formed. Here, the semiconductor element 10a is a MISFET (Metal | Insulator | Semiconductor | Field | Effect | Transistor). Similarly, a plurality of semiconductor elements 10b are formed in the memory portion, and a memory circuit is formed. Here, the semiconductor element 10b is a MISFET. 1 is a cross-sectional view of the MISFET of the semiconductor device 10 cut in the gate width W direction shown in FIG. 3, and FIG. 2 is a cross-sectional view of the MISFET of the semiconductor device 10 cut in the gate length L direction shown in FIG. FIG. Further, in order to distinguish between the structures of the logic unit and the memory unit, a is added to the end of the code related to the component of the logic unit and b is added to the end of the code related to the component of the memory unit for convenience.
　半導体素子１０ａは、図１に示すように半導体基板（シリコン基板）１００と、トレンチ（溝部）１０４ａと、熱酸化膜１０５ａと、素子分離絶縁膜（埋め込み絶縁膜）１０７ａと、活性領域１０８ａと、ゲート絶縁膜１０９ａと、窪み部（凹み部）１１０ａと、ゲート電極１１１ａと、サイドウォール１１２ａと、を備える。また、図２に示すように、半導体素子１０ａはドレイン領域１１３ａ、ドレイン電極１１４ａ、ソース領域１１５ａ、ソース電極１１６ａ、シリサイド層１１７ａ、およびExtension/Halo拡散層１１８ａ等を備える。 As shown in FIG. 1, the semiconductor element 10a includes a semiconductor substrate (silicon substrate) 100, a trench (groove) 104a, a thermal oxide film 105a, an element isolation insulating film (buried insulating film) 107a, an active region 108a, A gate insulating film 109a, a depression (depression) 110a, a gate electrode 111a, and a sidewall 112a are provided. As shown in FIG. 2, the semiconductor element 10a includes a drain region 113a, a drain electrode 114a, a source region 115a, a source electrode 116a, a silicide layer 117a, an Extension / Halo diffusion layer 118a, and the like.
　半導体基板１００は、シリコン基板であり、半導体基板１００の上面には、トレンチ１０４ａ、活性領域１０８ａ、ゲート絶縁膜１０９ａ、および熱酸化膜１０５ａを備える。 The semiconductor substrate 100 is a silicon substrate, and includes a trench 104a, an active region 108a, a gate insulating film 109a, and a thermal oxide film 105a on the upper surface of the semiconductor substrate 100.
　半導体基板１００に形成されたトレンチ１０４ａは、図３に示すように、半導体素子１０ａを区画し、隣接する他の半導体素子から分離している。また、トレンチ１０４ａは、その内側に素子分離絶縁膜１０７ａを備える。 The trench 104a formed in the semiconductor substrate 100 partitions the semiconductor element 10a and is separated from other adjacent semiconductor elements as shown in FIG. The trench 104a includes an element isolation insulating film 107a inside thereof.
　熱酸化膜１０５ａは、シリコン酸化膜から構成され、トレンチ１０４ａの表面に備わる。 The thermal oxide film 105a is made of a silicon oxide film and is provided on the surface of the trench 104a.
　素子分離絶縁膜（埋め込み絶縁膜）１０７ａは、シリコン酸化膜から構成され、トレンチ１０４ａを充填している。素子分離絶縁膜１０７ａの、熱酸化膜１０５ａと接する領域には窪み部（凹み部）１１０ａを有する。窪み部１１０ａによって、トレンチ１０４ａの開口に対応する領域の熱酸化膜１０５ａが露出する。なお、図１に示す半導体素子１０ａでは、窪み部１１０ａが形成される場合を例に挙げて説明しているが、半導体素子１０ａは、図４に示すように、窪み部１１０ａを備えなくとも良い。また、半導体素子１０ａは、図４に示すように、熱酸化膜１０５ａを備えなくとも良い。 The element isolation insulating film (buried insulating film) 107a is made of a silicon oxide film and fills the trench 104a. A region of the element isolation insulating film 107a that is in contact with the thermal oxide film 105a has a recess (depression) 110a. The recessed portion 110a exposes the thermal oxide film 105a in a region corresponding to the opening of the trench 104a. In the semiconductor element 10a shown in FIG. 1, the case where the depression 110a is formed is described as an example. However, the semiconductor element 10a does not need to have the depression 110a as shown in FIG. . Further, as shown in FIG. 4, the semiconductor element 10a may not include the thermal oxide film 105a.
　活性領域１０８ａは、シリコン基板１００の上側の、不純物が拡散された領域であり、トレンチ１０４ａによって定義される。活性領域１０８ａはゲート電極１１１ａに電圧が印加されるとチャネル領域として機能する。 The active region 108a is a region on the upper side of the silicon substrate 100 where impurities are diffused, and is defined by the trench 104a. The active region 108a functions as a channel region when a voltage is applied to the gate electrode 111a.
　ゲート絶縁膜１０９ａは、シリコン酸化膜から構成され、活性領域１０８ａ上に形成されている。 The gate insulating film 109a is made of a silicon oxide film and is formed on the active region 108a.
　ゲート電極１１１ａは、例えばポリシリコン等から構成される。ゲート電極１１１ａの周囲には図１に示すように絶縁材料、例えばシリコン窒化膜等から構成されるサイドウォール１１２ａが形成されている。 The gate electrode 111a is made of, for example, polysilicon. As shown in FIG. 1, a sidewall 112a made of an insulating material such as a silicon nitride film is formed around the gate electrode 111a.
　半導体素子１０ｂは、半導体素子１０ａとほぼ同じ構成であり、半導体基板（シリコン基板）１００と、トレンチ（溝部）１０４ｂと、熱酸化膜１０５ｂと、素子分離絶縁膜（埋め込み絶縁膜）１０７ｂと、活性領域１０８ｂと、ゲート絶縁膜１０９ｂと、窪み部（凹み部）１１０ｂと、ゲート電極１１１ｂと、サイドウォール１１２ｂと、を備える。また、半導体素子１０ｂは、図２に示すように、ドレイン領域１１３ｂ、ドレイン電極１１４ｂ、ソース領域１１５ｂ、ソース電極１１６ｂ、シリサイド層１１７ｂ、およびExtension/Halo拡散層１１８ｂ等を備える。 The semiconductor element 10b has substantially the same configuration as the semiconductor element 10a, and includes a semiconductor substrate (silicon substrate) 100, a trench (groove) 104b, a thermal oxide film 105b, an element isolation insulating film (buried insulating film) 107b, and an active element. A region 108b, a gate insulating film 109b, a depression (depression) 110b, a gate electrode 111b, and a sidewall 112b are provided. Further, as shown in FIG. 2, the semiconductor element 10b includes a drain region 113b, a drain electrode 114b, a source region 115b, a source electrode 116b, a silicide layer 117b, an Extension / Halo diffusion layer 118b, and the like.
　ロジック部の半導体素子１０ａとメモリ部の半導体素子１０ｂとが異なるのは、半導体素子１０ａの素子分離絶縁膜１０７ａに形成された凹み部１１０ａが、素子分離絶縁膜１０７ｂに形成された凹み部１１０ｂよりも浅い、もしくは凹み部１１０ａが形成されていない点にある。なお、素子分離絶縁膜１０７ａと１０７ｂの高さは、ほぼ同じである。このように、凹み部１１０ｂを、ロジック部の凹み部１１０ａより深く形成することにより、素子分離絶縁膜１０７ｂからトレンチ１０４ｂの側面領域が露出する量を増加させることができる。このため、活性領域１０８ｂの側面までゲート電極１１１ｂを延在させることができ、実効的なチャネル幅が増加する。なお、凹み部１１０ａの横方向の長さは３０ｎｍ以下が好適であり、望ましくは２０ｎｍ以下とすることが良い。 The difference between the semiconductor element 10a in the logic part and the semiconductor element 10b in the memory part is that the recessed part 110a formed in the element isolation insulating film 107a of the semiconductor element 10a is different from the recessed part 110b formed in the element isolation insulating film 107b. In other words, it is shallow, or the recess 110a is not formed. The element isolation insulating films 107a and 107b have substantially the same height. Thus, by forming the recessed portion 110b deeper than the recessed portion 110a of the logic portion, the amount of exposure of the side region of the trench 104b from the element isolation insulating film 107b can be increased. For this reason, the gate electrode 111b can be extended to the side surface of the active region 108b, and the effective channel width is increased. The horizontal length of the recess 110a is preferably 30 nm or less, and preferably 20 nm or less.
　特に、本実施形態では、このような素子分離絶縁膜１０７ａの凹み部１１０ａが、素子分離絶縁膜１０７ｂの凹み部１１０ｂより浅い、もしくは凹み部１１０ａを備えていない。それにより、素子分離絶縁膜１０７ａ，１０７ｂの高さをロジック部とメモリ部とで変化させずに、メモリ部の半導体素子の実効的なチャネル幅を増加させることができる。 In particular, in this embodiment, the recess 110a of the element isolation insulating film 107a is shallower than the recess 110b of the element isolation insulating film 107b or does not include the recess 110a. Thus, the effective channel width of the semiconductor element in the memory portion can be increased without changing the height of the element isolation insulating films 107a and 107b between the logic portion and the memory portion.
　次に本実施形態に係る半導体装置の製造工程について図５Ａ～図５Ｉを用いて説明する。なお、図５Ａ～図５Ｉは、半導体装置のＭＩＳＦＥＴをゲート幅Ｗ方向に切った断面図である。また、比較のためにロジック部とメモリ部の断面図を逐次並べて示している。 Next, the manufacturing process of the semiconductor device according to this embodiment will be described with reference to FIGS. 5A to 5I. 5A to 5I are cross-sectional views of the MISFET of the semiconductor device cut in the gate width W direction. For comparison, cross-sectional views of the logic portion and the memory portion are sequentially shown.
　まず、図５Ａに示すように、シリコン基板１００上に、例えば膜厚１０ｎｍ程度の犠牲酸化膜１０１（第一の絶縁膜）を熱酸化法により形成する。犠牲酸化膜１０１は、シリコン酸化膜からなる。さらに減圧ＣＶＤ（Chemical Vapor Deposition）法によって窒化シリコン膜（第二の絶縁膜）１０２を、例えば１００ｎｍの厚みで形成する。なお、窒化シリコン膜１０２の厚みは、５０ｎｍ～１５０ｎｍ程度が好適である。続いて、窒化シリコン膜１０２上に、トレンチ１０４に対応した開口部を有するレジストパターン１０３ａ，１０３ｂを形成する。 First, as shown in FIG. 5A, a sacrificial oxide film 101 (first insulating film) having a thickness of, eg, about 10 nm is formed on a silicon substrate 100 by a thermal oxidation method. The sacrificial oxide film 101 is made of a silicon oxide film. Further, a silicon nitride film (second insulating film) 102 is formed to a thickness of, for example, 100 nm by low pressure CVD (Chemical Vapor Deposition). Note that the thickness of the silicon nitride film 102 is preferably about 50 nm to 150 nm. Subsequently, resist patterns 103 a and 103 b having openings corresponding to the trenches 104 are formed on the silicon nitride film 102.
　次に、レジストパターン１０３ａ，１０３ｂをマスクとしてフッ素系ガス（ＣＨＦ3やＣ2Ｆ6等）を主体としたエッチングガスを使用した異方性プラズマエッチングにより前記窒化シリコン膜１０２の一部を除去する。これにより、レジストパターン１０３ａ，１０３ｂに応じて窒化シリコン膜１０２ａ，１０２ｂが残存する。その後、レジストパターンをＳＰＭ（硫酸／過酸化水素水混合液）及びＡＰＭ（アンモニア／過酸化水素水混合液）で洗浄する。これによりレジストパターンを剥離する。さらにフッ酸緩衝溶液を主体としたウェットエッチングにより、シリコン基板１００上の犠牲酸化膜１０１を除去する。 Next, a part of the silicon nitride film 102 is removed by anisotropic plasma etching using an etching gas mainly composed of a fluorine-based gas (CHF 3 , C 2 F 6, etc.) using the resist patterns 103 a and 103 b as a mask. . As a result, the silicon nitride films 102a and 102b remain in accordance with the resist patterns 103a and 103b. Thereafter, the resist pattern is washed with SPM (sulfuric acid / hydrogen peroxide mixture) and APM (ammonia / hydrogen peroxide mixture). Thereby, the resist pattern is peeled off. Further, the sacrificial oxide film 101 on the silicon substrate 100 is removed by wet etching mainly using a hydrofluoric acid buffer solution.
　次に、塩素系ガス（ＣＣｌ4やＣｌ2など）を主体としたエッチングガスを使用した異方性プラズマエッチングによりシリコン基板１００をエッチングする（トレンチエッチング）。エッチング深さは、２００ｎｍ～４００ｎｍであることが好ましく、例えば３００ｎｍ程度とする。続いて、酸素雰囲気中で熱酸化を行うことにより、図５Ｂに示すように、トレンチ１０４ａ，１０４ｂの露出面に、例えば数ｎｍの厚みの薄い熱酸化膜１０５ａ，１０５ｂを形成する。さらに、結晶性の回復およびトレンチの角部を丸めるために、追加的に酸化性雰囲気内で例えば１０００℃以上の高温アニールを実施する。なお、熱酸化膜の形成による方法のほかに、フッ酸系溶液で洗浄した後に、水素雰囲気中での８００℃程度のアニールによりシリコン原子の再構成によって結晶性の回復およびトレンチ１０４ａ，１０４ｂの角部を丸める方法を使うこともできる。この場合、熱酸化膜１０５ａ，１０５ｂは形成されない、もしくは自然酸化膜程度に極めて薄くなる。 Next, the silicon substrate 100 is etched by anisotropic plasma etching using an etching gas mainly composed of a chlorine-based gas (CCl 4 or Cl 2 ) (trench etching). The etching depth is preferably 200 nm to 400 nm, for example, about 300 nm. Subsequently, by performing thermal oxidation in an oxygen atmosphere, thin thermal oxide films 105a and 105b having a thickness of, for example, several nm are formed on the exposed surfaces of the trenches 104a and 104b, as shown in FIG. 5B. Further, in order to recover the crystallinity and round the corners of the trench, a high temperature annealing of, for example, 1000 ° C. or higher is additionally performed in an oxidizing atmosphere. In addition to the method of forming a thermal oxide film, after cleaning with a hydrofluoric acid-based solution, the crystallinity is restored by reconfiguration of silicon atoms by annealing at about 800 ° C. in a hydrogen atmosphere, and the corners of the trenches 104a and 104b. You can also use the method of rounding parts. In this case, the thermal oxide films 105a and 105b are not formed or become extremely thin as natural oxide films.
　次に、減圧ＣＶＤ法により酸化膜１０６ａ，１０６ｂを、好ましくは５０ｎｍ以下、例えば１０ｎｍ程度の厚みで形成する。その後、リソグラフィ工程によりレジストパターン（図示せず）をメモリ部のみに形成する。希フッ酸を使ったエッチングにより、ロジック部の酸化膜１０６ａをエッチングすることにより、図５Ｃに示すように、メモリ部にのみ酸化膜１０６ｂが残存する。このエッチング工程では、窒化シリコン膜と選択比が取れるようなドライエッチングを使用してもよい。ここで、酸化膜１０６ｂのエッチングレートは熱酸化膜１０５ａ，１０５ｂに比べて極めて早い（例えば１０倍程度）ため、熱酸化膜１０５ａ，１０５ｂはほとんどエッチングされない。 Next, oxide films 106a and 106b are preferably formed with a thickness of about 50 nm or less, for example, about 10 nm, by low pressure CVD. Thereafter, a resist pattern (not shown) is formed only in the memory portion by a lithography process. By etching the oxide film 106a in the logic portion by etching using dilute hydrofluoric acid, the oxide film 106b remains only in the memory portion as shown in FIG. 5C. In this etching step, dry etching that can take a selectivity with the silicon nitride film may be used. Here, since the etching rate of the oxide film 106b is extremely fast (for example, about 10 times) compared to the thermal oxide films 105a and 105b, the thermal oxide films 105a and 105b are hardly etched.
　次に、例えば１６０℃程度の燐酸によるウェットエッチングにより、ロジック部のみ露出している窒化シリコン膜１０２ａの一部を等方的にエッチングする（この工程を第一プルバックと呼ぶ）。第一プルバックにより図５Ｄに示すように、ロジック部における窒化シリコン膜１０２ａの端部がトレンチ１０４ａの角から長さＷ１１だけ後退する。 Next, for example, a part of the silicon nitride film 102a exposed only in the logic portion is isotropically etched by wet etching with phosphoric acid at about 160 ° C. (this process is referred to as a first pullback). As shown in FIG. 5D, the first pullback causes the end portion of the silicon nitride film 102a in the logic portion to recede from the corner of the trench 104a by a length W11.
　次に、メモリ部に形成されたレジストパターンをＳＰＭ等で洗浄し、剥離する。さらにメモリ部に残った酸化膜１０６ｂを、希フッ酸を用いてエッチングする。この段階ではロジック部とメモリ部の窒化シリコン膜１０２ａ，１０２ｂは共に露出している。このため、例えば１６０℃程度の燐酸によるウェットエッチングにより、窒化シリコン膜１０２ａ，１０２ｂの一部を等方的に追加エッチングする（この工程を第二プルバックと呼ぶ）。第二プルバックにより図５Ｅに示すようにメモリ部における窒化シリコン膜１０２ｂの端部がトレンチ１０４ｂの角から長さＷ１２だけ後退する。さらに、ロジック部における前記窒化シリコン膜１０２ａの端部はトレンチ１０４ａの角から長さＷ１１＋Ｗ１２だけ後退する。 Next, the resist pattern formed in the memory portion is washed with SPM or the like and peeled off. Further, the oxide film 106b remaining in the memory portion is etched using dilute hydrofluoric acid. At this stage, the silicon nitride films 102a and 102b in the logic part and the memory part are both exposed. Therefore, for example, a part of the silicon nitride films 102a and 102b is additionally etched isotropically by wet etching with phosphoric acid at about 160 ° C. (this process is referred to as a second pull back). By the second pullback, as shown in FIG. 5E, the end portion of the silicon nitride film 102b in the memory portion recedes from the corner of the trench 104b by a length W12. Further, the end portion of the silicon nitride film 102a in the logic portion recedes from the corner of the trench 104a by a length W11 + W12.
　次に、高密度プラズマ（ＨＤＰ；High Density Plasma）ＣＶＤ法により、前記トレンチ１０４ａ，１０４ｂをそれぞれ充填するように素子分離絶縁膜１０７ａ，１０７ｂを、例えば４５０ｎｍ程度の厚みで形成する。引き続いて、素子分離絶縁膜１０７ａ，１０７ｂを改質するための焼きしめを、例えば８００℃、１０分程度の条件で行う。焼きしめにより、素子分離絶縁膜１０７ａ，１０７ｂの性質は熱酸化膜のそれに近づき高品質化される。 Next, element isolation insulating films 107a and 107b are formed with a thickness of, for example, about 450 nm so as to fill the trenches 104a and 104b by high-density plasma (HDP) CVD. Subsequently, baking for modifying the element isolation insulating films 107a and 107b is performed under conditions of, for example, 800 ° C. and about 10 minutes. By baking, the properties of the element isolation insulating films 107a and 107b approach that of the thermal oxide film, and the quality is improved.
　次に、ＣＭＰ（Chemical Mechanical Polishing）法により、窒化シリコン膜１０２ａ，１０２ｂをエッチングストッパとして、図５Ｆに示すように、トレンチ部を除く素子分離絶縁膜１０７ａ，１０７ｂを除去する。 Next, as shown in FIG. 5F, the element isolation insulating films 107a and 107b excluding the trench portions are removed by CMP (Chemical-Mechanical Polishing) method using the silicon nitride films 102a and 102b as etching stoppers.
　次に、図５Ｇのように、例えば１６０℃程度の燐酸を用いたウェットエッチングにより、窒化シリコン膜１０２ａ，１０２ｂを除去する。この結果、ロジック部の素子分離絶縁膜１０７ａは、メモリ部の素子分離絶縁膜１０７ｂに比べて、トレンチ１０４ａの角部からＷ１１だけ長く素子分離領域の外方に延在する。 Next, as shown in FIG. 5G, the silicon nitride films 102a and 102b are removed by wet etching using phosphoric acid at about 160 ° C., for example. As a result, the element isolation insulating film 107a in the logic portion extends outward from the element isolation region by W11 longer than the corner portion of the trench 104a as compared with the element isolation insulating film 107b in the memory portion.
　続いて、犠牲酸化膜１０１越しに不純物をウェルおよびチャネル領域に注入する。注入条件はトランジスタの設計によりさまざまであるが、ウェル深さは例えば１５０ｎｍ程度、チャネル不純物濃度は１×１０17atm/cm3から１×１０19atm/cm3程度となるように制御する。続いて、例えば１０００℃程度のランプアニールによって活性化と結晶回復を行う。これにより活性領域１０８ａ，１０８ｂが形成される。 Subsequently, impurities are implanted into the well and channel region through the sacrificial oxide film 101. The implantation conditions vary depending on the transistor design, but the well depth is controlled to be, for example, about 150 nm and the channel impurity concentration is about 1 × 10 17 atm / cm 3 to 1 × 10 19 atm / cm 3 . Subsequently, activation and crystal recovery are performed by lamp annealing at about 1000 ° C., for example. As a result, active regions 108a and 108b are formed.
　その後、緩衝フッ酸溶液を用いたウェットエッチングにより犠牲酸化膜１０１を除去する。このとき、図５Ｈに示すように、素子分離絶縁膜１０７ａ，１０７ｂもエッチングされる。その後、例えば８５０℃程度の湿式アニールによって、図５Ｉに示すように、ゲート絶縁膜（酸化膜）１０９ａ，１０９ｂを形成する。ゲート絶縁膜１０９ａ，１０９ｂは、半導体装置１０を構成する複数の半導体素子１０ａ，１０ｂのうち、高耐圧トランジスタから順に形成される。高耐圧トランジスタの酸化膜厚は、例えば３．３Ｖ設計時で７ｎｍ程度である。ゲート酸化膜１０９ａ，１０９ｂの膜厚が薄いコアトランジスタ領域では、先に形成された厚いゲート絶縁膜１０９ａ，１０９ｂをフッ酸溶液により一度エッチングし、その後３ｎｍ以下の薄いゲート絶縁膜１０９ａ，１０９ｂを再度形成する。この過程で素子分離絶縁膜１０７ａ，１０７ｂはさらにエッチングされ、最終的な形状となる。ここで、上述のように、メモリ部の窒化シリコン膜１０２ｂのプルバック量はロジック部の窒化シリコン膜１０２ａに比べて少ないため、図５Ｉに示すように、メモリ部における活性領域１０８ｂ近傍のＳＴＩ絶縁膜の窪み部１１０ｂはロジック部の窪み部１１０ａに比べて深く形成される。 Thereafter, the sacrificial oxide film 101 is removed by wet etching using a buffered hydrofluoric acid solution. At this time, as shown in FIG. 5H, the element isolation insulating films 107a and 107b are also etched. Thereafter, gate insulating films (oxide films) 109a and 109b are formed by wet annealing at, eg, about 850 ° C., as shown in FIG. 5I. The gate insulating films 109 a and 109 b are formed in order from the high breakdown voltage transistor among the plurality of semiconductor elements 10 a and 10 b constituting the semiconductor device 10. The oxide film thickness of the high voltage transistor is, for example, about 7 nm at the time of 3.3V design. In the core transistor region where the gate oxide films 109a and 109b are thin, the previously formed thick gate insulating films 109a and 109b are etched once with a hydrofluoric acid solution, and then the thin gate insulating films 109a and 109b of 3 nm or less are again formed. Form. In this process, the element isolation insulating films 107a and 107b are further etched to have a final shape. Here, as described above, since the pull back amount of the silicon nitride film 102b in the memory portion is smaller than that in the silicon nitride film 102a in the logic portion, as shown in FIG. 5I, the STI insulating film in the vicinity of the active region 108b in the memory portion. The depression 110b is formed deeper than the depression 110a of the logic part.
　その後、公知の方法により、図２に示すように、ゲート電極１１１ａ，１１１ｂを形成し、Extension/Haloイオンを注入してExtension/Halo拡散層１１８ａ，１１８ｂを形成する。また、サイドウォール１１２ａ，１１２ｂを形成する。次に、ソース・ドレイン領域１１３ａ，１１３ｂ，１１５ａ、１１５ｂにイオンを注入し、注入したイオンを活性化するための活性化アニールを行う。さらにシリサイド層１１７ａ，１１７ｂを形成し、ドレイン電極１１４ａ，１１４ｂおよびソース電極１１６ａ、１１６ｂを設置する。ゲート絶縁膜１０９ａ，１０９ｂおよびゲート電極１１１ａ，１１１ｂは、窪み部１１０ａ，１１０ｂにより露出される活性領域１０８ａ，１０８ｂの側面に延在して形成される。このような工程を経て、半導体素子１０ａ，１０ｂが形成される。 Thereafter, as shown in FIG. 2, gate electrodes 111a and 111b are formed by a known method, and Extension / Halo ions are implanted to form Extension / Halo diffusion layers 118a and 118b. Further, sidewalls 112a and 112b are formed. Next, ions are implanted into the source / drain regions 113a, 113b, 115a, and 115b, and activation annealing is performed to activate the implanted ions. Further, silicide layers 117a and 117b are formed, and drain electrodes 114a and 114b and source electrodes 116a and 116b are provided. The gate insulating films 109a and 109b and the gate electrodes 111a and 111b are formed to extend to the side surfaces of the active regions 108a and 108b exposed by the depressions 110a and 110b. Through these steps, the semiconductor elements 10a and 10b are formed.
　さらに、ロジック部にはロジック回路を、メモリ部にはメモリ回路を形成する。これら回路は同時に形成されてもよく、又は別々に形成されてもよい。別々に形成する場合は、例えば、メモリ部をマスクし、ロジック回路を形成した後に、メモリ部のマスクを除去し、ロジック部をマスクして、メモリ回路を形成してもよい。或いは、その逆の順序で形成されてもよい。なお、これら回路の形成は、当業者にとって公知の方法を用いることができる。このような工程により、半導体装置１０が形成される。 Furthermore, a logic circuit is formed in the logic part, and a memory circuit is formed in the memory part. These circuits may be formed simultaneously or separately. In the case of forming separately, for example, after the memory portion is masked and the logic circuit is formed, the mask of the memory portion is removed and the logic portion is masked to form the memory circuit. Or you may form in the reverse order. These circuits can be formed by methods known to those skilled in the art. By such a process, the semiconductor device 10 is formed.
　本実施形態の半導体装置１０の製造方法では、メモリ部のみに酸化膜１０６ｂを形成し、ロジック部においてのみ、窒化シリコン膜１０２ａをエッチングする。更にメモリ部の酸化膜１０６ｂを除去した上で、ロジック部の窒化シリコン膜１０２ａおよびメモリ部の窒化シリコン膜１０２ｂをエッチングする。これにより、ロジック部の素子分離絶縁膜１０７ａの凹み部１１０ａを、メモリ部の素子分離絶縁膜１０７ｂの凹み部１１０ｂより浅く形成することができる。あるいはロジック部の素子分離絶縁膜１０７ａには凹み部１１０ａを設けず、メモリ部の素子分離絶縁膜１０７ｂにのみ凹み部１１０ｂを形成することができる。従って、メモリ部の活性領域１０８ｂに隣接した素子分離領域のみを掘り込んで、トレンチ１０４ｂの側面領域もチャネルとして利用することが可能な半導体装置を提供することができる。本実施形態では、掘り込まれる領域を活性領域１０８ａ，１０８ｂの近傍領域に限ることで、その後に形成されるゲート電極１１１ａ，１１１ｂの表面の段差が減少する。そのため、ゲート電極１１１ａ，１１１ｂの加工が容易であり、ゲート加工精度を維持することができる。これにより、セルサイズの増加を防ぎつつゲート幅を増加し、それに伴いセルトランジスタの駆動能力を増加させることができる。更にはセルトランジスタのランダムばらつきを改善することができる。 In the manufacturing method of the semiconductor device 10 of the present embodiment, the oxide film 106b is formed only in the memory portion, and the silicon nitride film 102a is etched only in the logic portion. Further, after removing the oxide film 106b in the memory portion, the silicon nitride film 102a in the logic portion and the silicon nitride film 102b in the memory portion are etched. Thereby, the recess 110a of the element isolation insulating film 107a in the logic part can be formed shallower than the recess 110b in the element isolation insulating film 107b of the memory part. Alternatively, the recess 110a can be formed only in the element isolation insulating film 107b of the memory portion without providing the recess 110a in the element isolation insulating film 107a of the logic portion. Therefore, it is possible to provide a semiconductor device in which only the element isolation region adjacent to the active region 108b of the memory portion is dug and the side region of the trench 104b can be used as a channel. In the present embodiment, by limiting the region to be dug to the vicinity of the active regions 108a and 108b, the steps on the surfaces of the gate electrodes 111a and 111b formed thereafter are reduced. Therefore, processing of the gate electrodes 111a and 111b is easy, and the gate processing accuracy can be maintained. As a result, the gate width can be increased while preventing the cell size from increasing, and the driving capability of the cell transistor can be increased accordingly. Furthermore, random variations of cell transistors can be improved.
　（第２実施形態）
　第２実施形態に係る半導体装置及び半導体装置の製造方法について図を用いて説明する。本実施形態の半導体装置が第１実施形態の半導体装置と異なるのは、本実施形態ではトレンチに埋め込まれる素子分離絶縁膜が、第１の埋め込み絶縁膜と第２の埋め込み絶縁膜から構成される点と、素子分離領域のＣＭＰ工程後にメモリ部の第１の埋め込み絶縁膜の一部をあらかじめエッチングしておくことにより、最終的な素子分離絶縁膜の窪み形状をメモリ部において深く掘り下げられるようにする点にある。 (Second Embodiment)
A semiconductor device and a method for manufacturing the semiconductor device according to the second embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is different from the semiconductor device of the first embodiment. In this embodiment, the element isolation insulating film embedded in the trench is composed of the first embedded insulating film and the second embedded insulating film. In addition, by etching a part of the first buried insulating film of the memory portion in advance after the CMP process of the element isolation region, the final recess shape of the element isolation insulating film can be deeply digged in the memory portion. There is in point to do.
　本実施形態に係る半導体装置２０は、図６及び図７に示すように第１の領域であるロジック部と、第２の領域であるメモリ部（ＳＲＡＭ部）と、２つの領域を備える。ロジック部には、複数の半導体素子２０ａが形成される。半導体素子２０ａはＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）である。また、メモリ部にも同様に複数の半導体素子２０ｂが形成され、半導体素子２０ｂは、ＭＩＳＦＥＴである。ロジック部とメモリ部の構造を区別するため、便宜的にロジック部の構成要素に係る符号の末尾にはａを、メモリ部の構成要素に係る符号の末尾にはｂをそれぞれ付加する。 As shown in FIGS. 6 and 7, the semiconductor device 20 according to the present embodiment includes two areas, a logic section that is a first area and a memory section (SRAM section) that is a second area. A plurality of semiconductor elements 20a are formed in the logic portion. The semiconductor element 20a is a MISFET (Metal | Insulator | Semiconductor | Field | Effect | Transistor). Similarly, a plurality of semiconductor elements 20b are formed in the memory portion, and the semiconductor elements 20b are MISFETs. In order to distinguish between the structure of the logic part and the memory part, a is added to the end of the code related to the component of the logic part and b is added to the end of the code related to the component of the memory part for convenience.
　半導体素子２０ａは、図６に示すように半導体基板（シリコン基板）２００と、トレンチ２０４ａと、熱酸化膜２０５ａと、第１の素子分離絶縁膜（埋め込み絶縁膜）２０６ａと、第２の素子分離絶縁膜（埋め込み絶縁膜）２０７ａと、活性領域２０９ａと、ゲート絶縁膜２１０ａと、窪み部（凹み部）２１１ａと、ゲート電極２１２ａと、サイドウォール２１３ａと、を備える。また、図７に示すように、半導体素子２０ａはドレイン領域２１４ａ、ドレイン電極２１５ａ、ソース領域２１６ａ、ソース電極２１７ａ、シリサイド層２１８ａ、およびExtension/Halo拡散層２１９ａ等を備える。本実施形態では素子分離絶縁膜は第１の素子分離絶縁膜（埋め込み絶縁膜）２０６ａと第２の素子分離絶縁膜（埋め込み絶縁膜）２０７ａとを備える。また、窪み部２１１ａは、第１の埋め込み絶縁膜２０６ａ及び／又は第２の埋め込み絶縁膜２０７ａに形成されている。 As shown in FIG. 6, the semiconductor element 20a includes a semiconductor substrate (silicon substrate) 200, a trench 204a, a thermal oxide film 205a, a first element isolation insulating film (buried insulating film) 206a, and a second element isolation. An insulating film (buried insulating film) 207a, an active region 209a, a gate insulating film 210a, a depression (depression) 211a, a gate electrode 212a, and a sidewall 213a are provided. Further, as shown in FIG. 7, the semiconductor element 20a includes a drain region 214a, a drain electrode 215a, a source region 216a, a source electrode 217a, a silicide layer 218a, an extension / halo diffusion layer 219a, and the like. In the present embodiment, the element isolation insulating film includes a first element isolation insulating film (buried insulating film) 206a and a second element isolation insulating film (buried insulating film) 207a. The recess 211a is formed in the first buried insulating film 206a and / or the second buried insulating film 207a.
　半導体基板２００は、シリコン基板であり、半導体基板２００の上面には、トレンチ２０４ａと、活性領域２０９ａと、ゲート絶縁膜２１０ａとが形成されている。 The semiconductor substrate 200 is a silicon substrate, and a trench 204a, an active region 209a, and a gate insulating film 210a are formed on the upper surface of the semiconductor substrate 200.
　トレンチ２０４ａは、半導体基板２００に形成され、半導体素子２０ａを囲み、隣接する半導体素子から分離するように形成されている。また、トレンチ２０４ａ内には第１の素子分離絶縁膜２０６ａと第２の素子分離絶縁膜２０７ａとが形成されている。 The trench 204a is formed in the semiconductor substrate 200, surrounds the semiconductor element 20a, and is formed so as to be separated from the adjacent semiconductor element. A first element isolation insulating film 206a and a second element isolation insulating film 207a are formed in the trench 204a.
　熱酸化膜２０５ａは、例えばシリコン酸化膜から形成され、トレンチ２０４ａの表面に形成されている。 The thermal oxide film 205a is formed of, for example, a silicon oxide film, and is formed on the surface of the trench 204a.
　第１の素子分離絶縁膜（埋め込み絶縁膜）２０６ａは、例えば酸窒化シリコン膜から形成されている。なお、第１の素子分離絶縁膜２０６ａは、窒素とは別の元素、例えば炭素やフッ素を導入した酸化膜を用いてもよい。第１の素子分離絶縁膜２０６ａは、図６に示すようにトレンチ２０４ａ表面に形成された熱酸化膜２０５ａの表面を覆うように形成されている。 The first element isolation insulating film (buried insulating film) 206a is formed of, for example, a silicon oxynitride film. Note that the first element isolation insulating film 206a may be an oxide film into which an element other than nitrogen, for example, carbon or fluorine is introduced. As shown in FIG. 6, the first element isolation insulating film 206a is formed so as to cover the surface of the thermal oxide film 205a formed on the surface of the trench 204a.
　第２の素子分離絶縁膜（埋め込み絶縁膜）２０７ａは、例えばシリコン酸化膜から形成され、トレンチ２０４ａを充填する。第１の素子分離絶縁膜２０６ａおよび第２の素子分離絶縁膜２０７ａが熱酸化膜２０５ａに隣接する領域には、窪み部（凹み部）２１１ａが形成されている。窪み部２１１ａは、第１の素子分離絶縁膜２０６ａと第２の素子分離絶縁膜２０７ａとにわたって、又は第１の素子分離絶縁膜２０６ａに形成されている。なお、図６に示す半導体素子２０ａでは、窪み部２１１ａが形成される場合を例に挙げて説明しているが、半導体素子２０ａは窪み部２１１ａを備えなくとも良い。 The second element isolation insulating film (buried insulating film) 207a is formed of, for example, a silicon oxide film and fills the trench 204a. In the region where the first element isolation insulating film 206a and the second element isolation insulating film 207a are adjacent to the thermal oxide film 205a, a recess (depression) 211a is formed. The recess 211a is formed across the first element isolation insulating film 206a and the second element isolation insulating film 207a or in the first element isolation insulating film 206a. In the semiconductor element 20a shown in FIG. 6, the case where the recess 211a is formed is described as an example. However, the semiconductor element 20a may not include the recess 211a.
　活性領域２０９ａは、シリコン基板２００の上面に形成され、不純物が拡散された領域である。活性領域２０９ａはゲート電極２１０ａに電圧が印加されるとチャネル領域として機能する。 The active region 209a is a region formed on the upper surface of the silicon substrate 200 and in which impurities are diffused. The active region 209a functions as a channel region when a voltage is applied to the gate electrode 210a.
　ゲート絶縁膜２１０ａは、例えば、シリコン酸化膜から構成され、トレンチ２０４ａによって囲まれた活性領域２０９ａ上に形成されている。 The gate insulating film 210a is made of, for example, a silicon oxide film, and is formed on the active region 209a surrounded by the trench 204a.
　ゲート電極２１２ａは、例えばポリシリコン等から構成される。ゲート電極２１２ａの周囲には図６に示すように絶縁材料、例えばシリコン窒化膜等から構成されるサイドウォール２１３ａが形成されている。 The gate electrode 212a is made of, for example, polysilicon. As shown in FIG. 6, a sidewall 213a made of an insulating material such as a silicon nitride film is formed around the gate electrode 212a.
　半導体素子２０ｂは、半導体素子２０ａとほぼ同じ構成であり、半導体基板（シリコン基板）２００と、トレンチ２０４ｂと、熱酸化膜２０５ｂと、第１の素子分離絶縁膜２０６ｂと、第２の素子分離絶縁膜２０７ｂと、活性領域２０９ｂと、ゲート絶縁膜２１０ｂと、窪み部（凹み部）２１１ｂと、ゲート電極２１２ｂと、サイドウォール２１３ｂとを備える。また、図７に示すように、半導体素子２０ｂはドレイン領域２１４ｂ、ドレイン電極２１５ｂ、ソース領域２１６ｂ、ソース電極２１７ｂ、シリサイド層２１８ｂ、およびExtension/Halo拡散層２１９ｂ等を備える。また、半導体素子２０ｂでは、窪み部２１１ｂは、第１の素子分離絶縁膜２０６ｂおよび第２の素子分離絶縁膜２０７ｂに亘って形成されている。 The semiconductor element 20b has substantially the same configuration as the semiconductor element 20a, and includes a semiconductor substrate (silicon substrate) 200, a trench 204b, a thermal oxide film 205b, a first element isolation insulating film 206b, and a second element isolation insulation. A film 207b, an active region 209b, a gate insulating film 210b, a depression (depression) 211b, a gate electrode 212b, and a sidewall 213b are provided. As shown in FIG. 7, the semiconductor element 20b includes a drain region 214b, a drain electrode 215b, a source region 216b, a source electrode 217b, a silicide layer 218b, an Extension / Halo diffusion layer 219b, and the like. In the semiconductor element 20b, the recess 211b is formed across the first element isolation insulating film 206b and the second element isolation insulating film 207b.
　ロジック部の半導体素子２０ａとメモリ部の半導体素子２０ｂとが異なるのは、半導体素子２０ａの凹み部２１１ａの深さが、半導体素子２０ｂの第２の素子分離絶縁膜２０７ｂに形成された凹み部２１１ｂの深さより浅い、もしくは凹み部２１１ａが形成されない点にある。なお、第２の素子分離絶縁膜２０７ａと２０７ｂの高さは、ほぼ同じである。このように、メモリ部の凹み部２１１ｂを、ロジック部の凹み部２１１ａより深く形成することにより、トレンチ２０４ｂの開口近傍領域を掘り下げることができる。これにより、ゲート絶縁膜２１０ｂを、半導体基板２００上のトレンチ２０４ｂで囲まれた領域と、トレンチ２０４ｂの開口近傍領域とに形成することができ、半導体素子２０ｂの実効的なチャネル幅を増加させることができる。また、本実施形態では、第２の素子分離絶縁膜２０７ａ，２０７ｂの絶縁膜の高さをロジック部とメモリ部とで変化させずに、メモリ部の半導体素子の実効的なチャネル幅を増加させることができる。 The difference between the semiconductor element 20a in the logic portion and the semiconductor element 20b in the memory portion is that the depth of the recessed portion 211a of the semiconductor element 20a is the recessed portion 211b formed in the second element isolation insulating film 207b of the semiconductor element 20b. This is in that the depth is less than the depth or the recess 211a is not formed. Note that the heights of the second element isolation insulating films 207a and 207b are substantially the same. Thus, by forming the recessed portion 211b of the memory portion deeper than the recessed portion 211a of the logic portion, the region near the opening of the trench 204b can be dug down. Thereby, the gate insulating film 210b can be formed in a region surrounded by the trench 204b on the semiconductor substrate 200 and a region near the opening of the trench 204b, and the effective channel width of the semiconductor element 20b is increased. Can do. Further, in this embodiment, the effective channel width of the semiconductor element in the memory unit is increased without changing the height of the insulating films of the second element isolation insulating films 207a and 207b between the logic unit and the memory unit. be able to.
　以下、本実施形態に係る半導体装置の製造方法を図８Ａ～図８Ｊを用いて説明する。なお、図８Ａ～図８Ｊは、半導体装置のＭＩＳＦＥＴをゲート幅方向に切った断面図である。なお、比較のためにロジック部とメモリ部の断面図を逐次並べて示している。 Hereinafter, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 8A to 8J. 8A to 8J are cross-sectional views in which the MISFET of the semiconductor device is cut in the gate width direction. For comparison, cross-sectional views of the logic portion and the memory portion are sequentially shown.
　まず、図８Ａに示すように、シリコン基板２００上に、例えば１０ｎｍ程度の膜厚の犠牲酸化膜（第一の絶縁膜）２０１を熱酸化法により形成する。続いて犠牲酸化膜２０１の上に、減圧ＣＶＤ法によって窒化シリコン膜（第二の絶縁膜）２０２を形成する。窒化シリコン膜２０２の厚みは、５０ｎｍ～１５０ｎｍ程度が好ましく、例えば１００ｎｍ程度の厚みに形成する。次に、窒化シリコン膜２０２上に素子分離領域に対応した開口部を有するレジストパターン２０３ａ，２０３ｂを形成する。 First, as shown in FIG. 8A, a sacrificial oxide film (first insulating film) 201 having a thickness of, for example, about 10 nm is formed on a silicon substrate 200 by a thermal oxidation method. Subsequently, a silicon nitride film (second insulating film) 202 is formed on the sacrificial oxide film 201 by low pressure CVD. The thickness of the silicon nitride film 202 is preferably about 50 nm to 150 nm, and is formed to a thickness of about 100 nm, for example. Next, resist patterns 203 a and 203 b having openings corresponding to the element isolation regions are formed on the silicon nitride film 202.
　次に、レジストパターン２０３ａ，２０３ｂをマスクとして、フッ素系ガス（ＣＨＦ3やＣ2Ｆ6など）を主体としたエッチングガスを使用した異方性プラズマエッチングにより窒化シリコン膜２０２の一部を除去する。これにより、レジストパターン２０３ａ，２０３ｂに応じて窒化シリコン膜２０２ａ，２０２ｂが残存する。その後、レジストパターン２０３ａ，２０３ｂをＳＰＭ（硫酸／過酸化水素水）およびＡＰＭ（アンモニア／過酸化水素水）を用いた洗浄によって剥離する。さらにフッ酸緩衝溶液を主体としたウェットエッチングにより、犠牲酸化膜２０１を除去する。 Next, a part of the silicon nitride film 202 is removed by anisotropic plasma etching using an etching gas mainly containing a fluorine-based gas (CHF 3 , C 2 F 6, etc.) using the resist patterns 203 a and 203 b as a mask. . Thereby, the silicon nitride films 202a and 202b remain according to the resist patterns 203a and 203b. Thereafter, the resist patterns 203a and 203b are peeled off by cleaning using SPM (sulfuric acid / hydrogen peroxide solution) and APM (ammonia / hydrogen peroxide solution). Further, the sacrificial oxide film 201 is removed by wet etching mainly using a hydrofluoric acid buffer solution.
　引き続いて、塩素系ガス（ＣＣｌ4やＣｌ2など）を主体としたエッチングガスを使用した異方性プラズマエッチングにより、シリコン基板２００をエッチング（トレンチエッチング）し、トレンチ２０４ａ，２０４ｂを形成する。エッチング深さは、２００ｎｍ～４００ｎｍ程度が好ましく、例えば３００ｎｍ程度である。引き続いて、酸素雰囲気中での熱酸化を行うことにより、図８Ｂに示すように、トレンチ２０４ａ，２０４ｂの露出面に数ｎｍ程度の厚みの薄い熱酸化膜２０５ａ，２０５ｂを形成する。さらに、結晶性の回復およびトレンチの角部を丸めるために、追加的に酸化性雰囲気内で１０００℃以上の高温アニールを実施する。このような熱酸化膜の形成による方法のほかに、フッ酸系溶液で洗浄した後に水素雰囲気中８００℃程度でアニールする方法もある。この方法によればシリコン原子の再構成が起こり、結晶性の回復およびトレンチの角部が丸まるといった効果を得ることができる。この場合、熱酸化膜２０５ａ，２０５ｂは形成されない、あるいは、自然酸化膜厚の程度に極めて薄い膜が形成される。なお、ここまでの工程は、第１実施形態とほぼ同じである。また、第１実施形態では、この後にプルバック工程を実施するが、本実施形態ではプルバック工程を行わなくてもよい。 Subsequently, the silicon substrate 200 is etched (trench etching) by anisotropic plasma etching using an etching gas mainly composed of a chlorine-based gas (CCl 4 or Cl 2 ) to form trenches 204a and 204b. The etching depth is preferably about 200 nm to 400 nm, for example, about 300 nm. Subsequently, by performing thermal oxidation in an oxygen atmosphere, thin thermal oxide films 205a and 205b having a thickness of about several nm are formed on the exposed surfaces of the trenches 204a and 204b, as shown in FIG. 8B. Further, in order to recover the crystallinity and round the corners of the trench, a high temperature annealing at 1000 ° C. or higher is additionally performed in an oxidizing atmosphere. In addition to such a method of forming a thermal oxide film, there is a method of annealing at about 800 ° C. in a hydrogen atmosphere after washing with a hydrofluoric acid solution. According to this method, reconfiguration of silicon atoms occurs, and it is possible to obtain effects such as recovery of crystallinity and rounding of the corners of the trench. In this case, the thermal oxide films 205a and 205b are not formed, or a film extremely thin to the extent of the natural oxide film thickness is formed. The steps so far are almost the same as those in the first embodiment. In the first embodiment, the pullback process is performed after this, but in the present embodiment, the pullback process may not be performed.
　次に、プラズマＣＶＤ法により、図８Ｃに示すように、第１の素子分離絶縁膜２０６ａ，２０６ｂを薄く等方的に、例えば１０ｎｍ程度の厚みに形成する。ここで第１の素子分離絶縁膜２０６ａ，２０６ｂとしては酸窒化シリコン膜を用いてもよく、窒素とは別の元素、例えば炭素やフッ素を導入した絶縁膜を用いてもよい。続いて、高密度プラズマ（ＨＤＰ）ＣＶＤ法により、図８Ｄに示すように、トレンチ２０４ａ，２０４ｂを充填するように第２の素子分離絶縁膜２０７ａ，２０７ｂを形成する。第２の素子分離絶縁膜２０７ａ，２０７ｂは、例えば４５０ｎｍの厚みに形成する。 Next, as shown in FIG. 8C, the first element isolation insulating films 206a and 206b are thinly and isotropically formed to a thickness of about 10 nm, for example, by plasma CVD. Here, a silicon oxynitride film may be used as the first element isolation insulating films 206a and 206b, or an insulating film into which an element other than nitrogen, for example, carbon or fluorine is introduced may be used. Subsequently, as shown in FIG. 8D, second element isolation insulating films 207a and 207b are formed by high density plasma (HDP) CVD so as to fill the trenches 204a and 204b. The second element isolation insulating films 207a and 207b are formed to a thickness of 450 nm, for example.
　次に、第２の素子分離絶縁膜２０７ａ，２０７ｂを改質するための焼きしめを、８００℃下で、１０分程度行う。焼きしめにより、第２の素子分離絶縁膜２０７ａ，２０７ｂの性質は熱酸化膜の性質に近づき高品質化される。この工程で重要なことは、次のエッチング工程で、第１の素子分離絶縁膜２０６ａ，２０６ｂのエッチングレートが、第２の素子分離絶縁膜２０７ａ，２０７ｂのエッチングレートに比べ、好ましくは２倍以上となるようにそれぞれの絶縁膜を形成することにある。 Next, baking for modifying the second element isolation insulating films 207a and 207b is performed at 800 ° C. for about 10 minutes. By baking, the properties of the second element isolation insulating films 207a and 207b are close to those of the thermal oxide film, and the quality is improved. What is important in this step is that in the next etching step, the etching rate of the first element isolation insulating films 206a and 206b is preferably at least twice that of the second element isolation insulating films 207a and 207b. Each insulating film is formed so that
　次に、図８Ｅに示すように、ＣＭＰ（Chemical Mechanical Polishing）法により、窒化シリコン膜２０２ａ，２０２ｂをエッチングストッパとして、トレンチ２０４ａ，２０４ｂに対応する領域以外の、第２の素子分離絶縁膜２０７ａ，２０７ｂと第１の素子分離絶縁膜２０６ａ，２０６ｂを除去する。 Next, as shown in FIG. 8E, the second element isolation insulating films 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207b and the first element isolation insulating films 206a and 206b are removed.
　次に、図８Ｆに示すように、レジストを塗布・現像し、メモリ部に対応する開口を有し、メモリ部を露出させたレジストパターン２０８ａを形成する。続いて、レジストパターン２０８ａをマスクとして、図８Ｇに示すようにメモリ部の第１の素子分離絶縁膜２０６ｂの一部を選択的にエッチングする。ここで、エッチングはフッ酸溶液を用いた、ウェットエッチングにより行ってもよく、第１の素子分離絶縁膜２０６ｂを選択的にエッチングすることが可能であればドライエッチングを用いても良い。 Next, as shown in FIG. 8F, a resist is applied and developed to form a resist pattern 208a having an opening corresponding to the memory portion and exposing the memory portion. Subsequently, using the resist pattern 208a as a mask, a part of the first element isolation insulating film 206b of the memory portion is selectively etched as shown in FIG. 8G. Here, the etching may be performed by wet etching using a hydrofluoric acid solution, and dry etching may be used as long as the first element isolation insulating film 206b can be selectively etched.
　次に、レジストパターン２０８ａをＳＰＭ及びＡＰＭを用いた洗浄により除去する。更に、１６０℃程度の燐酸を用いたウェットエッチングにより、図８Ｈに示すように窒化シリコン膜２０２ａ，２０２ｂを除去する。 Next, the resist pattern 208a is removed by cleaning using SPM and APM. Further, the silicon nitride films 202a and 202b are removed by wet etching using phosphoric acid at about 160 ° C. as shown in FIG. 8H.
　続いて、犠牲酸化膜２０１越しにウェル領域およびチャネル領域にイオンを注入する。注入条件はトランジスタの設計によりさまざまであるが、ウェル深さは、例えば１５０ｎｍ程度、チャネル不純物濃度は１×１０17atm/cm3～１×１０19atm/cm3程度となるように制御する。引き続いて、１０００℃程度のランプアニールによって活性化と結晶回復を行う。これにより、活性領域２０９ａ，２０９ｂが形成される。その後、緩衝フッ酸溶液を用いたウェットエッチングにより犠牲酸化膜２０１を除去する。このとき、図８Ｉに示すように、第１の素子分離絶縁膜２０６ａ，２０６ｂ及び第２の素子分離絶縁膜２０７ａ，２０７ｂもエッチングされる。 Subsequently, ions are implanted into the well region and the channel region through the sacrificial oxide film 201. The implantation conditions vary depending on the transistor design. For example, the well depth is controlled to be about 150 nm, and the channel impurity concentration is controlled to be about 1 × 10 17 atm / cm 3 to 1 × 10 19 atm / cm 3 . Subsequently, activation and crystal recovery are performed by lamp annealing at about 1000 ° C. Thereby, the active regions 209a and 209b are formed. Thereafter, the sacrificial oxide film 201 is removed by wet etching using a buffered hydrofluoric acid solution. At this time, as shown in FIG. 8I, the first element isolation insulating films 206a and 206b and the second element isolation insulating films 207a and 207b are also etched.
　その後、図８Ｊに示すように、ゲート絶縁膜（酸化膜）２１０ａ，２１０ｂを形成する。ゲート絶縁膜２１０ａ，２１０ｂは、半導体装置２０を構成する複数の半導体素子２０ａ，２０ｂのうち、高耐圧トランジスタから順に形成される。高耐圧トランジスタの酸化膜厚は例えば３．３Ｖ設計時で７ｎｍ程度である。ここでゲート酸化膜の膜厚が薄いコアトランジスタ領域では、先に形成された厚いゲート絶縁膜２１０ａ，２１０ｂをフッ酸溶液により一度エッチングし、その後３ｎｍ以下の薄いゲート絶縁膜２１０ａ，２１０ｂを再度形成する。この過程で第１の素子分離絶縁膜２０６ａ，２０６ｂ及び第２の素子分離絶縁膜２０７ａ，２０７ｂはさらにエッチングされ、最終的な形状となる。ここで、メモリ部の第１の素子分離絶縁膜２０６ｂはロジック部の第１の素子分離絶縁膜２０６ａに比べて多くエッチングされている。このため、図８Ｊに示すように、メモリ部における活性領域２０９ｂ近傍の窪み部（凹み部）２１１ｂはロジック部の窪み部（凹み部）２１１ａに比べて深く形成される。なお、熱酸化膜２０５ａ，２０５ｂは薄いため、第１の素子分離絶縁膜２０６ａ，２０６ｂが窪んでエッチングされる際、熱酸化膜２０５ａ，２０５ｂは、第１の素子分離絶縁膜２０６ａ，２０６ｂと同程度の高さまで同時にエッチングされる。 Thereafter, as shown in FIG. 8J, gate insulating films (oxide films) 210a and 210b are formed. The gate insulating films 210 a and 210 b are formed in order from the high breakdown voltage transistor among the plurality of semiconductor elements 20 a and 20 b constituting the semiconductor device 20. The oxide film thickness of the high voltage transistor is, for example, about 7 nm at the time of 3.3V design. Here, in the core transistor region where the gate oxide film is thin, the previously formed thick gate insulating films 210a and 210b are once etched with a hydrofluoric acid solution, and then the thin gate insulating films 210a and 210b of 3 nm or less are formed again. To do. In this process, the first element isolation insulating films 206a and 206b and the second element isolation insulating films 207a and 207b are further etched to have a final shape. Here, the first element isolation insulating film 206b in the memory portion is etched more than the first element isolation insulating film 206a in the logic portion. For this reason, as shown in FIG. 8J, the dent part (dent part) 211b near the active region 209b in the memory part is formed deeper than the dent part (dent part) 211a of the logic part. Since the thermal oxide films 205a and 205b are thin, when the first element isolation insulating films 206a and 206b are recessed and etched, the thermal oxide films 205a and 205b are the same as the first element isolation insulating films 206a and 206b. It is simultaneously etched to a certain height.
　その後、公知の方法により、図７に示すように、ゲート電極２１２ａ，２１２ｂを形成し、Extension/Haloイオンを注入してExtension/Halo拡散層２１９ａ，２１９ｂを形成する。また、サイドウォール２１３ａ，２１３ｂを形成する。次に、ソース・ドレイン領域２１４ａ，２１４ｂ，２１６ａ、２１６ｂにイオン注入し、注入したイオンを活性化するための活性化アニールを行う。さらにシリサイド層２１８ａ，２１８ｂを形成し、ドレイン電極２１５ａ，２１５ｂおよびソース電極２１７ａ、２１７ｂを設置する。このような工程を経て、図６および図７に示すように半導体素子２０ａ，２０ｂが形成される。 Thereafter, as shown in FIG. 7, gate electrodes 212a and 212b are formed by a known method, and Extension / Halo ions are implanted to form Extension / Halo diffusion layers 219a and 219b. In addition, sidewalls 213a and 213b are formed. Next, ions are implanted into the source / drain regions 214a, 214b, 216a, and 216b, and activation annealing is performed to activate the implanted ions. Further, silicide layers 218a and 218b are formed, and drain electrodes 215a and 215b and source electrodes 217a and 217b are provided. Through these steps, semiconductor elements 20a and 20b are formed as shown in FIGS.
　さらに、ロジック部にはロジック回路を、メモリ部にはメモリ回路を形成する。これら回路は同時に形成されてもよく、又は別々に形成されてもよい。別々に形成する場合は、例えば、メモリ部をマスクし、ロジック回路を形成した後に、メモリ部のマスクを除去し、ロジック部をマスクして、メモリ回路を形成してもよい。或いは、その逆の順序で形成されてもよい。なお、これら回路の形成は、当業者にとって公知の方法を用いることができる。このような工程によって、半導体装置２０が形成される。 Furthermore, a logic circuit is formed in the logic part, and a memory circuit is formed in the memory part. These circuits may be formed simultaneously or separately. In the case of forming separately, for example, after the memory portion is masked and the logic circuit is formed, the mask of the memory portion is removed and the logic portion is masked to form the memory circuit. Or you may form in the reverse order. These circuits can be formed by methods known to those skilled in the art. By such a process, the semiconductor device 20 is formed.
　本実施形態の半導体装置の製造方法では、トレンチ２０４ａ，２０４ｂ内に、第１の埋め込み絶縁膜２０６ａ，２０６ｂと、第２の埋め込み絶縁膜２０７ａ，２０７ｂと、を形成し、メモリ部の第１の埋め込み絶縁膜２０６ｂの上部を選択的にエッチングする。これにより、ロジック部の凹み部２１１ａを、メモリ部の凹み部２１１ｂより浅い又は、凹み部２１１ａを設けないように形成することができる。従って、メモリ部の活性領域２０９ｂに隣接した素子分離領域のみを掘り込んで、トレンチ２０４ｂの側面領域もチャネルとして利用することが可能な半導体装置を提供することができる。本実施形態では、掘り込まれる領域を活性領域の近傍領域に限ることで、半導体素子表面の段差が減少され、ゲート電極２１２ａ，２１２ｂの加工が容易となり、ゲート加工精度を維持することができる。これにより、セルサイズの増加を防ぎつつゲート幅の増加に伴いセルトランジスタの駆動能力を増加させることができ、更にはランダムばらつきを改善することができる。 In the semiconductor device manufacturing method of the present embodiment, first buried insulating films 206a and 206b and second buried insulating films 207a and 207b are formed in the trenches 204a and 204b, and the first buried insulating films 207a and 207b are formed. The upper part of the buried insulating film 206b is selectively etched. Thereby, the recess 211a of the logic part can be formed to be shallower than the recess 211b of the memory part or not to provide the recess 211a. Accordingly, it is possible to provide a semiconductor device in which only the element isolation region adjacent to the active region 209b of the memory portion is dug and the side region of the trench 204b can be used as a channel. In the present embodiment, by limiting the region to be dug to the vicinity of the active region, the step on the surface of the semiconductor element is reduced, the processing of the gate electrodes 212a and 212b is facilitated, and the gate processing accuracy can be maintained. As a result, it is possible to increase the driving capability of the cell transistor as the gate width increases while preventing an increase in cell size, and to improve random variations.
　上記実施形態で開示する各部分の形成方法は、それぞれ必須な部分のみを例示しており、実際の半導体装置には本実施形態には明示されない部分を含むものである。本発明は上述した実施形態に限られず、様々な変形及び応用が可能である。例えば、上述した実施形態で開示した工程の順序は、適宜変化させる、例えば順番を前後させることも可能である。更に、上記各実施形態の構成の一部又は全部を相互に適宜組み合わせてもよい。 The method for forming each part disclosed in the above embodiment exemplifies only essential parts, and an actual semiconductor device includes a part that is not explicitly shown in this embodiment. The present invention is not limited to the above-described embodiments, and various modifications and applications are possible. For example, the order of the steps disclosed in the above-described embodiments can be changed as appropriate, for example, the order can be changed. Furthermore, some or all of the configurations of the above-described embodiments may be appropriately combined with each other.
　なお、図８Ｄに示す工程では、シリコン基板２００と第１の埋め込み絶縁膜２０６ａ，２０６ｂの間には、薄い熱酸化膜が存在しても良い。 In the step shown in FIG. 8D, a thin thermal oxide film may exist between the silicon substrate 200 and the first buried insulating films 206a and 206b.
　また、上述した実施形態ではＳＲＡＭである場合を例に挙げて説明したが、これに限られず、その他のメモリ素子、例えばＤＲＡＭ等に適用することもできる。 In the above-described embodiment, the case of an SRAM has been described as an example. However, the present invention is not limited to this. The present invention can also be applied to other memory elements such as a DRAM.
　１０，２０，５０　半導体装置
　１０ａ，１０ｂ，２０ａ，２０ｂ，５０ａ，５０ｂ　半導体素子
　１００，２００，５００　半導体基板（シリコン基板）
　２０１，１０１　犠牲酸化膜（第一の絶縁膜）
　１０２，１０２ａ，１０２ｂ，２０２，２０２ａ，２０２ｂ　窒化シリコン膜（第二の絶縁膜）
　１０３ａ，１０３ｂ，２０３ａ，２０３ｂ，２０８ａ　レジストパターン
　１０４ａ，１０４ｂ，２０４ａ，２０４ｂ，５０４ａ，５０４ｂ　トレンチ（溝部）
　１０５ａ，１０５ｂ，２０５ａ，２０５ｂ　熱酸化膜
　１０６ｂ　酸化膜
　１０７ａ，１０７ｂ，５０１ａ，５０１ｂ　素子分離絶縁膜（埋め込み絶縁膜）
　１０８ａ，１０８ｂ，２０９ａ，２０９ｂ，５０５ａ，５０５ｂ　活性領域
　１０９ａ，１０９ｂ，２１０ａ，２１０ｂ，５０２ａ，５０２ｂ　ゲート絶縁膜
　１１０ａ，１１０ｂ，２１１ａ，２１１ｂ　窪み部（凹み部）
　１１１ａ，１１１ｂ，２１２ａ，２１２ｂ，５０３ａ，５０３ｂ　ゲート電極
　１１２ａ，１１２ｂ，２１３ａ，２１３ｂ，５０６ａ，５０６ｂ　サイドウォール
　１１３ａ，１１３ｂ，２１４ａ，２１４ｂ　ドレイン領域
　１１４ａ，１１４ｂ，２１５ａ，２１５ｂ　ドレイン電極
　１１５ａ，１１５ｂ，２１６ａ，２１６ｂ　ソース領域
　１１６ａ，１１６ｂ，２１７ａ，２１７ｂ　ソース電極
　１１７ａ，１１７ｂ，２１８ａ，２１８ｂ　シリサイド層
　１１８ａ，１１８ｂ，２１９ａ，２１９ｂ　Extension/Halo拡散層
　２０６ａ，２０６ｂ　第１の素子分離絶縁膜（第１の埋め込み絶縁膜）
　２０７ａ，２０７ｂ　第２の素子分離絶縁膜（第２の埋め込み絶縁膜） 10, 20, 50 Semiconductor device 10a, 10b, 20a, 20b, 50a, 50b Semiconductor element 100, 200, 500 Semiconductor substrate (silicon substrate)
201, 101 Sacrificial oxide film (first insulating film)
102, 102a, 102b, 202, 202a, 202b Silicon nitride film (second insulating film)
103a, 103b, 203a, 203b, 208a Resist pattern 104a, 104b, 204a, 204b, 504a, 504b Trench (groove)
105a, 105b, 205a, 205b Thermal oxide film 106b Oxide film 107a, 107b, 501a, 501b Element isolation insulating film (buried insulating film)
108a, 108b, 209a, 209b, 505a, 505b Active region 109a, 109b, 210a, 210b, 502a, 502b Gate insulating film 110a, 110b, 211a, 211b Recessed portion (recessed portion)
111a, 111b, 212a, 212b, 503a, 503b Gate electrodes 112a, 112b, 213a, 213b, 506a, 506b Side walls 113a, 113b, 214a, 214b Drain regions 114a, 114b, 215a, 215b Drain electrodes 115a, 115b, 216a, 216b Source region 116a, 116b, 217a, 217b Source electrode 117a, 117b, 218a, 218b Silicide layer 118a, 118b, 219a, 219b Extension / Halo diffusion layer 206a, 206b First element isolation insulating film (first buried insulating film )
207a, 207b Second element isolation insulating film (second buried insulating film)

Claims (14)

  1. 　第１の領域及び第２の領域を有する半導体基板と、
    　前記半導体基板の前記第１の領域に形成された第１の活性領域と、
    　前記半導体基板の前記第２の領域に形成された第２の活性領域と、
    　前記第１の領域に形成され、前記第１の活性領域を定義する第１の溝部と、
    　前記第２の領域に形成され、前記第２の活性領域を定義する第２の溝部と、
    　前記第１の溝部に埋め込まれた第１の素子分離絶縁膜と、
    　前記第２の溝部に埋め込まれた第２の素子分離絶縁膜と、
    を有し、
    　前記第２の素子分離絶縁膜には、前記第２の活性領域に隣接した部分に、凹み部が形成されており、
    　該凹み部の底部は、前記第１の素子分離絶縁膜の前記第１の活性領域に隣接した部分よりも低い位置に形成されている、
    ことを特徴とする半導体装置。     A semiconductor substrate having a first region and a second region;
    A first active region formed in the first region of the semiconductor substrate;
    A second active region formed in the second region of the semiconductor substrate;
    A first groove formed in the first region and defining the first active region;
    A second groove formed in the second region and defining the second active region;
    A first element isolation insulating film embedded in the first groove,
    A second element isolation insulating film embedded in the second trench,
    Have
    The second element isolation insulating film has a recess formed in a portion adjacent to the second active region,
    The bottom of the recess is formed at a position lower than a portion of the first element isolation insulating film adjacent to the first active region.
    A semiconductor device.
  2. 　前記第１の素子分離絶縁膜には、前記第１の活性領域に隣接した部分に、前記第２の素子分離絶縁膜に形成された凹み部に比べて浅い凹み部が形成されている、又は、前記第１の素子分離絶縁膜は、前記第１の活性領域に隣接した部分に亘ってほぼ平坦である、
    ことを特徴とする請求項１に記載の半導体装置。     The first element isolation insulating film is formed with a recess that is shallower than the recess formed in the second element isolation insulating film in a portion adjacent to the first active region, or The first element isolation insulating film is substantially flat across a portion adjacent to the first active region.
    The semiconductor device according to claim 1.
  3. 　前記第１の素子分離絶縁膜の表面の高さと、前記第２の素子分離絶縁膜の表面の高さとが実質的に等しい、
    ことを特徴とする請求項１に記載の半導体装置。     The height of the surface of the first element isolation insulating film is substantially equal to the height of the surface of the second element isolation insulating film;
    The semiconductor device according to claim 1.
  4. 　前記第１の領域に形成された電界効果トランジスタと前記第２の領域に形成された電界効果トランジスタとを備え、
    　前記第１の領域に形成された前記電界効果トランジスタのチャネル領域は、前記第１の素子分離絶縁膜に形成された前記凹み部によって露出する前記第１の活性領域の側面に延在して形成されており、
    　前記第２の領域に形成された前記電界効果トランジスタのチャネル領域は、前記第２の素子分離絶縁膜に形成された前記凹み部によって露出する前記第２の活性領域の側面に延在して形成されている、
    ことを特徴とする請求項２に記載の半導体装置。     A field effect transistor formed in the first region and a field effect transistor formed in the second region;
    A channel region of the field effect transistor formed in the first region is formed to extend to a side surface of the first active region exposed by the recess formed in the first element isolation insulating film. Has been
    A channel region of the field effect transistor formed in the second region is formed to extend to a side surface of the second active region exposed by the recess formed in the second element isolation insulating film. Being
    The semiconductor device according to claim 2.
  5. 　前記第１の活性領域と前記第１の素子分離絶縁膜との間と、前記第２の活性領域と前記第２の素子分離絶縁膜との間に、それぞれ熱酸化膜を備える、
    ことを特徴とする請求項２に記載の半導体装置。     Thermal oxide films are provided between the first active region and the first element isolation insulating film and between the second active region and the second element isolation insulating film, respectively.
    The semiconductor device according to claim 2.
  6. 　前記第１の領域に形成されたロジック回路と、前記第２の領域に形成されたメモリ回路とを備える、
    ことを特徴とする請求項２に記載の半導体装置。     A logic circuit formed in the first region and a memory circuit formed in the second region;
    The semiconductor device according to claim 2.
  7. 　前記第１の領域に形成されたロジック回路と、前記第２の領域に形成されたStatic Random Access Memory回路とを備える、
    ことを特徴とする請求項２に記載の半導体装置。     A logic circuit formed in the first region; and a static random access memory circuit formed in the second region;
    The semiconductor device according to claim 2.
  8. 　前記第１の領域に形成された前記電界効果トランジスタのゲート絶縁膜の膜厚と、前記第２の領域に形成された前記電界効果トランジスタのゲート絶縁膜の膜厚と、は等しい、
    ことを特徴とする請求項４に記載の半導体装置。     The thickness of the gate insulating film of the field effect transistor formed in the first region is equal to the thickness of the gate insulating film of the field effect transistor formed in the second region.
    The semiconductor device according to claim 4.
  9. 　第１の領域及び第２の領域を有する半導体基板を用意するステップと、
    　第１の活性領域を定義する第１の溝部を前記半導体基板の前記第１の領域に、第２の活性領域を定義する第２の溝部を前記半導体基板の前記第２の領域に、それぞれ形成するステップと、
    　前記第１の溝部に第１の素子分離絶縁膜を、前記第２の溝部に第２の素子分離絶縁膜を、それぞれ形成するステップと、
    を備え、
    　前記素子分離絶縁膜を形成するステップは、
    　底部が、前記第１の素子分離絶縁膜の前記第１の活性領域に隣接した部分よりも低い位置となるように、前記第２の素子分離絶縁膜の前記第２の活性領域に隣接する部分に凹み部を形成するステップを含む、
    ことを特徴とする半導体装置の製造方法。     Providing a semiconductor substrate having a first region and a second region;
    A first groove defining a first active region is formed in the first region of the semiconductor substrate, and a second groove defining a second active region is formed in the second region of the semiconductor substrate. And steps to
    Forming a first element isolation insulating film in the first groove portion and a second element isolation insulating film in the second groove portion;
    With
    The step of forming the element isolation insulating film includes:
    A portion adjacent to the second active region of the second element isolation insulating film such that a bottom portion is positioned lower than a portion adjacent to the first active region of the first element isolation insulating film. Forming a recess in the
    A method for manufacturing a semiconductor device.
  10. 　前記溝部を形成するステップは、
    　前記半導体基板の表面に第一の絶縁膜と第二の絶縁膜を順番に形成するステップと、
    　前記第一の絶縁膜および前記第二の絶縁膜および前記半導体基板をエッチングして、前記半導体基板上の前記第１の領域と前記第２の領域にそれぞれ溝部を形成するステップと、
    を備え、
    　前記素子分離絶縁膜を形成するステップは、
    　前記半導体基板上にマスクを形成するステップと、
    　前記マスクのうち、前記第１の領域に対応する部分に開口を形成するステップと、
    　前記マスクを用いて、前記第二の絶縁膜を等方的にエッチングするステップと、
    　前記マスクを除去するステップと、
    　前記第１の領域および前記第２の領域の前記第二の絶縁膜を等方的にエッチングするステップと、
    　前記溝部に埋め込み絶縁膜を形成するステップと、
    を含む、
    ことを特徴とする請求項９に記載の半導体装置の製造方法。     The step of forming the groove includes
    Sequentially forming a first insulating film and a second insulating film on the surface of the semiconductor substrate;
    Etching the first insulating film, the second insulating film, and the semiconductor substrate to form grooves in the first region and the second region on the semiconductor substrate; and
    With
    The step of forming the element isolation insulating film includes:
    Forming a mask on the semiconductor substrate;
    Forming an opening in a portion of the mask corresponding to the first region;
    Isotropically etching the second insulating film using the mask;
    Removing the mask;
    Isotropically etching the second insulating film in the first region and the second region;
    Forming a buried insulating film in the groove;
    including,
    A method for manufacturing a semiconductor device according to claim 9.
  11. 　前記溝部を形成するステップは、
    　前記半導体基板の表面に第一の絶縁膜と第二の絶縁膜とを順番に形成するステップと、
    　前記第一の絶縁膜および前記第二の絶縁膜および前記半導体基板をエッチングして、前記半導体基板上の前記第１の領域と前記第２の領域にそれぞれ溝部を形成するステップと、
    を備え、
    　前記素子分離絶縁膜を形成するステップは、
    　前記半導体基板の表面に、第一の埋め込み絶縁膜を形成し、さらに第二の埋め込み絶縁膜によって前記溝部を完全に埋設するステップと、
    　前記第二の絶縁膜をエッチングストッパとして前記第一および第二の埋め込み絶縁膜を平坦化するステップと、
    　前記半導体基板上に、前記第２の領域のみ開口したレジストパターンを形成し、前記レジストパターンをマスクとして前記第一の埋め込み絶縁膜の一部を選択的にエッチングするステップと、
    　前記レジストパターンを除去した後、前記第二の絶縁膜を除去するステップと、
    　前記第一の絶縁膜を犠牲膜として前記半導体基板に不純物を導入するステップと、
    　表面に露出した前記第一の埋め込み絶縁膜を除去した後、前記半導体基板にゲート酸化膜を形成するステップと、
    を含む、
    ことを特徴とする請求項９に記載の半導体装置の製造方法。     The step of forming the groove includes
    Sequentially forming a first insulating film and a second insulating film on the surface of the semiconductor substrate;
    Etching the first insulating film, the second insulating film and the semiconductor substrate to form grooves in the first region and the second region on the semiconductor substrate;
    With
    The step of forming the element isolation insulating film includes:
    Forming a first buried insulating film on the surface of the semiconductor substrate, and further completely filling the groove with a second buried insulating film;
    Planarizing the first and second buried insulating films using the second insulating film as an etching stopper;
    Forming a resist pattern having an opening only in the second region on the semiconductor substrate, and selectively etching a part of the first buried insulating film using the resist pattern as a mask;
    Removing the second insulating film after removing the resist pattern;
    Introducing an impurity into the semiconductor substrate using the first insulating film as a sacrificial film;
    Forming a gate oxide film on the semiconductor substrate after removing the first buried insulating film exposed on the surface;
    including,
    A method for manufacturing a semiconductor device according to claim 9.
  12. 　窒素、炭素、フッ素、ボロン、燐、砒素の少なくともいずれか１つを含む酸化シリコンを堆積することにより、前記第一の埋め込み絶縁膜を形成する、
    ことを特徴とする請求項１１に記載の半導体装置の製造方法。     Forming the first buried insulating film by depositing silicon oxide containing at least one of nitrogen, carbon, fluorine, boron, phosphorus, and arsenic;
    The method of manufacturing a semiconductor device according to claim 11.
  13. 　酸化シリコンを堆積することにより、前記第二の埋め込み絶縁膜を形成する、
    ことを特徴とする請求項１１に記載の半導体装置の製造方法。     Forming the second buried insulating film by depositing silicon oxide;
    The method of manufacturing a semiconductor device according to claim 11.
  14. 　前記素子分離絶縁膜を形成するステップの後に、前記第１の領域にロジック回路を形成し、前記第２の領域にメモリ回路を形成するステップを備える、
    ことを特徴とする請求項９に記載の半導体装置の製造方法。     After the step of forming the element isolation insulating film, a step of forming a logic circuit in the first region and forming a memory circuit in the second region,
    A method for manufacturing a semiconductor device according to claim 9.
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