WO2010010164A2

WO2010010164A2 - Processor circuit with shared memory

Info

Publication number: WO2010010164A2
Application number: PCT/EP2009/059524
Authority: WO
Inventors: Yves Théoduloz; Hugo Jaeggi; Tomas Toth
Original assignee: Em Microelectronic-Marin Sa
Priority date: 2008-07-25
Filing date: 2009-07-23
Publication date: 2010-01-28
Also published as: WO2010010164A3; CH699207A1; CH699207B1

Abstract

The invention relates to a processor circuit (1) that comprises a computation unit (2), a first memory element (3) for storing data and a second memory element (4) for storing instructions. The first and second memory elements (3, 4) are each connected by a communication bus (5, 6) to the computation unit. The first and second memory elements define a single memory unit (7) in order to define a memory of the shared type.

Description

CIRCUIT PROCESSOR WITH SHARED MEMORY

The present invention generally relates to a processor circuit. The processor circuit includes a computing unit, a first memory element for storing data, and a second memory element for storing instructions. Said first and second memory elements are connected by at least one communication bus to the computing unit.

BACKGROUND TECHNOLOGY

The Harvard-type processor circuits are known in the prior art and are shown in FIG. 1. This Harvard architecture thus allows for an increased speed of the processor circuit because access to the instructions and the data can be performed at the same time. The processor circuits 1 having such an architecture are in the form of a calculation unit 2 communicating with two separate memory units 3, 4. One of the memory units 4 is used for storing the instructions while the other memory unit 3 used for storing data. Each memory unit 3, 4 communicates with the calculation unit 2 via a respective communication bus 5, 6. This architecture is then characterized by a separation of the stored data and stored instructions.

Nevertheless, this type of architecture has certain disadvantages. Indeed, this architecture imposes two physically distinct memory units thus increasing the area dedicated to said memory units and thus the surface of the integrated processor circuit.

On the other hand, this type of architecture with two separate memory units is not flexible to use. Indeed, even if it is possible to adapt the size of the two memory units according to the use that will be made, this adaptation requires a physical modification of the size of the two memory units. This change entails additional costs due to the need to perform design work at the component level itself. It is also known from the prior art US patent document 2002/0184465 which discloses a processor circuit using architecture similar to a Harvard architecture. This processor circuit is designed to have the processing speed advantages of Harvard architecture. Indeed, the processor circuit described by US patent document 2002/0184465 comprises an architecture where the memory area containing the instructions is also capable of storing data. This architecture nevertheless has two separate memory units, one for instructions and one for data. This ability to store data in the memory unit that contains the instructions allows some flexibility of use. This distinction results in a large area which does not solve the surface problem of Harvard architecture.

In addition, another disadvantage of this processor circuit is that it has a flexibility of use resulting from a modification of a conventional Harvard architecture. Indeed, the processor circuit describes a conventional Harvard architecture which has two separate memory units and each communicating with the computing unit via a communication bus. On the other hand, this modification is carried out so that the data bus is connected to both the data memory and the program memory. Thus, the flexibility of use provided by this processor circuit requires modifying the processor circuit in its depth and therefore leads to significant manufacturing costs.

SUMMARY OF THE INVENTION

One of the main aims of the present invention is to overcome the aforementioned drawbacks of the prior art, namely to produce a Harvard architecture processor circuit which is both flexible in its use and of a smaller surface area, without said architecture being be modified. For this purpose, the invention relates to the processor circuit exclusively of Harvard architecture cited above, characterized in that the first and second memory elements forming a single memory unit for making a memory of the shared memory type, and in that it further comprises means for managing communications between the computing unit and the memory shared to provide a blocking signal that acts on the computing unit to block the operation of said computing unit and to prevent the execution of an instruction.

Advantageous embodiments of the processor circuit are the subject of dependent claims 2 to 3.

An advantage of the processor circuit according to the invention is that this processor circuit has a smaller area than that of a Harvard architecture according to the prior art. Indeed, the use of a shared memory allows the processor circuit according to the present invention to have only one physical memory unit to contain both data and instructions, thus allowing to gain surface. Thus for an equivalent storage volume, a shared memory has a smaller area than two separate memory units. This surface difference comes from the fact that for the case of two separate memory units, everything is doubled such as the control and control elements whereas for a shared memory, that is to say a single memory unit, all the elements are only present in one copy.

A second benefit is the flexibility of using shared memory. Indeed, having a single memory unit allows more flexibility in the allocation of the memory volume. This flexibility is a consequence of grouping data and instructions in the same physical unit. Virtual separation can be easily realized and adapted to allocate more or less memory volume to data or instructions.

BRIEF DESCRIPTION OF THE FIGURES

The purposes, advantages and characteristics of the processor circuit will appear more clearly in the following detailed description of at least one embodiment of the invention given solely by way of nonlimiting example and illustrated by the appended drawings in which: FIG. 1 schematically represents the processor circuit according to the prior art; Figure 2 schematically shows the processor circuit according to the present invention; and FIG. 3 schematically represents a preferred embodiment of the processor circuit according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following description, all parts of the processor circuit that are well known to those skilled in the art will only be explained in a simplified manner.

Figure 2 schematically shows a processor circuit 1 having a Harvard architecture according to the present invention. This processor circuit 1 thus comprises a calculation unit 2 and two memory elements 3, 4 containing for one, the data and for the other 4, the instructions. The computing unit 2 also called arithmetic and logic unit is used to perform the basic operations, this unit 2 being the heart of said processor circuit. This calculation unit 2 communicates with the memory elements 3, 4 via respective communication buses 5, 6. These communication buses 5, 6 respectively connect said calculation unit 2 to the memory element 3 containing the data and said data unit. calculation 2 to the memory element 4 containing the instructions and are respectively called data bus 5 and program bus 6.

In order to increase the flexibility of use and reduce the surface of the processor circuit, the present invention proposes to join the two memory elements 3, 4 in a single physical block to form a single memory unit 7 thus forming a shared memory. This memory is said to be shared because it contains both data and instructions. Preferably, the data and instructions are grouped together, thus forming two distinct zones. This arrangement advantageously saves time and allows ease of programming because the data and instructions are not mixed.

Moreover, this separation also allows said invention to be more flexible in its use. As the data and instructions are grouped together, the space, which is devolved to them, can be optimized according to the applications. Indeed, it can be considered that the areas containing the data and the instructions are separated by a virtual limit easily adaptable. Thus, if an application of the processor circuit 1 requires few instructions but a lot of space to save the data then this virtual limit is moved to allow storage of a larger amount of data. On the other hand, if the application of the processor circuit 1 requires a large number of instructions but few data then the virtual limit is moved to give the instructions a larger space. This flexibility of use is all the more appreciable that it is easier to move a purely software virtual limit than to physically optimize the size of the memories 3, 4 as is the case of unshared memories.

In Figure 3 is shown a particular embodiment. This embodiment is characterized by management means 8 for managing the communications between the shared memory 7 and the calculation unit 2. These management means 8 are in the form of a memory interface 8 located between the shared memory 7 and the computation unit 2. This interface is, on the one hand, connected to the shared memory 7 by a communication bus 9 called the memory bus and, on the other hand, connected to the calculation unit 2 via the program bus 6 and the data bus 5.

The operation of this interface 8 consists of receiving the read commands of the computing unit 2 to read given memory addresses. Then, the interface 8 interprets these orders and fetches the data or instructions to the corresponding memory addresses. Once these addresses are targeted, the interface 8 reads the data or instructions contained therein and sends the result to the calculation unit 2 so that the latter can process it.

Or one of the problems that could occur is that the calculation unit 2 executes the next instruction while the interface 8 is reading an address previously requested by said calculation unit 2. Indeed, this problem could arise from the makes the number of cycle times necessary, for reading, which would be too important.

For this, the invention proposes to solve this problem by allowing the interface 8 to block the calculation unit 2. For this, the interface 8 comprises a blocking means for solving the problem above. This blocking means consists of an S_block blocking signal connecting said interface 8 and the calculation unit 2. In a preferred embodiment, this connection is made at the level of the calculation unit 2 via the clock input. 21, also called CLK. During operation of the processor circuit 1, as long as the calculation unit

2 requests to read instructions, the processor circuit 1 acts as explained before. Thus, a read command is sent to the memory interface 8 which interprets it and reads the corresponding instruction. Once this instruction read, it is sent to the calculation unit 2 which executes it. On the other hand, when the computation unit 2 gives the order to read a datum, the memory interface 8 will detect that the command comes from the data bus 5. This detection will then trigger the blocking of the computation unit. 2 by said interface 8 via the blocking signal S_block. This blocking is accomplished by forcing the clock input CLK to a logic level. Preferably, the CLK input will be forced to zero. For this, an AND logic gate is placed at the CLK input and at the input of this gate are connected the clock and S_block signals. The S_block signal is then set to a logic zero level causing the zero of the output of said AND gate. This blocking then makes it impossible for said unit 2 to execute instructions. This impossibility is due to the fact that the clock signal is no longer transmitted to the calculation unit 2 thus preventing the execution of instructions. Thus, there is no risk that the calculation unit 2 executes an instruction while a data item is being read.

Of course, the blocking of the computing unit 2 by action on its clock input is not the only way to achieve this blocking. Indeed, specific or existing entries, such as an "enable" entry that makes the component to function and generally present, are usable.

On the other hand, it can be pointed out that this blocking of the calculation unit 2 also makes it possible to reduce the consumption of electrical energy. In fact, if the blocking makes it possible not to execute an instruction at the same time as the reading of a piece of data, this blocking makes it possible to stop the operation of the unit 2. Thus in the case where there is no instructions to execute, this blocking of the calculation unit 2 makes it possible not to operate said unit 2 in a vacuum. It will be understood that the memory or memories used may be a non-volatile memory also called ROM memory (Read OnIy Memory), such as an EEPROM (Electrically Erasable Programmable Read OnIy) memory.

Memory) or a volatile memory such as a flash memory, RAM (Random Access Memory) or others.

It will be understood that various modifications and / or improvements and / or combinations obvious to those skilled in the art can be made to the various embodiments of the invention set forth above without departing from the scope of the invention defined by the appended claims.

Claims

Processor circuit (1) comprising a computing unit (2), a first memory element (3) for data storage and a second memory element (4) for storing instructions, said first and second memory elements (3). , 4) being connected by at least one communication bus (5, 6) to the computing unit, the first and second memory elements forming a single memory unit (7) for producing a memory of the shared memory type, characterized in that it further comprises means (8) for managing communications between the computing unit (2) and the shared memory (7) provided to provide a blocking signal (S_block) which acts on the computing unit ( 2) to block the operation of said computing unit (2) and to prevent execution of an instruction.

2. Processor circuit (1) according to claim 1, characterized in that the blocking signal (S_block) acts on the clock input (CLK) of the computing unit (2).

Processor circuit (1) according to claim 1 or 2, characterized in that the management means comprise a memory interface (8) connected to the computing unit (2) by means of at least a first bus (5). , 6) and connected to the shared memory (7) by a second communication bus (9)