WO2010010164A3 - Processor circuit with shared memory - Google Patents

Processor circuit with shared memory Download PDF

Info

Publication number
WO2010010164A3
WO2010010164A3 PCT/EP2009/059524 EP2009059524W WO2010010164A3 WO 2010010164 A3 WO2010010164 A3 WO 2010010164A3 EP 2009059524 W EP2009059524 W EP 2009059524W WO 2010010164 A3 WO2010010164 A3 WO 2010010164A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
processor circuit
shared memory
computation unit
block
Prior art date
Application number
PCT/EP2009/059524
Other languages
French (fr)
Other versions
WO2010010164A2 (en
Inventor
Yves Théoduloz
Hugo Jaeggi
Tomas Toth
Original Assignee
Em Microelectronic-Marin Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Em Microelectronic-Marin Sa filed Critical Em Microelectronic-Marin Sa
Publication of WO2010010164A2 publication Critical patent/WO2010010164A2/en
Publication of WO2010010164A3 publication Critical patent/WO2010010164A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)

Abstract

The invention relates to a processor circuit (1) that comprises a computation unit (2), a first memory element (3) for storing data and a second memory element (4) for storing instructions. The first and second memory elements (3, 4) are each connected by a communication bus (5, 6) to the computation unit. The first and second memory elements define a single memory unit (7) in order to define a memory of the shared type. A blocking signal (S-block) acts on the computation unit (2) in order to block the operation thereof.
PCT/EP2009/059524 2008-07-25 2009-07-23 Processor circuit with shared memory WO2010010164A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH01177/08A CH699207B1 (en) 2008-07-25 2008-07-25 shared memory processor circuit.
CH01177/08 2008-07-25

Publications (2)

Publication Number Publication Date
WO2010010164A2 WO2010010164A2 (en) 2010-01-28
WO2010010164A3 true WO2010010164A3 (en) 2010-03-25

Family

ID=41506465

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2009/059524 WO2010010164A2 (en) 2008-07-25 2009-07-23 Processor circuit with shared memory

Country Status (2)

Country Link
CH (1) CH699207B1 (en)
WO (1) WO2010010164A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0713170A1 (en) * 1994-11-21 1996-05-22 Nec Corporation Data processing apparatus
EP1315090A1 (en) * 2000-08-30 2003-05-28 Matsushita Electric Industrial Co., Ltd. Memory access controller
US20050210215A1 (en) * 2004-03-19 2005-09-22 Renesas Technology Corp. Semiconductor device permitting rapid data reading and writing between processor and memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175841A (en) * 1987-03-13 1992-12-29 Texas Instruments Incorporated Data processing device with multiple on-chip memory buses
JPS6414648A (en) * 1987-07-08 1989-01-18 Mitsubishi Electric Corp Arithmetic processor
GB2345770B (en) * 1999-01-15 2003-06-25 Advanced Risc Mach Ltd Data processing memory system
JP2001043180A (en) * 1999-08-03 2001-02-16 Mitsubishi Electric Corp Microprocessor and storage device therefor
JP2001202285A (en) * 2000-01-18 2001-07-27 Nec Ic Microcomput Syst Ltd Microprocessor, and its program instruction and data storing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0713170A1 (en) * 1994-11-21 1996-05-22 Nec Corporation Data processing apparatus
EP1315090A1 (en) * 2000-08-30 2003-05-28 Matsushita Electric Industrial Co., Ltd. Memory access controller
US20050210215A1 (en) * 2004-03-19 2005-09-22 Renesas Technology Corp. Semiconductor device permitting rapid data reading and writing between processor and memory

Also Published As

Publication number Publication date
CH699207B1 (en) 2013-05-15
WO2010010164A2 (en) 2010-01-28
CH699207A1 (en) 2010-01-29

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