WO2009002940A3 - Systems and methods of reading nonvolatile memory - Google Patents

Systems and methods of reading nonvolatile memory Download PDF

Info

Publication number
WO2009002940A3
WO2009002940A3 PCT/US2008/067919 US2008067919W WO2009002940A3 WO 2009002940 A3 WO2009002940 A3 WO 2009002940A3 US 2008067919 W US2008067919 W US 2008067919W WO 2009002940 A3 WO2009002940 A3 WO 2009002940A3
Authority
WO
WIPO (PCT)
Prior art keywords
nonvolatile memory
systems
methods
raw data
reading nonvolatile
Prior art date
Application number
PCT/US2008/067919
Other languages
French (fr)
Other versions
WO2009002940A2 (en
Inventor
Jason T Lin
Original Assignee
Sandisk Corp
Jason T Lin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/767,587 external-priority patent/US7849383B2/en
Priority claimed from US11/767,582 external-priority patent/US20080320366A1/en
Application filed by Sandisk Corp, Jason T Lin filed Critical Sandisk Corp
Publication of WO2009002940A2 publication Critical patent/WO2009002940A2/en
Publication of WO2009002940A3 publication Critical patent/WO2009002940A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5631—Concurrent multilevel reading of more than one cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

In a nonvolatile memory system, first raw data is obtained from stored data using a first set of reading parameters. Subsequently, the first raw data is transferred to an ECC circuit where it is decoded. While the first raw data is being transferred and decoded, second raw data is obtained from the same stored data using a second set of reading parameters.
PCT/US2008/067919 2007-06-25 2008-06-23 Systems and methods of reading nonvolatile memory WO2009002940A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/767,587 US7849383B2 (en) 2007-06-25 2007-06-25 Systems and methods for reading nonvolatile memory using multiple reading schemes
US11/767,582 2007-06-25
US11/767,587 2007-06-25
US11/767,582 US20080320366A1 (en) 2007-06-25 2007-06-25 Methods of reading nonvolatile memory

Publications (2)

Publication Number Publication Date
WO2009002940A2 WO2009002940A2 (en) 2008-12-31
WO2009002940A3 true WO2009002940A3 (en) 2009-03-12

Family

ID=39855754

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/067919 WO2009002940A2 (en) 2007-06-25 2008-06-23 Systems and methods of reading nonvolatile memory

Country Status (2)

Country Link
TW (1) TWI387970B (en)
WO (1) WO2009002940A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7849383B2 (en) 2007-06-25 2010-12-07 Sandisk Corporation Systems and methods for reading nonvolatile memory using multiple reading schemes
TWI455142B (en) * 2010-04-08 2014-10-01 Silicon Motion Inc Data storage device and data read method of a flash memory
US8811081B2 (en) * 2011-12-09 2014-08-19 Sandisk Technologies Inc. Systems and methods of updating read voltages in a memory
US10417087B2 (en) * 2014-07-22 2019-09-17 Ngd Systems, Inc. System and method for adaptive multiple read of NAND flash
US10795765B2 (en) 2014-07-22 2020-10-06 Ngd Systems, Inc. SSD for long term data retention
CN104217765B (en) * 2014-09-09 2017-11-24 武汉新芯集成电路制造有限公司 The measuring method of flash chip operating time
CN106161022B (en) * 2015-03-31 2019-11-22 上海复旦微电子集团股份有限公司 Anti-attack method and device based on ECC crypto module
KR20180110412A (en) * 2017-03-29 2018-10-10 에스케이하이닉스 주식회사 Memory system and operating method thereof
US11237908B2 (en) 2017-03-29 2022-02-01 SK Hynix Inc. Memory system and operating method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060221696A1 (en) * 2005-04-01 2006-10-05 Yan Li Method for Non-Volatile Memory with Background Data Latch Caching During Read Operations
WO2007049272A2 (en) * 2005-10-25 2007-05-03 Sandisk Il Ltd. A method for recovering from errors in flash memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060221696A1 (en) * 2005-04-01 2006-10-05 Yan Li Method for Non-Volatile Memory with Background Data Latch Caching During Read Operations
WO2007049272A2 (en) * 2005-10-25 2007-05-03 Sandisk Il Ltd. A method for recovering from errors in flash memory

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"METHOD FOR GENERATING SOFT BITS IN FLASH MEMORIES", IP.COM JOURNAL, IP.COM INC., WEST HENRIETTA, NY, US, 4 March 2007 (2007-03-04), XP013118530, ISSN: 1533-0001 *
"SOFT DECODING OF HARD AND SOFT BITS READ FROM A FLASH MEMORY", IP.COM JOURNAL, IP.COM INC., WEST HENRIETTA, NY, US, 4 March 2007 (2007-03-04), XP013118528, ISSN: 1533-0001 *

Also Published As

Publication number Publication date
WO2009002940A2 (en) 2008-12-31
TW200907978A (en) 2009-02-16
TWI387970B (en) 2013-03-01

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