200907978 九、發明說明： 【發明所屬之技術領域】 本發明係關於非揮發記憶體及操作非揮發記憶體之方 法。詳言之，本申請案係關於浮動閘極記憶體單元個別地 保存資料之一或多個位元的非揮發記憶體陣列，及自該等 記憶體單元讀取資料的方法。 【先前技術】 用甲。一些非揮發記憶體 系統中。其他非揮發記憶 且可在不同主機系統之間 實例包括記憶卡及USB快200907978 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory and methods of operating non-volatile memory. In particular, the present application relates to a non-volatile memory array in which one or more bits of data are individually stored in a floating gate memory cell, and a method of reading data from the memory cells. [Prior Art] Use A. Some non-volatile memory systems. Other non-volatile memories and between different host systems Examples include memory cards and USB fast
非揮發記憶體系統用於各種應 系統嵌入於諸如個人電腦之較大 體系統可抽取地連接至主機系統 互換。該等抽取式記憶體系統之 閃驅動器。包括非揮發記憶卡 电卞尾路卡已根據多個熟 知標準而在商業上實施。記憶卡與個人電腦、蜂巢式電 話、個人數位助理（PDA) '數彳立相攙 ^ )歎位相機、數位電影攝影機、 攜帶型音訊播放器及用於儲存大量資料的其他主機電子設 備一起使用。該等卡通常含有一可重複程式化之非揮發半 導體記憶體單元陣列以及一控制器，該控制器控制並支援 記憶體單元陣狀操作且與該切連接至之主機介面連 接。若干相同類型之卡可在經設計以接納該類型之卡的主 機卡槽中互換。然而，許多電子卡標準之發展已形成在各 種知度上彼此不相容的不同類型卡。根據一標準而製造之 卡通常不可與一經設計以與另—標準之卡一起操作的主機 一起使用。記憶卡標準包括Pc卡標準、c_paetFiashTM卡 仰™卡）標準、Smar则㈣切m請卡（mmctm) I32526.doc 200907978 標準、安全數位（SD)卡標準、miniSD™卡標準、 用戶識別 碼模組（SIM)標準、Memory Stick™標準、記憶棒雙重卡乾 準及microSD/TransFlashTM記憶體模組標準。存在可以^ 標"Cruzer®”自SanDisk公司購得的若干USB快閃驅動器產 品。USB快閃驅動器通常比上文描述之記憶卡大且形狀與 上文描述之記憶卡不同。 不同類型之記憶體陣列架構用於非揮發記憶體系統中。 在一類型之架構中’ NAND陣列、一連串兩個以上（諸如Μ 或32個）記憶體單元之串與在個別位元線與參考電位之間 的或夕個選擇電晶體連接在一起以形成記憶體單元之 行。字線延伸越過大量此等行内的記憶體單元。 在稱為單位階記憶體單元（SLC)設計的設計中，個別記 憶體單元可保存資料之—位元m财，在稱為多 ㈣記憶體單元（MLC)設計的設計中，—記憶體單元可保 存貧料之兩個或兩個以上位元。 【發明内容】 中：：本發明之一實施例的讀取儲存於非揮發記憶體陣列 —貝料的方法包含：藉由個別比較複數個記憶體單元中 記情齊ί的電特性之值與第—至少—預定值而對該複數個 中執行第一讀取操作，以自該複數個記憶體單元 第t獲得包括至少一位元之第-原始資料；執行該 解碼的始貝料之ECC解碼；在執行該第—原始資料之ECC 解石馬的同眛，站 者、精由個別比較該複數個記憶體單元中之每-、電特性之值與不同於第一至少一預定值的第二至少一 132526.doc 200907978 預定值而對該複數個記憶體單元執行第 該複數個記憶體單元中之每-者獲得包括至广作以自 。符主少—位开夕牮 一’、始資料；若第一原始資料之Ec 笫-馬私次丨 鮮喝不成功，則執行 第一原始資料之ECC解碼；及若第— 仃Non-volatile memory systems are used for a variety of systems that are embedded in a larger system such as a personal computer that is detachably connected to the host system for interchange. Flash drives for such removable memory systems. Including non-volatile memory cards Electric tail cards have been commercially implemented in accordance with a number of well-known standards. Memory cards are used with personal computers, cellular phones, personal digital assistants (PDAs), sigh cameras, digital cinema cameras, portable audio players, and other host electronic devices for storing large amounts of data. . The cards typically include a reprogrammable array of non-volatile semiconductor memory cells and a controller that controls and supports the memory cell array operation and is coupled to the host interface to which the switch is connected. Several cards of the same type may be interchanged in a host card slot designed to accept cards of this type. However, the development of many electronic card standards has resulted in different types of cards that are incompatible with each other in various ways. Cards manufactured according to a standard are generally not compatible with a host that is designed to operate with another standard card. Memory card standard includes Pc card standard, c_paetFiashTM card standard), Smar (4) cut m request card (mmctm) I32526.doc 200907978 standard, secure digital (SD) card standard, miniSDTM card standard, user ID module (SIM) standard, Memory StickTM standard, memory stick dual card dry and microSD/TransFlashTM memory module standard. There are several USB flash drive products available from SanDisk Corporation. The USB flash drive is usually larger than the memory card described above and has a different shape than the memory card described above. Different types of memory The bulk array architecture is used in non-volatile memory systems. In a type of architecture, a NAND array, a series of two or more (such as Μ or 32) memory cells, and between individual bit lines and a reference potential Or the selected transistors are connected together to form a row of memory cells. The word lines extend across a large number of memory cells within the rows. In a design called a unit cell memory cell (SLC) design, individual memory cells The data can be saved as a bit, in a design called a multi (four) memory cell (MLC) design, the memory cell can hold two or more bits of poor material. [Summary] The method for reading and storing in a non-volatile memory array-bean material according to an embodiment of the present invention comprises: comparing the value of the electrical characteristic of the plurality of memory cells with the first Performing a first read operation on the plurality of at least a predetermined value to obtain a first-original data including at least one bit from the plurality of memory unit t; performing ECC decoding of the initial material of the decoding; In the peer of the ECC calculus horse performing the first-original data, the station, the individual compares each of the plurality of memory units to a value different from the first at least one predetermined value. At least one 132526.doc 200907978 predetermined value and the execution of each of the plurality of memory units for the plurality of memory units is obtained by including the maximum number of bits of the memory unit. If the Ec 笫-马 private 丨 fresh drink of the first original data is unsuccessful, the ECC decoding of the first original data is performed; and if the first 仃
成功’則丢棄第二原始資料而不執行第解碼 解碼。 仃第—原始資料之：ECC 中實施例之讀取儲存於非揮發記憶體陣列 H 貝枓的方法包含：使用第—組讀取參數讀取儲存於非 “己隐體陣列中之複數個位元，以獲 料；對第一組原妗資料勃—Prr p从 、，原始貝 資㈣1 科執灯CC操作；及在對第一組原始 斜執仃ECC#作的同時，使用第二 於非揮發記愔妒瞌s丨士 、·喝取參數璜取儲存 資料揮發體陣列中之複數個位元，以獲得第二組原始 i. =據本發明之—實施例之讀取儲存於快閃記憶體陣列中 =貝料的方法包含：藉由個別比較複數個記憶體單元之每 :的：限，與第—至少一參考電里而對該複數個記憶 讀取操作，以獲得對應於館存於該複數個 «己IS體早το中之邏輯頁之杳祖结 一 L铒貝之貝枓的弟一原始資料；執行第一 = ; Μ㈣料之ECC解碼的 =盘別比較複數個記憶體單元中之每一者的臨限 U同於忒第—至少一參考電壓之第二至少一 屢而對該複數個記憶體單元執行第二讀取操作，以獲 應於館存於該複數個記憶體單元中之邏輯頁之資料的第二 原始資料’·若第一原始資料的ECC解碼不成功， ^ 132526.doc 200907978 =原㈣料之咖解碼；及若第—原始f料的咖解碼成 —貝輸出自解碼第一原始資料所獲得之資料，且 二原始資料而不執行對第二原始資料之ecc 〃 :據本發明之-實施例的非揮發記憶體系統包含：―非 揮么。己it體陣列包括並行讀取的複數個記憶體單元丨 ::電：’其根據第一讀取方案讀取儲存於該複數個記 :體早：t的資料之複數個位元以提供一第一輸出，且根 弟-項取方案讀取儲存於該複數個記憶體單元中 之複數個位7C以提供一第二輸出；及一 ECC解碼電路，其 ^接至讀取電路’該ECC解碼電路接收來自讀取電路之第 一輸出’且在讀取電路根據第二讀取方案讀取料於該複 數個記憶體單元+的㈣之複數個位 出執行ECC解碼。 對第-輸 根據本發明之—實施例的非揮發記憶體系統包含：—非 揮發記憶體陣列’其儲存複數個資料頁；一讀取電路，其 具有複數個讀取模式，該複數個讀取模式巾之每—者: 來自記憶體單元之電量測與不同組之—或多個預定值以二 供一輸出，該讀取電路在模式之非重複序列中對資料之一 部分執行複數個讀取操作直至指示—結束條件為止；及一 ^cc電路’其在讀取電路在模式之序列中之後續模式中對 資料之該#分執行讀取操作的同時對讀取電路之每一輸出 執行ECC解碼’當該ECC電路成功解碼讀取電路之輸出 :’該ECC電路將一指示結束條件之信號提供至讀取電 132526.doc 200907978 【實施方式】 圖1展示根據本發明夕 _ 月之—實施例的非揮發記憶體系統100 之一部分。詳，国 π〇 ° ，圖1展示用於儲存資料之非揮發記憶 體早元的陣列102。ϋΐι·Λ·ρ> ^ 圖亦展示連接至陣列102並用於存取 °己憶體陣列1 0 2之記情_ U體早兀以用於讀取、寫入及抹除資Success' discards the second source without performing the decoding.仃第—original data: The method of reading and storing the non-volatile memory array H 枓 in the ECC includes: reading the plurality of bits stored in the non-hidden array using the first set of read parameters Yuan, to obtain the material; for the first group of original data Bo-Prr p from, the original shellfish (four) 1 branch to operate the CC operation; and in the first group of original oblique 仃 ECC#, while using the second Non-volatile 愔妒瞌s gentleman, drink parameters take a plurality of bits in the array of stored data volatiles to obtain a second set of original i. = according to the invention - the reading of the embodiment is stored in the fast The method of flash memory array=battery comprises: comparing each of the plurality of memory cells by: a limit, and the first at least one reference memory to read the plurality of memory operations to obtain a corresponding The museum is stored in the plural number of the logical pages of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The threshold U of each of the memory cells is the same as the first - at least one reference voltage Performing a second read operation on the plurality of memory cells at least one time to obtain a second original data of the data of the logical page stored in the plurality of memory cells. ECC decoding is unsuccessful, ^ 132526.doc 200907978 = original (four) material coffee decoding; and if the first - raw f material coffee decoding into - shell output from the decoding of the first source of data obtained, and the two original data without Execating the ecc 对 of the second original data: The non-volatile memory system according to the embodiment of the present invention comprises: “non-waxing. The array of the body includes a plurality of memory cells read in parallel”:: Electricity: ' And reading a plurality of bits stored in the plurality of data: the early: t data according to the first reading scheme to provide a first output, and the root-item reading program is stored in the plurality of memory a plurality of bits 7C in the cell to provide a second output; and an ECC decoding circuit coupled to the read circuit 'the ECC decoding circuit receives the first output from the read circuit' and the read circuit is based on the second The reading scheme reads the plurality of readings The plurality of bits of the (4) of the memory unit + are subjected to ECC decoding. The non-volatile memory system according to the embodiment of the present invention includes: - a non-volatile memory array that stores a plurality of data pages; Taking a circuit having a plurality of read modes, each of the plurality of read mode wipes: a power measurement from the memory unit and a different set - or a plurality of predetermined values to provide an output for two, the read The circuit performs a plurality of read operations on a portion of the data in the non-repetitive sequence of the pattern up to the indication-end condition; and a ^cc circuit that is in the subsequent mode of the read circuit in the sequence of modes. ECC decoding is performed on each output of the read circuit while the read operation is performed. 'When the ECC circuit successfully decodes the output of the read circuit: 'The ECC circuit supplies a signal indicating the end condition to the read power 132526.doc 200907978 [Embodiment] FIG. 1 shows a portion of a non-volatile memory system 100 in accordance with an embodiment of the present invention. In detail, country π〇 °, Figure 1 shows an array 102 of non-volatile memory early elements for storing data. Ϋΐι·Λ·ρ> ^ The figure also shows the connection to the array 102 and for accessing the memory of the memory array 1 0 2 _ U body early for reading, writing and erasing
料的周邊電路104、106、1〇8。列解碼器電路⑽連接至字 線’該等字線在水平方向上延伸。行解碼器及讀取/寫入 電路106連接至位元線，該等位元線在垂直方向上延伸。 行解馬器及，取/寫人電路1Q6可包括感測放大器、多工電 路及或夕個暫存器。儘管圖1展示一簡單組態，但是亦 可使用其他組態。在美國專利公開案第2〇〇6/〇221696號中 描述了該等組態之實例。 本發明之態樣可與多種非揮發記憶體陣列一起使用。在 一實例中，記憶體陣列由快閃記憶體單元組成，快閃記憶 體單元個別地包括一具有浮動閘極之電晶體。在程式化期 間根據待儲存於記憶體單元中之資料而使電荷位於浮動閘 極上，且記憶體單元之臨限電壓相應地改變。可藉由比較 記憶體單元之臨限電壓與預定電壓來讀取記憶體單元。快 閃記憶體陣列之實例包括N〇r及nAND陣列。 在典型NOR陣列中’行中之記憶體單元連接於兩個位元 線之間且沿一列之記憶體單元具有由字線連接在一起的選 擇閘極。在典型NAND配置中，記憶體單元串聯連接在— 起以形成串’在串之每一末端處具有選擇電晶體。該串在 一末端（沒極）處連接至一位元線且列中之串在另一（源極） I32526.doc 200907978 末端處連接在—起。字線延伸以形成記憶體單元之控制問 極。在美國專利第5,57〇,315號、第5,774,397號及第 6,046,935號中提供了 nanD架構之實例。 在NAND記憶體系統中’大體藉由在將預定電壓施加至 字線及選擇線時感測各位元線之電流或電壓而自記憶體陣 列讀取資料。詳言之，串中之一記憶體單元具有一（經由 字線）施加至其控制閘極的讀取電壓，同時所有其他記憶The peripheral circuits 104, 106, 1〇8 of the material. The column decoder circuit (10) is connected to the word line 'the word lines extend in the horizontal direction. The row decoder and read/write circuit 106 are connected to bit lines that extend in the vertical direction. The line de-magging device and the fetch/write circuit 1Q6 may include a sense amplifier, a multiplex circuit, and or a temporary register. Although Figure 1 shows a simple configuration, other configurations can be used. Examples of such configurations are described in U.S. Patent Publication No. 2/6,221,696. Aspects of the invention can be used with a variety of non-volatile memory arrays. In one example, the memory array is comprised of flash memory cells, each of which individually includes a transistor having a floating gate. During the stylization, the charge is placed on the floating gate according to the data to be stored in the memory cell, and the threshold voltage of the memory cell changes accordingly. The memory cell can be read by comparing the threshold voltage of the memory cell with a predetermined voltage. Examples of flash memory arrays include N〇r and nAND arrays. In a typical NOR array, the memory cells in the row are connected between two bit lines and the memory cells along a column have select gates connected together by word lines. In a typical NAND configuration, memory cells are connected in series to form a string ' having a select transistor at each end of the string. The string is connected to one bit line at one end (no pole) and the string in the column is connected at the end of the other (source) I32526.doc 200907978. The word lines extend to form the control questions of the memory cells. Examples of nanD architectures are provided in U.S. Patent Nos. 5,57,315, 5,774,397, and 6,046,935. In a NAND memory system, data is read from a memory array by sensing the current or voltage of each bit line when a predetermined voltage is applied to the word line and the select line. In particular, one of the memory cells in the string has a read voltage applied to its control gate (via the word line) while all other memories
體單元藉由將一充足電壓施加至其控制閘極而接通。因 而，被讀取之記憶體單元控制流過該串之電流及位元線上 之所得電壓。所得電流及電壓視正被讀取之記憶體單元的 臨限電壓而^。因巾，可藉由感測—流過記憶體單元之電 流、位70線上之電壓或藉由感測位元線經由記憶體單元而 放電的時間來讀取記憶體單元之狀態及其臨限電壓。即使 此等技術可能不直接量測臨限電壓，但是其量測一視記憶 體單元電晶體之臨限電壓而定的參數且可被認為間接地感 測記憶體單元之臨限電壓。 圖1亦展不一連接至行解碼器及讀取/寫入電路⑽之錯 誤校正編碼（ECC)電路1 〇8。ργγ φ功，Λ ; tCC電路108可位於與記憶體 陣列102相同（例如，盥專用曰y /、寻用日日片上電路相同）之晶粒上，或The body unit is turned on by applying a sufficient voltage to its control gate. Thus, the memory unit being read controls the current flowing through the string and the resulting voltage on the bit line. The resulting current and voltage depend on the threshold voltage of the memory cell being read. The state of the memory cell and its threshold voltage can be read by sensing the current flowing through the memory cell, the voltage on the bit 70, or by sensing the time that the bit line is discharged through the memory cell. . Even though these techniques may not directly measure the threshold voltage, they measure the parameters of the threshold voltage of the memory cell and can be considered to indirectly sense the threshold voltage of the memory cell. Figure 1 also shows an error correction coding (ECC) circuit 1 连接8 connected to the row decoder and the read/write circuit (10). Ργγ φ work, Λ ; tCC circuit 108 may be located on the same die as memory array 102 (eg, 盥 dedicated y / / find the same on-day on-chip circuit), or
°形成位於同曰曰片或不同晶片上的控制器之部分。ECC 電路⑽對㈣執行編碼及解碼操作。詳言之，待儲存之 貝料係在儲存之前被編碼。編. 雨馬大體涉及變換資料，使得 在所儲存之資料中存在某些冗 % “ 几餘而得以偵測並校正在讀 取資料時可能發生在其中的伊 扪錯镟。可使用各種ECC方率， 132526.doc 200907978 包括附加多個位元(例如，同位位元)之方案及變換一 料位元或所有資料位元之方案。簡單錯誤校正碼藉由储二 額外的同位位元而編碼資料，其係在將資料寫入至記情二 系統尹時，將位元群之同位設定成—所需邏輯值。在^' 憶體系統讀取資料後，即藉由Ecc再次計算位元群之同 位々。由於資料損毀，所計算之同位可能與所需的同位料 不符’且ECC可能㈣職損毀。可㈣段為基礎將咖 套用於區段，使得每一區段儲存有一些額外的冗餘位元。 舉例而言，具有512個位元組之資料的區段可在儲存之前 附加8個位元組之ECC資料。大體而言，所使用的冗餘位 疋愈多，可偵測並校正之錯誤的數目愈高。 ECC可具有至少兩個功能··錯誤谓測及錯誤校正。此等 功能中之每一者的能力通常是以可摘測為錯誤且後續可校 正的位元之數目來量測。伯測能力可與校正能力相同或大 於校正能力。典型Ecc可偵測的錯誤位元之數目高於其可 校正的錯誤位元之數目。有時將資料位元及同位位元之集 合稱為字。早期實例為（7,4則㉟，其具㈣測每字（在 此實例中為七個位元）最多達兩個錯誤的能力，且具有在 及七位7L字中校正一個錯誤的能力。 更複雜之ECC可校正每字超過單—錯誤，但直在計算上 變得更加複雜以重新建構資料。常見的方法係恢復資料並 “擔某種可接文且機率較小的復原失敗可能性。然而，隨 者錯5吳數目增加’可靠資料恢復之可能性亦迅速降低，或 1卜更體及/或效能方面的相關聯成本變得過高。 132526.doc 200907978 當讀取具有高數目之不可校正錯誤的資料時，可進行第 二次嘗試以讀取資料。舉例而言，可應用不同組之讀取條 二=看不同讀取條件是否提供具有較低數目之可校正錯 7的貝料。記憶體系統可以此方式經歷多次嘗試以讀取資 料直至特定組之讀取參數提供足夠好之資料⑽c可校正資 料）為止。 ' 圖2展示可如何使用不同讀取參數的實例。圖2展示經程 式化至兩個不同記憶體狀態(邏輯0狀態及邏輯1狀態)的記 :體：元之臨限電壓(Vt)。在此實例中，儲存邏輯2之記 隐體單疋（由分布21〇表示）具有較低臨限電壓且儲存邏輯〇 :體單元（由分布212表示）具有較高臨限電壓。邏輯卫 6»限電塵可簡單地為對應於抹除狀態的臨限電麼，使得儲 存邏輯1之記憶體單元在程式化期間保持相同臨限電廢。 S貴取記憶體單元中之資料大體涉及比較記憶體單元之臨 限電壓與某預定·或—些預定錢。在—實例中，第一 區別電壓vi用於執行第-讀取。此意謂具有小於VI之臨 限電C的所有5己憶體單元被認為儲存i，而具有大於V1之 —阳電[的所有記憶體單元被認為錯存0。此意謂經程式 化至邏輯1狀態之記憶體單元的分布210之陰影部分214中 的記憶體單元被錯誤地讀取為處於邏輯0狀態。此可提供 具有顯者數目錯言吳夕咨冰止 ^ ^ ^ ,,. 碎兩之貝枓。之，此可提供具有不可由 所使用之ECC方案校正的多個錯誤的資料。 在ECC解碼判定資料中存在大量不可校正錯誤時，可使 用不同5貝取參數來執行第二讀取。在本實例中，使用作為 132526.doc -12· 200907978 區別電Μ之V2來執行第二讀取。此導致陰影部分川中之 3己憶體單兀被正確地識別為含有】。因而，錯誤之數目減 少至一可接文數目且資料可由ECC完全校正。 在此實例中’藉由量AV將區別電麼自VI調整至V2。調 整（增加或減少）之方向及調整之量值可以任何適當方式來 判疋。調整可基於記憶體單元特性歸因於記憶體單元壽命 内之磨損而發生的預期變化，或基於記憶體單元特性之量 測變化。在一實例中，參考記憶體單元用於追蹤可在記憶 體陣列之哥命内*生的變化且經調整之讀取參數可基於同 一设備之參考記憶體單元中所觀測的變化。在另一實例 中’由ECC電路進行的校正經受統計分析則貞測記憶體單 το性能之圖案且在言免備壽命期間相應地調整讀取參數。對 设備之失敗分析亦可提供關於臨限電壓隨時間之變化分布 的資訊，使得可進行一些預測且基於磨損計算適當調整。 舉例而言’調整可基於區塊或其他記憶體單元所經歷的抹 除循環之數目。電腦模擬可用於獲得記憶體讀取參數之適 §調玉了在頁接頁、區塊接區塊基礎上對於設備之所有 區塊共同進行調整，或對於記憶體之某其他記憶體單元進 行調整。因而，在使用某預設區別電壓（例如，νι)的讀取 頁的記憶體系統中，所使用之實際區別電壓（例如，可 在设備之整個壽命内變化且對於設備内之不同頁可不同。 在一實例中，使用諸如VI之預設區別電壓執行第—讀取操 作且僅當ECC指示自第一讀取所獲得之資料不可由校 正時，使用諸如V2之不同區別電壓執行第二讀取。在其2 132526.doc 200907978 實例中’可使用多個不同區別電壓直至所讀取之資料可校 正為止0 圖3展示非揮發記憶體中之不同邏輯狀態的臨限電壓分 布3 20至3 23之另一實例。在此狀況下，個別記憶體單元經 程式化至四個狀態中之一者，使得在可稱為多位階記憮體 單元（MLC)記憶體之記憶體中每一記憶體單元儲存資料之 兩位元。其他MLC設計每記憶體單元儲存兩個以上（例 如，四個）位元。大體而言，隨著每記憶體單元位元數目 增加，指派給每一記憶體狀態之臨限電壓範圍變得更小且 錯誤讀取資料之風險增加。圖3展示對於不同記憶體狀態 的分布320至323之間的某重疊。因為ECC可校正達至某限 制之錯誤，所以某重疊係可接受的。然而，若過多錯誤存 在於自記憶體所讀取的資料中，則ECC不能校正該資料。 因此，使用正確的區別電壓係重要的。在第一讀取操作 中，區別電壓V3、V4及V5可用於識別每一記憶體單元之 記憶體狀態。區別電壓V3、¥4及V5可為預設電壓，或可 經文自如上文描述之預設電壓的某偏移或偏移組。在第二 肩取操作中’區別電壓V6、V7、V8、V9、V10、V11用於 進一步解析記憶體單元之臨限電壓。可將第二讀取操作認 為係一比第一讀取操作解析度高的讀取。第二讀取操作提 供第一讀取操作之結果為正確的可能性之指示。舉例而 。，在第一讀取中將具有臨限電壓V12及V13之記憶體單 凡白識別為儲存（丨，0)(在V3與V4之間的臨限電壓;）。在第二 ’取中’冑具有臨限電壓V12之記憶體單元識別為具有相 132526.doc -14- 200907978 對較低之被正確讀取的可能性，因為其臨限電壓係在分布 320與321重疊之處（在¥3與乂7之間）。在第二讀取中，將具 有臨限電壓V13之記憶體單元識別為具有相對較高之被^ 確讀取的可純，因為其臨限電㈣在存在很少或不存在 與其他分布之重疊的分布321之中央（在¥7與乂8之間卜此 可能性資訊可用於執行如在美國專利申請案第丨1/536,286 號及第1 1/536,327號中描述的Ecc校正。在一些狀況下，° Form part of the controller on the same wafer or on different wafers. The ECC circuit (10) performs encoding and decoding operations on (4). In particular, the shell material to be stored is encoded prior to storage. Editing. The rain horse generally involves changing the data so that there is some tedium in the stored data. “How many times to detect and correct the errors that may occur in reading the data. Various ECC methods can be used. Rate, 132526.doc 200907978 Includes a scheme for appending multiple bits (eg, co-located bits) and a scheme for transforming one bit or all data bits. The simple error correction code is encoded by storing two additional parity bits. The data is set to the same logical value as the required logical value when the data is written to the estrus II system Yin. After the data is read by the ^' memory system, the bit is calculated again by Ecc. The group is in the same position. Due to data corruption, the calculated parity may not match the required peers' and the ECC may be (4) job damage. The (4) segment can be used for the segment, so that each segment has some extra Redundant bits. For example, a section with 512 bytes of data can be appended with 8 bytes of ECC data before storage. In general, the more redundant bits used, the more The number of errors detected and corrected ECC can have at least two functions: error predicate and error correction. The ability of each of these functions is usually measured by the number of bits that are measurable as errors and subsequently correctable. The measurement capability can be the same or greater than the correction capability. The number of error bits that can be detected by a typical Ecc is higher than the number of error bits that can be corrected. Sometimes the collection of data bits and parity bits is called a word. The early examples were (7, 4, 35, which had (4) the ability to measure up to two errors per word (seven bits in this example) and the ability to correct an error in seven 7-bit words. More complex ECC can correct each word beyond the single-error, but it becomes more complicated to re-construct the data. The common method is to recover the data and “make some kind of achievable and less likely recovery failure. Sexuality. However, the number of erroneous 5 wu increases. The probability of reliable data recovery is also rapidly decreasing, or the associated cost of 1 and/or performance becomes too high. 132526.doc 200907978 When reading is high Uncorrectable number For the second time, a second attempt can be made to read the data. For example, different sets of read bars can be applied. = See if different reading conditions provide a bead with a lower number of correctable errors 7. Memory The volume system can undergo multiple attempts in this way to read the data until the reading parameters of a particular group provide sufficiently good data (10)c to correct the data). Figure 2 shows an example of how different read parameters can be used. Figure 2 shows the process of programming to two different memory states (logic 0 state and logic 1 state): body: the threshold voltage (Vt) of the element. In this example, the hidden logic of storage logic 2 (represented by distribution 21 )) has a lower threshold voltage and the storage logic 〇: the body unit (represented by distribution 212) has a higher threshold voltage. Logic 6»Limited dust can simply be the threshold power corresponding to the erase state, so that the memory unit of the storage logic 1 maintains the same threshold power waste during the stylization. The data in the memory unit is generally related to the threshold voltage of the comparison memory unit and a predetermined or some predetermined amount. In the example, the first difference voltage vi is used to perform the first read. This means that all 5 memory cells having a power limit C less than VI are considered to store i, while all memory cells having a voltage greater than V1 are considered to be zero. This means that the memory cells in the shaded portion 214 of the distribution 210 of memory cells that are programmed to a logical one state are erroneously read as being in a logic 0 state. This can be provided with the number of the wrong words Wu Xishui ice ^ ^ ^,,. This provides information with multiple errors that cannot be corrected by the ECC scheme used. When there are a large number of uncorrectable errors in the ECC decoding decision data, a different 5 parameters can be used to perform the second reading. In the present example, the second reading is performed using V2 which is a differential of 132526.doc -12. 200907978. This causes the shadows of the 3 parts of the river to be correctly identified as containing. Thus, the number of errors is reduced to an acceptable number and the data can be fully corrected by the ECC. In this example, 'the amount of AV will be adjusted from VI to V2. The direction of adjustment (increase or decrease) and the amount of adjustment can be determined in any suitable way. The adjustment may be based on an expected change in memory cell characteristics due to wear within the life of the memory cell, or a measurement change based on the characteristics of the memory cell. In one example, the reference memory unit is used to track changes that can occur within the memory array and the adjusted read parameters can be based on observed changes in the reference memory unit of the same device. In another example, the correction by the ECC circuit is subjected to statistical analysis to speculate the pattern of memory το performance and to adjust the read parameters accordingly during the lifetime of the spare. Failure analysis of equipment can also provide information on the distribution of threshold voltage over time, allowing for some predictions and appropriate adjustments based on wear calculations. For example, the adjustment can be based on the number of erase cycles experienced by a block or other memory unit. Computer simulation can be used to obtain the parameters of the memory read parameters. Adjust all the blocks of the device on the basis of the page block and the block block, or adjust some other memory unit of the memory. . Thus, in a memory system that uses a predetermined read voltage (eg, νι) read page, the actual differential voltage used (eg, can vary throughout the life of the device and can be different for different pages within the device) In an example, the first read operation is performed using a preset difference voltage such as VI and only when the ECC indicates that the data obtained from the first read cannot be corrected, the second is performed using a different differential voltage such as V2. Read. In its 2 132526.doc 200907978 example, 'a number of different voltages can be used until the data read is correctable. 0 Figure 3 shows the threshold voltage distribution of different logic states in non-volatile memory. Another example of 3 23. In this case, the individual memory cells are programmed into one of four states such that each memory can be referred to as a multi-level memory cell (MLC) memory. The memory unit stores two bits of data. Other MLC designs store more than two (eg, four) bits per memory unit. In general, as the number of bits per memory unit increases, it is assigned to The threshold voltage range of a memory state becomes smaller and the risk of erroneous reading of data increases. Figure 3 shows some overlap between the distributions 320 to 323 for different memory states. Because the ECC can be corrected to reach a certain limit. Error, so an overlap is acceptable. However, if too many errors exist in the data read from the memory, the ECC cannot correct the data. Therefore, it is important to use the correct differential voltage system. In operation, the distinguishing voltages V3, V4, and V5 can be used to identify the memory state of each memory cell. The distinguishing voltages V3, ¥4, and V5 can be preset voltages, or can be freely preset as described above. An offset or offset group. In the second shoulder-splitting operation, 'different voltages V6, V7, V8, V9, V10, and V11 are used to further resolve the threshold voltage of the memory unit. The second read operation can be considered a read having a higher resolution than the first read operation. The second read operation provides an indication of the likelihood that the result of the first read operation is correct. For example, there will be a threshold voltage in the first read. Memory list of V12 and V13 The white is identified as stored (丨, 0) (the threshold voltage between V3 and V4;). The memory unit with the threshold voltage V12 is identified as having the phase 132526.doc -14 in the second 'taken' - 200907978 The possibility of being read correctly for the lower one, since its threshold voltage is where the distributions 320 and 321 overlap (between ¥3 and 乂7). In the second reading, there will be a threshold The memory cell of voltage V13 is identified as being relatively pure and can be read purely because its power limiting (4) is in the middle of the distribution 321 with little or no overlap with other distributions (at ¥7 with Between the 乂8, the possibility information can be used to perform the Ecc correction as described in U.S. Patent Application Serial No. 1/536,286 and No. 1 1/536,327. In some cases,
以較高解析度執行額外讀取操作直至獲得Ecc可校正資料 為止。Perform additional read operations at a higher resolution until Ecc correctable data is obtained.
在配置中’最初將來自非揮發記憶體陣列中之頁的資 料讀取至為讀取/寫入電路之部分的暫存器中。接著將資 料傳送SECC電路用於解碼。記憶體系統可在執行任何額 外讀取操作之前特ECC解碼完成。若解碼成功（所有錯誤 由ECC校正），則記憶體系統讀取下—資料頁。若咖解碼 不成功（錯誤過多以致不能由ECC校正），則記憶體系統使 用不同讀取參數（例如，使用不同區別㈣）來重新讀取相 同資料。舉例而言’―或多個區別電壓可偏移，或可使用 較高解析度來執行讀取。 在-實例t，為增加速度，在將來自資料之第一讀取的 輸出（第-原始資料）傳送至咖電路的㈣及在執行Me 解碼的同時起始相同資料之第二讀取。以此方式，若對第 一輸出f狀ECC解碼^功，财㈣料第二次讀取 貝料的情況下執行對第二輸出資料（第二原始資料）之咖 解碼。此可被s忍為係一形式之讀取快取。 132526.doc 200907978 、圖4展不d憶體系統伽之_部分的實例，在系統彻中 並㈣行兩個操作。在第—操作44时，冑來自第一讀取 之貝料（第一原始貧料）自讀取/寫入電路444中之暫存器 傳送至解碼資料之ECC電路446。同時，使用不同於°第一 讀取之讀取參數執行第二操作447以讀取相同資料。將第 二原始資料自記憶體陣列45〇中之頁448讀取至讀取/寫入 電路444中之另一暫存器452中。來自第一讀取之資料的傳 送與ECC解碼兩者可與第：讀取並行執行，或此等操作中 之僅一者可並行執行。在任一狀況下，來自第一讀取之資 料的至少某進一步處置與執行第二讀取並行執行。 應注意，在圖4之實例中在第一讀取與第二讀取兩者中 項取資料之相同位元。因而，第一原始資料及第二原始資 料對應於相同儲存之資料位元，但由於所使用之不同讀取 參數，第一原始資料及第二原始資料可含有不同位元。在 另實例中，可在來自第一頁之資料正被傳送或被解碼的 同％自第二頁讀取資料。在又一實例中，MLC記憶體將— 個以上邏輯資料頁保存於記憶體陣列之單一實體頁中，且 在傳送及/或解碼一邏輯資料頁的同時，可自同一實體頁 讀取另一邏輯資料頁。在此狀況下，儘管在兩次讀取操作 中皆讀取相同記憶體單元，但是讀取資料之不同位元。舉 例而言，在每記憶體單元儲存兩位元之記憶體（參見圖3之 實例）中，可將一位元認為是低位元且將一位元認為是高 位元。可將實體頁之低位元認為係一低邏輯頁且可將實體 頁之向位元認為係一高邏輯頁。在MLC記憶體中，在解碼 132526.doc -16· 200907978 來自同一實體頁之先前邏輯頁的同時讀取後續邏輯頁可為 有效的。相比而言，圖4之記憶體系統400在兩次讀取操作 令讀取資料之相同位元（上頁或下頁）。 在某些狀況下，兩次讀取操作便足以獲得ECC可校正資 料。在其他狀況下，可能需要三次或三次以上的讀取操 作在一·«例中，使用不同讀取參數執行連續讀取操作直 至獲传ECC可校正資料或達到某限制為止。 圖5展不一並仃操作之實例’其中使用不同讀取參數之 序列自記憶體陣列讀取資料頁，且在執行每—讀取的同 時’將來自同-頁之較早讀取的資料傳送至執行ECC解碼 之ECC電路。圖5展示在相同資料之一連串反覆讀取期 門在匯流排（匯流排”線）上與記憶體及讀取/忙碌（”r/b" ”W R/B”）的通信。詳言之，圖5展示與使用—不同於第 -讀取電壓之第二讀取電麼(2„d Vrd)的第二感測並行地傳 送第一讀取資料、U"〜d"。在傳送第一讀取資料 後且在傳送第二資料之前，將第三讀取電屋” Vrd Qf γ （例如，自記憶體控制器）發送至讀取/寫入電路。第 …貝取電壓可藉由任何適當方案來判定。隨後，此電壓用 於執行與第二讀取資料之傳送"D〇ut 2nd㈤”並行發生的 ^三感測W sensing w/3,d Vrd")。以此方式執行多次反 ，且在每一反覆中使用不同的讀取電S。可執行反覆直 讀取ECC可校正之貢料為止。允許反覆次數可能有所限 ’因此若達到限制則認為該頁為無法校正。 圖6展示讀取含有三個邏輯資料頁（字線wl〇之下頁、中 132526.doc -17. 200907978 間頁及上頁）之MLC記憶體的杏 m只體頁的實例。在第一反覆 中，使用第一組讀取電壓來# 水喝取下頁'中間頁及上頁，且 將藉由此讀取操作所獲得之次 X侍之資料輸出至ECC電路。邏輯頁 之讀取可與將先前邏輯頁 、 貝之-貝料輸出至ECC電路並行發 生。當第一反覆讀取結走拉 果寺’使用先前供應至讀取/寫入 電路的第二組讀取電壓（V d ^ of 2 set)開始第二反覆。隨 後，當第二反覆讀取結束時，二 ± 弟二反覆讀取開始，其使用 第一、’且取電壓。持續反覆直至最終反覆為止。此程序可 因為讀取ECC可校正資料而終止，或因為達到某最大反覆 次數而終止。 本文所引用之所有專务丨、击*丨山 專利申請案、論文、書、說明 書、其他公開案、文件及畜 及事物之全部内容為所有目的特此 以引用的方式併入本文中。 Τ 就在所併入之公開案、文件或 事物中之# |與本文件之文字之間的術語之定義或使用 中的任何不一致或衝突而言，本文件中的術語之定義或使 用應占主導。In the configuration, the data from the pages in the non-volatile memory array is initially read into a register that is part of the read/write circuit. The data is then passed to the SECC circuit for decoding. The memory system can perform ECC decoding before performing any additional read operations. If the decoding is successful (all errors are corrected by ECC), the memory system reads the next-data page. If the coffee decoding is unsuccessful (too many errors to be corrected by ECC), the memory system uses different read parameters (for example, using different differences (4)) to reread the same data. For example, 'or multiple differential voltages may be offset, or higher resolution may be used to perform the reading. In the instance t, in order to increase the speed, the output (first-original data) from the first reading of the data is transmitted to (4) of the coffee circuit and the second reading of the same data is started while the Me decoding is performed. In this way, if the first output f-shaped ECC is decoded, the fourth (fourth source) data is decoded in the case where the second material is read. This can be tolerated by a form of read cache. 132526.doc 200907978, Figure 4 shows an example of the _ _ part of the system, in the system and (4) two operations. At the first operation 44, the sputum from the first read (the first raw lean) is transferred from the register in the read/write circuit 444 to the ECC circuit 446 which decodes the data. At the same time, a second operation 447 is performed using a read parameter different from the first read to read the same data. The second source material is read from page 448 in memory array 45A into another register 452 in read/write circuit 444. Both the transfer and the ECC decoding from the first read data can be performed in parallel with the first: read, or only one of the operations can be performed in parallel. In either case, at least some further processing from the first read of the material is performed in parallel with performing the second read. It should be noted that in the example of Figure 4, the same bits of data are taken in both the first read and the second read. Thus, the first original data and the second original data correspond to the same stored data bits, but the first original data and the second original data may contain different bits due to different read parameters used. In another example, the data may be read from the second page at the same % of the data from the first page being transmitted or decoded. In yet another example, the MLC memory stores more than one logical data page in a single physical page of the memory array, and can read another logical page from the same physical page while transmitting and/or decoding a logical data page. Logical data page. In this case, although the same memory cell is read in both read operations, different bits of the data are read. For example, in a memory that stores two bits per memory cell (see the example of Figure 3), a bit can be considered a low bit and a bit is considered a high bit. The lower bits of the physical page can be thought of as a low logical page and the physical bit of the physical page can be considered to be a high logical page. In MLC memory, it is possible to read subsequent logical pages while decoding 132526.doc -16· 200907978 from the previous logical page of the same physical page. In contrast, the memory system 400 of Figure 4 reads the same bits (upper or lower page) of the data in two read operations. In some cases, two read operations are sufficient to obtain ECC calibratable data. In other cases, three or more read operations may be required. In the example, a continuous read operation is performed using different read parameters until the ECC correctable data is received or a certain limit is reached. Figure 5 shows an example of an operation in which a data page is read from a memory array using a sequence of different read parameters, and the data read from the same page is read at the same time as each read. Transfer to the ECC circuit that performs ECC decoding. Figure 5 shows the communication with the memory and the read/busy ("r/b" "W R/B") on the bus (bus) line in a series of identical readings. In detail, FIG. 5 shows that the first read data, U"~d" is transmitted in parallel with the second sense using a second read voltage (2'd Vrd) different from the first read voltage. The third read house "Vrd Qf γ (eg, from the memory controller) is sent to the read/write circuit after transmitting the first read data and before transmitting the second data. The first fetch voltage can be determined by any suitable scheme. Subsequently, this voltage is used to perform a three-sensing W sensing w/3, d Vrd" in parallel with the transmission of the second read data "D〇ut 2nd(5)". In this way, multiple inverses are performed, and A different reading power S is used in each of the repetitions. It is possible to perform a reverse reading of the ECC correctable tract. The number of repetitions allowed may be limited. Therefore, if the limit is reached, the page is considered uncorrectable. Figure 6 shows reading Take an example of an apricot m body page containing three logical data pages (pages below the word line wl〇, 132526.doc -17. 200907978 page and above). In the first iteration, use The first group reads the voltage to #水水取下下' the middle page and the upper page, and outputs the data of the second X obtained by the reading operation to the ECC circuit. The reading of the logical page can be The logic page, the shell-bee output to the ECC circuit occurs in parallel. When the first repeat reads the junction, the Lagoon' uses the second set of read voltages previously supplied to the read/write circuit (V d ^ of 2 Set) begins the second iteration. Then, when the second repeat reading ends, the two ± brothers repeatedly read Initially, it uses the first, 'and takes the voltage. It continues to repeat until it finally repeats. This program can be terminated by reading the ECC correctable data, or terminated because it reaches a certain maximum number of repetitions. All the specialties cited in this article丨The entire contents of the patent application, papers, books, specifications, other publications, documents, and articles of animals and articles of the 丨 丨 为 为 为 为 为 为 为 为 为 为 全部 全部 全部 全部 全部 Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ Τ The definition or use of terms in this document shall be dominant in the definition or use of terms in the file or in the definition of the terms in this document or in any inconsistency or conflict in use.
儘管已關於特定較#眘A 罕乂佳實把例描述了本發明之各種態樣， 但是應理解，本發明古描+ @ 1 + 货月有榣在隨附申請專利範圍之全範疇内 受到保護。 【圖式簡單說明】 圖1展丁。己隐體系統之包括非揮發記憶體陣列、解碼器 電路及ECC電路之_部分。 圖展示在非揮發&己憶體陣列中經程式化至邏輯0狀態及 邏輯1狀態的記情、體置 〜體早7L與用於判定記憶體單元之狀態的 132526.doc -18- 200907978 電壓的分布。 圖3展示在MLC記憶體陣列中經程式化至不同邏輯狀態 之記憶體單元與用於判定記憶體單元之狀態的電壓之分 布。 圖4展示在並行執行兩個操作之情況下的記憶體系統之 一部分’將使用第一讀取參數讀取之資料傳送至Ecc電路 且使用第^一讀取參數讀取相同資料。 圖5展示在不同反覆中使用不同讀取參數來讀取資料 頁，及在執行後續讀取的同時輸出來自—讀取之資料的實 例0 圖6展示在不同反覆中使用不同讀取參數來讀取三個邏 輯資料頁，及在執行後續讀取的同時輪出來自—讀取之資 料的實例。 【主要元件符號說明】 100 102 104 106 108 210 212 214 320 321 非揮發記憶體系統 非揮發記憶體單元之陣列/記憶體陣列 周邊電路/列解碼器電路 周邊電路//行解碼器及讀取/寫入電路 周邊電路/錯誤校正編碼（Eec)電路. 分布 分布 陰影部分 臨限電壓分布 臨限電壓分布 132526.doc •19· 200907978 322 臨限電壓分布 323 臨限電壓分布 400 記憶體糸統 440 第一操作 442 暫存器 444 讀取/寫入電路 446 ECC電路 447 第二操作 448 頁 450 記憶體陣列 452 暫存器 132526.doc -20-Although various aspects of the present invention have been described with respect to specific examples, it should be understood that the present invention is subject to the full scope of the accompanying claims. protection. [Simple description of the diagram] Figure 1 shows the show. The hidden system includes a non-volatile memory array, a decoder circuit, and a portion of the ECC circuit. The figure shows the characterization of the logic 0 state and the logic 1 state in the non-volatile & memory array, the body ~ body 7L and the state used to determine the state of the memory unit 132526.doc -18- 200907978 The distribution of voltage. Figure 3 shows the distribution of voltages programmed into different logic states in the MLC memory array and the voltage used to determine the state of the memory cells. Figure 4 shows a portion of the memory system in the case where two operations are performed in parallel. The data read using the first read parameter is transferred to the Ecc circuit and the same data is read using the first read parameter. Figure 5 shows an example of using different read parameters to read a data page in different iterations, and outputting data from-read data while performing subsequent reads. Figure 6 shows reading with different read parameters in different iterations. Take three logical data pages, and rotate the instance of the data from-read while performing subsequent reads. [Main component symbol description] 100 102 104 106 108 210 212 214 320 321 Non-volatile memory system Non-volatile memory cell array / memory array peripheral circuit / column decoder circuit peripheral circuit / / row decoder and read / Write circuit peripheral circuit / error correction coding (Eec) circuit. Distribution distribution shadow part threshold voltage distribution threshold voltage distribution 132526.doc •19· 200907978 322 threshold voltage distribution 323 threshold voltage distribution 400 memory system 440 An operation 442 register 444 read/write circuit 446 ECC circuit 447 second operation 448 page 450 memory array 452 register 132526.doc -20-