TWI455142B - Data storage device and data read method of a flash memory - Google Patents

Description

Method for reading data of flash memory and data storage device

The present invention relates to data storage devices, and more particularly to flash memory.

Flash memory is a kind of non-volatile memory, that is, when the flash memory does not receive power, the data stored in the flash memory will not disappear due to loss of power, so the flash memory Widely used in portable devices with limited power for storing data. The flash memory contains a plurality of memory cells, each of which can store 2 ^N potentials. For example, each memory unit can store two kinds of potential flash memory, which is called a single level cell (SLC) flash memory, and each memory unit can store four kinds of potential flash memory. It is a multi-level cell (MLC) flash memory, and each memory cell can store 8 kinds of potential flash memory called triple level cell (TLC) flash memory.

When the host wants to read data from the flash memory, the flash memory determines the desired reading according to a set of read voltages to determine which range of the read voltage the voltage of the memory cell to be read falls. What is the value of the data stored in the memory unit? For example, when the flash memory is a single-layer cell flash memory, the corresponding read voltage has only one demarcation value. When the voltage of the memory cell is higher than the demarcation value, the data storage value of the memory cell is determined. It is bit 0, and when the voltage of the memory cell is lower than the threshold value, the data storage value of the memory unit is determined as bit 1. In addition, when the flash memory is a multi-level cell flash memory, the corresponding read voltage has three demarcation values, and the data storage value of the memory cell is discriminated according to the relative magnitude of the voltage of the memory cell and the three demarcation values. 11, 01, 00, or 10. Similarly, when the flash memory is a three-layer cell flash memory, the corresponding read voltage has seven demarcation values to distinguish the data storage value of the memory cell according to the relative magnitude of the voltage of the memory cell and the seven demarcation values. It is a bit 111, 011, 001, 101, 100, 000, 010, or 110. Figure 1 is a schematic diagram of a set of read voltages for a three-layer cell flash memory. The read voltage may vary depending on the number of bits stored in the memory cells of the three-layer cell flash memory.

Therefore, the read voltage determines the read data value of the memory cell of the flash memory. That is, the determination of the voltage stored in a memory cell through different read voltages may result in different data readout values. Therefore, when the flash memory receives the command to read the data from the host and reads the stored data, but the data is read incorrectly, an attempt can be made to read the stored data again using different read voltages. However, how to select the correct read data value from a plurality of different read data values generated from a plurality of different read voltages is a problem. Therefore, the present invention provides a method for reading data of a flash memory so that when a data is read but an error occurs, the read voltage can be modified to generate a correct read data value.

In view of the above, an object of the present invention is to provide a method for reading data of a flash memory to solve the problems of the prior art. In one embodiment, the flash memory includes a plurality of pages, each of which is written with a predetermined amount of information. First, an address is read from the flash memory at an original read voltage to obtain an original data and an original error correction code. Then, the error bit of the original data is corrected according to the original error correction code by a first error correction process. When the first error correction program cannot correct the error bit of the original data, the predetermined information corresponding to the original data is read from the flash memory by the original read voltage to obtain a calibration information (calibration information) ). Then, the original data is modified according to the difference between the correction information and the predetermined information to generate a modified data. Then, the original error correction code is modified according to the difference between the correction information and the predetermined information to generate a modified error correction code. Then, the error bit of the modified data is corrected according to the modified error correction code by a second error correction program. Finally, when the second error correction program successfully corrects the error bit of the original data to obtain a second output data, the second output data is transmitted to the host as read data.

The invention further provides a data storage device. In one embodiment, the data storage device is coupled to a host, including a flash memory and a controller. The flash memory includes a plurality of pages for storing data, wherein each of the pages is written with a predetermined information. The controller instructs the flash memory to read an address with an original read voltage to obtain a raw data and an original error correction code, and the first error correction process is based on the original error correction code. Correcting an error bit of the original data, and when the first error correction program cannot correct the error bit of the original data, instructing the flash memory to read the predetermined correspondence corresponding to the original data with the original read voltage The information is obtained by a calibration information, and the original data is modified according to the difference between the correction information and the predetermined information to generate a modified data, and the original error correction code is modified according to the difference between the correction information and the predetermined information to generate a Modifying the error correction code, correcting the error bit of the modified data according to the modified error correction code by a second error correction program, and obtaining a second when the second error correction program successfully corrects the error bit of the original data When the data is output, the second output data is transmitted to the host as read data.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

2 is a schematic diagram of a block 200 for storing data in accordance with the flash memory of the present invention. The data block 200 includes a plurality of pages 201-20K for storing data, and each page can store a plurality of data sectors. In one embodiment, each data segment has a size of 512 bytes, and a page of data block 200 stores 4 data segments. In general, in order to reduce the errors generated during data storage, the flash memory controller encodes an error correction code (ECC) according to the data segment before storing the data segment in the flash memory. ), and store the data section and store the corresponding error correction code to the flash memory. For example, page 201 stores four data sections 201a, 201b, 201c, and 201d, each of which contains a corresponding error correction code. In addition, in order to find the correct read data from the plurality of read data read from the flash memory according to the plurality of sets of read voltages, the controller writes a predetermined information to the flash when the data is stored. In memory. In one embodiment, each page of the data block 200 stores a predetermined message. For example, page 201 stores a predetermined message 201e. In an embodiment, the predetermined information has only one tuple. For example, the value of the predetermined information may be 0x55 (bit 0101101).

Figure 3 is a block diagram of a data storage device 302 in accordance with the present invention. The data storage device 302 is coupled to a host 304. In one embodiment, the data storage device 302 includes a controller 312 and a flash memory 314. The controller 312 accesses the data of the flash memory 314 in accordance with the instruction of the host 304. When the host 304 sends a write command to the data storage device 302, the controller 312 writes the data to the flash memory 314 in accordance with the write command. In particular, the controller 312 writes a predetermined piece of information to the flash memory 314 when the data is written, as shown in FIG. When the host 304 sends a read command to the data storage device 302, the controller 312 reads the data from the flash memory 314 in accordance with the read command. However, even if a read error occurs in the read data, the controller 312 can instruct the flash memory 314 to generate a plurality of read data values at different read voltages, and according to the reservation stored in the flash memory 314 in advance. Information determines the correct reading of data values to avoid read errors.

Figure 4 is a flow diagram of a method 400 of reading data from a flash memory in accordance with the present invention. Controller 312 performs data reading on flash memory 314 in accordance with method 400. In one embodiment, the controller 312 includes an error correction module 322, a data modification module 324, and a buffer 326. First, controller 312 instructs flash memory 314 to read an address at an original voltage (step 402). After the flash memory 314 reads the original data and the corresponding error correction code according to the command of the controller 312, the error correction module 322 corrects the error according to an error correction process. The code corrects the error bit of the original data (step 404). At this time, if the error bit of the original data is successfully corrected to generate an output data (step 406), the controller 312 stores the output data generated by the error correction module 322 to the buffer 326, and then the buffer 326. The output data is delivered to host 304 (step 420).

If the error bit of the original material cannot be successfully corrected (step 406), the error correction module 322 cannot generate a correct output data for transmission to the host 304. At this time, the controller 312 requests the flash memory 314 to read the predetermined information corresponding to the original data with the original read voltage to obtain a correction information (step 408). In one embodiment, the predetermined information is stored in the same page as the original data in the same block of the flash memory 314, as shown in FIG. The controller 312 can find out the type of error bit occurrence based on the difference between the read correction information and the original predetermined information. For example, suppose the original predetermined information is a byte 0x55 (bit string 01010101), and the correction information read by the flash memory 314 according to the original read voltage is a byte 0x54 (bit string 01010100). . Thus, the controller 312 can know that part of the bit 1 in the predetermined information 0x55 is determined to be the bit 0 in the correction information 0x54 via the original read voltage, so the controller 312 can determine an error bit from the correction information. The value is 0. That is, the bit 0 of the correction information is an error bit.

Next, the controller 312 requests the flash memory 314 to read the address with a modified read voltage (step 410), wherein the modified read voltage is not the same as the original read voltage. In one embodiment, the controller 312 adjusts the original read voltage according to the predetermined information and the correction information to obtain the modified read voltage. In one embodiment, the flash memory 314 includes a read voltage setting circuit 330 that changes the set value of the read voltage in accordance with an instruction from the controller 312. Next, the flash memory 314 performs data reading according to the modified read voltage to obtain a reread data and a reread error correction code (step 410). Of course, since the read voltages are different, the re-reading data and the original data will be different in some bits, and the re-reading error correction code and the original error correction code will also be different. At this time, the data modification module 324 can modify the partial difference bits of the reread data and the original data according to the error bit value determined by the difference between the correction information and the predetermined information, so as to obtain a modification with a higher correct rate. Information (step 412). Similarly, the data modification module 324 can also modify the partial error bits of the reread error correction code and the original error correction code according to the error bit value determined by the difference between the correction information and the predetermined information, so as to obtain a higher correctness. A modified error correction code for the rate (step 414). The detailed flow of steps 412 and 414 will be described with reference to FIG.

Figure 5 is a flow diagram of a method 500 of modifying original data and original error correction code in accordance with the present invention. The data modification module 324 generates modified data and modifies the error correction code according to the method 500. First, the data modification module 324 discriminates a plurality of first difference bits that are different from the original data and the reread data (step 502). Assume that the original data is the bit string 0000011111, and the reread data is 0000111110. Therefore, the original data and the reread data have two different bits, which are the bit 0 of the order 5 and the bit 1 of the order 10 in the original data. Next, the data modification module 324 discriminates a plurality of second difference bits that are different from the reread error correction code (step 504). Assume that the original error correction code is the bit string 01010 and the reread error correction code is 01011. Therefore, the difference bit between the original error correction code and the reread error correction code is the bit 1 of the order 5 in the original error correction code.

Next, the data modification module 324 compares the difference between the correction information and the predetermined information to select an error bit value from the bit 0 and the bit 1 (step 506). As in the previous example, it is assumed that the predetermined information is the byte 0x55 (bit string 01010101), and the correction information is the byte 0x54 (bit string 01010100), so the data modification module 324 can determine from the correction information. An error bit value of 0. Next, the data modification module 324 identifies a plurality of third difference bits having the error bit value from the plurality of first difference bits of the original data (step 508), and inverts the third of the original data. The value of the difference bit is obtained to obtain the modified material (step 510). For example, since only the bit 0 of the order 5 of the two difference bits of the bit string 0000011111 of the original material is equal to the error bit value 0, the data modification module 324 inverts the bit 0 of the order 5 in the original material. For bit 1, the bit string 0000111111 of the modified data is obtained.

Next, the data modification module 324 discriminates a plurality of fourth difference bits having the error bit value from the plurality of second difference bits of the original error correction code (step 512), and inverts the original error correction code. The values of the fourth difference bits are used to obtain the modified error correction code (step 514). For example, since only the difference bit 0 of the order 5 in the bit string 01010 of the original error correction code is equal to the error bit value 0, the data modification module 324 inverts the bit 0 of the order 5 in the original error correction code as Bit 1, and the bit string 01011 of the modified error correction code is obtained.

Finally, after the data modification module 324 generates the modification data and modifies the error correction code, the data modification module 324 sends the modification data and the modification error correction code to the error correction module 322. Next, the error correction module 322 corrects the error bit of the modified data according to the modified error correction code by the error correction program (step 416). At this time, if the error correction module 322 can successfully correct the error bit of the modified data to generate an output data (step 418), the error correction module 322 transmits the output data to the buffer 326. Next, buffer 326 transmits the correct output data to host 304 to complete the execution of the read operation. On the other hand, if the error correction module 322 cannot successfully correct the error bit of the modified data, the controller 312 can again reset the newly modified read voltage by the read voltage setting circuit 330, and then perform steps 410-418 again. In the event that the error correction module 322 still fails to successfully correct the error bit of the modified data, the controller 312 reports that the host 304 failed to read the data (step 422).

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

(Fig. 2)

200. . . Data block

201a~201d, 202a~202d, 20ka~20kd. . . Data section

201e, 202e, 20ke. . . Booking information

(Fig. 3)

302. . . Data storage device

304. . . Host

312. . . Controller

314. . . Flash memory

322. . . Error correction module

324. . . Data modification module

326. . . buffer

as well as

330. . . Read voltage setting circuit

Figure 1 is a schematic diagram of a set of read voltages of a three-layer unit flash memory;

2 is a schematic diagram of a flash memory for storing a block of data according to the present invention;

Figure 3 is a block diagram of a data storage device in accordance with the present invention;

Figure 4 is a flow chart showing a method of reading data of a flash memory according to the present invention;

Figure 5 is a flow chart of a method of modifying the original data and the original error correction code in accordance with the present invention.

302. . . Data storage device

304. . . Host

312. . . Controller

314. . . Flash memory

322. . . Error correction module

324. . . Data modification module

326. . . buffer

as well as

330. . . Read voltage setting circuit

Claims (16)

A method for reading data of a flash memory, wherein the flash memory comprises a plurality of pages, each of the pages is written with a predetermined information, and the method comprises the following steps: Taking a voltage from the flash memory to read an address to obtain an original data and an original error correction code; correcting the original data error according to the original error correction code by a first error correction process a bit; when the first error correction program cannot correct the error bit of the original data, reading the predetermined information corresponding to the original data from the flash memory with the original read voltage to obtain a correction information (calibration information); modifying the original data according to the difference between the correction information and the predetermined information to generate a modified data; modifying the original error correction code according to the difference between the correction information and the predetermined information to generate a modified error correction code; a second error correction program corrects the error bit of the modified data according to the modified error correction code; and when the second error correction program succeeds When the modification information bit error correction to obtain a second output of the data, and the second output data as a read data transmitted to a host. The method for reading data of a flash memory according to claim 1, wherein the predetermined information corresponding to the original data is stored in the same page of the flash memory as the original data. Reading of the flash memory as described in item 1 of the patent application scope And the method further includes: when the first error correction program cannot correct the error bit of the original data, reading the address from the flash memory with a modified read voltage to obtain a reread Data and a reread error correction code; wherein the modified read voltage is different from the original read voltage, and the modified data is generated according to the difference between the original data and the reread data, and the modified error correction code is based on the original error The difference between the correction code and the reread error correction code is generated. The method for reading data of a flash memory according to claim 3, wherein the step of generating the modified data comprises: identifying a plurality of first difference bits that are different from the reread data; Determining the difference between the correction information and the predetermined information by selecting an error bit value from the bit 0 and the bit 1; selecting the plurality of error bit values from the first difference bits of the original data a third difference bit; and a value of the third difference bit of the original data to obtain the modified material. The method for reading data of a flash memory according to claim 4, wherein the step of selecting the error bit value comprises: when a plurality of bits 0 of the correction information correspond to the predetermined information Bit 1 determines that the error bit value is bit 0; and when the plurality of bits 1 of the correction information correspond to a plurality of bits 0 in the predetermined information, determining the error bit value as bit 1 . Reading of the flash memory as described in item 3 of the patent application scope And the method for generating the modified error correction code includes: identifying a plurality of second difference bits different from the original error correction code and the reread error correction code; comparing the difference between the correction information and the predetermined information Selecting an error bit value from bit 0 and bit 1; selecting a plurality of fourth difference bits having the error bit value from the second difference bit of the original error correction code; and inverting Flicking the values of the fourth difference bits of the original error correction code to obtain the modified error correction code. The method for reading data of a flash memory according to claim 3, wherein the modified read voltage is obtained by adjusting the original read voltage according to a difference between the correction information and the predetermined information. The method for reading data of a flash memory according to claim 1, wherein the method further comprises: obtaining a first output when the first error correction program successfully corrects the error bit of the original data; When the data is used, the first output data is transmitted to the host as read data. A data storage device is coupled to a host, comprising: a flash memory, comprising a plurality of pages for storing data, wherein each of the pages is written with a predetermined information; and a controller that commands the fast The flash memory reads an address with an original read voltage to obtain an original data and an original error correction code, and corrects the error of the original data according to the original error correction code by a first error correction process. a bit, and when the first error correcting program cannot correct the error bit of the original data, commanding the flash The memory device reads the predetermined information corresponding to the original data by using the original read voltage to obtain a calibration information, and modifies the original data according to the difference between the correction information and the predetermined information to generate a modified data. Correcting the original error correction code by the difference between the correction information and the predetermined information to generate a modified error correction code, correcting the error bit of the modified data according to the modified error correction code by a second error correction program, and when the second The error correction program successfully corrects the error bit of the modified data to obtain a second output data, and transmits the second output data to the host as the read data. The data storage device of claim 9, wherein the predetermined information corresponding to the original data is stored in the same page of the flash memory as the original data. The data storage device of claim 9, wherein when the first error correction program cannot correct the error bit of the original data, the controller commands the flash memory to read at a modified read voltage. The address is obtained by obtaining a reread data and a rereading error correction code, and modifying the original data according to the difference between the original data and the rereading data to generate the modified data, and according to the difference between the original error correction code and the rereading error correction code The original error correction code is modified to generate the modified error correction code, wherein the modified read voltage is different from the original read voltage. The data storage device of claim 11, wherein when the controller modifies the original data, the controller identifies the plurality of first difference bits that are different from the reread data, and compares the corrections. The difference between the information and the predetermined information is selected from the bit 0 and the bit 1 to select an error bit value from the first difference bit of the original data. There are a plurality of third difference bits of the error bit value, and values of the third difference bits of the original data are flipped to obtain the modified material. The data storage device of claim 12, wherein when the controller selects the error bit value, if a plurality of bits 0 of the correction information correspond to a plurality of bits 1 in the predetermined information, Then the controller determines that the error bit value is bit 0; and if the plurality of bits 1 of the correction information correspond to a plurality of bits 0 in the predetermined information, the controller determines the error bit value Bit 1. The data storage device of claim 11, wherein when the controller modifies the original error correction code, the controller discriminates the plurality of second differences that the original error correction code is different from the reread error correction code a bit, comparing the difference between the correction information and the predetermined information to select an error bit value from the bit 0 and the bit 1, and selecting the error from the second difference bit of the original error correction code A plurality of fourth difference bits of the bit value, and a value of the fourth difference bit of the original error correction code to obtain the modified error correction code. The data storage device of claim 11, wherein the controller adjusts the original read voltage according to the difference between the correction information and the predetermined information to obtain the modified read voltage. The data storage device of claim 9, wherein the controller outputs the first output data when the first error correction program successfully corrects the error bit of the original data to obtain a first output data. Transferred to the host as read data.