201135745 六、發明說明： 【發明所屬之技術領域】 本發明係有關於資料儲存裝置，特別是有關於快閃記 憶體。 【先前技術】 快閃記憶體（flash memory)係一種非揮發記憶體，亦 即，當快閃記憶體不接受供電時，快閃記憶體中儲存的資 料亦不會因失去電力而消失，因此快閃記憶體廣泛地被運 用在電力有限的可攜式裝置供儲存資料。快閃記憶體包含 多個記憶單元(memory cell)，每一記憶單元可儲存2N種電 位。例如，每一記憶單元可儲存2種電位的快閃記憶體稱 之為單層單元(single level cell, SLC)快閃記憶體，每一記憶 單元可儲存4種電位的快閃記憶體稱之為多層單元（multi level cell，MLC)快閃記憶體，而每一記憶單元可儲存8種 電位的快閃記憶體稱之為三層單元(triple level cell，TLC) 快閃記憶體。 當主機欲由快閃記憶體讀取資料時，快閃記憶體會依 據一組讀取電壓以判定所欲讀取的記憶單元的電壓落在讀 取電壓的哪一範圍，從而認定所欲讀取的記憶單元所儲存 之資料值為何。舉例來說，當快閃記憶體為單層單元快閃 記憶體時，對應的讀取電壓僅有一個分界值，當記憶單元 的電壓高於該分界值時記憶單元之資料儲存值會被判定為 位元0，而當記憶單元的電壓低於該分界值時記憶單元之 資料儲存值會被判定為位元1。另外，當快閃記憶體為多 層單元快閃記憶體時，對應的讀取電壓有三個分界值，以 SMI-10-003/9031 -A42398-TW/Final 4 201135745 依據記憶單元的電壓與三個分界值的相對大小辨別記憶單 元之資料儲存值為位元11、01、00、或10。同樣的，當快 閃記憶體為三層單元快閃記憶體時，對應的讀取電壓有七 個分界值，以依據記憶單元的電壓與七個分界值的相對大 小辨別記憶單元之資料儲存值為位元11卜01卜〇(Π、101、 100、000、010、或110。第1圖為三層單元快閃記憶體的 一組讀取電壓的示意圖。讀取電壓可因三層單元快閃記憶 體之記憶單元所儲存的位元數目而不同。 • 因此，讀取電壓決定了快閃記憶體之記憶單元的讀出 資料值。亦即，一記憶單元所儲存的電壓經過不同的讀取 電壓的判定可產生不同的資料讀出值。因此，當快閃記憶 體收到主機讀取資料的命令而對儲存資料進行讀取，但讀 出資料卻發生錯誤時，可嘗試運用不同的讀取電壓重新對 儲存資料進行讀取。然而，如何自依據多個不同的讀取電 壓所產生的多個不同的讀出資料值中選擇正確的讀出資料 值是一個問題。因此，本發明提出一種快閃記憶體之資料 • 讀取的方法，以便於讀出資料卻發生錯誤時，仍可藉修改 讀取電壓而產生正確的讀出資料值。 【發明内容】 有鑑於此，本發明之目的在於提供一種快閃記憶體之 資料讀取的方法，以解決習知技術存在之問題。於一實施 例中，該快閃記憶體包含多個頁（page)，每一該等頁皆被寫 入一筆該預定資訊。首先，以一原始讀取電壓自該快閃記 憶體讀取一位址，以得到一原始資料以及一原始錯誤修正 碼。接著，以一第一錯誤修正程序（errorcorrectionprocess) SMI-10-003/9031-A42398-TW/Final 5 201135745 依據該原始錯誤修正碼修正該原始資料之錯誤位元。當該 第錯决修j£程序無法修正該原始資料之錯誤位元時，以 “原始項取電墨自該快閃記憶體讀取對應於該原始資料之 該，定資訊，以得5丨卜校正資訊(calibration information)。 接著依據該校正資訊與該預定資訊之差別修改該原始資 ，以產生修改資料。接著，依據該校正資訊與該預定資 A之差，修改該原始錯誤修正碼以產生—修改錯誤修正 馬接著’以-第二錯誤修正程序依據該修改錯誤修正碼 〇正該修改資料之錯誤位元。最後，當該第二錯誤修正程 序成力也仏正該原始資料之錯誤位元而得到一第二輸出資 料時’將該第二輸出資料作為讀出資料而傳送至一主機。 本發明更提供一種資料儲存裝置。於一實施例中，該 貝料儲存裝置麵接至—主機，包括_快閃記憶體以及一控 制器°該快閃記憶體包括多個頁以供儲存資料，其中每-該等頁皆被寫一敎資訊^難㈣命令錄閃記憶體 以-原始讀取電壓讀取—位址以得到—原始資料以及一原 始錯誤修正碼，以-第—錯誤修正㈣（e_ e_cti〇n pro—依據該原始錯誤修正碼修正該原始f料之錯誤位 70，以及當該第-錯婦正程序無法修正該原始資料之錯 誤位元時，命令該快閃記憶體以該原始讀取電壓讀取對應 於該原始㈣之該預定資訊以得到—校正資訊(ea版ation information) ’依據該校正資訊與該預定資訊之差別修改該 原始資料以產生-修改資料’依據該校正資訊與該預定資 訊之差別修改㈣始錯誤修正·U生—修改錯誤修正 碼，以-第二錯誤修正程序依據該修改錯誤修正碼修正該 SMI-10-003/9031 -A42398-TW/Final Λ 201135745 修改資料之錯誤位元，以及當該第二錯誤修正程序成功地 修正該原始資料之錯誤位元而得到一第二輸出資料時將該 第二輸出資料作為讀出資料而傳送至該主機。 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂’下文特舉數較佳實施例，並配合所附圖示，作 詳細說明如下： 【實施方式】 第2圖為依據本發明之快閃記憶體用以儲存資料之一 • 區塊（bl〇Ck)2〇〇的示意圖。資料區塊200包括多個頁 (page)201〜20K以供儲存資料，每—頁可儲存多個資料區段 (sector)。於一實施例中，每一資料區段之大小為512位元 組，而資料區塊200的一頁可儲存4個資料區段。一般而 言’為了減少資料儲存時產生的錯誤，於—資料區段儲存 至快閃記憶體之前，快閃記憶體的控制器會事先依據資料 區段編碼-錯誤修正碼(Em)r e。職tiQn eQde，EC〇，並在 儲存資料區段時-併將對應的錯誤修正碼儲存至快閃記憶 #體。舉例來說，頁201儲存了 4個資料區段201a、屢、 201c、以及201d，每一資料區段2〇la、2〇lb、2〇ic、以及 腿皆包含-對應的錯誤修正碼。另外，為了自依據多組 δ貝取電壓自快閃記憶體所讀取多個的讀出資料中找出正瑞 的讀出資料’控制器會於儲存資料時一併將一預定資訊寫 入快閃記憶體中。於一實施例中，資料區塊的每一頁 儲存一預定資訊。例如，頁201儲存-預定資訊201e。於 -實施例中，該預定資訊僅有—位元組。例如，該預定資 訊之值可為0x55(位元OlOioioi)。 SMI-10-003/9031-A42398-TW/Final 7 201135745 第3圖為依據本發明之資料儲存裝置3〇2的區塊圖。 資料儲存裝置302耦接至一主機304。於一實施例中，資 料儲存裝置302包括一控制器312以及一快閃記憶體314。 控制器312依據主機304之指示存取快閃記憶體314之資 料。當主機304向資料儲存裝置302發送寫入命令時，控 制器312依據寫入命令將資料寫入快閃記憶體314。特別 是’控制器312會於寫入資料時將一預定資訊一併寫入快 閃記憶體314，如第2圖所示。當主機304向資料儲存裝 置302發送讀取命令時，控制器312依據讀取命令將資料 由快閃記憶體314讀出。然而，即使讀出的資料發生讀取 錯誤，控制器312依然可命令快閃記憶體314以不同的讀 取電壓產生多個讀取資料值，並依據事先儲存於快閃記憶 體314中的預定資訊決定正確的讀取資料值，以避免讀取 錯誤的發生。 第4圖為依據本發明之快閃記憶體之資料讀取的方法 400的流程圖。控制器312依據方法400以對快閃記憶體 314進行資料讀取。於一實施例中，控制器312包括錯誤 修正模組322、資料修改模組324、以及緩衝器326。首先， 控制器312命令快閃記憶體314以一原始電壓讀取一位址 (步驟402)。當快閃記憶體314依據控制器312的命令進行 資料讀取而讀出一原始資料及對應的錯誤修正碼後，錯誤 修正模組322會以一錯誤修正程序（error correcti〇n process) 依據該錯誤修正碼修正該原始資料的錯誤位元（步驟 404)。此時，若該原始資料的錯誤位元被成功地修正而產 生一輸出資料（步驟406)，則控制器312將錯誤修正模組 SMI-10-003/9031 -A42398-TW/Final 8 201135745 322產生的輸出資料儲存至緩衝器326,再由缓衝器326將 輸出資料輸送至主機304(步驟420)。 若該原始資料的錯誤位元無法被成功地修正（步驟 406)，則錯誤修正模組322無法產生一正確的輸出資料， 以供傳送至主機304。此時，控制器312要求快閃記憶體 314以該原始讀取電壓讀取對應於該原始資料之一預定資 訊，以得到一校正資訊（步驟408)。於一實施例中，該預定 資訊與該原始資料儲存於快閃記憶體314的同一區塊的同 φ 一頁，如第2圖所示。控制器312便可依據所讀出的校正 資訊與原本的預定資訊之差別以找出錯誤位元發生的型 態。舉例來說，假設原本的預定資訊為位元組0x55(位元串 οι前 ο_ι力-1-制共卞懷肯體m—H壓 的校正資訊為位元組0x54(位元串01010100)。由此，控制 器312可得知預定資訊0x55中的部份位元1經由原始讀取 電壓被判斷為校正資訊0x54中的位元0，因此控制器312 可自校正資訊中決定一錯誤位元值0。亦即，校正資訊中 • 部份的位元0為錯誤位元。 接著，控制器312要求快閃記憶體314以一修改讀取 電壓讀取該位址（步驟410)，其中該修改讀取電壓與該原始 讀取電壓不相同。於一實施例中，控制器312依據預定資 訊與校正資訊調整原始讀取電壓以得到該修改讀取電壓。 於一實施例中，快閃記憶體314包括一讀取電壓設定電路 330，可依據控制器312的指示更改讀取電壓的設定值。接 著，快閃記憶體314依據該修改讀取電壓進行資料讀取， 以得到一重讀資料以及一重讀錯誤修正碼（步驟410)。當 SMI-10-003/9031 -A42398-TW/Final 9 201135745 然由於4取電，不相同，重讀資料與原始資料的部份位 元會不同而重讀錯②修正喝與原始錯誤修正碼的部份位 元亦會不同。此時，資料修改模組似便可根據由校正資 訊與預定資默差異所^的錯μ元值，修改重讀資料 與原=枓的部份差異位^，以得到具有較高正確率的一 修改貝步驟412)。同樣的’資料修改模組324亦可根據 由板正貝雜預定貝訊之差異所決定的錯誤位元值，修改 重讀錯祕正碼與原始錯誤修㈣的部份差異位元 ，以得 到具有|^正>5|率的—修改錯誤修正碼（步驟叫）。步驟 412及414的詳細流㈣以第5圖進行說明。 第5圖為依據本發明修改原始資料及原始錯誤修正碼 -乏方—法]『的流身-料-㈣^:纟打2作貧方贫獨言 生修改資料以及修改錯誤修正喝。首先，資料修改模組324 辨別原始資料與重讀資料不相同的多個第一差異位元（步 驟502)。假設原始資料為位元串〇〇〇〇〇Ulll，而重讀資料 為0000111110。因此，原始資料與重讀資料有兩個差異位 元’分別為原始資料中次序5的位元〇及次序1〇的位元ρ 接著’資料修改模組324辨別原始錯誤修正碼與重讀錯誤 修正碼不相同的多個第二差異位元（步驟5〇4)〇假設原始錯 誤修正碼為位元串01010，而重讀錯誤修正碼為因 此，原始錯誤修正碼與重讀錯誤修正碼之差異位元為原始 錯誤修正碼中次序5的位元1。 接著’資料修改模組324比較校正資訊與預定資訊之 差異以自位元0與位元1中選取一錯誤位元值（步驟506)。 一如之前所舉之例，假設預定資訊為位元組〇χ55(位元串 SMI-10-003/9031 -A42398-TW/Final 10 201135745 而校正資訊為位元組Gx54(位元串_10】00)， 因此貝料修改描細} 〇。接著，資⑽\ :#訊巾決定—錯誤位元值 -改模組324自原始資料之多個第-差異位 該錯誤位元值之多個第三差異位元 丄料3料之該等第三差異位元之值以得到該 ‘改身枓㈣510)。例如，201135745 VI. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The present invention relates to a data storage device, and more particularly to a flash memory. [Prior Art] Flash memory is a non-volatile memory, that is, when the flash memory does not receive power, the data stored in the flash memory does not disappear due to loss of power, so Flash memory is widely used in portable devices with limited power for storing data. The flash memory contains a plurality of memory cells, each of which can store 2N potentials. For example, each memory unit can store two kinds of potential flash memory, which is called a single level cell (SLC) flash memory, and each memory unit can store four kinds of potential flash memory. It is a multi-level cell (MLC) flash memory, and each memory cell can store 8 kinds of potential flash memory called triple level cell (TLC) flash memory. When the host wants to read data from the flash memory, the flash memory determines the desired reading according to a set of read voltages to determine which range of the read voltage the voltage of the memory cell to be read falls. What is the value of the data stored in the memory unit? For example, when the flash memory is a single-layer cell flash memory, the corresponding read voltage has only one demarcation value. When the voltage of the memory cell is higher than the demarcation value, the data storage value of the memory cell is determined. It is bit 0, and when the voltage of the memory cell is lower than the threshold value, the data storage value of the memory unit is determined as bit 1. In addition, when the flash memory is a multi-level cell flash memory, the corresponding read voltage has three demarcation values, with SMI-10-003/9031 - A42398-TW/Final 4 201135745 depending on the voltage of the memory cell and three The relative size of the cutoff value identifies the data storage value of the memory unit as bit 11, 11, 00, or 10. Similarly, when the flash memory is a three-layer cell flash memory, the corresponding read voltage has seven demarcation values to distinguish the data storage value of the memory cell according to the relative magnitude of the voltage of the memory cell and the seven demarcation values. It is a bit 11 (1, 01, 100, 000, 010, or 110. Fig. 1 is a schematic diagram of a set of read voltages of a three-layer unit flash memory. The read voltage can be due to a three-layer unit. The number of bits stored in the memory unit of the flash memory is different. • Therefore, the read voltage determines the read data value of the memory unit of the flash memory. That is, the voltage stored in a memory unit is different. The determination of the read voltage can produce different data readout values. Therefore, when the flash memory receives the command to read the data from the host and reads the stored data, but the read data is wrong, try different The read voltage re-reads the stored data. However, how to select the correct read data value from a plurality of different read data values generated from a plurality of different read voltages is a problem. The present invention provides a method for reading data of a flash memory, so that when the data is read out and an error occurs, the read voltage can be modified to generate a correct read data value. An object of the present invention is to provide a method for reading data of a flash memory to solve the problems of the prior art. In one embodiment, the flash memory includes a plurality of pages, each of which All the pages are written into the predetermined information. First, an address is read from the flash memory with an original read voltage to obtain an original data and an original error correction code. Then, with a first error Correction process (errorcorrectionprocess) SMI-10-003/9031-A42398-TW/Final 5 201135745 Correct the error bit of the original data according to the original error correction code. When the first error repair program cannot correct the original data In the case of an error bit, the original information is taken from the flash memory to read the information corresponding to the original data, so as to obtain 5 calibration information. Modifying the original capital by the difference between the correction information and the predetermined information to generate the modified data. Then, according to the difference between the correction information and the predetermined asset A, modifying the original error correction code to generate a modified error correction horse and then The second error correction program corrects the error bit of the data according to the modified error correction code. Finally, when the second error correction program is also correcting the error bit of the original data to obtain a second output data, The second output data is transmitted to the host as read data. The present invention further provides a data storage device. In an embodiment, the bedding storage device is connected to the host, including the _ flash memory and a control The flash memory includes a plurality of pages for storing data, wherein each of the pages is written with a message (hard) (four) command to record the flash memory - the original read voltage is read - the address is obtained - The original data and an original error correction code, with - the first error correction (four) (e_e_cti〇n pro - correct the original error material error bit 70 according to the original error correction code, and when - when the wrong woman is unable to correct the error bit of the original data, the flash memory is instructed to read the predetermined information corresponding to the original (4) with the original read voltage to obtain - correction information (ea version information) 'Modify the original data according to the difference between the correction information and the predetermined information to generate-modify the data' according to the difference between the correction information and the predetermined information. (4) Initial error correction, U--Modification error correction code, - Second error The correction program corrects the error bit of the modified data according to the modified error correction code, and when the second error correction program successfully corrects the error bit of the original data. When a second output data is obtained, the second output data is transmitted to the host as read data. The above and other objects, features and advantages of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The flash memory of the present invention is used to store one of the data blocks of the block (bl〇Ck). The data block 200 includes a plurality of pages 201 to 20K for storing data, and each page can store a plurality of data sectors. In one embodiment, each data segment has a size of 512 bytes, and a page of data block 200 stores 4 data segments. In general, in order to reduce errors in data storage, the flash memory controller will pre-code the error-based code (Em) r e before the data segment is stored in the flash memory. Job tiQn eQde, EC〇, and when saving the data section - and store the corresponding error correction code to the flash memory #body. For example, page 201 stores four data sections 201a, multiples, 201c, and 201d, each data section 2〇la, 2〇lb, 2〇ic, and leg containing a corresponding error correction code. In addition, in order to find out the read data of the positive and negative data from the read data read from the flash memory according to the plurality of sets of δ-beat voltages, the controller will write a predetermined information when storing the data. Flash memory. In one embodiment, each page of the data block stores a predetermined message. For example, page 201 stores - predetermined information 201e. In the embodiment, the predetermined information is only - a byte. For example, the value of the predetermined information may be 0x55 (bits OlOioioi). SMI-10-003/9031-A42398-TW/Final 7 201135745 Figure 3 is a block diagram of a data storage device 3〇2 in accordance with the present invention. The data storage device 302 is coupled to a host 304. In one embodiment, the data storage device 302 includes a controller 312 and a flash memory 314. Controller 312 accesses the data of flash memory 314 in accordance with the instructions of host 304. When the host 304 sends a write command to the data storage device 302, the controller 312 writes the data to the flash memory 314 in accordance with the write command. In particular, the controller 312 will write a predetermined message to the flash memory 314 as it is written, as shown in FIG. When the host 304 sends a read command to the data storage device 302, the controller 312 reads the data from the flash memory 314 in accordance with the read command. However, even if a read error occurs in the read data, the controller 312 can instruct the flash memory 314 to generate a plurality of read data values at different read voltages, and according to the reservation stored in the flash memory 314 in advance. Information determines the correct reading of data values to avoid read errors. Figure 4 is a flow diagram of a method 400 of reading data from a flash memory in accordance with the present invention. Controller 312 performs data reading on flash memory 314 in accordance with method 400. In one embodiment, the controller 312 includes an error correction module 322, a data modification module 324, and a buffer 326. First, controller 312 instructs flash memory 314 to read an address at an original voltage (step 402). After the flash memory 314 reads the original data and the corresponding error correction code according to the command of the controller 312, the error correction module 322 will use an error correction procedure (error correcti〇n process). The error correction code modifies the error bit of the original material (step 404). At this time, if the error bit of the original data is successfully corrected to generate an output data (step 406), the controller 312 will error correction module SMI-10-003/9031 - A42398-TW/Final 8 201135745 322 The resulting output data is stored in buffer 326, which in turn transmits the output data to host 304 (step 420). If the error bit of the original material cannot be successfully corrected (step 406), the error correction module 322 cannot generate a correct output data for transmission to the host 304. At this time, the controller 312 requests the flash memory 314 to read the predetermined information corresponding to the original data with the original read voltage to obtain a correction information (step 408). In one embodiment, the predetermined information is stored in the same φ page of the same block as the flash memory 314, as shown in FIG. The controller 312 can find the type of error bit occurrence based on the difference between the read correction information and the original predetermined information. For example, suppose that the original predetermined information is the byte 0x55 (the bit string οι ο ι -1- -1- 制 制 的 m m m m m m m m 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Thus, the controller 312 can know that part of the bit 1 in the predetermined information 0x55 is determined to be the bit 0 in the correction information 0x54 via the original read voltage, so the controller 312 can determine an error bit from the correction information. The value is 0. That is, the bit 0 of the correction information is the error bit. Next, the controller 312 requests the flash memory 314 to read the address with a modified read voltage (step 410), where The modified read voltage is different from the original read voltage. In an embodiment, the controller 312 adjusts the original read voltage according to the predetermined information and the correction information to obtain the modified read voltage. In an embodiment, the flash memory The body 314 includes a read voltage setting circuit 330, which can change the set value of the read voltage according to the instruction of the controller 312. Then, the flash memory 314 reads the data according to the modified read voltage to obtain a reread data and One reread error correction code Step 410). When SMI-10-003/9031 -A42398-TW/Final 9 201135745 However, due to 4 power-off, not the same, the re-reading data and the original data will be different in the bit and the re-reading error 2 correction drinking and original error Some bits of the correction code will also be different. At this point, the data modification module may modify the partial difference between the reread data and the original = 根据 according to the wrong μ value from the correction information and the predetermined error. ^, to obtain a modified shell step 412) with a higher correct rate. The same 'data modification module 324 can also modify the re-reading error code and the original error correction (4) part of the difference bit according to the error bit value determined by the difference between the board and the predetermined subscription, to obtain |^正>5| Rate-Modify the error correction code (step called). The detailed flow (4) of steps 412 and 414 is illustrated in Fig. 5. Figure 5 is a modification of the original data and the original error correction code in accordance with the present invention - the lack of the method - the "flow body - material - (four) ^: beaten 2 for the poor side of the poor students to modify the information and modify the error correction drink. First, the data modification module 324 discriminates a plurality of first difference bits that are different from the original data and the reread data (step 502). Assume that the original data is a bit string 〇〇〇〇〇Ulll and the reread data is 0000111110. Therefore, the original data and the reread data have two difference bits 'the bit 5 of the order 5 in the original data and the bit ρ of the order 1 接着 then the 'data modification module 324 discriminates the original error correction code and the reread error correction code. A plurality of second difference bits (step 5〇4) that are different from each other assume that the original error correction code is the bit string 01010, and the error correction code is reread. Therefore, the difference bit between the original error correction code and the reread error correction code is Bit 1 of order 5 in the original error correction code. Next, the data modification module 324 compares the difference between the correction information and the predetermined information to select an error bit value from the bit 0 and the bit 1 (step 506). As in the previous example, assume that the predetermined information is byte 〇χ55 (bit string SMI-10-003/9031 -A42398-TW/Final 10 201135745 and the correction information is byte Gx54 (bit string _10) 】 00), so the batting material is modified} 〇. Next, the capital (10)\:# towel decision--error bit value-modification module 324 from the original data, the first-differential bit, the error bit value The third difference bit is the value of the third difference bit of the material 3 to obtain the 'reformed body (four) 510). E.g,
0000仙11的兩個差餘元Μ有次序 ^立元值〇相等，因此資娜•組324反料^ 0_111U1。 而得到修改資料之位元串 接著 -貝科修改模組324自原始錯誤修正碼之多個 、：it 70中辨別出具有該錯誤位元值之多 , =步 =12)，敍轉縣錯婦正狀該㈣四差異位〕 传到該修改錯誤修正碼(步驟 錯誤修正碼的位元串0 *於原; _ 甲υΐυ】ϋ中僅有次序5的差異位元0 j 值G相等’因此資料修改模組324反轉原始錯言 踩‘久序5的位疋0為位元1 ’而得到修改錯誤修： 碼之位元串〇1011。 =後S資料修改模組324產生修改資料及修改錯誤 :、、，1後=貝料修改模組324將修改資料及修改錯誤修正 组^至1誤修正"322。接著’錯轉正模組322以錯 =、:正知序依據該修改錯誤修正碼修正該修改資料之錯誤 二元（步驟416)。此時，錯誤修正模組322可成功地修正 雜改資料之錯誤位元而產生—輸出資料(步驟418)，則錯 誤修正模組322將輸出資料傳送至緩衝器似。接著，缓 SMI-10-003/903 l-A42398-TW/Final 201135745 衝器326將正確的輸出資料傳送至主機304，以完成讀取 動作之執行。反之，若錯誤修正模組322無法成功地修正 該修改資料之錯誤位元，則控制器312可再度藉讀取電壓 設定電路330重新設定一新修改讀取電壓，然後重新執行 步驟410〜418。萬一錯誤修正模組322仍然無法成功地修 正該修改資料之錯誤位元，則控制器312回報主機304讀 取資料失敗（步驟422)。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技術者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖為三層單元快閃記憶體的一組讀取電壓的示意 圖， 第2圖為依據本發明之快閃記憶體用以儲存資料之一 區塊的不意圖， 第3圖為依據本發明之資料儲存裝置的區塊圖； 第4圖為依據本發明之快閃記憶體之資料讀取的方法 的流程圖；以及 第5圖為依據本發明修改原始資料及原始錯誤修正碼 之方法的流程圖。 【主要元件符號說明】 (第2圖） 200~資料區塊， 201a〜201d、202a〜202d、20ka〜20kd〜資料區段； SMI-10-003/9031 -A42398-TW/Final 12 201135745 201e、202e、20ke〜預定資訊； (第3圖） 302〜資料儲存裝置； 304〜主機； 312〜控制器； 314〜快閃記憶體； 322〜錯誤修正模組； 324〜資料修改模組； • 326〜緩衝器；以及 330〜讀取電壓設定電路。 SMI-10-003/9031 -A42398-TW/Final 13The two difference elements of 0000 sen 11 have an order. The eigenvalues are equal, so the jinna group 324 counters ^ 0_111U1. And the bit string of the modified data is followed by the -Becco modification module 324 from the plurality of original error correction codes, :it 70, which has the value of the error bit value, =step=12), The correctness of the (four) four difference bits is passed to the modified error correction code (the bit error correction code bit string 0 * is in the original; _ A υΐυ υΐυ ϋ 仅有 only the order 5 difference bits 0 j value G equal ' Therefore, the data modification module 324 reverses the original erroneous stepping on the 'position 0 of the long-order 5 is the bit 1' and obtains the modified error repair: the bit string of the code 〇 1011. The post-S data modification module 324 generates the modified data. And modify the error:,,, after 1 = berm material modification module 324 will modify the data and modify the error correction group ^ to 1 miscorrected " 322. Then 'wrong positive module 322 with wrong =,: positive order according to the Modifying the error correction code to correct the error binary of the modified data (step 416). At this time, the error correction module 322 can successfully correct the error bit of the miscellaneous data to generate the output data (step 418), and the error correction mode Group 322 transfers the output data to the buffer. Then, SMI-10-003/903 l-A42398-TW/Fina l 201135745 The buffer 326 transmits the correct output data to the host 304 to complete the execution of the read operation. Conversely, if the error correction module 322 cannot successfully correct the error bit of the modified data, the controller 312 can re-borrow The read voltage setting circuit 330 resets a new modified read voltage, and then performs steps 410 to 418 again. In case the error correction module 322 still cannot successfully correct the error bit of the modified data, the controller 312 returns the host 304. Failed to read the data (step 422). Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can, without departing from the spirit and scope of the present invention, The scope of protection of the present invention is defined by the scope of the appended patent application. [Simplified Schematic] Figure 1 is a set of read voltages of a three-layer unit flash memory. FIG. 2 is a schematic diagram of a flash memory for storing a block of data according to the present invention, and FIG. 3 is a data storage device according to the present invention. Figure 4 is a flow chart showing a method of reading data of a flash memory according to the present invention; and Figure 5 is a flow chart showing a method of modifying the original data and the original error correction code according to the present invention. DESCRIPTION OF SYMBOLS (Fig. 2) 200~ data block, 201a~201d, 202a~202d, 20ka~20kd~ data section; SMI-10-003/9031 -A42398-TW/Final 12 201135745 201e, 202e, 20ke ~ Booking information; (Fig. 3) 302~ data storage device; 304~ host; 312~ controller; 314~ flash memory; 322~ error correction module; 324~ data modification module; ; and 330~ read voltage setting circuit. SMI-10-003/9031 -A42398-TW/Final 13