EP2186093B1 - Shared memory - Google Patents

Description

The present invention relates to a shared memory in particular by several processors integrated in the same circuit based on semiconductors. Shared memory finds its particular application in the field of microelectronics.

In a multiprocessor system, the processors can work in parallel on the same application. It is therefore necessary that the processors can exchange a large number of data between them. In order to reduce the data transfer time between the processors, it is advantageous that all the processors have access to the same memory. A first processor can thus work on a first task and then update the first data in the memory according to the results it has obtained. It can then signal to a second processor that the first data in the memory is ready for further processing. The second processor can then use the first data of the memory in a second task. Meanwhile, the first processor can process other data.

So that the memory sharing by multiple processors does not slow processor processing, a known method is to divide the memory into several independent memory banks. In this way, as long as the processors are each working with a different memory bank, memory sharing does not slow down their processing.

It is appropriate for such shared memory to use a design that allows both a reduction of production costs and an optimization of data transfer speeds. Different conceptions of shared memory have been proposed, for example in US 2005/249020 A1 , US 6,151,256 A or EP 0 420 339 A .

An existing solution uses multiplexers connected at their output to an input of the memory banks. The inputs of the multiplexers are connected to the outputs of the different processors to have access to the memory. An input data bus of each processor is connected to an output of a multiplexer receiving as input the output data buses of all memory banks.

A problem encountered with this implementation is the large number of necessary connections. In particular, the connecting connections the output data buses of the memory banks with the multiplexers located on the input data buses of the processors are in large numbers. The surface of these connections may be greater than the area of the memories and the total area of the shared memory can thus be doubled. Such an increase in the area of a shared memory generates significant production costs. In addition, the large length of these connections induces in particular a large parasitic capacitance. This stray capacitance can slow down data transfer and cause significant energy consumption.

Another existing solution is to connect several processors to the same multi-port memory. A multi-port memory is a memory having a number k of inputs / outputs. The multi-port memory comprises for example several memory cells, each memory cell having a number k of switches. The k switches of each memory cell make it possible to connect each memory cell to a memory output data bus, among k memory output data buses. Such memory allows k processors to have access to said memory. However this other solution also requires a large number of connections. This implies that a component integrating such a memory is of relatively large size.

The patent US5875470 describes in particular a memory providing multiple processors simultaneous read-write access to the data it contains.

An object of the invention is in particular to overcome the aforementioned drawbacks. For this purpose, the subject of the invention is a shared memory made on a first semiconductor-based integrated circuit as described in the claims.

The main advantages of the invention include allowing the production of shared memory, having high data access speeds as well as reduced power consumption at low cost.

• la figure 1a : un exemple d'architecture de mémoire partagée par plusieurs processeurs selon l'art antérieur ;
• la figure 1b : un exemple d'architecture d'une mémoire multi-ports selon l'art antérieur ;
• la figure 2 : un premier exemple d'architecture de mémoire partagée par plusieurs processeurs selon l'invention ;
• la figure 3 : un exemple détaillé d'une interconnexion selon l'invention entre un banc mémoire et un processeur ;
• la figure 4 : un chronogramme de fonctionnement d'une lecture de donnée sur un banc de la mémoire partagée selon l'invention ;
• la figure 5 : un deuxième exemple d'architecture d'une mémoire partagée selon l'invention ;
• la figure 6 : un troisième exemple schématique d'architecture d'une mémoire partagée selon l'invention.

Other features and advantages of the invention will become apparent with the aid of the description which follows, given by way of illustration and not limitation, and with reference to the appended drawings which represent:

• the figure 1a : an example of memory architecture shared by several processors according to the prior art;
• the figure 1b : an example architecture of a multi-port memory according to the prior art;
• the figure 2 : a first example of memory architecture shared by several processors according to the invention;
• the figure 3 : a detailed example of an interconnection according to the invention between a memory bank and a processor;
• the figure 4 a chronogram of operation of a reading of data on a bank of the shared memory according to the invention;
• the figure 5 : a second example of architecture of a shared memory according to the invention;
• the figure 6 : A third schematic example of architecture of a shared memory according to the invention.

The figure 1a represents, schematically, an architecture of a first shared memory 1 by a set of several elementary processors 2, according to the prior art.

For example, the first shared memory 1 may include a number b of memory banks. On the figure 1a three memory banks are represented for the example: a first memory bank 15, a second memory bank 16 and a third memory bank 17. Each memory bank 15, 16, 17 comprises in particular an input E and an output S. Each input E of each memory bank 15, 16, 17 is connected to a multiplexer 6, 7, 8, called the memory input multiplexer 6, 7, 8. Each output S of each memory bank 15, 16, 17 is connected to a first memory data bus 12, 13, 14 specific to each memory bank 15, 16, 17.

The shared memory 1 can be shared by a number n of elementary processors 2. On the figure 1a , three elementary processors are represented: a first elementary processor PE1, a second elementary processor PE2, and a third elementary processor PE3. Each elementary processor PE1, PE2, PE3 comprises a data bus and processor addresses 3, 4, 5, connected to its output SP. A data and address bus makes it possible to convey signals comprising data, addresses and also control signals. The control signals make it possible to control the memory. The control signals may in particular control: an activation of the memory, a reading and writing of data in memory and possibly a sequencing of previously named operations.
Each elementary processor PE1, PE2, PE3 comprises an input EP connected to a processor input multiplexer 9, 10, 11.

Each data and address bus of each processor 3, 4, 5 is connected to the memory input multiplexers 6, 7, 8. The data bus and processor address 3, 4, 5 can be used to write to memory one or more data calculated by an elementary processor PE1, PE2, PE3 for example. The data and processor address bus 3, 4, 5 also enables the elementary processor PE1, PE2, PE3 to perform data queries stored in the shared memory 1. The memory input multiplexers 6, 7, 8 for example, to select which data coming from the different elementary processors PE1, PE2, PE3 must arrive in each of the memory banks 15, 16, 17.

Each output S of each memory bank 15, 16, 17 is connected to each processor input multiplexer 9, 10, 11 via the memory data buses 12, 13, 14. Each input processor multiplexer 9, 10 11 is therefore connected to all the first memory data buses 12, 13, 14 of each memory bank 15, 16, 17.

This type of shared memory architecture therefore requires a large number of connections occupying a large area of the shared memory. In addition, the length of the connections implies a large parasitic capacitance.

The figure 1b represents in a simplified way a multi-port memory 100, according to the prior art, performed on a chip based on semiconductors. The multi-port memory 100 comprises in particular several input / output ports on which several connections can be connected. processors, not shown on the figure 1 b. The multi-port memory 100 has several memory cells 101, 102, 103. On the figure 1b three memory cells 101, 102, 103 are shown. Each memory cell 101, 102, 103 is connected to an integer number k of switches. On the figure 1b each memory cell 101, 102, 103 is connected to two switches 1010, 1011, 1020, 1021, 1030, 1031. For example an input / output of a first memory cell 101 is connected to a first switch 1010, and a second switch 1011.

The first switch 1010 is connected on the one hand to a first word line 107, and on the other hand to a first wire 105 of a first data bus 106. The first data bus 106 is for example connected to a pin an input / output port of the multi-port memory 100.

Similarly, the second switch 1011 is connected on the one hand to a second word line 104, and on the other hand to a first wire 108 of a second data bus 109.

Like the first memory cell 101, a second memory cell 102 is connected to two switches: a third switch 1020 and a fourth switch 1021. The third switch 1020 is connected on the one hand to the first word line 107 and on the other hand a second wire 110 of the first data bus 106. The fourth switch 1021 is connected firstly to the second word line 104, and secondly to a second wire 111 of the second data bus 109.

A third memory cell 103 is likewise connected to a fifth switch 1030 and to a sixth switch 1031. The fifth switch 1030 is connected on the one hand to a third word line 112 and on the other hand to the first wire 105 of the first data bus 106. The sixth switch 1031 is connected on the one hand to a fourth word line 113 and on the other hand to the first wire 108 of the second data bus 109.

In general, each memory cell 101, 102, 103 is connected to each data bus 109, 106.

Each word line 104, 107, 112, 113 is connected to a word line decoder 114, 115. The first word line 107 is connected to a first word line decoder 114, the second line of the word line decoder. words 104 is, in turn, connected to a second word line decoder 115. Similarly, the third word line 112 is connected to the second word line decoder 115 and the fourth word line 113 is connected to the second word line decoder 115. first word line decoder 114.

Each word line decoder 114, 115, therefore takes several word lines 104, 107, 112, 113 into input. An output of each word line decoder 114, 115, is connected to an address bus 116, 117 For example, the first word line decoder 114 is connected to a first address bus 116 and the second word line decoder 117 is connected to a second address bus 117. The two address buses 116, 117 are connected to an input / output port of the multi-port memory 100.

• commutateurs 1010, 1011, 1020, 1021, 1030, 1031 reliés à chaque cellule mémoire ;
• lignes de mots ;
• bus de données.

Such a multi-port memory 100 represented on the figure 1b , is a dual port memory, so it offers read and write access to two processors. In general, a multi-port memory allows a number k of processors to connect. k is in particular the number of:

• switches 1010, 1011, 1020, 1021, 1030, 1031 connected to each memory cell;
• lines of words;
• data bus.

A multi-port memory, if it provides memory access to several processors in parallel, has a large area, in particular due to the large number of connections to be made.

The figure 2 schematically represents an example of a structure of a shared memory 20 according to the invention.

• une mémoire 210, 220, 230 ;
• un multiplexeur 211, 221, 231 ;
• un bus de données mémoire 213, 223, 233 ;
• un bloc de commutateurs 214, 224, 234.

The structure of the shared memory 20 according to the invention comprises, for example, a number p of memory banks 21, 22, 23, p being an integer, for example greater than two. On the figure 2 and by way of example, three of the memory banks 21, 22, 23 are shown. Each of the memory banks 21, 22, 23 comprises:

• a memory 210, 220, 230;
• a multiplexer 211, 221, 231;
• a memory data bus 213, 223, 233;
• a switch block 214, 224, 234.

The memories 210, 220, 230 may be single port memories, for example SRAM type, acronym for the English expression Static Random Access Memory meaning static random access memory. SRAM type memories notably allow quick access to the data stored by said memories.

The shared memory 20 is shared by a number m of processors 25, m being an integer, for example greater than one. On the figure 2 , eight of the m processors 25 are represented for example. The m processors 25 may be elementary processors.

The shared memory 20 is described hereinafter more particularly for a first memory bank 21 and a first processor 26, this same description can be applied to all of the memory banks 21, 22, 23 and to all the memory modules. processors 25.

The structure of the shared memory 20 further includes a set of bidirectional parallel data buses 24, for example. In an embodiment of a shared memory 20 according to the invention, the parallel data buses 24 can be located physically, above the memory banks 21, 22, 23. The memory banks 21, 22, 23 can for example to be in the same plane. Placing the parallel data buses 24 physically above the memory banks 21, 22, 23 saves the silicon area used to achieve the shared memory 20 according to the invention. The silicon economy achieved advantageously makes it possible to improve the production cost of a shared memory 20 according to the invention. The parallel data buses 24 may be, for example, thirty-two-bit or sixty-four-bit buses or even one hundred and twenty-eight bits. The parallel data buses 24 may be differential buses.
Each of the parallel data buses 24 can make it possible to receive data coming from one of the memory banks 21, 22, 23, or to transmit data to these memory banks, via the buses 213, 223, 233. These transfers can be done simultaneously from or to the m processors 25, because of as many simultaneous transfers as there is data bus 24 (assuming a number of memory banks greater than or equal to the number of data buses 24).
The parallel data buses 24 may represent EP / SP data inputs / outputs of the shared memory 20 or be physically connected to EP / SP data inputs / outputs of the shared memory 20.

The EP / SP data I / O of the shared memory 20 is part of the input / output interfaces of the shared memory 20 with electronic components external to the shared memory 20. On the figure 2 , each input / output interface of the shared memory 20 is connected with one of the m processors 25. Each bit of an input / output of data EP / SP of the shared memory 20 can be made on the same wire or on two separated wires, thus realizing a differential connection.

Each of the parallel data buses 24 corresponds to one of the m processors 25. For example, on the figure 2 each of the processors 25 is connected to one of the parallel buses 24. Thus, the data entering and leaving each of the m processors 25 flows on one of the corresponding parallel buses 24 of corresponding data. For example, the first processor 26 is connected to a first parallel data bus 27 via a first input / output EP / SP of the shared memory 20. The first parallel data bus 27 is itself connected to a data bus 27. first memory data bus 213 of the first memory bank 21 through a first switch 215. The first switch 215 is part of a first set 214 of switches of the first memory bank 21. The first memory data bus 213 is in particular connected to an I / O data input / output of a first memory 210 forming part of the first memory bank 21. The memory data buses 213, 223, 233 may be differential buses. The first switch 215 makes it possible in particular to select data coming in particular from the first memory bank 21 to be circulated on the first parallel data bus 27 in the reading phase of the shared memory 20 by the first processor 26.

Each of the parallel data buses 24 is connected to an I / O data input / output of each of the memories 210, 220, 230 of the memory banks 21, 22, 23 through one of each set 214 , 224, 234 of switches of each of the banks of memory 21, 22, 23. Thus each of the banks of memory 21, 22, 23 has of a number m of switches enabling it to distribute data from the memories 210, 220, 230 over all the parallel data buses 24. This amounts to distributing a function of multiplexers connected to the parallel data buses 24, on each of the memory banks 21, 22, 23.

• d'activation de la mémoire 210, 220, 230 ;
• d'opérations de lecture et d'écriture de la mémoire 210, 220, 230 ;
• et, éventuellement de mise en séquence, ou séquencement, des différentes opérations effectuées par la mémoire 210, 220, 230.

The shared memory 20 also comprises a set of parallel address and control m buses 200 gathering the address and control buses of each of the m processors 25. One of the address and control buses 200, such as a first bus address and control 204, allows in particular to transmit address signals but also control signals. The control signals make it possible in particular to control the memories 210, 220, 230. A command of a memory 210, 220, 230 can be a command:

• activating the memory 210, 220, 230;
• reading and writing operations of the memory 210, 220, 230;
• and, optionally sequencing or sequencing, the various operations performed by the memory 210, 220, 230.

The address and control buses 200 are connected to m address and control entries SP 'of the shared memory 20. For example the first address and control bus 204, forming part of the address and address buses. 200, is connected to an address and control input SP 'of the shared memory 20. The address and control input SP' of the shared memory 20 is connected to an address and control bus of the first processor 26. The address and control inputs SP 'are part of the input / output interfaces EP / SP, SP' of the shared memory 20.

Each address and control bus 200 is connected to each of the memory banks 21, 22, 23. In particular, each address and control bus 200 is connected to an input of each multiplexer 211, 221, 231 of each Memory bus 21, 22, 23. The address and control bus 204 is connected to an input of a first multiplexer 211 forming part of the first memory bank 21. The address and control bus 204 is also connected. an input of a second multiplexer 221 forming part of a second memory bank 22, and an input of a third multiplexer 231, forming part of a third memory bank 23.

Each multiplexer 211, 221, 231 is connected to a control and control input E of a memory 210, 220, 230. For example, a command and control input E of the first memory 210 is connected to the output of the first multiplexer 211.

The parallel address and control buses 200 make it possible to convey to the p memory banks 21, 22, 23 requests from each of the m processors 25.

The connections between the memory banks 21, 22, 23 and the microprocessors 25 are therefore via the parallel data buses 24 and the parallel address and control buses 200. Each processor 25 is therefore connected to one parallel data buses 24 and one of the parallel address and control buses 20, which allows access to short data segments. The connections between the memory banks 21, 22, 23 and the microprocessors 25 thus generate little or no additional surface with respect to the surface occupied by the memory banks 21, 22, 23, these connections being able for example to be performed physically above the memory banks 21, 22, 23.

The shared memory 20 as well as the m processors 25 may be integrated on a first semiconductor-based chip for example. The parallel data buses 24, the address and control buses 200 can be made in layers of metals located physically above the layers forming the p memory banks 21, 22, 23. The memory banks 21, 22, 23 are indeed made using, inter alia, several layers of different metals. In other words, the parallel data buses 24, the address and control buses 200 can be made in layers of metals superimposed on the layers making up the p memory banks 21, 22, 23. The realization of the memories 210 , 220, 230 is also known to those skilled in the art.

In addition, in order to reduce the impact of the length of the connections on the speed of data transfer and the power consumption of the chip comprising these memories, the connections can be made differentially. This amounts to doubling each connection and joining each pair of connection by a differential amplifier thus allowing to use a small voltage excursion of the signal carried by the connections. Such an embodiment is described more precisely later. A similar device is commonly used on bit lines of memories for example.

The figure 3 represents a detailed example of an embodiment of an interconnection between a fourth memory bank 30, part of the shared memory 20 according to the invention, and a second processor 31. The figure also shows an interconnection between the fourth memory bank 30 and a third processor 32. The second processor 31 and the third processor 32 are, for example, part of the m processors 25 shown in FIG. figure 2 .

• soit un module de contrôle 311, 321 par processeur 31, 32, comme c'est le cas sur la figure 3,
• soit un module de contrôle par banc mémoire dans un autre mode de réalisation.

En effet, un module de contrôle 311 peut contrôler notamment un des p bancs mémoire 21, 22, 23 et l'un des m processeurs 25. L'utilisation d'un module de contrôle par processeur est notamment avantageuse lorsque l'on dispose d'un nombre plus important de bancs mémoires par rapport au nombre de processeurs.When the processor 31, 32 wants to read the contents of a word stored in a second memory 300 of the fourth memory bank 30, a control module 311, 321 associated with the processor 31, 32 sends a read request to the fourth memory bank 30. For example, it is possible to implement:

• a control module 311, 321 by processor 31, 32, as is the case on the figure 3 ,
• or a memory bank control module in another embodiment.

Indeed, a control module 311 may control in particular one of the memory banks 21, 22, 23 and one of the m processors 25. The use of a processor control module is particularly advantageous when there is a larger number of memory banks compared to the number of processors.

The reading request passes notably through the address and control buses 200 represented on the figure 2 . The address and control buses 200 comprise in particular a wire 313, 323, represented on the figure 3 , carrying a sequencing signal of the processor 31, 32 for controlling the bus driver 203 at the appropriate time. In the following, the son 313, 323 are called sequencing signals 313, 323.

• une première réalisation, dite arbitre à priorité tournante, peut considérer que chaque processeur 31, 32, est prioritaire à tour de rôle ;
• une deuxième réalisation, dite arbitre à priorité fixe, peut assigner une priorité fixe à chaque processeur 31, 32 par exemple.

L'arbitre à priorité fixe est relativement simple à mettre en oeuvre. L'arbitre à priorité tournante permet une même rapidité d'accès à la mémoire partagée 20 par tous les différents processeurs 31, 32. L'arbitre à priorité fixe permet également de mieux maîtriser le temps d'accès le plus défavorable. Un arbitre permettant une sélection du bus d'adresses et de contrôle 200 représenté sur la figure 2, à prendre en compte, peut utiliser un multiplexeur, comme le premier multiplexeur 211 représenté sur la figure 2. Les différentes réalisations possibles d'un arbitre sont bien connues de l'homme du métier.An arbitrator, not represented on the figure 3 , selects the request and controls a word line of the fourth memory bank 30 associated with an address contained in the read request. The arbiter is a logical function to hold read requests from example, different processors 31, 32. Several embodiments are possible for the arbitration function:

• a first embodiment, said revolving priority arbitrator, may consider that each processor 31, 32 has priority in turn;
• a second embodiment, said fixed priority arbitrator, can assign a fixed priority to each processor 31, 32 for example.

The fixed priority arbitrator is relatively simple to implement. The rotating priority arbitrator allows the same speed of access to the shared memory 20 by all the different processors 31, 32. The fixed priority arbitrator also makes it possible to better control the worst access time. An arbitrator permitting a selection of the address and control bus 200 represented on the figure 2 , to take into account, can use a multiplexer, as the first multiplexer 211 shown on the figure 2 . The various possible embodiments of an arbitrator are well known to those skilled in the art.

When sending a read request to the second memory 300, it then processes this request and sends the collected data to a data I / O input / output of the second memory 300. data carried out by the memory 300, the control module 311, 321 of the processor 31, 32 activates the sequencing signal 313, 323. The sequencing signal is intended to connect the output S of the second memory 300 to a second data bus memory 203. The sequencing signal 313, 323 is connected to a control component 33. The control component 33 controls the operation of one or more drivers 34. A driver 34 is a pilot electronic component. The drivers 34 are responsible for connecting the output S of the memory 300 to the parallel data buses 24. The parallel data buses 24 are represented by two pairs of wires 314, 324, each pair of wires 314, 324 being connected to the One of the processors 31, 32. By extension, hereinafter, the two pairs of wires 314, 324 are called data buses 314, 324. Each of the two pairs of wires 314, 324 represents, for example, thirty-two pairs of wires in each other. the case of a thirty-two bit data bus.

The control component 33 can be realized by means of an "OR" logic gate. The control component 33 may be an element of a multiplexer as the first multiplexer 211 shown on the figure 2 for the first memory bank 21.

The first driver or drivers 34 are, for example, three-state drivers. The function of the first driver 34 can be performed by a first differential reading amplifier of the second memory 300 for example. A first differential amplifier having one or two stages may be used, depending on the capacitive load of the parallel data buses 24, shown in FIG. figure 2 . A second memory data bus 203 is connected to the output of the driver 34. The control module 311, 321, or the arbitrator, can activate a selection control of a data bus 314, 324 of a processor 31, 32 having previously requested data. The selection control is performed by means of switches 315, 325, such as switches 214, 224, 234 shown in FIG. figure 2 . On the figure 3 a differential structure is used, each data bus 314, 324 being a differential data bus 314, 324. Thus each selection control uses in particular two switching elements, for example transistors, by switch 315, 325, or an element switching by differential bus line. The selection command makes it possible to connect the output of the driver 34 to a data bus 314, 324 itself connected to a processor 31, 32. At the same time as the selection command is executed, a pre-load module 312, 322 of the data bus 314, 324 cuts the preload. The pre-charge module 312, 322 has previously loaded the parasitic capacitance of the data bus lines 314, 324 with a voltage VDD or supply voltage. The voltage VDD is then the same in each of the lines of the data bus 314, 324. When the output signal of the memory is sufficiently strong, the driver or drivers 34 are activated. The drivers 34 then unload one of the complementary lines of the second memory data bus 203. The voltage difference is transmitted on the data bus 314, 324. Then, the voltage difference is detected by a second differential amplifier 316, 326 connected to each other. a part to an input or a data bus Din of the processor 31, 32 and secondly to the data bus 314, 324. The second differential amplifier 316, 326 can act as a driver for the data bus Din of the processor 31, 32. As soon as the output of the second differential amplifier 316, 326 has switched, the processor 31, 32 can record the data, the signal having recovered at the output of the second differential amplifier 316, 326 its full excursion. The data bus 314, 324 can then be preloaded by the pre-charge module 312, 322. The pre-charge module 312, 322 can be controlled by the control module 311, 321.

The writing of a data in memory by the processor 31, 32 can be done in the same way. The data conveyed by the data bus 314, 324 is in this case controlled by the processor 31, 32. For example, data to be stored in memory is encoded on a signal. The signal leaves the processor 31, 32 by an output Dout of the processor 31, 32 and is then transmitted in differential mode by a third differential amplifier 317, 327. The pre-charge of the data bus 314, 324 being cut off, one of the complementary lines data bus 314, 324 is charged by the output of the third differential amplifier 317, 327. The voltage difference of the data bus 314, 324 propagates to the second memory data bus 203. The voltage difference is then detected by the first differential amplifier 34 of the fourth memory bank 30. Once the signal, detected by the first differential amplifier 34, has switched on an output of the first differential amplifier 34, the data contained in the signal is recorded in the fourth memory bank 30.

Achieving shared memory using differential means enables increased efficiency. Indeed, it is not necessary to obtain a full signal excursion to propagate data from one bus to another, for example. This allows a saving of time as well as an energy saving during the transfer of data from the shared memory 20 to the processors 31, 32.

The figure 4 represents an example of different phases of the reading of a data by a processor 31, 32, for example, on the fourth memory bank 30 of the shared memory 20 according to the invention. The different phases are presented in the form of several chronograms 40, 43, 45, 48, 49, 403, 404 showing the variations of the different signals during each phase of the reading.

A first timing diagram 40 represents a signal transiting on the first address and control bus 200 represented on the figure 2 . A data read request 41 modifies the signal of the first address and control bus 200.

When the processor 31, 32 sends a read request 41 to the fourth memory bank 30, this triggers the reading of a value on the fourth memory bank 30 and thus the appearance of a first signal 44 on a bit line of the fourth memory bank 30. The appearance of the first signal 44 on the bit line of the fourth memory bank 30 is represented on the second timing diagram 45.

A little after sending the read request 41, the pre-load of the data bus 314, 324 is cut off. The cut-off 42 of the pre-charge, performed by the pre-charge module 312, 322, is represented on a third timing diagram 43.

When the first signal 44 on the bit lines of the fourth memory bank 30 has reached a first level 46 sufficient to allow the first differential amplifier 34 to function properly, then a first command 47 of the drivers 34 connected to the second memory data bus 203 is activated. . The first command 47 of the drivers 34 is represented on a fourth timing diagram 48.

Once the first command 47 of the drivers 34 executed by the drivers 34, the lines of the data bus 314, 324 of the processor 31, 32 to carry the information read in the fourth memory bank 30 begin to discharge. A fifth timing 49 represents the appearance of a second signal 400 on the lines of the data bus 314, 324.

When the first command 47 has been executed and the second signal 400 reaches a second level 401 sufficient for the operation of the second differential amplifier 316, 326, then a second command 402 is sent by the control module 311, 321 to the driver 316, 326 of the data bus Din processor 31, 32. The second control 402 is shown on a sixth timing 403.

The execution of the second command 402 by the driver 316, 326 causes a positioning 406 of the Din input of the processor 31, 32 to the value read in the fourth memory bank 30. The positioning 406 of the Din input of the processor 31 , 32 is represented on a seventh timing diagram 404 illustrating two possible state changes: a first change of state from zero to one and a second change of state from one to zero.

Once the value read has been recovered by the processor 31, 32, the control module 311, 321 sends a loading command to the pre-load module 312, 322 in order to load the lines of the bus. data 314, 324 as well as the lines of the second memory data bus 203.

The figure 5 represents another mode of use of the shared memory 20 according to the invention. The invention can, in fact, apply to a shared memory 20 realizing a first full-fledged circuit. The first circuit including the shared memory 20 can be realized on a second chip based semiconductors. In the figure 5 , a schematic representation of such an embodiment is presented. The m processors 25 as shown in the figure 2 are replaced on the figure 5 by a series of m input / output ports 50. The m input / output ports 50 may be connected to one or more external circuits to the first circuit comprising the shared memory 20. This connection can be made conventionally by the intermediate transfer ports connected to pins of the circuit having the shared memory 20. Generally, an input / output port is an element for connecting a chip to external electronic components. A port can therefore be a system implementing an exchange protocol and having input / output pins or for example a module capable of transforming signals entering or leaving the chip so that they can be transmitted for example by an inductive or capacitive coupling.

On the figure 5 , the m input / output ports 50 are connected to the shared memory 20 via the data inputs / outputs EP / SP of the shared memory 20 and via the address and control inputs SP ' of the shared memory 20. The shared memory 20 shown on the figure 5 is the same as the one shown on the figure 2 .

The input / output ports 50 may, in a first example of use of the shared memory 20 according to the invention, be connected to a processing chip. The processing chip, comprising for example m processors such as processors 25 represented on the figure 2 , can be connected with the input / output ports 50 by a three-dimensional interconnection. In this embodiment, the second chip having the shared memory 20 and the processing chip can be physically glued one above the other. The connections between the two chips can be made either via vias through the chip above, for example the second memory chip, or by inductive links, or by capacitive links. The vias are contacts between two levels of metals, the vias can especially cross the entire chip. As for the inductive links, they can be made from small coils with a coil for example. The capacitive connections can be made by metal surfaces facing each other. These connections can in particular be used to connect the data and address buses of the processing chip processors to the parallel data buses 24 and the parallel address and data buses 200 of the shared memory 20.

Such a memory chip is particularly relevant with the types of interconnection as described above. Such links notably make it possible to connect the shared memory 20 with the processing chip through multiple links. The interconnection links between the two chips make it possible to ensure a bandwidth much greater than that of the current memories. Indeed, the current memories are limited in particular by the number of pins of the housing integrating them and have only one input / output port.

The figure 6 represents, schematically, a second example of use of the shared memory 20 according to the invention. For example, several memory chips 60 having a shared memory 20 according to the invention can be placed physically one above the other. The data buses 24 and the address and control buses 200 shown in FIG. figure 2 are connected to data and address buses connecting the shared memories 20 of the different memory chips 60. Data and addresses connecting the shared memories 20 can traverse the memory chips 60 transversely by vias 61 or capacitive links or inductive links. Connections with processors 63 located for example on another chip 64 physically located above the memory chips 60 are effected, for example, via the vias 61.

Such an embodiment has the advantage of increasing the number of memories available to processors without significantly increasing the interconnection surfaces, especially between chips and processors.

The shared memory 20 according to the invention advantageously allows m processors 25 to be able to access all the memory banks 21, 22, 23 of the shared memory 20. All the m processors 25 can in particular have simultaneous access to the shared memory 20, each m processors 25 then accessing a memory bank 21, 22, 23 different.

The shared memory 20 according to the invention makes it possible to considerably reduce the interconnection surface between the memories and the processors of a multiprocessor system by making it possible to pass this interconnection for example over the memories. In addition, the use of single-port memories 210, 220, 230 advantageously makes it possible to optimize the surface area of the connections required with respect to a solution using multi-port memories.

The shared memory according to the invention also allows a gain in data transfer speed and a gain in energy consumption. Indeed, the reduction in the length of the connections reduces their parasitic capacitance and therefore the switching time of the signals as well as the energy consumption. Switching time and power consumption are further reduced by the use of a differential structure where the voltage swing used is reduced.

An efficient design in terms of silicon layers used in particular for making the connections in a chip comprising a shared memory 20 according to the invention advantageously reduces the production costs of such shared memory.

Advantageously, the shared memory 20 according to the invention has a mode of operation of the MIMD type, an acronym for the multiple statement Multiple Data, meaning "multiple instructions, multiple data", allowing different programs executing. on the m processors 25 to simultaneously access different data contained in the shared memory 20.

Claims (15)

1. A shared memory (20), made on a first integrated circuit based on semi-conductors, comprising:

   • an integer number m, greater than one, of input/output interfaces (EP/SP, SP'), each of the m input/output interfaces comprising 1 data input/output (EP/SP) and 1 address and control input (SP');

   • an integer number p, greater than one, of memory banks (21, 22, 23, 30), each memory bank (21, 22, 23, 30) comprising:

   - a memory (210, 220, 230, 300) comprising a data input/output (E/S) and an address and control input (E);

   - a block of m switches (214, 224, 234), each of the m switches (214, 224, 234) being connected via a memory data bus (213, 223, 233) to the data input/output (E/S) of the memory (210, 220, 230, 300),

   the shared memory (20) being characterised in that it comprises:

   • m bidirectional data buses (24), each of the m data buses (24) being respectively connected to one of the m data inputs/outputs (EP/SP) of the shared memory (20) on the one hand and being connected, on the other hand, to each of the p memory banks by means of one of the m switches of each memory bank,

   • m address and control buses (200), each being connected to one of the m address and control inputs of the shared memory (20) on the one hand, and being connected on the other hand to the address and control input (E) of each of the p memory banks by means of a multiplexer (211, 221, 231) provided in each memory bank.
2. The shared memory (20) according to Claim 1, characterised in that each multiplexer (211, 221, 231) of a memory bank has an output connected to the address and control input (E) of the memory (210, 220, 230, 300), inputs (211, 221, 231) of the multiplexer being connected to each of the address and control buses (200), the multiplexer selecting the address and control bus (200) that has to control the memory bank (21, 22, 23, 30).
3. The shared memory (20) according to Claim 1, characterised in that the first integrated circuit comprises several layers of metals, the p memory banks (21, 22, 23) using one or more layers of metals, the m data buses (24) and the address and control buses (200) are made in layers of metals overlaid on the layers comprising the p memory banks (21, 22, 23, 30).
4. The shared memory (20) according to any of Claims 1 to 3, characterised in that the m input/output interfaces (EP/SP, SP') of the shared memory (20) are able to be connected to inputs/outputs of m processors (25) internal to the first integrated circuit.
5. The shared memory (20) according to any of the preceding claims, characterised in that the m data buses (24) and the address and control buses (200) are parallel buses.
6. The shared memory (20) according to any of Claims 1 to 5, characterised in that the m data buses (24) are differential buses.
7. The shared memory (20) according to any of the preceding claims, characterised in that the memories (210, 220, 230, 300) are single-port memories.
8. The shared memory (20) according to any of the preceding claims, characterised in that the memories (210, 220, 230, 300) are memories of the SRAM type, the acronym standing for the expression Static Random Access Memory.
9. An integrated circuit based on semi-conductors characterised in that it comprises:

   • a shared memory according to any of claims 1 to 8;

   • m input/output ports (50) enabling connection of the integrated circuit to electronic components on the outside of the integrated circuit, each of the m ports (50) being linked to one of the m input/output interfaces (EP/SP, SP') of the shared memory (20).
10. The integrated circuit based on semi-conductors, characterised in that it comprises a shared memory according to any of Claims 1 to 8, and m processors (25), each of the m processors (25) being connected to one of the m input/output interfaces (EP/SP, SP') of the shared memory (20).
11. The integrated circuit based on semi-conductors, characterised in that it comprises a shared memory according to any of Claims 1 to 8, said integrated circuit being physically in contact with a second integrated circuit comprising m processors (25), each of the m processors (25) being connected to one of the m input/output interfaces (EP/SP, SP') of the shared memory (20), and in that the second integrated circuit is physically in contact with said first integrated circuit.
12. The integrated circuit based on semi-conductors according to Claim 11, characterised in that the m input/output interfaces (EP/SP, SP') of the shared memory are connected to the m processors (25) by vias.
13. The integrated circuit based on semi-conductors according to Claim 11, characterised in that the m input/output interfaces (EP/SP, SP') of the shared memory are connected to the m processors (25) by inductive links.
14. The integrated circuit based on semi-conductors according to Claim 11, characterised in that the m input/output interfaces of the shared memory are connected to the m processors (25) by capacitive links.
15. Integrated circuits based on semi-conductors, characterised in that they each comprise one or more of the p memory banks (21, 22, 23, 302) according to any of Claims 1 to 8, said integrated circuits being situated one above another, the m data buses (24) and the address and control buses (200) being positioned transversely to the integrated circuits.

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