WO2010007173A1 - Nouveau circuit d'amplification de détection - Google Patents

Nouveau circuit d'amplification de détection Download PDF

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Publication number
WO2010007173A1
WO2010007173A1 PCT/EP2009/059261 EP2009059261W WO2010007173A1 WO 2010007173 A1 WO2010007173 A1 WO 2010007173A1 EP 2009059261 W EP2009059261 W EP 2009059261W WO 2010007173 A1 WO2010007173 A1 WO 2010007173A1
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WO
WIPO (PCT)
Prior art keywords
sense amplifier
nmos transistor
amplifier circuit
transistors
circuit according
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PCT/EP2009/059261
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English (en)
Inventor
Claude Raphaël CHAPPERT
Weisheng Zhao
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Universite Paris Sud (Paris 11)
Centre National De La Recherche Scientifique - Cnrs -
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Publication of WO2010007173A1 publication Critical patent/WO2010007173A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type

Definitions

  • the invention relates to a sense amplifier circuit and logic circuits comprising said sense amplifier circuit.
  • the elemental brick of the application of magnetic control of electronic transports in nano-electronics is the magnetic tunnel junction (MTJ) .
  • a magnetic tunnel junction represented on figure 1, comprises at least a first and a second ferromagnetic layers Fl and F2 separated by a thin insulating layer I acting as tunnel barrier for electronic transport, and is patterned into nanopillar shape.
  • the resistance of the nanopillar depends on the relative orientations of the magnetizations of the first and second layer Fl and F2, represented by arrows on the figure 1.
  • the magnetization of one layer, for example F2 is fixed, usually by interfacial interaction with an antiferromagnetic layer, not represented on figure 1, while the magnetization of the other layer is free to rotate, for example for sensor applications, or can take two antiparallel orientations, for example for memory and logic applications such as discussed in this description.
  • the resistance of the tunnel junction can take one of two extreme values RMIN and RMAX.
  • Such devices have a natural aptitude to work in the frequency range around IGHz .
  • the magnetic tunnel junction is thus a commutable resistor that exhibits usual assets of magnetic storage, such as non-volatility and radiation hardness, while having transport properties, resistivity, write currents and operation speed compatible with CMOS electronics.
  • the integration of magnetic tunnel junctions is made by an "above CMOS” technology
  • the magnetic "back- end” process can be done after the CMOS “front-end” process, and with the new spin transfer torque writing scheme, requiring only bipolar current pulses sent through the magnetic tunnel junction itself, it becomes possible to finely distribute such magnetic tunnel junction cells into CMOS circuits. Therefore the magnetic tunnel junction can also be used to bring wide data non-volatility in the CMOS electronics, and exhibits great potential for embedded memory and logic applications.
  • the magnetic tunnel junctions When used in logic circuit, the magnetic tunnel junctions should be spread on the entire chip surface, while the standard MRAM sense amplifiers cannot provide the high sensing speed required by CMOS logic circuit.
  • the SRAM based sense amplifier represented in figure 2 and the dynamic current-mode logic sense amplifier represented on figure 3, were proposed to sense one pair of magnetic tunnel junctions with opposite magnetic configurations, one is at RMIN when the other is at RMAX, coding one logic bit.
  • the cell senses the magnetic information by briefly turning on the NMOS transistor MN2, "SEN” is the reading control signal.
  • This structure has been demonstrated to read the states of magnetic tunnel junctions in very high speed, which allows the FPGA circuits to realize a real "instant-on” .
  • the dynamic current-mode logic sense amplifier represented on figure 3 was proposed to sense the magnetic tunnel junction pair coding the logic signal.
  • each magnetic tunnel junction in the two branches of the circuit is associated with one NMOS transistor TNMOS MNl and MNO, which gates are controlled by a "SELECT" logic signal: hence, several pairs of magnetic tunnel junction and NMOS transistors can be connected to the same sense amplifier and addressed individually.
  • the "SELECT" signal is set to Vdd_logic and the transistors are thus open.
  • the SRAM based sense amplifier there are two operating phases. In the first one, "SEN" equals to
  • the circuit comprised ten transistors including MP0-MP3, MNO-3, plus the inverter necessary to generate the signal "SEN", and a capacitor CO. Comparing with the classical sense amplifier, there are too many transistors for a high density application.
  • the capacitor CO blocks the permanent currents from Vdd_Logic to GND, it also produces the voltage at Qm and Qm, through a chain of transistors and MAGNETIC TUNNEL JUNCTIONS. Therefore the outputs can not be exactly zero or Vdd_Logic and the margin between the two voltages should be well reduced, resulting in high sensitivity to mismatch variations and also numerous errors in the next stage of logic circuits.
  • One goal of the present invention is to provide a sense amplifier circuit that does not present the drawbacks of the sense amplifiers of the prior art. Such sense amplifier can then be used for sensing the configuration of any pair of variable resistors.
  • one subject of the invention is a sense amplifier circuit comprising:
  • a first and second NMOS transistors whose drains are respectively connected with the drains of the first and second PMOS transistors, and with the drains of the third and fourth PMOS transistors,
  • the sources of the first and second NMOS transistors being connected respectively to a first and second variable resistors that can be reversibly switched between two extreme states
  • the gate of the third NMOS transistor being connected to the gates of the first and fourth PMOS transistors, wherein the sense amplifier circuit is configured so that when one of the variable resistors is at minimum resistance state the other is at maximum resistance state.
  • the sense amplifier circuit according to the invention can improve significantly the stability, as a result shrink the die area, and reduce the sensing power down to be nearly negligible.
  • the sense amplifier according to the invention provides a similar sensing latency as for the conventional SRAM sense amplifier, while based on the operation mode all transistors could be taken to the lowest size of the given technology node.
  • the sense amplifier circuit is configured so as:
  • the first and second impulse current variable resistors are connected respectively to the drain of a first third NMOS transistor and a second third NMOS transistor, the gates of the first and second thirds NMOS transistors being connected together;
  • variable resistors are resistive memory devices
  • variable resistors are magnetic tunnel junctions
  • the current variable resistors are phase-change memory devices; - one of the current variable resistors is replaced by an invariable reference resistor of resistance comprised between the minimum and maximum values of the resistance of the variable resistor;
  • the sense amplifier circuit further comprises a fourth and fifth NMOS transistors, the drain of the fourth NMOS transistor being connected to a heating voltage, the source of the fourth NMOS transistor being connected to the first variable resistor, the drain of the fifth NMOS transistor being connected to the second variable resistor, the source of the fifth NMOS transistor being connected to a reference voltage, and the gates of the fourth and fifth NMOS transistors being arranged so as to receive a enabling signal;
  • the sense amplifier circuit further comprises a fourth and fifth NMOS transistors, the drains of the fourth and fifth NMOS transistors being connected together to a heating voltage, the source of the fourth NMOS transistor being connected to the source of the first NMOS transistor, the source of the fifth NMOS transistor being connected to the source of the second NMOS transistor, and the gates of the fourth and fifth NMOS transistors being arranged so as to receive a enabling signal;
  • the sense amplifier circuit further comprises a sixth NMOS transistor, the drain of the sixth NMOS transistor being connected to the
  • the first and fourth PMOS transistors are replaced by any CMOS circuit either specially attached to the sense amplifier or shared between several sense amplifiers in a word or register, and wherein the CMOS circuit is configured so as upon a sense signal to connect the drains of the second and third PMOS transistors and of the first and second NMOS transistors to a voltage substantially equal to Vdd.
  • the invention also relates to a hybrid CMOS logic circuit including magnetic tunnel junction comprising a sense amplifier circuit according to the invention.
  • the invention further relates to a look-up table of a programmable logic circuit comprising a sense amplifier circuit according to the invention. According to further embodiments of the invention:
  • the look-up table comprises at least two non-volatile bit comprising a switching circuit, two variable resistors and a sense amplifier circuit according to the invention; - at least two couples of magnetic tunnel junctions share fully or partly the same switching circuit and the same sense amplifier circuit according to the invention.
  • the invention also relates to a Latch circuit comprising a sense amplifier circuit according to the invention .
  • a writing circuit is arranged for memorizing information in magnetic tunnel junctions by switching them, and wherein the sensing circuit and the switching circuits are independent and the sensing circuit comprises a sense amplifier circuit according to the invention;
  • the writing circuit is arranged to switch magnetic tunnel junctions by spin transfer torque mechanism; - the magnetic tunnel junctions are arranged to be switched by thermally assisted switching mechanism.
  • FIG. 1 is a schematic representation of a magnetic tunnel junction
  • FIG. 2 is a schematic representation of a conventional Five transistor SRAM based sense amplifier
  • FIG. 3 a schematic representation of a dynamic current-mode logic sense amplifier
  • FIG. 4 is a schematic representation of a sense amplifier circuit according to the invention.
  • FIG. 5 is a schematic representation of a circuit for Spin Transfer Torque and Thermally Assisted Switching writing mode
  • - Figures 6a to 6 d are schematic representations of different heating circuit for Thermally Assisted Switching writing mode
  • FIG. 7 is a schematic representation of a non volatile Flip-Flop gate, or non volatile latch
  • FIGS. 8a to 8c are schematic representations of circuit for multi-context configuration for look-up table applications
  • FIG. 9 is a schematic representation of a two contexts A and B in a single sense amplifier circuit.
  • FIG. 10 is a schematic representation of a sense amplifier circuit according to an embodiment of the invention .
  • the elements shown on the figures are not necessarily to scale.
  • the sense amplifier circuit 10 may comprise:
  • a first 20 and second 22 NMOS transistors whose drains are respectively connected with the drains of the first 12 and second 14 PMOS transistors, and with the drains of the third 16 and fourth 18 PMOS transistors,
  • the sources of the first 20 and second 22 NMOS transistors being connected respectively to a first 24 and second 26 variable resistors that can be reversibly switched, for example by proper action, between two extreme states, the sense amplifier is configured so that one resistor is always at minimum resistance state while the other is at maximum resistance state,
  • the sense amplifier circuit 10 represented on figure 4 comprises inverters 14, 20 and 16, 22, two PMOS transistors 12, 18 in parallel with respectively the second 14 and third 16 PMOS transistors.
  • the third NMOS transistor 28 is connected to the reference voltage, for example the ground voltage.
  • the first and second variable resistors of the sense amplifier represented on figure 4 are magnetic tunnel junctions.
  • this sense amplifier represented on figure 4 comprises two operating phases depending on the control signal "SEN".
  • the control signal "SEN” is set to ' 0 '
  • the sense amplifier circuit 10 pre-charges the polarisation voltages VO and Vl of the two magnetic tunnel junctions 24, 26 to a value slightly below Vdd_logic, but there is no stationary current in the circuit.
  • the control signal "SEN” is set to y 0 '
  • the first, fourth PMOS transistors 12, 18 and the first, second NMOS transistors 20, 22 are open while the third NMOS transistor 28 is closed, therefore no stationary current passes through the circuit after the charging of VO and Vl has been completed, hence nearly zero power consumption during this operation phase.
  • the first and fourth PMOS transistors 12, 18 close while the third NMOS transistor 28 opens. So low discharge currents pass through the branches to sense the two magnetic tunnel junctions 24, 26, the resistance of the magnetic tunnel junctions 24, 26 determines the discharge speed. Since the two magnetic tunnel junctions 24, 26 have different resistances, the discharge speeds are different .
  • the resistance of the first magnetic tunnel junction 24 is lower than the resistance of the second magnetic tunnel junction 26 RMTJO>RMTJ1. Therefore the current Il through the first magnetic tunnel junction 24 is greater than the current IO through the second magnetic tunnel junction 26.
  • V3 is reduced faster than V2, and when V3 becomes smaller than the threshold switching voltage of the inverter composed by the third PMOS 16 and second NMOS 22 transistors, V2 charges to Vdd_logic and V3 continues the discharge process down to '0' .
  • the third PMOS transistor 16 and the first NMOS transistor 20 are open, the value of the output signal Qm is ' 1 ' for this configuration wherein the first magnetic tunnel junction 24 is parallel and the second magnetic tunnel junction 26 is anti-parallel.
  • the sense amplifier circuit according to the invention overcomes the drawbacks of the sense amplifier of the prior art.
  • the complete scheme requires only 7 transistors. Because only very small transitory currents are used, energy consumption for the sense phase is very small .
  • the scheme is less sensitive to mismatch variation than the conventional SRAM based scheme represented on figure 2. Hence transistors at the smallest size of a given technology can be used.
  • the output signal Qm results from the normal operation of a SRAM with only some resistances in series: the first and second magnetic tunnel junctions and the third NMOS transistor open when the control signal "SEN" is equal to ' 1 ' , contrary to the case of the Dynamic current-mode logic sense amplifier represented on figure 2.
  • the sense amplifier circuit according to the invention may be implemented associated with a writing circuit.
  • the sense amplifier circuit according to the invention may be used for the conventional magnetic tunnel junction writing approach using "Field Induced Magnetic Switching” (FIMS), where the sensing circuit and switching circuits are substantially independent.
  • FIMS Field Induced Magnetic Switching
  • the sense amplifier circuit according to the invention may also be adapted to be used with writing schemes that require sending a current through the magnetic tunnel junction. Indeed, during the precharge phase, when the value of the control signal "SEN" is y 0', the third NMOS transistor 28 is closed and the two magnetic tunnel junctions from the sensing circuit are just connected in series between VO and Vl, and somewhat electrically isolated if the first and second NMOS transistors 20, 22 are blocked.
  • the Spin Transfer Torque such as described in M.Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino and C. Fukumoto. "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching Spin-RAM” IEEE International Electron Devices Meeting (IEDM), USA, Dec. 5-7, 2005, pp 473-476 and Thermally Assisted Spin Transfer Torque switching (TAS-STT) such as described in US 7230844 modes only require bipolar current pulses injected through the magnetic tunnel junction to directly write a magnetic tunnel junction configuration.
  • TAS-STT Thermally Assisted Spin Transfer Torque switching
  • the Spin Transfer Torque and Thermally Assisted Spin Transfer Torque switching circuits may be connected directly to a sense amplifier circuit 10 according to the invention.
  • the Spin Transfer Torque and Thermally Assisted Spin Transfer Torque switching circuits can be active during the precharge phase and write the new data in the magnetic tunnel junction pair, but will have no impact on the sensing phase, as when the enabling signal EN is set to ' 0 ' the fourth 30, fifth 32, sixth 34 and seventh 36 NMOS transistors are blocked, and they require no additional transistors in the sense amplifier circuit.
  • Writing data by a current pulse in the magnetic tunnel junction pair may be done by setting the enabling signal "EN” to ' 1 ' in the precharge phase, i.e. when the control signal of the sense amplifier circuit 10 "SEN" equals ' 0 ' .
  • the third NMOS transistor 28 is closed, the gates voltages V2 and V3 of the first and second NMOS transistors 20, 22 are charged to Vdd_logic, and the writing current pass through the two magnetic tunnel junctions only.
  • the switching current circuit may be closed by simply setting the enabling signal "EN” from ' 1 ' to ' 0 ' with enough time left for the precharge circuit to stabilize before sensing.
  • Vl may be slightly lower than Vdd_logic and a low hypothesis 13 from V3 to Gnda passing through the first NMOS transistor to the seventh NMOS transistor 36 may appear. As it does not pass through the first magnetic tunnel junction 24, 13 may have no influence on the switching, but may be considered when optimizing the circuit .
  • the circuit represented on figure 5 comprises 3 NOT and 2 NOR gates. Said logic gates are used to fix the current direction and control the activation of the writing circuit .
  • the circuit represented on figure 5 may be simplified to 2 NOT and 2 NOR, which corresponds to 12 transistors.
  • the Spin Transfer Torque writing circuit thus requires 16 transistors per bit, to be added to the 7 transistors of the sensing circuit according to the invention.
  • a part of the logic block can be shared between several sense amplifier circuits in a multi-bit word or register. Besides, depending on the exact writing current density that may be required, all transistors could be taken to the smallest size of a given technology node below 90nm.
  • the Thermally Assisted Switching (TAS) writing mode uses a unipolar current pulse sent through the magnetic tunnel junction to rise its temperature above a given threshold, together with a bipolar magnetic field created by a bipolar current pulse sent through an independent conducting line to define the bit direction during the cool down step.
  • TAS Thermally Assisted Switching
  • FIGs 6a to 6d represent several heating circuits of the sense amplifier circuit for the Thermally Assisted Switching writing mode.
  • a first scheme for the application of Thermally Assisted Switching writing mode to the sense amplifier circuit adapted from the scheme represented on figure 5 as described in the text above. Similar to the Spin Transfer Torque mode, writing is done by setting the enabling signal "EN" to ' 1 ' during the precharge phase, i.e. when the control signal "SEN" equals ' 0 ' : then a current passes through the magnetic tunnel junctions to heat them, and a magnetic field pulse can then be applied to fix the new magnetic configuration.
  • Vdda may take a different value than Vdd_logic. This scheme adds only 2 transistors to a single bit sense amplifier circuit, and the logic block of Figure 5 is no more required.
  • Figure 6b represents a second scheme to implement the Thermally Assisted Switching writing mode to the sense amplifier circuit.
  • writing is done by setting the enabling signal "EN" to ' 1 ' in the precharge phase, i.e. when the control signal "SEN" equals ' 0 ' .
  • the logic block, an inverter, an OR gate and a AND gate ensures that the first and fourth PMOS transistor 12, 18 and the first, second and third NMOS transistors 20, 22, 28 are conducting, so that a current passes through the magnetic tunnel junctions to heat them.
  • this scheme requires no extra transistor in the sense amplifier circuit itself, which stays at 7 transistors per sense circuit in total, and the logic block can be shared between several sense amplifier circuits in a multi-bit word or register.
  • Figure 6c represents a third scheme to implement the Thermally Assisted Switching writing mode to the sense amplifier circuit, adapted from the scheme of Figure 6b to allow higher values of the heating currents.
  • Two NMOS transistors 40, 42 are added to connect the magnetic tunnel junctions 24, 26 to Vdda when the enabling signal "EN" is set to ' 1 ' : the heating current then passes through only two transistors in series with the magnetic tunnel junctions 24, 26, and furthermore Vdda can take a higher value than Vdd_logic.
  • the logic block of Figure 6b is kept to create the input signals "A" and "B” from the enabling signal "EN” and the control signal "SEN".
  • Figure 6d represents a fourth scheme to implement the Thermally Assisted Switching writing mode to the sense amplifier circuit, adapted from the scheme of figure 6c.
  • a transistor 44 is added to the sense amplifier circuit, which allows to get rid of the logic block used in figure 6c to create the input signals "A” and “B” from the enabling signal “EN” and control signal "SEN".
  • the enabling signal "EN” may be taken equal to the inverse of the clock signal “CLK_bar” and the control signal “SEN” may be taken equal to the clock signal "CLK”.
  • the complete magnetic logic bit described above plays the role of a non volatile Flip-Flop gate or non volatile latch, written at every period of the CLK as illustrated on figure 7. For other applications, it could also play the role of a memory that is written only at specific moment, for instance to register status information before powering down a device, or to reprogram dynamically a logic function in a Look Up Table (LUT) .
  • LUT Look Up Table
  • one non-volatile logic bit can be made, comparable to a non volatile SRAM memory cell.
  • Figure 8a shows an example of 2-inputs Look up table based on multi-context principle.
  • One non volatile bit is composed of one sense amplifier circuit according to the invention including two magnetic tunnel junctions, and one switching circuit. Such example illustrates how non volatile bits can be combined to form a non volatile, dynamically reprogrammable Look up Table.
  • the enabling signal "EN” may be then taken back to ' 0 ' while the writing signal “Write” is still at ' 0 ' : this closes all transistors MN03, MN04, MN05, MN06 in the writing circuit. b) if the writing signal "Write” is changed to '1' with the enabling signal "EN” still set to O', only bits with Input set to '1' are written to ' 1 ' state when setting the enabling signal "EN” from O' to ' ⁇ '. For the other bits, the previously written ' 0 ' state is preserved.
  • the logic block is shared on the whole word, with a compact 6-transistors writing circuit to be kept for each bit.
  • the total bit size is only 13 transistors and 2 magnetic tunnel junctions per bit.
  • an integrated sharing can be achieved using a multi-context configuration as shown on figure 9.
  • a single sense amplifier circuit is connected to several magnetic tunnel junction pairs storing the outputs of the logic function; two pairs A and B are shown on figure 9.
  • a coder may provide the commands A and B.
  • a (resp. .B) may be used to select the pair of magnetic tunnel junctions to read or write.
  • the sense amplifier circuit structure itself is modified as the third NMOS transistor attached to the two magnetic tunnel junctions is replaced by three NMOS transistors, two for connecting individually each magnetic tunnel junctions to Gnd_logic, and the transistor MNA2 (resp B2) connecting together the two magnetic tunnel junctions of a given pair.
  • the input signal "A” is set to ' 1 ' as the enabling signal “EN” is active and the input signal "B” is set to ' 0 ' , and the two magnetic tunnel junctions of the A pair can be switched by the Iw current provided by a single bipolar current source.
  • the input signal "A” is set to ' 1 ' and the control signal “SEN” is changed from ' 0 ' to ' 1 ' while the input signal "B” is kept to "0", and the data of the A pair is transferred to the output .
  • the scheme represented on figure 9 presents the advantage of completely sharing the sense amplifier circuit and the bipolar current writing circuit between all non volatile bits, at the expense of the shared coder providing the commands A and B, and of the gates, at each bit, charged to provide the combined commands SEN.
  • the N-bits register, LUT and multicontext architectures according to the invention may also be adapted for writing by the standard thermally assisted writing mode. As described, only a unipolar current pulse through the magnetic tunnel junction is needed, which simplifies a lot the standard writing circuit attached to the sense amplifier circuit, only two transistors.
  • the conducting line and bipolar current source may be shared between all bits, provided that the writing step is done in two steps: first step to write all magnetic tunnel junctions requiring one field direction, and second step to write the magnetic tunnel junctions requiring the reverse field direction.
  • the two steps writing just requires a supplemental logic to control which bits are heated at each step, which can be done in a similar way as used for the device of figure 8c.
  • the sense amplifier circuit may be implemented in Sharing writing circuit and assistance for Flip-Flop applications.
  • the non-volatile Flip-Flop application requires very high speed, normally of smaller or equal to a nanosecond.
  • the signals "SEN”, “EN”, “Write” may all be generated through the clock signal "CLK”.
  • the Flip-Flop application, and some others, also requires another mandatory circuit: a “Slave” logic block on the output of each bit, to save the output Qm during the writing phase when the control signal "SEN" I set to ' 0 ' .
  • the sense amplifier circuit may be configured so as to use only one magnetic tunnel junction device per logic bit, therefore avoiding the need to simultaneously switch a pair of magnetic tunnel junctions.
  • a convenient technique to achieve this goal may be to replace the pair of magnetic tunnel junctions 24, 26 of the sense amplifier circuit by a writeable magnetic tunnel junction 24 combined with a reference magnetic tunnel junction 25.
  • the reference magnetic tunnel junction 25 has an initial orientation of the free layer uniform on the whole chip and is kept unchanged by normal operation. An example of such structure is illustrated on figure 10.
  • the resistance of the reference magnetic tunnel junction 25 takes a value somewhere in between the P and AP resistances of the written magnetic tunnel junction, taking into account the bias voltage effect due to non zero voltage across the magnetic tunnel junctions. In that case, the effective TMR ratio may be about half compared to that of the sense amplifier circuit with the pair of writing magnetic tunnel junctions . The exact value of the resistance of the reference magnetic tunnel junction 25 may easily be evaluated from model electrical simulations.
  • the reference and the writing magnetic tunnel junctions 24 may be implemented with the same magnetic stack to save on fabrication costs, their resistances may be obtained by giving different lateral dimensions to both magnetic tunnel junctions.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

L'invention porte sur un circuit d'amplification de détection comprenant : quatre transistors PMOS dont les sources sont sur une source de tension Vdd, deux transistors NMOS dont les drains sont respectivement connectés avec les drains des transistors PMOS, les sources des transistors NMOS étant connectées à des résistances variables, les résistances variables étant connectées au drain d'un troisième transistor NMOS (28), la source du troisième transistor NMOS (28) étant connectée à une tension de référence (Vref), les portes des transistors (14, 20) étant connectées ensemble, les portes des transistors (16, 22) étant connectées ensemble, la porte du troisième transistor NMOS (28) étant connectée aux portes des transistors PMOS (12, 18).
PCT/EP2009/059261 2008-07-17 2009-07-17 Nouveau circuit d'amplification de détection WO2010007173A1 (fr)

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US61/081517 2008-07-17

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013163158A1 (fr) * 2012-04-25 2013-10-31 Qualcomm Incorporated Appareil à bascule bistable non volatile à faible courant de détection comportant des jonctions tunnel magnétiques
WO2016060617A1 (fr) * 2014-10-15 2016-04-21 Agency For Science, Technology And Research Circuit bistable, son procédé de commande et dispositif mémoire
CN112927737A (zh) * 2019-12-05 2021-06-08 上海磁宇信息科技有限公司 具使用磁性隧道结的非易失寄存器

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Publication number Priority date Publication date Assignee Title
JP2003157671A (ja) * 2001-11-22 2003-05-30 Internatl Business Mach Corp <Ibm> 不揮発性ラッチ回路
US20050122769A1 (en) * 2003-12-03 2005-06-09 International Business Machines Corporation Magnetic memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003157671A (ja) * 2001-11-22 2003-05-30 Internatl Business Mach Corp <Ibm> 不揮発性ラッチ回路
US20050122769A1 (en) * 2003-12-03 2005-06-09 International Business Machines Corporation Magnetic memory device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013163158A1 (fr) * 2012-04-25 2013-10-31 Qualcomm Incorporated Appareil à bascule bistable non volatile à faible courant de détection comportant des jonctions tunnel magnétiques
US9196337B2 (en) 2012-04-25 2015-11-24 Qualcomm Incorporated Low sensing current non-volatile flip-flop
WO2016060617A1 (fr) * 2014-10-15 2016-04-21 Agency For Science, Technology And Research Circuit bistable, son procédé de commande et dispositif mémoire
US10043563B2 (en) 2014-10-15 2018-08-07 Agency For Science, Technology And Research Flip-flop circuit, method of controlling a flip-flop circuit and memory device
CN112927737A (zh) * 2019-12-05 2021-06-08 上海磁宇信息科技有限公司 具使用磁性隧道结的非易失寄存器
CN112927737B (zh) * 2019-12-05 2024-01-05 上海磁宇信息科技有限公司 使用磁性隧道结的非易失寄存器

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