WO2010004647A1 - Dispositif à semi-conducteur et module rfid - Google Patents

Dispositif à semi-conducteur et module rfid Download PDF

Info

Publication number
WO2010004647A1
WO2010004647A1 PCT/JP2008/062586 JP2008062586W WO2010004647A1 WO 2010004647 A1 WO2010004647 A1 WO 2010004647A1 JP 2008062586 W JP2008062586 W JP 2008062586W WO 2010004647 A1 WO2010004647 A1 WO 2010004647A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
circuit
current
latch
semiconductor device
Prior art date
Application number
PCT/JP2008/062586
Other languages
English (en)
Japanese (ja)
Inventor
好和 飯田
利広 田中
章 加藤
貴志 山木
由紀子 梅本
次郎 石川
武文 遠藤
Original Assignee
株式会社ルネサステクノロジ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ルネサステクノロジ filed Critical 株式会社ルネサステクノロジ
Priority to PCT/JP2008/062586 priority Critical patent/WO2010004647A1/fr
Publication of WO2010004647A1 publication Critical patent/WO2010004647A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present invention relates to a semiconductor device including a memory for storing information using a change in resistance value.
  • a phase change memory using a phase change element as a memory cell and further, RFID (Radio Frequency Identification) equipped with a phase change memory
  • the present invention relates to a technology effective when applied to a chip.
  • phase change material By applying a reset pulse that heats the memory element using the phase change material used in the phase change memory above the melting point of the phase change material and then rapidly cools it, the phase change material becomes a high resistance amorphous state (reset) Status, for example, stored information “0”). Conversely, by applying a set pulse that keeps the memory element in a temperature range lower than the melting point and higher than the crystallization temperature equal to or higher than the glass transition point, the phase change material becomes a low resistance polycrystalline state. (Set state, for example, stored information “1”). As described above, a high voltage is not required for writing data to the phase change memory that stores information according to the two states of the phase change element, unlike the flash memory.
  • the phase change memory can be operated with a single power supply shared with the control logic, eliminating the need for a booster circuit that requires a large area, greatly reducing the area occupied by the chip, and eliminating the need for a booster circuit. There is an advantage that the power consumption can be kept low by reducing the power consumption by this, and thereby cost reduction and performance improvement can be realized.
  • the phase change memory is suitable for low voltage operation and low power consumption operation.
  • Documents describing the phase change memory include the following documents 1 and 2.
  • the present inventor examined further lower power consumption and low voltage operation of the phase change memory.
  • the operating power supply is provided by rectifying radio waves received by an antenna.
  • a phase change memory capable of low power consumption and low voltage operation has a limit, and further low power consumption is demanded in both read and write operations.
  • the phase change element has temperature characteristics, and it is necessary to set the timing of writing and reading in consideration of the temperature characteristics in order to improve the reliability of information storage. Further, this relates to the determination of read data, the speed of determination operation in verify read, the reliability of data writing, and the like.
  • An object of the present invention is to provide a semiconductor device capable of realizing low power consumption in a read operation.
  • An object of the present invention is to provide a semiconductor device that can alleviate soft write in a read operation.
  • Another object of the present invention is to provide a semiconductor device capable of stabilizing the read operation with respect to variations in temperature characteristics, parasitic capacitance, and the like of phase change elements.
  • Still another object of the present invention is to provide a semiconductor device capable of improving the reliability of a verify operation for writing.
  • Still another object of the present invention is to provide an RFID module with low power consumption.
  • a selection transistor is selected by a word line, and a change in the charging potential of the bit line is detected by an amplifier and latched in a read data latch.
  • the bit line is clamped at a low potential, and the timing of both the word line selection timing and the latch timing of the read data latch is generated in synchronization with the change of the instruction signal of the read operation given from the outside.
  • the current flowing through the phase change element can be reduced by clamping the bit line to a low potential during the read operation.
  • the data latch timing based on the selection of the memory cell is used in the external access control. It is easy to minimize the deviation. Further, when the latch data by the read data latch that holds the output of the amplifier that detects the potential change of the precharged bit line in the read operation is determined, the remaining charge on the bit line is discharged from a path other than the memory cell. As a result, the amount of discharge from the memory cell can be minimized, and in this respect, it is possible to contribute to low power consumption and suppression of soft light.
  • FIG. 1 is a block diagram illustrating an RFID tag module which is an example of a semiconductor device according to the present invention.
  • FIG. 2 is a schematic explanatory view illustrating the planar structure of the memory cell.
  • 3 is a cross-sectional view taken along line AA in FIG.
  • FIG. 4 is a characteristic diagram illustrating characteristics of a memory element using a phase change material.
  • FIG. 5 is a block diagram generally illustrating a more detailed configuration of the phase change memory.
  • FIG. 6 is a waveform diagram of main signals at the time of reading from the phase change memory.
  • FIG. 7 is a logic circuit diagram of the precharge pulse generation circuit (PCPGEN).
  • FIG. 8 is an explanatory diagram showing the truth value of the selector (SLC2) of FIG.
  • FIG. 1 is a block diagram illustrating an RFID tag module which is an example of a semiconductor device according to the present invention.
  • FIG. 2 is a schematic explanatory view illustrating the planar structure of the memory cell.
  • 3 is
  • FIG. 9 is a logic circuit diagram of the sense latch pulse generator (SLPGEN).
  • FIG. 10 is a logic circuit diagram illustrating a shift register.
  • FIG. 11 is an operation waveform diagram of the shift register.
  • FIG. 12 is an operation waveform diagram from the write input signal to the output of the write pulse generation circuit (WPGEN).
  • FIG. 13 is a logic circuit diagram of the write pulse generation circuit (WPGEN).
  • FIG. 14 is a logic circuit diagram illustrating the circuit configuration of the delay circuit WPDLY.
  • FIG. 15 is an operation waveform diagram from the output of the write pulse generation circuit (WPGEN) to the word line and bit line.
  • FIG. 16 is a timing chart of a comparative example showing an example in which a gap is generated between both pulses without overlap.
  • FIG. 16 is a timing chart of a comparative example showing an example in which a gap is generated between both pulses without overlap.
  • FIG. 17 is a timing chart showing an example of verify reading.
  • FIG. 18 is a circuit diagram showing an example in which high data (data at high resistance) and low data (data at low resistance) can be simultaneously verified.
  • FIG. 19 is a time chart showing main operation timings during normal reading in FIG.
  • FIG. 20 is a time chart showing main operation timings at the time of verify reading in FIG.
  • FIG. 21 is an explanatory diagram showing the truth value of the selector S1 ⁇ n> in FIG.
  • FIG. 22 is an explanatory diagram showing the truth value of the selector S2 ⁇ n> in FIG.
  • FIG. 23 is a processing flow from writing to verify writing.
  • FIG. 24 is a timing chart showing the operation from the write input signal to the output of the write pulse generation circuit in the verify write.
  • FIG. 24 is a timing chart showing the operation from the write input signal to the output of the write pulse generation circuit in the verify write.
  • FIG. 25 is a logic circuit diagram showing an example of a 2row ⁇ 16 bit register REG.
  • FIG. 26 is a logic circuit diagram showing an example of YDEC22.
  • FIG. 27 is a logic circuit diagram showing an example of the XDEC 14.
  • FIG. 28 is a timing chart illustrating an operation waveform at the time of register reading.
  • FIG. 29 is a timing chart illustrating an operation waveform at the time of register writing.
  • FIG. 30 is an explanatory diagram illustrating the significance of setting data in the register REG.
  • FIG. 31 is a timing chart showing main operation waveforms when the word line and the bit line are set in a write state in a DC manner instead of a pulse when performing a stress test regarding switching defined by regout1 ⁇ 15>.
  • FIG. 31 is a timing chart showing main operation waveforms when the word line and the bit line are set in a write state in a DC manner instead of a pulse when performing a stress test regarding switching defined by regout1 ⁇ 15>
  • FIG. 32 is a logic circuit diagram illustrating a circuit (MULTIT) that realizes the multi-bit simultaneous writing function.
  • FIG. 33 is an explanatory diagram showing an example of the relationship between the value of the register regout1 ⁇ 14:13> and the number of simultaneous multi-bit writes.
  • FIG. 34 is an explanatory diagram showing combinations of I / O written simultaneously by multi-bit simultaneous writing.
  • FIG. 35 is a block diagram illustrating details of the read data system.
  • FIG. 36 is a logic circuit diagram of the X decoder (XDEC) 14 for selecting the word line WL.
  • FIG. 37 is a logic circuit diagram of the Y switch circuit (YSW).
  • FIG. 38 is a logic circuit diagram of the Y decoder (YDEC) 22 for selecting the bit line BL.
  • FIG. 39 is a logic circuit diagram of the rewrite circuit (BLSW).
  • FIG. 40 is a circuit diagram illustrating a current switching circuit.
  • FIG. 41 is a circuit diagram illustrating a simple current switching circuit having one type of current.
  • FIG. 42 is a block diagram showing a configuration in the case where I ⁇ 0> to I ⁇ m> switching of the current switching circuit of FIG. 40 is switched by a temperature sensor.
  • FIG. 43 is a timing chart showing an operation sequence realized by the set / reset pulse generation circuit 76.
  • FIG. 44 is a waveform diagram showing a first example of a mode of changing the current flowing through the constant current source NMOS transistor XI0 by switching I ⁇ 0> to I ⁇ m> of the current switching circuit of FIG.
  • FIG. 45 is a waveform diagram showing a second example of a mode of changing the current flowing through the constant current source NMOS transistor XI0 by switching I ⁇ 0> to I ⁇ m> of the current switching circuit of FIG.
  • FIG. 46 is a waveform diagram showing a third example of a mode of changing the current flowing through the constant current source NMOS transistor XI0 by switching I ⁇ 0> to I ⁇ m> of the current switching circuit of FIG.
  • FIG. 47 is a circuit diagram showing an example of a power supply circuit for supplying the voltages Vreset and VBL.
  • FIG. 48 is a waveform diagram showing that the optimum temperature for crystallization of the phase change element varies due to process variations.
  • FIG. 49 is a waveform diagram illustrating the relationship between the word line voltage and the phase change temperature when the word line is a slow cooling pulse.
  • FIG. 50 is a circuit diagram illustrating a circuit configuration of the temperature sensor.
  • FIG. 51 is a waveform diagram showing the operation principle of the temperature sensor.
  • FIG. 52 is a logic circuit diagram illustrating a circuit configuration of the encoder.
  • FIG. 53 is an explanatory diagram showing the relationship among VOUT, temperature sensor output, and encoder output at temperature.
  • FIG. 54 is a block diagram showing a phase change memory employing memory cells in which select transistors are arranged in parallel.
  • FIG. 55 is a logic circuit diagram illustrating the word line driving circuit of FIG.
  • FIG. 56 is a timing chart illustrating the operation timing of the phase change memory of FIG. FIG.
  • FIG. 57 is a waveform diagram illustrating the change in crystallization temperature and the like when using parallel selection transistors.
  • FIG. 58 is a waveform diagram illustrating a change in crystallization temperature when a single selection transistor is used.
  • FIG. 59 is an explanatory diagram illustrating the relationship between the signal amount and the threshold voltage.
  • FIG. 60 is a circuit diagram showing an example of a sense amplifier (SA) that determines the potential of the bit line BL.
  • FIG. 61 is a circuit diagram illustrating a circuit for generating the voltage Vrtransg.
  • FIG. 62 is a circuit diagram illustrating a resistance measurement circuit (resistance value measurement sense amplifier) SA_b.
  • FIG. 63 is a timing chart illustrating the operation waveform of resistance measurement.
  • FIG. 64 is a circuit diagram showing another example of the resistance measurement circuit SA_b.
  • FIG. 65 is a timing chart illustrating an operation waveform using the resistance measurement circuit of FIG.
  • FIG. 66 is a circuit diagram illustrating a delay circuit (DLY) configured with a constant current circuit.
  • FIG. 67 is a circuit diagram illustrating a configuration using a plurality of delay circuits of FIG.
  • a semiconductor device (2) includes a plurality of memory cells (11) in which a selection transistor (CT) is connected in series to a phase change element (PCR) that stores information using a change in resistance value.
  • a bit line (BL) connected to one end of the current path of the memory cell, a precharge element (MPC) for precharging the bit line for a read operation, and a selection terminal of the selection transistor.
  • It has a memory (7) comprising a timing generation circuit (PCPGEN, SLPGEN) for generating latch timing.
  • both the word line selection timing and the latch timing of the read data latch are generated in synchronization with the change of the instruction signal of the read operation, data based on the selection of the memory cell in the external access control It is easy to minimize the deviation of the latch timing.
  • the latch data is determined by the read data latch that holds the output of the amplifier that detects the potential change of the precharged bit line in the read operation, the residual charge on the bit line is discharged from the discharge element (MNPD, MDC). Therefore, the amount of discharge from the memory cell can be minimized, and in this respect, it can contribute to the suppression of soft light.
  • the timing generation circuit includes a plurality of delay circuits (DLY connected in series) for generating the word line selection timing and the latch timing of the read data latch.
  • the delay time of the delay circuit is determined by the current flowing through the constant current element (P5, N5 in FIG. 66). Therefore, it becomes easy to reduce the influence and temperature dependency due to manufacturing variations, and it is possible to generate latch timings with less variations. This contributes to a stable operation of the latch timing.
  • the timing generation circuit uses a plurality of delay circuits (DLY) connected in series to control the latch timing of the read data latch.
  • DLY delay circuits
  • a pulse generator (SLPGEN) that generates a signal (SLACH) is provided, and the delay time of the delay circuit is determined by the current flowing through the constant current element (FIG. 66, P5, N5). Therefore, it becomes easy to reduce the influence and temperature dependency due to manufacturing variations, and it is possible to generate latch timings with less variations. This contributes to a stable operation of the latch timing.
  • the semiconductor device further includes a temperature sensor (80 in FIG. 50), and the pulse generator cancels the positive temperature characteristic of the delay circuit based on the detection result of the temperature sensor.
  • a delay selector SLC2 for selecting the number of serial stages of the delay circuit used for generating the latch timing signal (SLACH) is provided. The influence of the positive temperature characteristic of the delay circuit on the latch timing signal can be reduced.
  • the semiconductor device of Item 3 further includes a temperature sensor (80 in FIG. 50), and the pulse generator cancels the negative temperature characteristic of the delay circuit based on the detection result by the temperature sensor.
  • a delay selector SLC2 controlled by CENC ⁇ 0>, CENC ⁇ 1> for selecting the number of serial stages of the delay circuit used for generating the latch timing signal (SLACH) is provided. The influence of the negative temperature characteristic of the delay circuit on the latch timing signal can be mitigated.
  • the semiconductor device of [6] further includes a temperature sensor, and the delay selector generates the latch timing signal so as to cancel the positive temperature characteristic of the delay circuit based on a detection result by the temperature sensor. Select the number of delay circuits to be used in series. The influence of the positive temperature characteristic of the delay circuit on the latch timing signal can be reduced.
  • the semiconductor device further includes a temperature sensor, and the delay selector generates the latch timing signal so as to cancel the negative temperature characteristic of the delay circuit based on a detection result by the temperature sensor. Select the number of delay circuits to be used in series. The influence of the negative temperature characteristic of the delay circuit on the latch timing signal can be mitigated.
  • a clamp that clamps a precharge voltage of the bit line to a voltage lower than a supply voltage of the precharge element between the precharge element and the bit line. It has an element (MTRANS). Since the current flowing through the memory cell in the read operation can be reduced, it can contribute to prevention of soft write.
  • the threshold voltage of the clamp element is smaller than the threshold voltages of the precharge element and the discharge element.
  • the low threshold enables a stable read operation without damaging the memory cell current in the read operation even at a low power supply voltage, and contributes to the low voltage operation.
  • the amplifier is an inverter amplifier. No through current is generated during the sensing operation, contributing to low power consumption.
  • the semiconductor device further includes a capacitance element (CAP) coupled to an input node of the amplifier, and the capacitance element is obtained from a parasitic capacitance of a bit line selected in a read operation. Also have a large capacitance value. The influence of the parasitic capacitance variation in the path from the bit line to the amplifier input with respect to the change amount of the bit line potential can be reduced, and the read operation can be stabilized.
  • CAP capacitance element
  • the semiconductor device further includes a resistance value measurement circuit (SA_b) connected to the input node of the amplifier connection.
  • the resistance measurement circuit includes a current supply element (P1, P12) that supplies a current to the bit line in a measurement mode, a current mirror element (P2, N12) in which a current flowing through the current supply element is reflected, An external monitor terminal (PAD) that makes it possible to observe the current flowing through the current mirror element, a detection circuit (CMP4, AMP1) that stops the current supply operation by the current supply element when the voltage of the bit line reaches the reference voltage,
  • the resistance value of the phase change element can be measured without applying a current directly to the memory cell from the outside, which also contributes to the soft write suppression of the memory cell.
  • a semiconductor device (2) includes a plurality of memory cells (11) in which a selection transistor (CT) is connected in series to a phase change element (PCR) that stores information by utilizing a change in resistance value.
  • a local bit line (BL) connected to one end of the current path of the memory cell, a selection switch element (YSW) for selecting the local bit line and connecting it to a global bit line (BLSA), and the global bit A precharge element (MPC) for precharging a line for a read operation; a word line (WL) connected to a selection terminal of the selection transistor; and the local cell connected to the memory cell selected by the word line.
  • An amplifier (31) for detecting a potential change applied from the bit line to the global bit line, and a read data latch (30) for holding the output of the amplifier;
  • a discharge element (MDC) for discharging residual charges of the local bit line and the global bit line when latch data by the data latch is determined, and the word line in synchronization with a change in a read operation instruction signal applied from the outside
  • a timing generation circuit (SLPGEN, PCPGEN) for generating a selection timing and a latch timing of the read data latch; and the bit for changing a resistance value of a phase change element of the memory cell selected by the word line in a write operation
  • BLSW rewrite circuit
  • the semiconductor device further includes a logic unit (6) for controlling access to the memory.
  • the memory can operate with the same power supply as the logic circuit.
  • the semiconductor device further includes a transmission / reception unit (4) connected to the logic unit by performing proximity contactless communication via the antenna (3), and a power supply voltage by rectifying an input from the antenna. And a rectifying unit (5) for generating A power supply voltage (Vdd) generated by the rectifying unit is supplied as an operation power source for the memory, the logic unit, and the transmitting / receiving unit.
  • the semiconductor device is configured as an RFID chip. A memory can be stably operated in an RFID chip that requires low voltage and low power consumption.
  • the RFID tag module (1) includes the semiconductor device according to Item 16 and an antenna connected to the semiconductor device.
  • FIG. 1 illustrates an RFID (Radio Frequency Identification) tag module as an example of a semiconductor device according to the present invention.
  • An RFID tag module (RFID MDL) 1 shown in FIG. 1 includes an RFID chip (RFID CIP) 2 and an antenna (ANTN) 3, and reads and writes codes and identification data by near field communication (NFC). It is configured as a wireless tag that can be loaded, and is applied to various uses such as distribution management and traceability.
  • the RFID chip 2 includes a transmission / reception unit 4, a rectifier circuit 5, a control logic 6, and a phase change memory (PRAM) 7.
  • the rectifier circuit 5 rectifies the AC signal received by the antenna 3 and lowers the voltage with a regulator to generate the power supply voltage Vdd.
  • the transmission / reception unit 4 connected to the antenna 3 transmits and receives radio waves in a predetermined frequency band and generates a clock signal from the reception signal of the antenna 3.
  • the control logic 6 controls the operation according to the received command in synchronization with the generated clock signal. That is, operation control of the transmission / reception unit 4 and access control of the phase change memory 7 are performed.
  • the phase change memory 7 holds ID data and other data in a rewritable manner.
  • the phase change memory 7 that can operate at a low voltage and consumes less power is employed as the nonvolatile memory.
  • the phase change memory stores information using the state change of the phase change material that can vary in resistance value according to the stored information, and detects the resistance difference based on the information to discriminate the information.
  • a booster circuit is required, and the area and current consumption increase.
  • phase change memory 7 can be operated with a single power source shared with the control logic circuit 6, a booster circuit that requires a large chip occupation area is not required, and the area is greatly reduced and the power consumption is kept low. (The amount of power consumed by the booster circuit and the amount of power reduced by the same power supply as the control logic), and the effects of cost reduction and performance improvement are achieved.
  • FIG. 1 shows a schematic configuration of the phase change memory 7.
  • the memory array 10 includes word lines WL0 to WLn, bit lines BL0 to BLk, and a plurality of memory cells 11 (M00 to Mnk) arranged at each intersection of the word lines and the bit lines.
  • the memory cell 11 includes a selection transistor CT and a storage element PCR as a phase change element using a phase change material.
  • the memory cell 11 is configured by connecting a selection transistor CT and a storage element PCR in series from the bit line to the power supply line of the ground voltage Vss. The connection order of the selection transistor CT and the storage element PCR may be reversed.
  • the storage element PCR is made of, for example, a phase change material (or chalcogenide material) such as Ge—Sb—Te system or Ag—In—Sb—Te system containing at least antimony (Sb) and tellurium (Te) as a material for the recording layer. It is used as.
  • a phase change material or chalcogenide material
  • FIG. 2 The planar structure of the memory cell 11 is illustrated in FIG. 2, and FIG. 3 illustrates a cross section taken along the line AA in FIG. In the figure, a pair of adjacent memory cells 11 sharing a source is illustrated. A unit cell region surrounded by a broken line constitutes one memory cell 11.
  • the selection transistor CT is composed of a source / drain and a gate of a diffusion layer
  • the storage element PCR is composed of an interface film connected to the drain via a lower contact, a phase change film, and an upper electrode connected to the bit line.
  • the storage element using the phase change material when storing storage information “0” in this storage element, the storage element using the phase change material is rapidly cooled after being heated to the melting point Ta of the phase change material. Apply a reset pulse. By shortening the reset pulse to reduce the total energy applied and setting the cooling time t1 to be short, the phase change material becomes a high-resistance amorphous state (reset state). As shown in the figure, conversely, when the memory information '1' is written, the memory element is kept in a temperature region lower than the melting point and higher than the crystallization temperature Tx equal to or higher than the glass transition point. Apply a set pulse. By applying such a set pulse, the phase change material becomes a low resistance polycrystalline state (set state).
  • the time t2 required for crystallization varies depending on the composition of the phase change material, but is, for example, 1 us.
  • the temperature of the element shown in the figure depends on Joule heat generated by the memory element itself and thermal diffusion to the surroundings.
  • the amorphous state is associated with the storage information '0' and the crystal state is associated with the storage information '1'.
  • the amorphous state is associated with the storage information '1'
  • the crystal state is associated with the storage information '0'. You may make it correspond.
  • an address line ADRL, a data line DATL, and a control signal line CNTL are connected to a phase change memory 7 with a control logic 6.
  • a read permission signal / RE, a rewrite permission signal / WE, a reset signal / RES, and the like are applied to the control signal line CNTL.
  • Address information is supplied to the address line ADRL.
  • Data information is transmitted to the data signal line DATL.
  • Address information supplied to the address line ADRL is held in an address buffer (ADB) 13.
  • the X address information selectively drives the word lines WL0,..., WLn via the word line decoder (XDEC) 14 and the word line drive circuit (WLD) 15.
  • Bit lines BL0 to BLk as local bit lines of the memory cell are connected to a sense amplifier (SA) 16, and the sense amplifier 16 amplifies the information on the bit line. For example, the information held in the memory cell 11 is stored. In the case of binary, it is determined whether the information held in the memory cell is “0” or “1”.
  • the output of the sense amplifier 16 is supplied to a data buffer (DTB) 19 via a Y switch circuit (YSW) 18 which is a Y gate.
  • the data buffer 19 holds the read result, outputs read data to the data line DATL, and receives and holds write information from the data line DTL.
  • a rewrite circuit (BLSW) 21 supplies a write current for writing.
  • Y address information is decoded by a Y gate decoder (YDEC) 22, and the bit line selection operation by the Y gate 18 is controlled by the decoded signal.
  • the Y gate is disposed between the sense amplifier 16 and the data buffer 19, but may be disposed between the bit line and the sense amplifier.
  • Rewrite of the stored information is performed by controlling the bit line by the rewrite circuit 21, but if the control of the word line is also necessary, a rewrite control circuit is also arranged on the word driver side.
  • a memory control circuit (MCONT) 23 connected to the control signal line CNTL performs overall control of the phase change memory 7.
  • FIG. 5 generally illustrates a more detailed configuration of the phase change memory 7.
  • a specific example of the control function of the memory control circuit 23 and the like is shown in detail for one I / O_0.
  • FIG. 6 illustrates main signal waveforms when the phase change memory 7 is read.
  • the read enable signal / RE in FIG. 5 is asserted to low level (Low).
  • the read power control signal rtransenb becomes Low, and start-up (generation or supply) of the read power (Vrtans) (not shown) is started.
  • the read active signal / RA is asserted to a low level after the power supply for reading rises. Thereby, the operation of the internal circuit of the reading system is started. If the setup time required for starting up the read power supply is not required, the read active signal / RA is not required, and the read enable signal / RE is asserted to the low level to The operation of the internal circuit may be started.
  • the power consumption of the read power supply outside the read period is reduced.
  • the type MOS transistors MNPD and MDC are turned off, and a pulse pcrd for precharging the bit line is generated.
  • a circuit (PCPGEN) for generating the pulse pcrd is also shown in FIG. 7, and the pulse pcrd is generated by the logical sum (OR logic) of the signal RA1 and its delay signal RA2.
  • the delay circuit DLY is constituted by the constant current circuit of FIG. 66, for example.
  • the pulse width can be varied by the selector SLC1.
  • the width can be changed by the output regout0 ⁇ 11:10> of the register REG, but the configuration for realizing the variable width is not limited to this. Further, the variable function may not be provided.
  • the pulse pcrd is connected to the gate of the p-channel MOS transistor MPC whose drain is connected to the sense input bit line sain at the subsequent stage of the bit line BLSA ⁇ 0>, and the bit line is supplied with the power supply voltage Vdd with the pulse pcrd generated earlier. Is charged.
  • the n-channel MOS transistor that receives the signal rtansg at its gate is controlled to be turned on by the read power supply Vrtransg that rises at the / RE low level.
  • the delay signal output RA2 output from the precharge generation circuit (PCPGEN) in FIG. 7 is input to the circuit (SLPGEN) also shown in FIG. 9, and the word line selection pulse READW and the sense latch clock (latch timing signal) SLACH Used for generation.
  • the PCPGEN in FIG. 7 and the SLPGEN in FIG. 9 constitute a timing generation circuit that generates the word line selection timing and the latch timing of the read data latch.
  • a word line line selection pulse READW is generated by a logical product (AND logic) of the signal RA2 and the delay signal RA3.
  • the delay circuit DLY is composed of the constant current circuit of FIG. The pulse width can be varied by the selector SLC2.
  • the width can be changed by the output regout0 ⁇ 9: 8> of the register REG and the output CENC ⁇ 1: 0> from the temperature sensor.
  • the latch timing of the sense latch circuit (Sense Latch) 30 can be changed corresponding to the temperature. Since the signal RA2 is changed from the low level to the high level, the word driver 15 drives the word line WL ⁇ i> to the high level which is the selection level based on the decode signal of the address input. Further, the delay signal RA3 becomes the clock signal SLACH of the sense latch circuit (Sense Latch) 30, and the output of the sense amplifier inverter (SAINV) 31 is latched in the sense latch circuit 30 by switching the RA3 from high level to low level.
  • the word line WL ⁇ i> is deselected.
  • the MOS transistors MNPD and MDC pulling down the bit line BLSA ⁇ 0> are turned on to discharge the remaining charges on the bit line.
  • the selected state of the Y switch circuit 18 is maintained until the timing at which the discharge with respect to the residual charge on the bit line can be completed.
  • the above readout system has the following operational effects.
  • the word line is deselected and the residual charge on the bit line is discharged from the bit line BLSA ⁇ 0> side that does not pass through the memory cell, thereby minimizing the discharge from the memory cell. It can be suppressed to the limit and can contribute to the suppression of the soft write to the memory cell (FIGS. 5 and 6).
  • the potential of the bit line BL is high if the threshold voltage (Vth level) of the memory cell is high after a certain time, and is low if the Vth level of the memory cell is low.
  • This state is determined by the sense amplifier circuit SA, and information is read by outputting the determination result.
  • the timing for determining the potential of the bit line BL is determined by the sense latch signal SLACH generated in the control unit.
  • the sense latch signal SLACH can be generated at an arbitrary timing according to the circuit diagram of FIG. 9, and the details thereof will be described later with reference to FIGS. 18 to 20.
  • the verify read is performed by changing this timing at the time of write verification. As a result, the Vth level of the memory cell can be arbitrarily determined.
  • FIG. 35 illustrates details of the read data system.
  • XDEC X decoder
  • WLD word line driving circuit
  • YDEC Y decoder
  • YSW Y switch circuit
  • SA sense amplifier
  • BLSW rewrite circuit
  • the n-channel MOS transistor YSWN of the Y switch circuit YSW has a low threshold MOS transistor so that a read operation can be performed without damaging the read memory cell current even at a low power supply voltage. Is adopted. Since the bit line voltage at the time of reading is about .about.0.3 V as will be described later, the potential of the bit line is transmitted to the sense amplifier SA via the MOS transistor YSWN. In the low power supply voltage operation, if the voltage applied to the gate of the MOS transistor YSWN becomes low, the ability necessary to pass the read memory cell current cannot be obtained. For example, if the threshold is lowered as illustrated in FIG.
  • the necessary current supply capability can be obtained with the same gate voltage, but if it is too low, leakage current becomes a problem, and it is necessary to take measures against this. Since the phase change memory 7 sets the bit line potential to 0 V during the standby operation, the leak path due to the low threshold MOS transistor does not occur, and the MOS transistor YSWN is within the allowable range of the operation specification during the write / read operation. Is set to a low threshold voltage. In order to obtain the current supply capability necessary for the NMOS transistor YSWN to pass the read current, there is a method of boosting the gate voltage of the MOS transistor YSWN, but in that case, a power supply circuit for boosting is provided. In order to increase the module area, the means for boosting the gate is not employed here, and the configuration described below is employed for the sense amplifier (SA) 16.
  • SA sense amplifier
  • the sense amplifier 16 includes a sense amplifier SA_a used in a normal read operation and a sense amplifier SA_b for measuring the resistance value of the phase change element resistance.
  • the sense amplifier SA_a is used for clamping the precharge level of the p-channel MOS transistor MPC for precharging the bit line BLSA, the n-channel MOS transistor MDC for discharging, the capacitor element CAP, and the global bit line BLSA to a desired voltage Vrpc. It comprises an n-channel MOS transistor MTRANS, a sense inverter 31 and a latch circuit (SALT) 30 that receives the sense inverter output.
  • SALT latch circuit
  • the purpose of clamping the precharge level of the global bit line BLSA to the desired voltage Vrpc (eg, 0.3 V) by the MOS transistor MTRANS is to prevent soft write due to continuous access to the same memory cell.
  • the voltage Vrtransg for clamping the voltage precharged by the MOS transistor MPC to a desired bit line precharge voltage Vrpc is applied to the gate of the MOS transistor MTRANS.
  • the voltage Vrtransg is desired to be a value at which the precharge voltage Vrpc becomes a constant value regardless of element variations and temperature variations.
  • the voltage Vrtransg is generated by a circuit shown in FIG. 61, for example. In FIG.
  • a voltage Vrpc_ref input to the comparator is a reference voltage corresponding to a target precharge voltage.
  • the n-channel MOS transistor M203 constitutes a current mirror circuit with the n-channel MOS transistor MTRANS.
  • MOS transistor MTRANS a low threshold MOS transistor is used for the same reason as the YSW MOS transistor YSWN.
  • the capacitive element CAP is a capacitive element that is positively added to reduce the influence of variations in parasitic capacitance from the bit line BL to the sense amplifier input sain on the amount of change in the bit line potential due to the read current.
  • the parasitic capacitances of the bit lines BL and BLSA and the sense amplifier input unit sain are Cbl and Csain, respectively, and the positively added capacitance is Cp.
  • the precharge voltage at the sense amplifier input section is the power supply voltage Vdd. At this time, the charge stored in the sense amplifier input section from the bit line is (Cbl ⁇ Vrpc) + (Csain ⁇ Vdd) + (Cp ⁇ Vdd).
  • FIG. 50 shows a circuit configuration example of the temperature sensor. Assuming that the operating temperature of the temperature sensor is T, the temperature sensor shown in the figure detects four temperature regions of T ⁇ T1, T1 ⁇ T ⁇ T2, T2 ⁇ T ⁇ T3, and T ⁇ T3. Note that T1, T2, and T3 are arranged in ascending order of temperature.
  • the temperature sensor includes a p-channel switch MOS transistor SWM, a p-channel constant current source MOS transistor IM, a bipolar transistor BIP, and three comparators CMP1 to CMP3.
  • the switch MOS transistor SWM, the constant current source MOS transistor IM, and the bipolar transistor BIP are connected in series.
  • connection wiring VOUT between the constant current source MOS transistor IM and the bipolar transistor BIP is one of the comparator CMP1, the comparator CMP2, and the comparator CMP3. Connected to the input terminal.
  • the other input terminals of the comparator CMP1, the comparator CMP2, and the comparator CMP3 are connected to the comparison potential V1, the comparison potential V2, and the comparison potential V3 that are used as a comparison reference, respectively.
  • the horizontal axis is the voltage of VOUT
  • the vertical axis is the current I
  • the drain-source current Ids of the constant current source MOS transistor IM and the collector-emitter current Ice of the bipolar transistor BIP are plotted.
  • the collector-emitter current Ice of the bipolar transistor BIP is plotted when the temperatures are T1, T2, and T3. Since the drain-source current Ids of the constant current source MOS transistor IM is a constant current source, it is constant regardless of temperature, and the collector-emitter current Ice of the bipolar transistor BIP is high when VOUT is the same voltage (T3 ) So much current flows.
  • VOUT at T ⁇ T1, T1 ⁇ T ⁇ T2, T2 ⁇ T ⁇ T3, T ⁇ T3 is shown in FIG. ⁇ T ⁇ T1 VOUT> V1 ⁇ T1 ⁇ T ⁇ T2 V1 ⁇ VOUT> V2 ⁇ T2 ⁇ T ⁇ T3 V2 ⁇ VOUT> V3 ⁇ T ⁇ T3 VOUT ⁇ V3 become.
  • FIG. 52 shows an example of the circuit configuration of the encoder, which encodes the output of the temperature sensor into 2 bits.
  • FIG. 53 shows a summary of VOUT, temperature sensor output, and encoder output at the temperature described above.
  • the temperature sensor and the other circuit may be directly connected, or an encoder may be inserted between the temperature sensor and the other circuit.
  • the bipolar transistor BIP in FIG. 50 may be a diode. Further, although the temperature region is divided into four, it is not limited to this. An example of using encoder outputs CENC ⁇ 0> and CENC ⁇ 1> will be described later.
  • the phase change memory 7 has a resistance measurement circuit that enables measurement of the resistance value of the phase change element PCR after rewriting. It is possible to measure the resistance value by directly applying voltage / current to the phase change element PCR from the outside, but there are many areas such as increased area due to the addition of a circuit to connect to the external terminal, and countermeasures for disturbance when measuring the resistance value
  • FIG. 62 illustrates a resistance measurement circuit (resistance value measurement sense amplifier) SA_b.
  • the gate of select MOS transistor CT of memory cell 11 is connected to word line WL, its source is connected to ground voltage Vss, and its drain is connected to bit line BL via phase change element PCR.
  • the node N0 of the bit line BL is connected to the drain of the MOS transistor whose signal Vrtransg is connected to the gate and the drain of the current source MOS transistor P1 from the p-channel where the signal Vgp is connected to the gate.
  • the node N0 is connected to one input terminal of the comparator CMP4, and the other input terminal of the comparator CMP4 is connected to the reference potential Vref.
  • the output Cout of the comparator CMP4 is input to the flip-flop FF, and the output of the flip-flop FF is out.
  • the NAND signal out and the signal regout0 ⁇ 7> are connected to the gate of the p-channel MOS transistor P0.
  • MOS transistor P0 serves as a switch for P1.
  • Vgp is generated by the power supply circuit 40, and its voltage value is controlled by the register output signal regout0 ⁇ 6: 1>.
  • a p-channel MOS transistor P2 in the monitor circuit 41 has a gate connected to Vgp, a source connected to Vdd, and a drain connected to a tester measurement pad PAD.
  • P1 and P2 are current mirrors of the same size, and the current flowing through P2 can be monitored from the PAD.
  • FIG. 63 shows an operation waveform of resistance measurement.
  • a current is passed from the MOS transistors P0 and P1 to the bit line BL with regout0 ⁇ 7>, out, WL at a high level and Vrtransg at a low level.
  • the current value of the MOS transistor P1 is controlled by regout0 ⁇ 6: 1>, and the reference voltage Vref is set to a voltage value that does not cause rewriting of the phase change element.
  • the potential of the bit line BL rises.
  • the comparator CMP4 When the potential of the bit line BL becomes higher than the reference voltage Vref, the comparator CMP4 operates, the signal Cout changes from the high level to the low level, is taken into the flip-flop FF, and is reflected on out.
  • the potential of the bit line BL is the same as the reference voltage Vref, and if the current flowing through the MOS transistor P1 is clear, the resistance value of the phase change element PCR can be obtained by calculation. Since the MOS transistors P1 and P2 are current mirrors, the current flowing through the MOS transistor P1 (current flowing through the bit line BL) can be known by externally monitoring the current of the MOS transistor P2 from the pad PAD.
  • the resistance measurement circuit SA_b contributes to the realization of the following functions. For example, it is possible to realize a verify function that determines a resistance value of a memory cell during a rewrite sequence and performs rewrite again according to the resistance value. Alternatively, it is a refresh function that determines a resistance value when an arbitrary time has elapsed after rewriting of the memory cell, and rewrites again according to the resistance value. In addition, it can be used for measurement of parasitic resistance of wiring.
  • regout0 ⁇ 6: 1> is set to low level, Vgp is set to high level, and MOS transistor P1 is turned off.
  • a voltage equal to the reference voltage Vref is applied to the pad PAD.
  • each of the output out, the word line WL, and regout0 ⁇ 7> is set to the high level, and the voltage Vrtransg is set to the low level.
  • the register value regout0 ⁇ 6: 1> is incremented, the voltage value of Vgp decreases, the current flowing from the transistor P1 increases, and the potential of the bit line BL increases.
  • the bit line BL is gradually shifted from a low voltage to a high voltage to prevent disturbance to the memory cell.
  • FIG. 64 shows another example of the resistance measurement circuit SA_b.
  • One input of the amplifier AMP1 receives the potential of the bit line BL, and the reference voltage Vref is applied to the other input terminal.
  • the drain of a p-channel current source MOS transistor P12 that receives the output Cout of the amplifier AMP1 at its gate is connected to the bit line BL.
  • the output Cout of the amplifier AMP1 is connected to the drain of the p-channel type output Cout fixing MOS transistor P14 connected to the gate of the signal regout0 ⁇ 7> and the gate of the p-channel type MOS transistor P13 having the same size as P12. ing.
  • the MOS transistors P12 and P13 form a current mirror whose source is connected to the power supply voltage Vdd and whose gate is common.
  • the drain of the MOS transistor P13 is connected to Dout.
  • Dout is connected to the drain of an n-channel MOS transistor N11 that receives a signal Vgn at its gate, the drain of an n-channel MOS transistor N13 for fixing Dout that receives a signal regout0 ⁇ 7> n at its gate, and the input terminal of an inverter INV1.
  • the output of the inverter INV1 is out.
  • Vgn is generated by the power supply circuit 42, and its voltage value Vgn is controlled by a signal regout0 ⁇ 6: 1>.
  • N12 is an n-channel MOS transistor having the same size as N11, Vgn applied to the gate, the source connected to Vss, and the drain connected to the tester measurement pad PAD.
  • the MOS transistors N11 and N12 are current mirrors, and can monitor the current flowing from the pad PAD to the MOS transistor N12, that is, the current flowing to N11, in other words, the current flowing to P12.
  • the voltage of Dout decreases and out changes from low level to high level.
  • the current of the transistor N11 at this time can be known by monitoring the current of the transistor N12. Since the current of the transistor N11 is equal to that of the transistor P13 and the currents of the transistors P13 and P12 are also equal, the current flowing through the phase change element 11 I understand.
  • the potential of the bit line BL is the reference voltage Vref, and the resistance value can be obtained using the above calculation formula. Since the voltage of the bit line BL becomes the reference voltage Vref, the memory cell is not disturbed.
  • FIG. 65 illustrates an operation waveform using the resistance measurement circuit of FIG.
  • regout0 ⁇ 6: 1> is set to a low level, and the voltage Vgn is set to a low level.
  • the reference voltage Vref is applied to the pad PAD and the current value is measured.
  • the word line WL and the register value regout0 ⁇ 7> are set to the high level and the voltage Vrtransg is set to the low level, a current flows into the bit line BL, and the voltage value of the bit line BL becomes the same as the reference voltage Vref.
  • a delay circuit is used for generation of memory cell read / write timing, for example, adjustment of the precharge time of the bit line BL and the operation timing of the sense amplifier.
  • the delay circuit generally uses a gate of an inverter or the like, charge / discharge to a capacitor, etc., and the delay time is determined by a charge / discharge current value. Since the current value of the MOS constituting the inverter fluctuates due to manufacturing variations, temperature changes, etc., the delay time also fluctuates. Therefore, the phase change memory 7 employs a delay circuit that suppresses variations in charge / discharge current values to the capacitors and reduces delay variations by operating the inverter at a constant current value.
  • FIG. 66 shows an example of a delay circuit.
  • the input terminal is in, and the output terminal is out.
  • the p-channel MOS transistor P6 whose input terminal in is connected to the gate has a source connected to Vdd and a drain connected to the source of the p-channel constant current MOS transistor P5.
  • the gate of P5 is connected to Vgp, and the drain is connected to the output terminal out.
  • the n-channel MOS transistor N6 whose input terminal in is connected to the gate has a source connected to Vss and a drain connected to the source of the n-channel constant current MOS transistor N5.
  • the gate of the MOS transistor N5 is connected to Vgn, and the drain is connected to the output terminal out.
  • Vgp and Vgn are arbitrary voltage values that compensate for manufacturing variations and current value variations due to temperature changes, and are set so that the currents of P5 and N5 are equal. Since the charge / discharge current value to the capacity of the output terminal out becomes constant regardless of manufacturing variations and temperature changes, the delay time of the output terminal out with respect to the input terminal in becomes equal. In this configuration, the delay time can be adjusted by adjusting Vgp and Vgn. For example, for a normal read operation, the delay time can be changed in the test mode and used for checking the operation margin.
  • FIG. 67 illustrates a circuit configuration using a plurality of delay circuits DLY of FIG. This is an example using current trimming described in JP-A-2004-164700.
  • P7 is a p-channel MOS transistor
  • N6 is an n-channel MOS transistor
  • Vref is a reference potential
  • Vgn is a gate potential of N7
  • Vgp is an output of the amplifier AMP2.
  • N7 is a constant current source controlled by Vgn.
  • the amplifier AMP2 controls P7 so that the node A (nodeA) has the same potential as the reference voltage Vref.
  • N7 is a constant current source, a constant current flows through P7 connected via node A.
  • Vgn compensates for manufacturing variations and current value variations due to temperature changes, the delay circuit DLY of FIG. 66 in which the gates of P7 and N7 are connected in common also operates at a constant current, and delay time variations are reduced. can do.
  • FIG. 17 shows main operation waveforms in the verify read operation.
  • the verify read signal / VR shown in FIG. 5 is asserted to low level.
  • the read power control signal rtransenb becomes low level, and the read power is turned on.
  • Read active / RA is asserted low after the power supply for reading rises. Thereby, the internal circuit operation is started. If the setup time required for starting up the power supply for reading is not required, / VRRA and / RA may be asserted to the low level at the same time.
  • VR1 is high level (negate), so the CENC ⁇ 0> and CENC ⁇ 1> inputs from the temperature sensor are invalid, and the output RA3 is output by the regout0 ⁇ 8> and regout0 ⁇ 9> inputs from the register REG. Is determined as one of a to d.
  • the register REG can be set from outside the phase change memory 7.
  • the signal VR1 goes low, the inputs regout0 ⁇ 8> and regout0 ⁇ 9> from the register REG become invalid, and the output RA3 is delayed by the inputs CENC ⁇ 0> and CENC ⁇ 1> from the temperature sensor.
  • the application of the method of changing the word line selection pulse width and the sense latch clock timing with temperature dependence is not limited to the verify read operation, and may be applied during normal read. If the temperature characteristics are not required for the word line selection pulse width and the sense latch clock timing, the selector input from the temperature sensor is unnecessary, and if the change is not required, the selector is not required and the delay circuit DLY is used alone. Good.
  • the verify read operation is started by asserting the read active signal / RA to the low level as in the normal read, and the word line selection pulse width and the sense latch clock timing are changed as described above. The operation until the read data is stored in is the same as the normal read.
  • the NOR logic of the output EOR ⁇ n: 0> obtained by taking the EOR logic of the read data stored in the sense latch 30 of each I / O and the write data signal dinn_0 of each I / O is verified latch output buffer (Verify Latch OUT BUF) 50 input data.
  • Verify Latch OUT BUF verified latch output buffer
  • FIG. 18 shows an example of a circuit that can simultaneously verify and read high data (data at high resistance) and low data (data at low resistance).
  • 21 and 22 illustrate the truth values of the selectors S1, S2 ⁇ n> in FIG. 19 shows main operation waveforms at the time of normal reading of FIG. 18, and
  • FIG. 20 shows main operation waveforms at the time of verify reading of the circuit of FIG.
  • the circuit operation starts when the signal / VR is at a high level and the signal / RA is asserted at a low level. Since the signal VR1 is at the high level, the signal read having the intermediate delay time is selected as the input of the selectors S1 and S2 ⁇ n>. Based on this signal read, the signal rdltenb ⁇ n> serving as the clock of the sense latch 30 becomes high level, the output of the sense amplifier inverter 31 is stored in the sense latch 30, and the word line WL ⁇ 0> falls. Next, at the time of verify reading, as shown in FIG. 20, the circuit operation starts when the signal / VR is in the low level state and the signal / RA is asserted at the low level.
  • the signal VR1 Since the signal VR1 is at a low level, the signal vrfyrst having the longest delay time is selected as the input of the selector S1. Accordingly, as shown in FIG. 20, the word line WL ⁇ 0> is stored in the word line WL ⁇ 0> after the sense latch 30 stores the high data (data at the time of high resistance) at the time of the verify read with the slowest clock timing of the sense latch 30. ⁇ 0> falls. On the other hand, when a high level is input to Din ⁇ 0>, din0 ⁇ 0> is at a high level and signal VR1 is at a low level, so the delay time is the longest as the output rdltenb ⁇ 0> of selector S2 ⁇ 0>.
  • the signal vrfyrst is selected, the latch timing of the sense latch 30 is the latest, and high data can be determined strictly.
  • the signal vrfyset that has the shortest delay time as the output rdltenb ⁇ 1> of the selector S2 ⁇ 1> Is selected, and the latch timing of the sense latch 30 becomes the earliest, so that the raw data can be determined strictly.
  • a function for making the pulse width temperature dependent may be added as shown in FIG.
  • Verify read can be realized by changing the sense latch timing.
  • the latch timing can be set later than usual for high data (data at high resistance), and the latch timing can be set earlier than normal for low data (data at low resistance) (FIG. 9, FIG. 8, FIG. 17, FIG. 18, FIG. 20, FIG. 21, FIG. 22).
  • the sense latch timing can be changed in accordance with the temperature characteristics of the resistance value of the memory cell (FIGS. 9 and 18).
  • FIG. 25 shows an example of a 2 row ⁇ 16 bit register REG.
  • reg ⁇ 0>, reg ⁇ 1> are address inputs
  • DINREG ⁇ 15: 0> are write data inputs
  • regout ⁇ 15: 0> are register outputs, connected to the output buffer of RFIDMDL1, and can be output outside of RFIDMDL1 It is.
  • regout0 ⁇ 15: 0> and regout1 ⁇ 15: 0> are also outputs of the registers, but are connected to the inside of RFIDMDL1.
  • FIG. 26 shows an example of the YDEC 22
  • FIG. 27 shows an example of the XDEC 14.
  • the address space of the register is assumed to be 111111xx to 111110xx, for example.
  • FIG. 28 illustrates an operation waveform at the time of register reading.
  • the register REG can be accessed by setting the address to 111111xx or 111110xx. Further, by asserting the signal / REG to the low level, the signal rdoutenb becomes the low level, and the logical product (AND logic) output SENOUT2 with the output rdout ⁇ n: 0> of the sense latch 30 becomes the low level. Also, by asserting the signal / REG to low level, the signal regotenb becomes high level, and the logical product (AND logic) output REGOUT2 with the output regout ⁇ 15: 0> from the register REG becomes regout ⁇ 15: 0> Value.
  • the output Do_0 is composed of OR logic of SENOUT2, REGOUT2, and TSTOUT. Since SENOUT2 and TSTOUT are at a low level, the output regout ⁇ 15: 0> from the register is output.
  • FIG. 29 shows an operation waveform at the time of register writing.
  • the register can be accessed by setting the address to 111111xx or 111110xx. Further, by asserting the signal / REG to a low level, the output signals of the write control input / WE and write data input Din_ ⁇ 15: 0> are not transmitted to the phase change memory array 10, and only the signal WEREG and data DINREG are sent to the register REG. Sent and written as ⁇ 15: 0>.
  • FIG. 30 illustrates the function of the register REG.
  • regout0 ⁇ 15:12> is input to the power supply circuit of FIG. 47, and the voltage VBL can be changed by the register value.
  • regout0 ⁇ 11:10> is input to the precharge pulse generation circuit (PCPGEN) in FIG. 7, and the precharge pulse width can be changed by the register value.
  • regout0 ⁇ 9: 8> is input to the word line selection / sense latch pulse generation circuit (SLPGEN) in FIG. 9, and the word line selection time / sense latch timing can be changed by the register value.
  • regout0 ⁇ 7> controls activation / deactivation of the resistance measurement circuit SA_b in FIGS. 62 and 64, and switches between the resistance value measurement mode and the normal read mode.
  • regout0 ⁇ 6: 1> is a code for controlling the gate potential of the resistance measurement circuit SA_b in FIGS.
  • Regout1 ⁇ 15> switches the control of the word line and bit line during writing between pulse control and DC control. For example, when performing a stress test, it is more effective to leave the word lines and bit lines in the write state in DC rather than pulses, and use this function.
  • FIG. 31 shows main operation waveforms. Even if the write pulse is not input to Wreset ⁇ 15: 0>, by rewriting register regout1 ⁇ 15> from “0” to “1” and setting regout1 ⁇ 15> n to “0”, Wreset0_0 to Wreset15_0 It becomes “0”, and the word line and bit line are in the write state. While the value of the register regout1 ⁇ 15> is set to “1”, the word line and the bit line are maintained in the write state.
  • Regout1 ⁇ 14:13> will be explained. As described above, writing is performed by serial control for each 1 bit. For example, a multi-bit simultaneous writing function is required for speeding up the writing operation, but this is achieved by register regout1 ⁇ 14:13>. .
  • An example of the relationship between the value of the register regout1 ⁇ 14:13> and the number of simultaneous multi-bit writes is shown in FIG.
  • FIG. 33 shows an example up to 8-bit simultaneous writing, the number of bits that can be simultaneously written is not limited.
  • FIG. 34 shows combinations of I / O written simultaneously.
  • FIG. 32 shows an example of a circuit (MULTIT) that realizes the multi-bit simultaneous writing function.
  • each I / O write pulse generator is combined and input to the selector, and the output of the I / O write pulse generator selected by the register regout1 ⁇ 14:13> output signal is used as the bit line control signal BLVP ⁇ n>.
  • I / O parallel number that enables write operation in synchronization with one write pulse / WP can be selected as x1, x2, x4, x8, and write test operation is efficient. It is possible to select Of course, the same write data is supplied to the I / Os operated in parallel.
  • regout1 ⁇ 12: 9> is input to the circuit of FIG. 47 and controls the monitoring of the reset pulse, set pulse, word line potential, and bit line potential at the external terminals.
  • regout1 ⁇ 8: 7> is input to the circuit of FIG. 14, and the reset pulse width can be changed.
  • regout1 ⁇ 6: 5> is input to the circuit of FIG. 47, and the word line potential at the time of reset writing can be changed.
  • regout1 ⁇ 4: 3> an inversion signal is input to the circuit of FIG. 36, and all word lines are selected, all not selected, and disabled.
  • regout1 ⁇ 2: 1> an inversion signal is input to the circuit of FIG. 38, and all selection, all non-selection, and invalidity of the Y switch are controlled.
  • the pulse width, word line potential, and bit line potential at the time of writing can be changed depending on the temperature, and it can correspond to the temperature characteristics of the writing condition of the memory cell. it can.
  • thermal disturbance can be suppressed during simultaneous writing (FIGS. 34, 5, and 32).
  • ⁇ Phase change memory write control system The writing of the memory cell will be described. Although not particularly limited, the random write operation is written in 1-bit units.
  • the shift register illustrated in FIG. 5 is used to realize writing in 1-bit units. A detailed example of the shift register is shown in FIG.
  • the write enable signal WE1 controls the initialization of the shift register 60
  • the write pulse signal WP1 is a write signal for the phase change memory 7.
  • Q0_0 to Q15_0 are 16-bit I / O in this example, and are output as write signals to each I / O.
  • FIG. 11 shows operation waveforms of the shift register 60.
  • the signal WE1 in FIG. 10 is switched to the low level, whereby the initialization of the shift register 60 is started.
  • each signal is changed as shown in FIG. 11, and the outputs Q0_0 to Q15_0 of the shift register 60 become high level, and the initialization is completed.
  • FIG. 12 shows operation waveforms from the write input signal to the output of the write pulse generation circuit (WPGEN).
  • FIG. 15 shows operation waveforms from the output of the write pulse generation circuit (WPGEN) to the word line and bit line.
  • Each figure shows an example of writing low data to I / O ⁇ 0> and writing high data to I / O ⁇ 1>.
  • FIG. 13 illustrates a write pulse generation circuit (WPGEN) also shown in FIG.
  • the delay circuit WPDLY is configured by the constant current circuit described with reference to FIG. 66, for example.
  • Q0_0 becomes low level when the first signal / WP is asserted low, and the first pulse Wreset0_0 is generated by the logical sum (OR logic) of Q0_1 and its delayed signal Q0_6.
  • the circuit configuration of FIG. 14 may be employed for the delay circuit WPDLY.
  • the delay circuit DLY formed of a constant current circuit and the selector SLC3 may be used.
  • the Wreset0_0 pulse width can be changed by the trimming value and the register value by the signals trm0 and trm1 from the trimming circuit and the signals regout1 ⁇ 7> and regout1 ⁇ 8> from the register circuit 60.
  • the number of inputs / outputs of the selector SLC3 is not limited.
  • the second pulse Wset0_0 is generated by the OR logic of the signals Q0_3 and Q0_4 in the previous stage of Q0_6, the signal din0_0 from the write data, and the signal from / WP.
  • the pulse width of Wreset0_0 can be changed by the delay circuit WPDLY, and the pulse width of Wset0_0 can be changed by the external signal / WP.
  • the Wreset0_0 pulse and the Wset0_0 pulse can overlap, and when a gap occurs between both pulses, the gap becomes wlmode1 (this signal is in the high level period (Which defines the word line driving period) to affect the write characteristics.
  • FIG. 16 shows an example in which a gap is generated between both pulses without overlap. If a gap occurs in wlmode1, WL ⁇ 0> is in the Hi-Z (high impedance) state for the gap, and stable writing cannot be performed.
  • the pulse generated by the write pulse generation circuit controls the word line WL ⁇ n> and the rewrite circuit BLSW ⁇ n>.
  • Wreset0_2 whose pulse width is reduced (shrinked) is generated by an AND circuit ANDW that takes a logical product by making the low level input of the first pulse Wreset0_0 and its delayed signal Wreset0_1 active.
  • Wset0_2 whose pulse width is shrunk by the second pulse Wset0_0 and its delayed signal Wset0_1 is generated. From these two signals, W0_1, W0_2, and W0_4 are generated by the circuit of FIG.
  • W_or is obtained by OR logic (logical sum) of outputs W0_1 to W15_1 from each I / O
  • wlmode2 is obtained by OR logic of Wset0_2 to Wset15_2
  • wlmode3 is generated by the OR logic of W0_3 to W15_3
  • wlmode4 is generated by the AND logic of W0_4 to W15_4.
  • the signal wlmode1, the signal wlmode2, the signal wlmode3, and the signal wlmode4 generated by the OR logic of W_or and the read system control signal READW are input to the word line drive circuit (WLD) 15 as shown in FIG.
  • WLD word line drive circuit
  • the first half waveform of the word line WL ⁇ 0> of FIG. 15 is the word line selection waveform output by the pulses generated by the first pulse Wreset0_0 and the second pulse Wset0_0, and the second half waveform is generated by the first pulse Wreset1_0. It is a word line selection waveform output by a pulse.
  • the bit line control signal BLVP Generate ⁇ 0> and BLVN ⁇ 0>.
  • An n-channel MOS transistor MNPD having BLVN ⁇ 0> as a gate input and a drain connected to the global bit line BLSA ⁇ 0> is controlled by a logical product signal of the signal wyin ⁇ 0> and the read system signal BLPD.
  • the p-channel MOS transistor MPPC is for supplying a write current to the bit line BL
  • the n-channel MOS transistor MNPD is a discharge circuit for the bit line BL after writing.
  • the pulse widths of the bit line control signals BLVP ⁇ 0> and BLVN ⁇ 0> are expanded by taking the logical product of Wreset0_0, Wreset0_1, Wset0_0, and Wset0_1.
  • BLSA ⁇ 0> and BL ⁇ 0> indicate bit line line waveforms output by signals generated based on the first pulse Wreset0_0 and the second pulse Wset0_0
  • BLSA ⁇ 1> and BL ⁇ 0 1> shows a bit line waveform output by a signal generated based on the first pulse Wreset1_0 and the second pulse Wset1_0.
  • the signal for generating the word line drive signal key signal
  • the setup time (set) up) and hold time (hold) of the word line drive are secured.
  • the key control signal width can be shrunk and the key control signal width can be expanded to ensure the setup time and hold time of the key control signal. , All of the key control signals can be effectively supplied (FIGS. 5, 12, and 15).
  • a large number of memory cells 11 (MM ⁇ 0,0> to MM ⁇ x, n (y + 1) + y>) are arranged in a matrix.
  • the phase change element PRC and the selection MOS transistor CT are connected in series, and the phase change element PRC is connected to the bit line BL.
  • the source of the memory cell 11 is connected to the ground voltage Vss.
  • the X decoder (XDEC) 14 selects one of Xadd ⁇ 0> to Xadd ⁇ x> according to the input address.
  • the word line drive circuits WLD ⁇ 0> to WLD ⁇ x> have the circuit configuration shown in FIG. 36 and are commonly connected to the wiring VX.
  • the power supply voltage Vdd and analog switch are connected to the wiring VX via a P-channel MOS transistor PM0.
  • a power source Vreset and a capacitor C are connected via SW0.
  • the feature of this configuration is that two kinds of voltages can be applied to the word line WL, and since the analog switch SW0 is provided, it is possible to cope with the case where the power supply Vreset is at a low voltage. Next, the capacity is shared, which has the effect of reducing the area.
  • the MOS transistor PM0, the analog switch SW0, and the capacitor C are each one, but they may be arranged in units of a plurality of word line drive circuits WLD.
  • the word line driving circuit WLD includes an n-channel type constant current source MOS transistor XI0 as shown in FIG. 36, and the constant current source MOS transistor XI0 is normally used in a logic circuit or the like. Longer gate length is preferable than MOS transistor. The reason is to suppress current variation due to gate length variation.
  • the wiring VX and the word line WL are connected by an analog switch XSW0. The reason for connecting with the analog switch XSW0 is that the voltage changes from 1.5V to 0V, for example, when the charge charged in the capacitor C is extracted by the constant current source NMOS transistor XI0, so a transfer capability of 1.5V to 0V is required That's why.
  • all the word lines WL can be selected by regout1 ⁇ 4> _n which is an inverted signal of regout1 ⁇ 4>, and all the word lines WL can be unselected by regout1 ⁇ 3> _n which is an inverted signal of regout1 ⁇ 3>. .
  • These functions can be used for tests such as disturb.
  • the Y switch 18 (YSW ⁇ 0> to YSW ⁇ n>) is connected to bit lines BL ⁇ 0> to BL ⁇ n (n) by an n-channel MOS transistor YSWN and a p-channel MOS transistor YSWP. y + 1) + y> and BLSA ⁇ 0> to BLSA ⁇ n> are selectively connected.
  • YB is an inverted signal of YT, and when YB is H (high level), that is, when the bit lines BL and BLSA are not connected, the bit line BL is fixed to the ground voltage Vss by the MOS transistor BLDIS. .
  • the Y decoder 22 selects one of Yadd ⁇ 0> to Yadd ⁇ y> according to the input address.
  • Y drivers YD ⁇ 0> to YD ⁇ y> select YT and YB according to Yadd as shown in FIG.
  • the Y switch is selected.
  • YB is an inverted signal of YT.
  • all Y switches can be selected by regout1 ⁇ 2> _n which is an inverted signal of regout1 ⁇ 2>, and all Y switches can be unselected by regout1 ⁇ 1> _n which is an inverted signal of regout1 ⁇ 1>.
  • the rewrite circuit 21 (BLSW ⁇ 0> to BLSW ⁇ n>) outputs the voltages VBL, VSS, and OPEN to BLSA by BLVP and BLVN.
  • SA ⁇ 0> to SA ⁇ n> are read sense amplifiers 16.
  • the configuration of the current switching circuit 75 is shown in FIGS.
  • the current flowing through the constant current source NMOS transistor XI0 of FIG. 36 can be changed by switching I ⁇ 0> to I ⁇ m>.
  • the configuration includes a reference mirror Iref, NI ⁇ 0> to NI ⁇ m>, a current mirror of an n-channel constant current source MOS transistor XI0, and analog switches ASW ⁇ 0> to ASW ⁇ m>.
  • the gate widths of NI ⁇ 0> to NI ⁇ m> are different.
  • FIG. 41 shows a simple circuit configuration with one type of current.
  • the set / reset pulse generation circuit 76 follows WP1, Din ⁇ n: 0> according to wlmode1, wlmode2, wlmode3, wlmode4, regout1 ⁇ 1> _n to regout1 ⁇ 4> _n, BLVP ⁇ 0> to BLVP ⁇ n>, BLVN Generate ⁇ 0> to BLVN ⁇ n>.
  • FIG. 43 shows an operation sequence realized by the set / reset pulse generation circuit 76.
  • FIG. 43 shows a case where set data is written to the memory cell MM ⁇ 0,0> and reset data is written to the memory cell MM ⁇ 0, y + 1>.
  • the set / reset pulse generation circuit 76 When writing set data to memory cell MM ⁇ 0,0>, input H (high level) to WP1 and L (low level) to Din ⁇ n>. With WP1 and Din ⁇ n: 0>, the set / reset pulse generation circuit 76 generates wlmode1 to wlmode4, BLVP ⁇ 0> to BLVP ⁇ n>, and BLVN ⁇ 0> to BLVN ⁇ n> as shown in FIG. . The rewrite circuit BLSW ⁇ 0> applies 1.5V to the bit line BL ⁇ 0> when the VBL voltage is set to 1.5V by BLVP ⁇ 0> and BLVN ⁇ 0>.
  • the word line drive circuit WLD ⁇ 0> is turned on by the wlmode1, wlmode2, and wlmode3 so that the PMOS transistor PM0 is turned on, the analog switch XSW0 is turned on, the MOS transistor XN0 is turned off, and the word line WL ⁇ 0> is turned on, for example, 1.5V To charge. Thereafter, in the period t2-t3, the MOS transistor PM0 is turned off and the MOS transistor XISW0 is turned on, and the charge charged in the capacitor C and the word line WL ⁇ 0> is extracted by the constant current source MOS transistor XI0.
  • the voltage transition at the time of extraction has a constant slope because of the constant current, and the extraction time (gradient of the slow cooling pulse) is determined by the current value of the constant current source MOS transistor XI0.
  • the set / reset pulse generation circuit 76 When writing reset data to memory cell MM ⁇ 0, y + 1>, input H to WP1 and L to Din ⁇ n-1>. With WP1 and Din ⁇ n: 0>, the set / reset pulse generation circuit 76 generates wlmode1 to wlmode4, BLVP ⁇ 0> to BLVP ⁇ n>, and BLVN ⁇ 0> to BLVN ⁇ n> as shown in FIG. .
  • the rewrite circuit BLSW ⁇ 1> applies 1.5V to the bit line BL ⁇ y + 1> when BLBL ⁇ 1> and BLVN ⁇ 1> set the VBL voltage to 1.5V, for example.
  • the wiring VX is controlled to 1.0 V by wlmode3 and wlmode4, the MOS transistor PM0 is turned off, and the analog switch SW0 is turned on.
  • the word line driving circuit WLD ⁇ 0> charges the word line WL ⁇ 0> to, for example, 1.0 V by turning on the analog switch XSW0 and turning off the MOS transistor XN0 in the period t4-t5 by wlmode1 and wlmode2. Thereafter, the analog switch XSW0 is turned off, the MOS transistor XN0 is turned on, and the charge charged in the word line WL ⁇ 0> is extracted. The extraction time is determined by the current value of the MOS transistor XN0.
  • the current value of the constant current source MOS transistor XI0 is changed to the current value of the MOS transistor XN0 in FIG. Set smaller compared.
  • the fall time of the word line WL when writing set data depends on the value of the current flowing through the constant current source NMOS transistor XI0 that draws this charge because the amount of charge charged in the capacitor C and the word line WL is constant. That is, the fall time of the word line WL can be arbitrarily set by changing the current flowing through the constant current source NMOS transistor XI0 by switching I ⁇ 0> to I ⁇ m> of the current switching circuit of FIG. For example, as shown in FIG.
  • FIG. 42 shows a configuration example in the case where I ⁇ 0> to I ⁇ m> switching of the current switching circuit of FIG. 40 is switched by a temperature sensor.
  • the configuration of the temperature sensor 80 is FIG. 50
  • the configuration of the encoder 81 is FIG. 52
  • the information from the temperature sensor 80 is converted into a 2-bit signal by the encoder 81 as shown in FIG.
  • the 2-bit signals CENC ⁇ 0> and CENC ⁇ 0> are transmitted to CENC_LAT ⁇ 0> and CENC_LAT ⁇ 1> by the flip-flop 82 when the rewrite signal WE1 falls from H to L, and the values are held.
  • the CENC_LAT ⁇ 0> and CENC_LAT ⁇ 1> are decoded by the decoder 83, and the temperature information is input to the current switching circuit 75.
  • the reason why the flip-flop 82 is inserted between the encoder 81 and the decoder 83 is to prevent value fluctuations of I ⁇ 0> to I ⁇ m> due to temperature fluctuations during rewriting. As a result, since the values of I ⁇ 0> to I ⁇ m> during rewriting are fixed, there is no fluctuation in the fall time of the word line WL, and stable setting is possible.
  • FIG. 47 shows a configuration example of a power supply circuit that supplies the voltage Vreset and the voltage VBL.
  • the power supply circuit includes a step-down power supply ⁇ 0> 90, a step-down power supply ⁇ 1> 91, and voltage and pulse monitoring switches MSW ⁇ 0> to MSW ⁇ 3>.
  • the step-down power supply ⁇ 0> 90 is a power supply circuit that generates a voltage Vreset based on the reference voltage Vrefp, and has a function of changing the voltage Vreset by regout1 ⁇ 6: 5>. This voltage changing function is used for trimming, verifying, testing, and the like.
  • Step-down power supply ⁇ 1> 91 is a power supply that generates voltage VBL based on reference voltage Vrefp, and has a function of changing voltage VBL by regout0 ⁇ 15:12>. This voltage changing function is used for trimming, verifying, testing, and the like.
  • Vreset is connected to the external terminal via voltage and pulse monitor switch MSW ⁇ 0>, and the monitor enable / disable can be controlled by regout1 ⁇ 10>.
  • VBL is connected to the external terminal via the voltage and pulse monitor switch MSW ⁇ 1>, and the monitor enable / disable can be controlled by regout1 ⁇ 9>.
  • Wreset0_2 is connected to the external terminal via the voltage and pulse monitor switch MSW ⁇ 2>, and the monitor enable / disable can be controlled by regout1 ⁇ 12>.
  • Wset0_2 is connected to an external terminal via the voltage and pulse monitor switch MSW ⁇ 3>, and monitor enable / disable can be controlled by regout1 ⁇ 11>.
  • the optimum temperature for crystallization of the phase change element varies due to process variations. This variation can be suppressed by using the slow cooling pulse described above.
  • FIG. 49 shows the word line voltage and the phase change element temperature when the word line is a slow cooling pulse.
  • the phase change element is cooled rapidly, so that the fall time of the word line needs to be sufficiently faster than the set.
  • the capacitor C is disconnected from the word line WL by the switch XSW0 in FIG. Therefore, the size of the extraction MOS transistor XN0 can be reduced. Since the capacitor C is shared by the drive circuits WLD ⁇ 0> to WLD ⁇ x> in units of word lines, it is possible to contribute to the reduction of the occupied area.
  • FIG. 54 shows a phase change memory 7A that employs memory cells in which select transistors are arranged in parallel.
  • Non-volatile memory cells 11A MM ⁇ 0,0> to MM ⁇ x, n (y + 1) + y>
  • a phase change element PCR and n-channel type selection MOS transistors CT1 and CT2 are connected in series, and a phase change element is connected to the bit line BL.
  • Two selection MOS transistors CT1 and CT2 are connected in parallel, and the gates of the selection MOS transistors CT1 and CT2 are connected to independent word lines WLA and WLB, respectively.
  • Four or more selection MOS transistors CT1 and CT2 may be connected in parallel.
  • the source of the memory cell 11A is connected to the ground voltage VSS.
  • the X decoder (XDEC) 14 selects one of Xadd ⁇ 0> to Xadd ⁇ x> according to the input address.
  • WLDA ⁇ 0> to WLDA ⁇ x> and WLDB ⁇ 0> to WLDB ⁇ x> are word line drive circuits, and the circuit configuration is illustrated in FIG.
  • the word line drive circuits WLDA and WLDB are commonly connected to the wiring VX.
  • the power supply voltage Vdd is connected to the wiring VX via the p-channel MOS transistor PM0 and the power supply Vreset is connected to the wiring VX via the analog switch SW0. ing.
  • the feature of this configuration is that two types of word line drive voltages can be applied to the word lines WLA and WLB, and since the analog switch SW0 is provided, it is possible to cope with a case where the power supply Vreset is at a low voltage.
  • one MOS transistor PM0 and one analog switch SW0 are provided, but they may be arranged in units of a plurality of word line drive circuits WLDA and WLDB.
  • the wiring VX and the word lines WLA and WLB are connected by an analog switch XSW0.
  • the reason for connecting with the analog switch XSW0 is to cope with the case where the power supply Vreset is at a low voltage. If the power supply Vreset is not a low voltage, only the P channel type MOS transistor may be used.
  • WLMODE0 is connected to the word line drive circuit WLDA
  • WLMODE1 is connected to the word line drive circuit WLDB. Therefore, the word lines WLA and WLB can be independently controlled by WLMODE0 and WLMODE1. Further, all the word lines WLA and WLB can be selected by XALLS, and all the word lines WLA and WLB can be completely unselected by XUNS. These functions can be used for tests such as disturb.
  • YSW ⁇ 0> to YSW ⁇ n> are Y switches.
  • the circuit configuration is the same as in FIG.
  • the Y decoder (YDEC) 22 selects one of Yadd ⁇ 0> to Yadd ⁇ y> according to the input address.
  • YD ⁇ 0> to YD ⁇ y> are Y drivers.
  • the circuit configuration is the same as in FIG. BLSW ⁇ 0> to BLSW ⁇ n> are rewrite circuits (21), and the circuit configuration is the same as in FIG. SA ⁇ 0> to SA ⁇ n> are read sense amplifiers (16).
  • WLMODE0, WLMODE1, WLVMODE0, WLVMODE1, XUNS, XALLS, regout1 ⁇ 1> _n, regout1 ⁇ 2> _n, BLVP ⁇ 0> to BLVP ⁇ n>, BLVN ⁇ 0> to BLVN ⁇ n> are rewrite modes, RESETMODE, It is generated by the set / reset pulse generation circuit 70 in accordance with SETMODE. RESETMODE and SETMODE are generated by the set / reset signal generation circuit 71 according to the rewrite data.
  • FIG. 56 illustrates the operation timing of the phase change memory 7A.
  • FIG. 56 shows the set data (logical value 1 data write, low resistance) in the memory cell MM ⁇ 0,0>, and the reset data (logical value 0 data write, high resistance) in the memory cell MM ⁇ 0, y + 1>. The case of writing is shown.
  • the SET / reset signal generation circuit 71 sets SETMODE to H (high level) and RESETMODE to L (low level).
  • the rewrite circuit BLSW ⁇ 0> applies 1.5V to the bit line BL ⁇ 0> when the VBL voltage is set to 1.5V by BLVP ⁇ 0> and BLVN ⁇ 0>.
  • the wiring VX is controlled to 1.5V by RESETMODE when the power supply voltage vdd is 1.5V, for example, the MOS transistor PM0 is turned on and the analog switch SW0 is turned off.
  • the word line drive circuit WLDA ⁇ 0> drives the word line WLA ⁇ 0> to, for example, 1.5V during the t1-t3 period by WLMODE0.
  • the word line drive circuit WLDB ⁇ 0> drives the word line WLB ⁇ 0> to, for example, 1.5V during the period t1-t2 by WLMODE1.
  • the current flowing through the phase change element is doubled during the t1-t2 period with respect to the t2-t3 period, since both the selection MOS transistors CT1, CT2 are on.
  • the SET / reset signal generation circuit 71 sets SETMODE to L and RESETMODE to H.
  • the wiring VX is controlled to 1.0 V by RESETMODE, the MOS transistor PM0 is turned off, the analog switch SW0 is turned on.
  • the word line drive circuits WLDA ⁇ 0> and WLDB ⁇ 0> drive the word lines WLA ⁇ 0> and WLB ⁇ 0> to, for example, 1.0 V during the period t4-t5 by WLMODE0 and WLMODE1.
  • the configuration can cope with the word line voltage change at the time of reset data writing to realize the above.
  • FIG. 58 shows the word line voltage, phase change element current, and phase change element temperature when one selection MOS transistor is set
  • FIG. 54 shows the word line WLA and word line when there are two selection MOS transistors
  • FIG. 57 shows WLB voltage, phase change element current, and phase change element temperature. Assuming that the phase change element current is a single selection MOS transistor and the phase change element temperature is the crystallization temperature. In the case where there are two selection MOS transistors, the word line WLA and the word line WLB are simultaneously driven. Since the phase change element current is doubled, the temperature change of the phase change element is faster than in the case of one selection MOS transistor.
  • the temperature transition time can be shortened. Since the set time is the temperature transition time + the crystallization temperature holding time, the set time can be shortened by employing the two selection MOS transistors CT1 and CT2. In the operation waveform of FIG. 56, the word line voltage is lower when reset data is written, in order to reduce current consumption during the low resistance period when the phase change element transitions from low resistance to high resistance. It is.
  • FIG. 23 shows a processing flow from writing to verify writing.
  • the register REG built in the memory module is accessed by a method described later, and the code is written in the bit for storing the write voltage value code.
  • the write power supply is changed, verify write is performed, and verify read is performed again. If it is failed at this time, the next code is written into the register, the writing power supply is changed, and verify writing is performed to set the failed memory cell to a pass level resistance value.
  • FIG. 24 shows waveforms from the write input signal to the output of the write pulse generation circuit.
  • I / O ⁇ 0> passes and I / O ⁇ 1> fails in verify reading will be described as an example.
  • / WE and / VW in FIG. 5 are asserted to a low level.
  • the signal WE1 is switched to a low level, and the power supply for writing rises.
  • the signal / WP is started.
  • the setup time required for starting up the write power supply is not required, / WE is not required, and the write power supply start-up and internal circuit operation may be started by asserting / WP low.
  • the output Qn_0 of the shift register 60 is switched from the high level to the low level.
  • the other input VW2 ⁇ n> of the OR logic circuit (ORW0 in FIG. 5) that receives Qn_0 is the output of the OR logic circuit ORW0 according to the verify read result EOR ⁇ n> signal because / VW is low level.
  • Qn_1 is high level or low level. In short, the output of EOR ⁇ 0> can be validated and reflected in VW2 ⁇ 0> by the low level of / VW.
  • EOR ⁇ 0> is at a low level and EOR ⁇ 1> is at a high level.
  • Q0_1 is fixed at a high level even when Q0_0 switches from a high level to a low level, and thereafter is fixed at a high level up to the write pulse generation circuit outputs Wreset0_0 and Wset0_0, and no write pulse is generated.
  • EOR ⁇ 1> is at the high level, Q1_1 is the same as the normal write operation, and Q1_0 is switched as the high level is switched to the low level, and a write pulse is generated. Thereafter, the write pulse is applied only to the memory cell that has failed in the verify read operation as in the normal write operation.
  • the configuration of the verify light has the following effects.
  • the logical configuration of the timing generation circuit for reading and writing, the circuit configuration of various drivers, and the like are not limited to the configurations described in the drawings, and can be changed as appropriate.
  • the control for shifting the write data in the partial bit unit or the partial memory mat unit is not limited to the one bit unit or the one memory mat unit, and the output destination of the shift register 60 may be changed as appropriate to shift in a plurality of units. Is possible.
  • the present invention is not limited to being applied to an RFID chip or an RFID module, but is not limited thereto, and can be widely applied to a data processing LSI such as a microcomputer and a single memory LSI.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

Selon la présente invention, lorsqu'un transistor donné (CT) est sélectionné par une ligne de mots (WL) pour une cellule de mémoire (1) dans laquelle des transistors donnés sont reliés en série à un élément de changement de phase, le changement provoqué dans le potentiel de charge d'une ligne de mots (BL) est détecté par un amplificateur (31) et la lecture est verrouillée à un mécanisme de verrouillage de données de lecture (30), la ligne de bits est calée sur un faible potentiel (MTRANS) et les temporisations correspondant à la fois à la temporisation de sélection de la ligne de mots susmentionnée et à la temporisation du verrouillage de données susmentionné sont générées en synchronisation avec le changement d'un signal d'instruction d'opération de lecture fourni de manière externe (/RA). Il est possible de diminuer le courant qui alimente l'élément de changement de phase pendant l'opération de lecture en calant la ligne de bits sur un faible potentiel. En outre, lors de l'opération de lecture, la charge résiduelle de la ligne de bits s'évacue lors de la vérification des données de verrouillage produites par le système de verrouillage des données de lecture, qui retient la sortie de l'amplificateur détectant les changements de potentiel de la ligne de mots déjà préchargée.
PCT/JP2008/062586 2008-07-11 2008-07-11 Dispositif à semi-conducteur et module rfid WO2010004647A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2008/062586 WO2010004647A1 (fr) 2008-07-11 2008-07-11 Dispositif à semi-conducteur et module rfid

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2008/062586 WO2010004647A1 (fr) 2008-07-11 2008-07-11 Dispositif à semi-conducteur et module rfid

Publications (1)

Publication Number Publication Date
WO2010004647A1 true WO2010004647A1 (fr) 2010-01-14

Family

ID=41506778

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/062586 WO2010004647A1 (fr) 2008-07-11 2008-07-11 Dispositif à semi-conducteur et module rfid

Country Status (1)

Country Link
WO (1) WO2010004647A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106575205A (zh) * 2014-09-23 2017-04-19 英特尔公司 可选择的存储访问时间
CN114582412A (zh) * 2022-03-02 2022-06-03 长鑫存储技术有限公司 存储芯片的测试方法、装置、存储介质与电子设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003123492A (ja) * 2001-10-04 2003-04-25 Fujitsu Ltd センスアンプの動作マージンを改善した不揮発性半導体メモリ
WO2008044300A1 (fr) * 2006-10-12 2008-04-17 Renesas Technology Corp. Circuit intégré à semi-conducteurs

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003123492A (ja) * 2001-10-04 2003-04-25 Fujitsu Ltd センスアンプの動作マージンを改善した不揮発性半導体メモリ
WO2008044300A1 (fr) * 2006-10-12 2008-04-17 Renesas Technology Corp. Circuit intégré à semi-conducteurs

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106575205A (zh) * 2014-09-23 2017-04-19 英特尔公司 可选择的存储访问时间
JP2017528814A (ja) * 2014-09-23 2017-09-28 インテル・コーポレーション 選択可能なメモリアクセス時間
CN106575205B (zh) * 2014-09-23 2020-06-23 英特尔公司 可选择的存储访问时间
CN114582412A (zh) * 2022-03-02 2022-06-03 长鑫存储技术有限公司 存储芯片的测试方法、装置、存储介质与电子设备

Similar Documents

Publication Publication Date Title
US7656719B2 (en) Phase change memory device generating program current and method thereof
KR100895387B1 (ko) 상 변화 메모리 장치
US7391644B2 (en) Phase-changeable memory device and read method thereof
US7570524B2 (en) Circuitry for reading phase change memory cells having a clamping circuit
US8199603B2 (en) Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same
US8369173B2 (en) Semiconductor devices and methods for changing operating characteristics and semiconductor systems including the same
US8310891B2 (en) Resistance variable memory device for protecting coupling noise
JP4786948B2 (ja) プログラミング方法、相変化メモリ装置、及び、相変化メモリ書込み動作の駆動回路
KR20090016195A (ko) 상 변화 메모리 장치
US7668007B2 (en) Memory system including a resistance variable memory device
US8228711B2 (en) Bi-directional resistive memory devices and related memory systems and methods of writing data
KR20120096531A (ko) 상변화 메모리 비트의 리셋
KR102055375B1 (ko) 저항체를 이용한 비휘발성 메모리 장치 및 이를 포함하는 메모리 시스템
US8223535B2 (en) Phase-change memory device with discharge of leakage currents in deselected bitlines and method for discharging leakage currents in deselected bitlines of a phase-change memory device
JP5657876B2 (ja) 半導体メモリ装置
US7317655B2 (en) Memory cell array biasing method and a semiconductor memory device
WO2010004647A1 (fr) Dispositif à semi-conducteur et module rfid
US7710767B2 (en) Memory cell array biasing method and a semiconductor memory device
JP2008004264A (ja) 不揮発性半導体メモリ及び不揮発性半導体メモリにおける不良カラムの検出及び置き換え方法
KR20140081027A (ko) 비휘발성 메모리 장치
WO2010004646A1 (fr) Dispositif à semi-conducteur et module rfid
JP5031324B2 (ja) 相変化メモリ装置及びそれの読み出し方法
KR100934853B1 (ko) 상 변화 메모리 장치
JP5668489B2 (ja) 半導体メモリおよび半導体メモリの製造方法
KR20170063319A (ko) 동작환경 정보 저장회로 및 커맨드 저장 기능을 구비한 반도체 메모리 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08778101

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08778101

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP