WO2010001958A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2010001958A1
WO2010001958A1 PCT/JP2009/062114 JP2009062114W WO2010001958A1 WO 2010001958 A1 WO2010001958 A1 WO 2010001958A1 JP 2009062114 W JP2009062114 W JP 2009062114W WO 2010001958 A1 WO2010001958 A1 WO 2010001958A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
circuit
film
diode
resistor
Prior art date
Application number
PCT/JP2009/062114
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French (fr)
Japanese (ja)
Inventor
下村　奈良和
理史 橋本
吉田　健一
光昭 田渕
浩一 上山
敏雄 三本
朋世 藤井
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シャープ株式会社
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Publication of WO2010001958A1 publication Critical patent/WO2010001958A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0676—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors

Definitions

  • the present invention relates to a semiconductor device having an electrostatic discharge protection circuit for a power supply terminal or a reference power supply terminal for supplying a voltage to the semiconductor integrated circuit from the outside.
  • Electronic devices used in various electronic devices may be destroyed (deteriorated) due to electrostatic discharge during the manufacturing process or mounting on electronic devices. Therefore, when designing an electronic device, it is necessary to ensure a sufficient resistance against static electricity.
  • HBM human-body model
  • CDM charged-device model
  • MM machine model
  • HBM and MM are modes in which the electronic device itself is not charged, but discharge occurs when another electrostatically charged object (human or machine) touches the terminal of the electronic device, thereby destroying the electronic device. is there.
  • CDM is a mode in which the electronic device itself is charged by friction, dielectrics, or direct contact with a charged object, and the electronic device is destroyed by discharge that occurs when an external conductor contacts the terminal of the electronic device.
  • the International Electrotechnical Commission (IEC) has established an IEC-61000-4-2 test standard as an immunity test for electrostatic discharge.
  • the test based on the IEC-61000-4-2 test standard is performed for the purpose of simulating electrostatic discharge from a charged human body or object to the evaluation target device, and an ESD is schematically shown in the circuit diagram of FIG.
  • an applicator called a gun that can apply a high voltage, a high voltage is applied to the evaluation target device, and whether the evaluation target device operates normally after the application is tested.
  • the waveform of the output current of the applicator is determined according to the IEC-61000-4-2 test standard as shown in the waveform diagram shown in FIG. 16. The strength of immunity tolerance is judged.
  • a semiconductor device is one that has a weak immunity resistance.
  • a protection circuit that does not allow surge noise such as static electricity to flow into the semiconductor device is devised in Patent Document 1.
  • surge noise such as static electricity is prevented from flowing into a semiconductor device by providing a low-pass filter including a constant voltage diode (zener diode), a resistor, and a capacitor at a terminal portion of the semiconductor device.
  • a low-pass filter including a constant voltage diode (zener diode), a resistor, and a capacitor at a terminal portion of the semiconductor device.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 2005-228807 (published on August 25, 2005)”
  • the capacitor formed by the method disclosed in Patent Document 1 is a MIS capacitor (MIS capacitor, MetalMetaInsulator Semiconductor capacitor) made of metal, an insulating film and a P-type semiconductor.
  • a depletion layer is formed on the surface of the P-type semiconductor. For this reason, the electrostatic capacity of the MIS capacitor decreases. Therefore, the cut-off frequency increases, and the filter capability as a low-pass filter decreases.
  • the display panel driving LSI is often mounted on a film carrier called COF (Chip On Film).
  • COF Chip On On Film
  • the LSI input terminals, output terminals, reference power supply terminals and power supply terminals are mounted in a manner facing the wiring pattern formed on the film carrier. For this reason, it is difficult to take out the electrode from the back surface of the LSI.
  • the protection circuit devised in Patent Document 1 is required to form a Zener diode having a high Zener voltage and to form a capacitor having a high breakdown voltage.
  • There are problems such as electrode area, electrode formation on the backside of the LSI accompanying COF (Chip On On Film) mounting.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device that improves immunity resistance by allowing immunity noise flowing into the interior to escape to a ground terminal.
  • a semiconductor device is a semiconductor device, which is supplied with a voltage from the outside of the semiconductor device, one end connected to a voltage supply terminal, and the other end connected to an internal circuit of the semiconductor device. And a first circuit protection means connected between the voltage supply terminal and a ground terminal that is electrically grounded, wherein one end of the first circuit protection means and one end of the resistor are Connected to the voltage supply terminal, the other end of the first circuit protection means is connected to the ground terminal, and the first circuit protection means is any one having a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure. Or one.
  • a voltage is applied to the first circuit protection means.
  • a reverse bias voltage is applied to the first diode, and the reverse bias voltage exceeds the breakdown voltage of the first diode.
  • the drain-source voltage of the PMOS transistor exceeds the drain-source breakdown voltage of the MOS transistor.
  • a current flows through the first circuit protection means.
  • the diode is used as the first circuit protection means, a large current flows due to avalanche breakdown from the cathode of the diode to the anode of the diode.
  • the PMOS transistor is used as the first circuit protection means, a large current flows due to avalanche breakdown from the source of the first PMOS transistor to the drain of the first PMOS transistor.
  • immunity noise flowing into the semiconductor device can be released to the ground terminal, and the immunity resistance of the semiconductor device can be improved.
  • the current flowing into the internal circuit is reduced by interposing the resistor between the voltage supply terminal and the internal circuit.
  • the diode when used as the first circuit protection means, since a normal avalanche diode is used, it is not necessary to form a Zener diode or capacitor having a high Zener voltage.
  • the semiconductor device further includes second circuit protection means, one end of the second circuit protection means is connected to the other end of the resistor, and the other end of the second circuit protection means is connected to the ground terminal.
  • the connected second circuit protection means may be any one of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure.
  • surge noise during an electrostatic breakdown test in the HBM model or MM model is caused by the grounding after passing through the resistor.
  • Surge noise goes to the terminal.
  • the diode is used as the first circuit protection means
  • the surge noise is released to the ground terminal by utilizing the reverse direction characteristic of the diode.
  • the reverse direction characteristic of the diode is provided through the resistor. May worsen and the tolerance may decrease.
  • the semiconductor device may further include third circuit protection means having one end connected to the input terminal or the output terminal of the internal circuit and the other end connected to one end of the first circuit protection means.
  • the third circuit protection means may be any one of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure.
  • the voltage supply terminal and the ground terminal may be formed on the same surface of the semiconductor substrate forming the semiconductor device.
  • the resistor may be a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are stacked.
  • the first circuit protection means is any one of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure.
  • 1 is a cross-sectional view of an electrostatic discharge protection circuit according to an embodiment of the present invention. It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on the Example of this invention. It is a cross-sectional view of an electrostatic discharge protection circuit according to another embodiment of the present invention. 6 is an equivalent circuit of an electrostatic discharge protection circuit according to another embodiment of the present invention. It is a cross-sectional view of an electrostatic discharge protection circuit according to still another embodiment of the present invention. It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on another Example of this invention. It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on another Example of this invention. It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on another Example of this invention. It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on another Example of this invention.
  • FIG. 1 is a cross-sectional view of the electrostatic discharge protection circuit 10 according to the first embodiment.
  • the element isolation part 2 is formed of an oxide film having a thickness (length in the Y direction) of 0.2 ⁇ m to 0.8 ⁇ m on the P-type semiconductor substrate 1 implanted with boron.
  • the substrate concentration of the P-type semiconductor substrate 1 is 1 ⁇ 10 15 / cm 3 to 1 ⁇ 10 18 / cm 3 .
  • an N-type impurity region 3 implanted with phosphorus or arsenic and a P-type impurity region 4 implanted with boron are formed inside the surface 1a of the P-type semiconductor substrate 1 (Y ⁇ 0).
  • the impurity concentration of the N-type impurity region 3 is 1 ⁇ 10 18 / cm 3 to 5 ⁇ 10 20 / cm 3
  • the impurity concentration of the P-type impurity region 4 is 1 ⁇ 10 18 / cm 3 to 5 ⁇ 10 20 / cm 3. cm 3 .
  • the multilayer film 5 is formed on the surface 1a of the P-type semiconductor substrate 1 (Y> 0).
  • the multilayer film 5 is a polycrystalline silicon film having a thickness of 50 nm to 500 nm and implanted with phosphorus, arsenic, boron, or the like, or a film in which a polycrystalline silicon film and a refractory metal film are laminated.
  • an interlayer insulating film 6 having a thickness of 100 nm to 1500 nm is formed on the surface 1a of the P-type semiconductor substrate 1 (Y> 0), and after opening the connection holes, an aluminum alloy having a thickness of 100 nm to 1500 nm, Metal wiring 7 to metal wiring 9 made of a multilayer film containing at least one of titanium alloy or copper, or aluminum alloy, titanium alloy and copper are formed.
  • the N-type impurity region 3, the P-type semiconductor substrate 1, and the P-type impurity region 4 form a diode D.
  • the N-type impurity region 3 is a cathode electrode of the diode D
  • the P-type impurity region 4 is an anode electrode of the diode D.
  • the P-type semiconductor substrate 1 constitutes the main body of the diode D.
  • the multilayer film 5 which is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated forms a resistor R.
  • the metal wiring 7 connects the P-type impurity region 4 and the ground terminal (ground terminal) of the semiconductor device to which the electrostatic discharge protection circuit 10 is connected.
  • the metal wiring 8 connects the N-type impurity region 3, the multilayer film 5 and the power supply terminal of the semiconductor device, or connects the N-type impurity region 3, the multilayer film 5 and the reference power supply terminal of the semiconductor device.
  • the metal wiring 9 connects the multilayer film 5 and the internal circuit of the semiconductor device.
  • the power supply terminal and the reference power supply terminal are voltage supply terminals.
  • FIG. 2 is an equivalent circuit of the electrostatic discharge protection circuit 10.
  • a diode D is provided between the power supply terminal or the reference power supply terminal and the ground terminal to release immunity noise
  • a resistor is provided between the power supply terminal or the reference power supply terminal and the internal circuit of the semiconductor device. The current flowing into the internal circuit of the semiconductor device is reduced by passing through the body R.
  • the resistance value of the resistor R needs to be selected in consideration of the current flowing through the power supply line inside the LSI during LSI operation and the voltage drop caused by the resistor R during LSI operation, and is usually about 1 ⁇ to 10 ⁇ . It is desirable to select a resistance value.
  • the diode D may be divided into a plurality of diodes and connected in parallel, but the total perimeter is preferably selected in the range of 1000 ⁇ m to 20000 ⁇ m.
  • the electrostatic discharge protection circuit 10 when immunity noise that flows into the semiconductor device flows, a reverse bias voltage is applied to the diode D, and the reverse bias voltage is , Exceeding the breakdown voltage of the diode D.
  • the electrostatic discharge protection circuit 10 according to the first embodiment uses a normal avalanche diode, it is not necessary to form a Zener diode or a capacitor having a high Zener voltage. Further, the electrodes (the cathode electrode of the diode D and the anode electrode of the diode D) can be formed only on the surface 1 a side of the P-type semiconductor substrate 1. For these reasons, the electrostatic discharge protection circuit 10 according to the first embodiment is suitable for a semiconductor device that performs COF (Chip-On-Film) mounting.
  • COF Chip-On-Film
  • FIG. 3 is a cross-sectional view of the electrostatic discharge protection circuit 20 according to the second embodiment.
  • the element isolation portion 22 is formed of an oxide film having a thickness of 0.2 ⁇ m to 0.8 ⁇ m on the P-type semiconductor substrate 21 into which boron is implanted.
  • the substrate concentration of the P-type semiconductor substrate 21 is 1 ⁇ 10 15 / cm 3 to 1 ⁇ 10 18 / cm 3 .
  • the impurity concentration of the N-type impurity region 23a and the N-type impurity region 23b is 1 ⁇ 10 18 / cm 3 to 5 ⁇ 10 20 / cm 3
  • the impurity concentration of the P-type impurity region 24a and the P-type impurity region 24b is 1 ⁇ 10 18 / cm 3 to 5 ⁇ 10 20 / cm 3 .
  • the multilayer film 25 is formed on the surface 21a (Y> 0) of the P-type semiconductor substrate 21.
  • the multilayer film 25 has a thickness of 50 nm to 500 nm and is a polycrystalline silicon film into which phosphorus, arsenic, boron, or the like is implanted, or a film in which a polycrystalline silicon film and a refractory metal film are stacked.
  • an interlayer insulating film 26 having a thickness of 100 nm to 1500 nm is formed on the surface 21a of the P-type semiconductor substrate 21 (Y> 0), and after opening the connection holes, an aluminum alloy having a thickness of 100 nm to 1500 nm, Metal wiring 27 to metal wiring 29 made of a multilayer film containing at least one of titanium alloy or copper, or aluminum alloy, titanium alloy and copper are formed.
  • the N-type impurity region 23a, the P-type semiconductor substrate 21 and the P-type impurity region 24a form the first diode D1
  • the N-type impurity region 23b, the P-type semiconductor substrate 21 and the P-type impurity are formed.
  • Region 24b forms second diode D2.
  • the N-type impurity region 23a is the cathode electrode of the first diode D1
  • the P-type impurity region 24a is the anode electrode of the first diode D1
  • the P-type semiconductor substrate 21 constitutes the main body of the first diode D1.
  • the N-type impurity region 23b is the cathode electrode of the second diode D2
  • the P-type impurity region 24b is the anode electrode of the second diode D2
  • the P-type semiconductor substrate 21 is connected to the second diode D2. Configure the body.
  • the multilayer film 25 which is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated forms a resistor R.
  • the metal wiring 27 connects the P-type impurity region 24a and the ground terminal of the semiconductor device to which the electrostatic discharge protection circuit 20 is connected.
  • the metal wiring 28 connects the N-type impurity region 23a, the multilayer film 25, and the power supply terminal of the semiconductor device, or connects the N-type impurity region 23a, the multilayer film 25, and the reference power supply terminal of the semiconductor device.
  • the metal wiring 29 connects the multilayer film 25, the N-type impurity region 23b, and the internal circuit of the semiconductor device.
  • the P-type impurity region 24b is connected to the ground terminal of the semiconductor device in the same manner as the P-type impurity region 24a.
  • FIG. 4 is an equivalent circuit of the electrostatic discharge protection circuit 20.
  • the first diode D1 is provided between the power supply terminal or the reference power supply terminal and the ground terminal to release immunity noise, and between the power supply terminal or the reference power supply terminal and the internal circuit of the semiconductor device. Further, the current flowing into the internal circuit of the semiconductor device is reduced through the resistor R.
  • the electrostatic breakdown test includes standards based on the HBM model (human-body model) and MM model (machine model). .
  • HBM model human-body model
  • MM model machine model
  • surge noise such as static electricity
  • surge noise entered from the input terminal and output terminal is installed at the input terminal and output terminal. It goes to the ground terminal through the electrostatic protection element and internal circuit.
  • a second diode D2 is provided between the power supply line P and the ground line G, and static electricity in the HBM model and the MM model is provided. Surge noise during the electric breakdown test can escape to the ground terminal via the second diode D2 without passing through the resistor R. For this reason, the tolerance of the electrostatic breakdown test in the HBM model and the MM model can be improved.
  • the resistance value of the resistor R it is desirable to select a resistance value of about 1 ⁇ to 10 ⁇ as in the first embodiment.
  • each diode a plurality of divided diodes may be connected in parallel as in the first embodiment, but the total perimeter of the first diode D1 is preferably selected from the range of 1000 ⁇ m to 20000 ⁇ m, The total perimeter of the diode D2 is preferably selected from the range of 1000 to 10,000 um.
  • the electrodes (the cathode electrode of the diode D1, the anode electrode of the diode D1, the cathode electrode of the diode D2, and the anode electrode of the diode D2) can be formed only on the surface 21a side of the P-type semiconductor substrate 21.
  • the electrostatic discharge protection circuit 20 according to the second embodiment is suitable for a semiconductor device in which COF (Chip On On Film) mounting is performed.
  • FIG. 5 is a cross-sectional view of the electrostatic discharge protection circuit 30 according to the third embodiment.
  • phosphorus is further injected into the P-type semiconductor substrate 31 into which boron has been injected, and an N-type impurity well 32 is formed in the P-type semiconductor substrate 31.
  • the element isolation portion 33 is formed on the P-type semiconductor substrate 31 with an oxide film having a thickness (length in the Y direction) of 0.2 ⁇ m to 0.8 ⁇ m.
  • the substrate concentration of the P-type semiconductor substrate 31 is 1 ⁇ 10 15 / cm 3 to 1 ⁇ 10 18 / cm 3 .
  • the impurity concentration of the N-type impurity well 32 is 1 ⁇ 10 15 / cm 3 to 1 ⁇ 10 18 / cm 3 , and the depth (the length in the Y direction) of the N-type impurity well 32 is 0.5 ⁇ m to 5 ⁇ m.
  • a gate electrode is formed on the surface 31a of the P-type semiconductor substrate 31 (Y> 0) with the oxide film 34 having a thickness of 10 nm to 100 nm and the multilayer film 35 having a thickness of 50 nm to 500 nm.
  • the multilayer film 35 is a polycrystalline silicon film implanted with phosphorus, arsenic, boron, or the like, or a film in which a polycrystalline silicon film and a refractory metal film are stacked.
  • a drain region is formed by a P-type impurity region 36a into which boron is implanted.
  • a source region is formed by a P-type impurity region 36b implanted with boron on the inner side (Y ⁇ 0) side of the surface 31a of the P-type semiconductor substrate 31.
  • the impurity concentration of the P-type impurity region 36a and the P-type impurity region 36b is 1 ⁇ 10 18 / cm 3 to 5 ⁇ 10 20 / cm 3 .
  • an N well contact region is formed by an N type impurity region 37 implanted with phosphorus or arsenic.
  • the impurity concentration of the N-type impurity region 37 is 1 ⁇ 10 18 / cm 3 to 5 ⁇ 10 20 / cm 3 .
  • a channel injection region 38 for adjusting the threshold voltage is formed at a position facing the oxide film 34 on the inner side (Y ⁇ 0) side of the surface 31a of the P-type semiconductor substrate 31.
  • a multilayer film 39 is formed on the surface 31a of the P-type semiconductor substrate 31 (Y> 0).
  • the multilayer film 39 has a thickness of 50 nm to 500 nm and is a polycrystalline silicon film in which phosphorus, arsenic, boron, or the like is implanted, or a film in which a polycrystalline silicon film and a refractory metal film are stacked.
  • an interlayer insulating film 41 having a thickness of 100 nm to 1500 nm is formed on the surface 31a of the P-type semiconductor substrate 31 (Y> 0), and after opening the connection holes, an aluminum alloy having a thickness of 100 nm to 1500 nm, Metal wiring 42 to metal wiring 44 made of a multilayer film containing at least one of titanium alloy or copper, or aluminum alloy, titanium alloy and copper are formed.
  • N-type impurity well 32, oxide film 34, the multilayer film 35, P-type impurity region 36a, P-type impurity region 36b and the N-type impurity region 37 form a PMOS transistor M P.
  • P-type impurity region 36a is a drain electrode of the PMOS transistor M P
  • P-type impurity region 36b is the source electrode of the PMOS transistor M P
  • N-type impurity region 37 is an N-well contact electrode of the PMOS transistor M P
  • multilayer film 35 is a gate electrode of the PMOS transistor M P.
  • N-type impurity well 32 constitutes the N-well region of the PMOS transistor M P.
  • the multilayer film 39 which is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated forms a resistor R.
  • the metal wiring 42 connects the P-type impurity region 36a and the ground terminal of the semiconductor device to which the electrostatic discharge protection circuit 30 is connected.
  • the metal wiring 43 connects the P-type impurity region 36b, the N-type impurity region 37, the multilayer film 35, the multilayer film 39, and the power supply terminal of the semiconductor device, or connects the P-type impurity region 36b, the N-type impurity region 37, and the multilayer.
  • the film 35, the multilayer film 39, and the reference power supply terminal of the semiconductor device are connected.
  • the metal wiring 44 connects the multilayer film 39 and the internal circuit of the semiconductor device.
  • FIG. 6 is an equivalent circuit of the electrostatic discharge protection circuit 30.
  • the equivalent circuit of FIG. 6 between the power supply terminal or the reference power supply terminal and the ground terminal is provided with a PMOS transistor M P connected source electrode, the gate electrode and the N-well contact electrode in common.
  • the resistance value of the resistor R it is desirable to select a resistance value of about 1 ⁇ to 10 ⁇ as in the first embodiment.
  • Channel length of the PMOS transistor M P is desirably chosen from the range of 0.5 [mu] m ⁇ 10 [mu] m, the channel width of the PMOS transistor M P is preferably selected from the range of 300 ⁇ m ⁇ 7000 ⁇ m.
  • PMOS transistors M P may be connected to those division into a plurality of PMOS transistors in parallel, but the total channel width is desirably selected within the range of 300um ⁇ 7000um.
  • the drain of the PMOS transistor M P - source voltage, the drain of the PMOS transistor M P - The breakdown voltage between sources is exceeded.
  • the electrode (gate electrode of the PMOS transistor M P, the source electrode of the PMOS transistor M P, the drain electrode of the PMOS transistor M P, N well contact electrode of the PMOS transistor M P) is a surface 31a side of the P-type semiconductor substrate 31 Can only be formed.
  • the electrostatic discharge protection circuit 30 according to the third embodiment is suitable for a semiconductor device that performs COF (Chip On Film) mounting.
  • FIG. 7 is an equivalent circuit of the electrostatic discharge protection circuit 40 of the fourth embodiment.
  • the second PMOS transistor MP2 is provided between the power supply line P and the ground line G, similarly to the electrostatic discharge protection circuit 20 of the second embodiment.
  • a first PMOS transistor MP1 is provided between the power supply terminal or the reference power supply terminal and the ground terminal.
  • the resistance value of the resistor R it is desirable to select a resistance value of about 1 ⁇ to 10 ⁇ as in the first embodiment.
  • Each PMOS transistors, as in Example 3 may be connected to those divided into a plurality in parallel, but the total channel width of the first PMOS transistor M P1 is desirably selected within the range of 300 ⁇ m ⁇ 7000 ⁇ m , the total channel width of the second PMOS transistor M P2, it is desirable to select from a range of 300 ⁇ m ⁇ 3500 ⁇ m.
  • Example 5 An equivalent circuit of a more general electrostatic discharge protection circuit is an equivalent circuit as shown in FIG. 8 of the fifth embodiment and FIG. 9 of the sixth embodiment described later.
  • FIG. 8 is an equivalent circuit of the electrostatic discharge protection circuit 50 of the fifth embodiment.
  • one electrostatic protection element (first circuit protection means) 51 is used, and the electrostatic protection element 51 is provided between the power supply terminal or the reference power supply terminal and the ground terminal.
  • the resistance value of the resistor R it is desirable to select a resistance value of about 1 ⁇ to 10 ⁇ as in the first embodiment.
  • FIG. 9 is an equivalent circuit of the electrostatic discharge protection circuit 60 of the sixth embodiment.
  • two electrostatic protection elements are used, and a second electrostatic protection element (second circuit protection means) 62 is provided between the power supply line P and the ground line G.
  • a first electrostatic protection element (first circuit protection means) 61 is provided between the power supply terminal or the reference power supply terminal and the ground terminal.
  • the resistance value of the resistor R it is desirable to select a resistance value of about 1 ⁇ to 10 ⁇ as in the first embodiment.
  • an NMOS transistor and a bipolar transistor are used as the electrostatic protection elements 51, 61, and 62 in the equivalent circuit shown in FIGS. 8 and 9, in addition to the diode and the PMOS transistor described in Examples 1 to 4 of this embodiment.
  • an NMOS transistor and a bipolar transistor are used as the electrostatic protection elements 51, 61, and 62 in the equivalent circuit shown in FIGS. 8 and 9, in addition to the diode and the PMOS transistor described in Examples 1 to 4 of this embodiment, an NMOS transistor and a bipolar transistor are used.
  • a transistor or a transistor having a thyristor structure may be used.
  • FIG. 12 is a block diagram illustrating a path of surge noise in the HBM model or the MM model in a semiconductor device including the electrostatic discharge protection circuit 70 according to the seventh embodiment.
  • the surge noise path is a surge noise path with the ground terminal reference + applied.
  • the diode D7 which is an electrostatic protection element, is formed in the same manner as in the first embodiment, but is connected between the input terminal or output terminal and the power supply line P (an electrostatic protection element ( By devising the connection method of one end of the circuit protection device (third circuit protection means) 71, as in the case of the electrostatic discharge protection circuit 20 of the second embodiment, it is possible to improve the tolerance in the HBM model and the MM model. .
  • a diode D7 are connected to a connection point P 71 between the cathode electrode of the resistor and one end of the resistor R.
  • the resistance value of the resistor R it is desirable to select a resistance value of about 1 ⁇ to 10 ⁇ as in the first embodiment.
  • the diode D7 may be divided into a plurality of diodes connected in parallel, but the total perimeter of the diode is preferably selected from a range of 1000 ⁇ m to 20000 ⁇ m.
  • FIG. 13 is a block diagram illustrating a path of surge noise in the HBM model or the MM model in a semiconductor device including the electrostatic discharge protection circuit 80 according to the eighth embodiment.
  • the surge noise path is a surge noise path with the ground terminal reference + applied.
  • the PMOS transistor MP8 which is an electrostatic protection element, is formed in the same manner as in the third embodiment, but is connected between the input terminal and the output terminal and the power supply line P.
  • the connection method of one end of the element (circuit protection device, third circuit protection means) 81 as in the case of the electrostatic discharge protection circuit 40 of the fourth embodiment, it is possible to improve the tolerance in the HBM model and the MM model. It is.
  • one end E 81 of the electrostatic protection element 81 connected between the input terminal or the output terminal and the power supply line P is connected to the PMOS transistor.
  • the source electrode of the M P8 are connected to one end of the connection point P 81 of the gate electrode and the resistor R of the PMOS transistor M P8.
  • the resistance value of the resistor R it is desirable to select a resistance value of about 1 ⁇ to 10 ⁇ as in the first embodiment.
  • PMOS transistor M P8, as in Example 3 may be connected to those divided into a plurality in parallel, but the total channel width of the PMOS transistor is desirably selected from the range of 300 ⁇ m ⁇ 7000 ⁇ m.
  • FIG. 14 is a block diagram illustrating a path of surge noise in the HBM model or the MM model in a semiconductor device including the electrostatic discharge protection circuit 90 according to the ninth embodiment.
  • the surge noise path is a surge noise path with the ground terminal reference + applied.
  • the semiconductor device of FIG. 14 is a semiconductor device provided with a more general electrostatic discharge protection circuit 90.
  • the electrostatic protection element (first circuit protection means) 92 is formed in the same manner as in the fifth embodiment, but is connected between the input terminal or the output terminal and the power supply line P.
  • the connection method of one end of the electrostatic protection element (circuit protection device, third circuit protection means) 91 as in the case of the electrostatic discharge protection circuit 60 of the sixth embodiment, an improvement in withstand capability in the HBM model and the MM model is realized. To do.
  • one end E 91 of the electrostatic protection element 91 connected between the input terminal or the output terminal and the power supply line P is connected to the power supply terminal.
  • it is connected to a connection point P 91 between one end E 92 of the electrostatic protection element 92 and one end of the resistor R, which is connected between the reference power supply terminal and the ground terminal.
  • the resistance value of the resistor R it is desirable to select a resistance value of about 1 ⁇ to 10 ⁇ as in the first embodiment.
  • the electrostatic protection element 92 connected between the power supply terminal or the reference power supply terminal and the ground terminal is described in Examples 1 to 4 of this embodiment.
  • an NMOS transistor, a bipolar transistor, or a thyristor structure may be used.
  • the tolerance of the electrostatic breakdown test in the HBM model or MM model can be improved without adding additional electrostatic protection elements at both ends of the internal circuit. Accordingly, since it is not necessary to increase the size of the semiconductor device, it is possible to improve the tolerance when performing the electrostatic breakdown test in the HBM model or the MM model without increasing the chip cost.
  • NMOS transistors in addition to the diodes and PMOS transistors described in Examples 1 to 4 of the present embodiment, NMOS transistors, A bipolar transistor or a thyristor structure may be used.
  • the present invention when a plurality of electrostatic discharge protections are used at both ends of the resistor R, the same element is used.
  • the present invention is not limited to this, and different elements may be combined.
  • a PMOS transistor may be provided instead of the diode D2.
  • the semiconductor device of the present invention improves the immunity resistance by letting immunity noise flowing into the ground terminal escape to the ground terminal, and therefore can be suitably used for a display panel driving LSI such as a liquid crystal display or a plasma display.
  • Electrostatic discharge protection circuit 32 N Type impurity well 38 channel injection region 51, 92 electrostatic protection element (first circuit protection means) 61 1st electrostatic protection element (1st circuit protection means) 62 Second electrostatic protection element (second circuit protection means) 71, 81, 91 Static electricity protection element (third circuit protection means) D diode (first circuit protection means) D1 first diode (first circuit protection means) D2 Second diode (second circuit protection means) D7 diode (first circuit protection means) E 71 , E 81 , E 91 , E 92 one end G ground line M P , M P

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Abstract

One end of an electrostatic protection element (51) and one end of a resistor (R) are connected to a power source terminal or a reference power source terminal.  The other end of the electrostatic protection element (51) is connected to a ground terminal.  The electrostatic protection element (51) has a structure of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, or a thyristor.

Description

半導体装置Semiconductor device
　本発明は、半導体集積回路に外部から電圧を供給する、電源端子または基準電源端子に対する静電気放電保護回路を有する半導体装置に関するものである。 The present invention relates to a semiconductor device having an electrostatic discharge protection circuit for a power supply terminal or a reference power supply terminal for supplying a voltage to the semiconductor integrated circuit from the outside.
　各種の電子機器に用いられる電子デバイスは、その製造過程や電子機器への実装時などにおいて、静電放電により破壊（劣化）することがある。従って、電子デバイスの設計に際しては、静電気に対する耐量を十分に確保することが必要となる。 Electronic devices used in various electronic devices may be destroyed (deteriorated) due to electrostatic discharge during the manufacturing process or mounting on electronic devices. Therefore, when designing an electronic device, it is necessary to ensure a sufficient resistance against static electricity.
　この静電気放電に対する破壊耐量を測定するために、電子デバイスにおける静電気放電をシミュレーションする試験が静電破壊試験であり、近年重要性が指摘されている。従来から、静電破壊のモデルはその発生要因によって、ＨＢＭ（human-body model：人体モデル）、ＣＤＭ（charged-device model：帯電デバイス・モデル）、ＭＭ（machine model：マシン・モデル）の三つに大別されてきた。 In order to measure the breakdown tolerance against this electrostatic discharge, a test for simulating electrostatic discharge in an electronic device is an electrostatic breakdown test, and the importance has been pointed out in recent years. Conventionally, there are three types of electrostatic breakdown models, HBM (human-body model), CDM (charged-device model), and MM (machine model), depending on the generation factors. Have been broadly divided.
　ＨＢＭやＭＭは、電子デバイス自体は帯電していないが、静電帯電した他の物体（人や機械）が電子デバイスの端子に触れることにより、放電が起こり、これにより電子デバイスが破壊するモードである。ＣＤＭは、電子デバイス自体が、摩擦や、誘電あるいは帯電物体との直接な接触により帯電し、電子デバイスの端子へ外部の導体が接触したときに起こる放電によって、電子デバイスが破壊するモードである。 HBM and MM are modes in which the electronic device itself is not charged, but discharge occurs when another electrostatically charged object (human or machine) touches the terminal of the electronic device, thereby destroying the electronic device. is there. CDM is a mode in which the electronic device itself is charged by friction, dielectrics, or direct contact with a charged object, and the electronic device is destroyed by discharge that occurs when an external conductor contacts the terminal of the electronic device.
　この他にも、静電気放電に関連した試験として、電磁妨害に対する耐性を評価するイミュニティ試験があり、複数の電子デバイスで構成された電子機器装置の品質確認のひとつとして採用されている。 In addition to this, there is an immunity test for evaluating resistance to electromagnetic interference as a test related to electrostatic discharge, which is adopted as one of the quality confirmations of an electronic equipment device composed of a plurality of electronic devices.
　国際電気標準会議（International Electrotechnical Commission：ＩＥＣ）では、静電気放電に関するイミュニティ試験として、IEC-61000-4-2という試験規格を設けている。IEC-61000-4-2試験規格に基づく試験は、帯電した人体や物体から評価対象装置への静電気放電をシミュレーションする目的で行われており、概略構成が図１５の回路図で示される、ＥＳＤガンと呼ばれる高電圧を印加可能な印加機を用いて、評価対象装置に高電圧を印加し、印加後も評価対象装置が正常動作するかを試験している。 The International Electrotechnical Commission (IEC) has established an IEC-61000-4-2 test standard as an immunity test for electrostatic discharge. The test based on the IEC-61000-4-2 test standard is performed for the purpose of simulating electrostatic discharge from a charged human body or object to the evaluation target device, and an ESD is schematically shown in the circuit diagram of FIG. Using an applicator called a gun that can apply a high voltage, a high voltage is applied to the evaluation target device, and whether the evaluation target device operates normally after the application is tested.
　印加機の出力電流の波形は、IEC-61000-4-2試験規格により図１６に示される波形図のように決められており、正常動作が確認できた印加電圧の大小で、評価対象装置のイミュニティ耐性の強弱を判断している。 The waveform of the output current of the applicator is determined according to the IEC-61000-4-2 test standard as shown in the waveform diagram shown in FIG. 16. The strength of immunity tolerance is judged.
　電子機器装置を構成する電子デバイスの中で、上記イミュティ耐性が弱いものとして、半導体装置がある。半導体装置のイミュニティ耐性を向上させるために、半導体装置内に静電気などのサージノイズを流入させない保護回路が特許文献１で考案されている。特許文献１では、定電圧ダイオード（ツェナーダイオード）、抵抗体及びコンデンサーから成るローパスフィルターを、半導体装置の端子部に設けることにより、半導体装置内に静電気などのサージノイズが流入を防止することが開示されている。 Among the electronic devices that constitute the electronic device apparatus, a semiconductor device is one that has a weak immunity resistance. In order to improve the immunity tolerance of a semiconductor device, a protection circuit that does not allow surge noise such as static electricity to flow into the semiconductor device is devised in Patent Document 1. In Patent Document 1, it is disclosed that surge noise such as static electricity is prevented from flowing into a semiconductor device by providing a low-pass filter including a constant voltage diode (zener diode), a resistor, and a capacitor at a terminal portion of the semiconductor device. Has been.
日本国公開特許公報「特開２００５－２２８８０７号公報（２００５年８月２５日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 2005-228807 (published on August 25, 2005)”
　しかし、液晶ディスプレイやプラズマディスプレイ等の表示パネル駆動用ＬＳＩは、電源電圧が１０Ｖ以上のものが多く、ツェナー降伏電圧が１０Ｖ以上となる定電圧ダイオード（ツェナーダイオード）を、表示パネル駆動用ＬＳＩ内に形成することは困難である。 However, many display panel driving LSIs such as liquid crystal displays and plasma displays have a power supply voltage of 10 V or more, and a constant voltage diode (zener diode) having a Zener breakdown voltage of 10 V or more is included in the display panel driving LSI. It is difficult to form.
　また、特許文献１に開示されている方法で形成されるコンデンサーは、金属、絶縁膜及びＰ型半導体から成るＭＩＳ容量（ＭＩＳコンデンサー、Metal Insulator Semiconductor capacitor）であるので、高周波ノイズに対しては、Ｐ型半導体表面に空乏層が形成される。このため、ＭＩＳコンデンサーの静電容量が低下する。従って、カットオフ周波数が上昇し、ローパスフィルターとしてのフィルター能力が低下してしまう。 Further, the capacitor formed by the method disclosed in Patent Document 1 is a MIS capacitor (MIS capacitor, MetalMetaInsulator Semiconductor capacitor) made of metal, an insulating film and a P-type semiconductor. A depletion layer is formed on the surface of the P-type semiconductor. For this reason, the electrostatic capacity of the MIS capacitor decreases. Therefore, the cut-off frequency increases, and the filter capability as a low-pass filter decreases.
　また、ＭＩＳコンデンサーを構成する絶縁膜は、１０Ｖ以上の電圧に耐える必要があることから膜厚が厚くなり、必要な静電容量を得るのに必要な電極面積が大きくなる。さらに、表示パネル駆動用ＬＳＩは、ＣＯＦ（Chip On Film）と呼ばれる、フィルムキャリア上に実装されることが多い。ＣＯＦ（Chip On Film）実装では、ＬＳＩの、入力端子、出力端子、基準電源端子及び電源端子と、フィルムキャリア上に形成される配線パターンとが対向する形で実装される。このため、ＬＳＩの裏面から電極を取り出すことは困難である。 In addition, since the insulating film constituting the MIS capacitor needs to withstand a voltage of 10 V or more, the film thickness is increased, and the electrode area necessary for obtaining a necessary capacitance is increased. Further, the display panel driving LSI is often mounted on a film carrier called COF (Chip On Film). In COF (Chip On On Film) mounting, the LSI input terminals, output terminals, reference power supply terminals and power supply terminals are mounted in a manner facing the wiring pattern formed on the film carrier. For this reason, it is difficult to take out the electrode from the back surface of the LSI.
　このように、表示パネル駆動用ＬＳＩへの適用を考えた場合、特許文献１で考案されている保護回路は、高いツェナー電圧を有するツェナーダイオードの形成、高い耐圧を有するコンデンサーを形成するのに要する電極面積、ＣＯＦ（Chip On Film）実装に伴うＬＳＩ裏面での電極形成といった課題がある。 Thus, when considering application to a display panel driving LSI, the protection circuit devised in Patent Document 1 is required to form a Zener diode having a high Zener voltage and to form a capacitor having a high breakdown voltage. There are problems such as electrode area, electrode formation on the backside of the LSI accompanying COF (Chip On On Film) mounting.
　本発明は、上記の問題点に鑑みてなされたものであって、その目的は、内部に流入するイミュニティノイズを接地端子に逃がすことで、イミュニティ耐性を向上させる半導体装置を提供することにある。 The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device that improves immunity resistance by allowing immunity noise flowing into the interior to escape to a ground terminal.
　本発明の半導体装置は、半導体装置であって、上記半導体装置の外部から電圧を供給される、電圧供給端子に一端が接続され、上記半導体装置の内部回路に他端が接続される抵抗体と、上記電圧供給端子と、電気的に接地される接地端子との間に接続される第１回路保護手段とを備える半導体装置において、上記第１回路保護手段の一端及び抵抗体の一端は、上記電圧供給端子に接続され、上記第１回路保護手段の他端は、上記接地端子に接続され、上記第１回路保護手段は、ダイオード、ＰＭＯＳトランジスター、ＮＭＯＳトランジスター、バイポーラトランジスター及びサイリスター構造を有するもののいずれか１つであることを特徴とする。 A semiconductor device according to the present invention is a semiconductor device, which is supplied with a voltage from the outside of the semiconductor device, one end connected to a voltage supply terminal, and the other end connected to an internal circuit of the semiconductor device. And a first circuit protection means connected between the voltage supply terminal and a ground terminal that is electrically grounded, wherein one end of the first circuit protection means and one end of the resistor are Connected to the voltage supply terminal, the other end of the first circuit protection means is connected to the ground terminal, and the first circuit protection means is any one having a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure. Or one.
　上記発明によれば、上記半導体装置の内部にイミュニティノイズが流入する場合、上記第１回路保護手段に電圧が印加される。例えば上記第１回路保護手段として上記ダイオードを用いる場合、上記第１ダイオードに逆バイアスの電圧が印加され、該逆バイアスの電圧が、上記第１ダイオードの降伏電圧を上回る。同様に、上記第１回路保護手段として上記ＰＭＯＳトランジスターを用いる場合、上記ＰＭＯＳトランジスターのドレイン－ソース間電圧が、上記ＭＯＳトランジスターのドレイン－ソース間耐圧を上回る。 According to the invention, when immunity noise flows into the semiconductor device, a voltage is applied to the first circuit protection means. For example, when the diode is used as the first circuit protection means, a reverse bias voltage is applied to the first diode, and the reverse bias voltage exceeds the breakdown voltage of the first diode. Similarly, when the PMOS transistor is used as the first circuit protection means, the drain-source voltage of the PMOS transistor exceeds the drain-source breakdown voltage of the MOS transistor.
　この時、上記第１回路保護手段に電流が流れる。上記第１回路保護手段として上記ダイオードを用いる場合、上記ダイオードのカソードから上記ダイオードのアノードへアバランシェ降伏により大きな電流が流れる。上記第１回路保護手段として上記ＰＭＯＳトランジスターを用いる場合、上記第１ＰＭＯＳトランジスターのソースから上記第１ＰＭＯＳトランジスターのドレインへアバランシェ降伏により大きな電流が流れる。 At this time, a current flows through the first circuit protection means. When the diode is used as the first circuit protection means, a large current flows due to avalanche breakdown from the cathode of the diode to the anode of the diode. When the PMOS transistor is used as the first circuit protection means, a large current flows due to avalanche breakdown from the source of the first PMOS transistor to the drain of the first PMOS transistor.
　従って、上記半導体装置の内部に流入するイミュニティノイズを上記接地端子に逃がすことが可能となり、上記半導体装置のイミュニティ耐性を向上させることが可能となる。特に、表示パネル駆動用ＬＳＩのイミュニティ耐性を向上させることが可能となる。 Therefore, immunity noise flowing into the semiconductor device can be released to the ground terminal, and the immunity resistance of the semiconductor device can be improved. In particular, it is possible to improve the immunity resistance of the display panel driving LSI.
　また、上記電圧供給端子と上記内部回路との間に上記抵抗体を介することで、上記内部回路に流入する電流を低減させている。 Also, the current flowing into the internal circuit is reduced by interposing the resistor between the voltage supply terminal and the internal circuit.
　さらに、上記第１回路保護手段として上記ダイオードを用いる場合、通常のアバランシェダイオードを用いているので、高いツェナー電圧を有するツェナーダイオードやコンデンサーを形成する必要が無い。 Furthermore, when the diode is used as the first circuit protection means, since a normal avalanche diode is used, it is not necessary to form a Zener diode or capacitor having a high Zener voltage.
　上記半導体装置では、第２回路保護手段をさらに備え、上記第２回路保護手段の一端は、上記抵抗体の上記他端に接続され、上記第２回路保護手段の他端は、上記接地端子に接続され、上記第２回路保護手段は、ダイオード、ＰＭＯＳトランジスター、ＮＭＯＳトランジスター、バイポーラトランジスター及びサイリスター構造を有するもののいずれか１つであってもよい。 The semiconductor device further includes second circuit protection means, one end of the second circuit protection means is connected to the other end of the resistor, and the other end of the second circuit protection means is connected to the ground terminal. The connected second circuit protection means may be any one of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure.
　上記第１回路保護手段のみを備え、上記第２回路保護手段を備えない半導体装置においては、ＨＢＭモデルやＭＭモデルでの静電破壊試験時のサージノイズは、上記抵抗体を通った後に上記接地端子にサージノイズが向かう。例えば上記第１回路保護手段として上記ダイオードを用いる場合、上記ダイオードの逆方向特性を利用して上記接地端子に上記サージノイズを逃がすが、この場合、上記抵抗体を介するので上記ダイオードの逆方向特性が悪くなり、耐量が低下する場合がある。 In a semiconductor device that includes only the first circuit protection means and does not include the second circuit protection means, surge noise during an electrostatic breakdown test in the HBM model or MM model is caused by the grounding after passing through the resistor. Surge noise goes to the terminal. For example, when the diode is used as the first circuit protection means, the surge noise is released to the ground terminal by utilizing the reverse direction characteristic of the diode. In this case, the reverse direction characteristic of the diode is provided through the resistor. May worsen and the tolerance may decrease.
　電源ラインとグランドラインとの間に上記第２回路保護手段を備えることにより、ＨＢＭモデルやＭＭモデルでの静電破壊試験時のサージノイズは、上記抵抗体を介することなく、上記第２回路保護手段を経由して、上記接地端子へ逃げることができる。このため、ＨＢＭモデルやＭＭモデルでの静電破壊試験時の耐量の向上が図られる。 By providing the second circuit protection means between the power supply line and the ground line, surge noise during the electrostatic breakdown test in the HBM model or MM model can be protected without passing through the resistor. It is possible to escape to the ground terminal via the means. For this reason, the tolerance of the electrostatic breakdown test in the HBM model and the MM model can be improved.
　上記半導体装置では、上記内部回路の、入力端子または出力端子に一端が接続され、上記第１回路保護手段の一端に他端が接続される第３回路保護手段をさらに備えてもよい。 The semiconductor device may further include third circuit protection means having one end connected to the input terminal or the output terminal of the internal circuit and the other end connected to one end of the first circuit protection means.
　また、上記半導体装置では、上記第３回路保護手段は、ダイオード、ＰＭＯＳトランジスター、ＮＭＯＳトランジスター、バイポーラトランジスター及びサイリスター構造を有するもののいずれか１つであってもよい。 In the semiconductor device, the third circuit protection means may be any one of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure.
　これにより、ＨＢＭモデルやＭＭモデルにおいて静電破壊試験を行う時のサージノイズは、抵抗体Ｒを介することなく、上記第１回路保護手段を経由して、グランド端子へ逃げることができる。このため、ＨＢＭモデルやＭＭモデルでの静電破壊試験時の耐量の向上が図られる。 Thus, surge noise when performing the electrostatic breakdown test in the HBM model or MM model can escape to the ground terminal via the first circuit protection means without passing through the resistor R. For this reason, the tolerance of the electrostatic breakdown test in the HBM model and the MM model can be improved.
　上記いずれかの半導体装置では、前記電圧供給端子と、前記接地端子とは、上記半導体装置を形成する、半導体基板の同じ面に形成されてもよい。 In any of the above semiconductor devices, the voltage supply terminal and the ground terminal may be formed on the same surface of the semiconductor substrate forming the semiconductor device.
　これにより、上記第１回路保護手段を備え、かつＣＯＦ（Chip On Film）実装を行う半導体装置を実現できる。 Thereby, it is possible to realize a semiconductor device including the first circuit protection means and performing COF (Chip On Film) mounting.
　上記いずれかの半導体装置では、上記抵抗体は、多結晶シリコン膜、または多結晶シリコン膜と高融点金属膜とを積層した膜であってもよい。 In any of the above semiconductor devices, the resistor may be a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are stacked.
　これにより、上記内部回路に流入する電流を低減することが可能となる。 This makes it possible to reduce the current flowing into the internal circuit.
　本発明の半導体装置は、以上のように、第１回路保護手段の一端及び抵抗体の一端は、電圧供給端子に接続され、上記第１回路保護手段の他端は、接地端子に接続され、上記第１回路保護手段は、ダイオード、ＰＭＯＳトランジスター、ＮＭＯＳトランジスター、バイポーラトランジスター及びサイリスター構造を有するもののいずれか１つであるものである。 In the semiconductor device of the present invention, as described above, one end of the first circuit protection unit and one end of the resistor are connected to the voltage supply terminal, and the other end of the first circuit protection unit is connected to the ground terminal. The first circuit protection means is any one of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure.
　それゆえ、内部に流入するイミュニティノイズを接地端子に逃がすことで、イミュニティ耐性を向上させる半導体装置を提供するという効果を奏する。 Therefore, there is an effect of providing a semiconductor device that improves immunity resistance by escaping immunity noise flowing into the interior to the ground terminal.
本発明の実施例に係る静電気放電保護回路の横断面図である。1 is a cross-sectional view of an electrostatic discharge protection circuit according to an embodiment of the present invention. 本発明の実施例に係る静電気放電保護回路の等価回路である。It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on the Example of this invention. 本発明の他の実施例に係る静電気放電保護回路の横断面図である。It is a cross-sectional view of an electrostatic discharge protection circuit according to another embodiment of the present invention. 本発明の他の実施例に係る静電気放電保護回路の等価回路である。6 is an equivalent circuit of an electrostatic discharge protection circuit according to another embodiment of the present invention. 本発明のさらに別の実施例に係る静電気放電保護回路の横断面図である。It is a cross-sectional view of an electrostatic discharge protection circuit according to still another embodiment of the present invention. 本発明のさらに別の実施例に係る静電気放電保護回路の等価回路である。It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on another Example of this invention. 本発明のさらに別の実施例に係る静電気放電保護回路の等価回路である。It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on another Example of this invention. 本発明のさらに別の実施例に係る静電気放電保護回路の等価回路である。It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on another Example of this invention. 本発明のさらに別の実施例に係る静電気放電保護回路の等価回路である。It is the equivalent circuit of the electrostatic discharge protection circuit which concerns on another Example of this invention. 本発明の実施例に係る静電気放電保護回路を備える半導体装置における、ＨＢＭモデルまたはＭＭモデルでのサージノイズの経路を示すブロック図である。It is a block diagram which shows the path | route of the surge noise in a HBM model or a MM model in a semiconductor device provided with the electrostatic discharge protection circuit based on the Example of this invention. 本発明の他の実施例に係る静電気放電保護回路を備える半導体装置における、ＨＢＭモデルまたはＭＭモデルでのサージノイズの経路を示すブロック図である。It is a block diagram which shows the path | route of the surge noise in a HBM model or a MM model in a semiconductor device provided with the electrostatic discharge protection circuit which concerns on the other Example of this invention. 本発明のさらに別の実施例に係る静電気放電保護回路を備える半導体装置における、ＨＢＭモデルまたはＭＭモデルでのサージノイズの経路を示すブロック図である。It is a block diagram which shows the path | route of the surge noise in a HBM model or a MM model in a semiconductor device provided with the electrostatic discharge protection circuit which concerns on another Example of this invention. 本発明のさらに別の実施例に係る静電気放電保護回路を備える半導体装置における、ＨＢＭモデルまたはＭＭモデルでのサージノイズの経路を示すブロック図である。It is a block diagram which shows the path | route of the surge noise in a HBM model or a MM model in a semiconductor device provided with the electrostatic discharge protection circuit which concerns on another Example of this invention. 本発明のさらに別の実施例に係る静電気放電保護回路を備える半導体装置における、ＨＢＭモデルまたはＭＭモデルでのサージノイズの経路を示すブロック図である。It is a block diagram which shows the path | route of the surge noise in a HBM model or a MM model in a semiconductor device provided with the electrostatic discharge protection circuit which concerns on another Example of this invention. IEC-61000-4-2試験用高電圧印加機の概略構成を示す回路図である。It is a circuit diagram which shows schematic structure of the high voltage applicator for IEC-61000-4-2 testing. IEC-61000-4-2試験用高電圧印加機が出力する電流の波形図である。It is a wave form diagram of the electric current which the IEC-61000-4-2 test high voltage applicator outputs.
　本発明の一実施形態について実施例１～実施例９、及び図１～図１４に基づいて説明すれば、以下の通りである。 An embodiment of the present invention will be described below with reference to Examples 1 to 9 and FIGS. 1 to 14.
　〔実施例１〕
　図１は、本実施例１に係る静電気放電保護回路１０の横断面図である。静電気放電保護回路１０では、ボロンを注入したＰ型半導体基板１に厚さ（Ｙ方向の長さ）が０．２μｍ～０．８μｍの酸化膜で素子分離部２を形成する。Ｐ型半導体基板１の基板濃度は、１×１０１５　／ｃｍ３～１×１０１８　／ｃｍ３である。 [Example 1]
FIG. 1 is a cross-sectional view of the electrostatic discharge protection circuit 10 according to the first embodiment. In the electrostatic discharge protection circuit 10, the element isolation part 2 is formed of an oxide film having a thickness (length in the Y direction) of 0.2 μm to 0.8 μm on the P-type semiconductor substrate 1 implanted with boron. The substrate concentration of the P-type semiconductor substrate 1 is 1 × 10 15 / cm 3 to 1 × 10 18 / cm 3 .
　Ｐ型半導体基板１の表面１ａの内側（Ｙ＜０）に、リンや砒素を注入したＮ型不純物領域３とボロンを注入したＰ型不純物領域４とを形成する。Ｎ型不純物領域３の不純物濃度は、１×１０１８　／ｃｍ３～５×１０２０　／ｃｍ３であり、Ｐ型不純物領域４の不純物濃度は１×１０１８　／ｃｍ３～５×１０２０　／ｃｍ３である。 Inside the surface 1a of the P-type semiconductor substrate 1 (Y <0), an N-type impurity region 3 implanted with phosphorus or arsenic and a P-type impurity region 4 implanted with boron are formed. The impurity concentration of the N-type impurity region 3 is 1 × 10 18 / cm 3 to 5 × 10 20 / cm 3 , and the impurity concentration of the P-type impurity region 4 is 1 × 10 18 / cm 3 to 5 × 10 20 / cm 3. cm 3 .
　また、Ｐ型半導体基板１の表面１ａ上（Ｙ＞０）に、多層膜５を形成する。多層膜５は、厚さが５０ｎｍ～５００ｎｍであり、リンや砒素、ボロンなどを注入した多結晶シリコン膜であるか、または多結晶シリコン膜と高融点金属膜とを積層した膜である。 Also, the multilayer film 5 is formed on the surface 1a of the P-type semiconductor substrate 1 (Y> 0). The multilayer film 5 is a polycrystalline silicon film having a thickness of 50 nm to 500 nm and implanted with phosphorus, arsenic, boron, or the like, or a film in which a polycrystalline silicon film and a refractory metal film are laminated.
　その後、Ｐ型半導体基板１の表面１ａ上（Ｙ＞０）に、厚さが１００ｎｍ～１５００ｎｍの層間絶縁膜６を形成し、接続穴を開口後、厚さが１００ｎｍ～１５００ｎｍの、アルミ合金、チタン合金または銅、もしくはアルミ合金、チタン合金及び銅の少なくとも１つを含む多層膜から成るメタル配線７～メタル配線９を形成する。 Thereafter, an interlayer insulating film 6 having a thickness of 100 nm to 1500 nm is formed on the surface 1a of the P-type semiconductor substrate 1 (Y> 0), and after opening the connection holes, an aluminum alloy having a thickness of 100 nm to 1500 nm, Metal wiring 7 to metal wiring 9 made of a multilayer film containing at least one of titanium alloy or copper, or aluminum alloy, titanium alloy and copper are formed.
　本実施例１では、Ｎ型不純物領域３、Ｐ型半導体基板１及びＰ型不純物領域４がダイオードＤを形成している。Ｎ型不純物領域３がダイオードＤのカソード電極であり、Ｐ型不純物領域４がダイオードＤのアノード電極である。Ｐ型半導体基板１は、ダイオードＤの本体を構成する。 In the first embodiment, the N-type impurity region 3, the P-type semiconductor substrate 1, and the P-type impurity region 4 form a diode D. The N-type impurity region 3 is a cathode electrode of the diode D, and the P-type impurity region 4 is an anode electrode of the diode D. The P-type semiconductor substrate 1 constitutes the main body of the diode D.
　また、多結晶シリコン膜、または多結晶シリコン膜と高融点金属膜とを積層した膜である多層膜５は、抵抗体Ｒを形成している。 The multilayer film 5 which is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated forms a resistor R.
　さらに、メタル配線７は、Ｐ型不純物領域４と、静電気放電保護回路１０が接続される半導体装置のグランド端子（接地端子）とを接続する。メタル配線８は、Ｎ型不純物領域３、多層膜５及び上記半導体装置の電源端子を接続するか、Ｎ型不純物領域３、多層膜５及び上記半導体装置の基準電源端子を接続する。メタル配線９は、多層膜５と上記半導体装置の内部回路とを接続する。電源端子及び基準電源端子は、電圧供給端子である。 Furthermore, the metal wiring 7 connects the P-type impurity region 4 and the ground terminal (ground terminal) of the semiconductor device to which the electrostatic discharge protection circuit 10 is connected. The metal wiring 8 connects the N-type impurity region 3, the multilayer film 5 and the power supply terminal of the semiconductor device, or connects the N-type impurity region 3, the multilayer film 5 and the reference power supply terminal of the semiconductor device. The metal wiring 9 connects the multilayer film 5 and the internal circuit of the semiconductor device. The power supply terminal and the reference power supply terminal are voltage supply terminals.
　図２は、静電気放電保護回路１０の等価回路である。図２の等価回路では、電源端子または基準電源端子とグランド端子との間にダイオードＤを設けて、イミュニティノイズを逃がすと共に、電源端子または基準電源端子と上記半導体装置の内部回路との間に抵抗体Ｒを介することで半導体装置内部回路に流入する電流を低減させている。 FIG. 2 is an equivalent circuit of the electrostatic discharge protection circuit 10. In the equivalent circuit of FIG. 2, a diode D is provided between the power supply terminal or the reference power supply terminal and the ground terminal to release immunity noise, and a resistor is provided between the power supply terminal or the reference power supply terminal and the internal circuit of the semiconductor device. The current flowing into the internal circuit of the semiconductor device is reduced by passing through the body R.
　抵抗体Ｒの抵抗値は、ＬＳＩの動作時にＬＳＩ内部の電源ラインに流れる電流と、ＬＳＩの動作時に抵抗体Ｒにより生じる電圧降下とを考慮して選ぶ必要があり、通常は１Ω～１０Ω程度の抵抗値を選ぶことが望ましい。また、ダイオードＤは複数に分割したものを並列に接続しても良いが、その総周囲長は１０００μｍ～２００００μｍの範囲で選ぶことが望ましい。 The resistance value of the resistor R needs to be selected in consideration of the current flowing through the power supply line inside the LSI during LSI operation and the voltage drop caused by the resistor R during LSI operation, and is usually about 1Ω to 10Ω. It is desirable to select a resistance value. The diode D may be divided into a plurality of diodes and connected in parallel, but the total perimeter is preferably selected in the range of 1000 μm to 20000 μm.
　以上のように、本実施例１に係る静電気放電保護回路１０では、上記半導体装置の内部に流入するイミュニティノイズが流入する場合、ダイオードＤに逆バイアスの電圧が印加され、該逆バイアスの電圧が、ダイオードＤの降伏電圧を上回る。 As described above, in the electrostatic discharge protection circuit 10 according to the first embodiment, when immunity noise that flows into the semiconductor device flows, a reverse bias voltage is applied to the diode D, and the reverse bias voltage is , Exceeding the breakdown voltage of the diode D.
　この時、ダイオードＤのカソードからダイオードＤのアノードへらアバランシェ降伏により大きな電流が流れる。これにより、上記半導体装置の内部に流入するイミュニティノイズをグランド端子に逃がすことが可能となり、上記半導体装置のイミュニティ耐性を向上させることが可能となる。特に、表示パネル駆動用ＬＳＩのイミュニティ耐性を向上させることが可能となる。 At this time, a large current flows from the cathode of the diode D to the anode of the diode D due to avalanche breakdown. As a result, immunity noise flowing into the semiconductor device can be released to the ground terminal, and the immunity resistance of the semiconductor device can be improved. In particular, it is possible to improve the immunity resistance of the display panel driving LSI.
　本実施例１に係る静電気放電保護回路１０は、通常のアバランシェダイオードを用いているので、高いツェナー電圧を有するツェナーダイオードやコンデンサーを形成する必要が無い。また、電極（ダイオードＤのカソード電極、ダイオードＤのアノード電極）は、Ｐ型半導体基板１の表面１ａ側にのみ形成できる。これらの理由から、本実施例１に係る静電気放電保護回路１０は、ＣＯＦ（Chip On Film）実装を行う半導体装置に適している。 Since the electrostatic discharge protection circuit 10 according to the first embodiment uses a normal avalanche diode, it is not necessary to form a Zener diode or a capacitor having a high Zener voltage. Further, the electrodes (the cathode electrode of the diode D and the anode electrode of the diode D) can be formed only on the surface 1 a side of the P-type semiconductor substrate 1. For these reasons, the electrostatic discharge protection circuit 10 according to the first embodiment is suitable for a semiconductor device that performs COF (Chip-On-Film) mounting.
　〔実施例２〕
　図３は、本実施例２に係る静電気放電保護回路２０の横断面図である。静電気放電保護回路２０では、ボロンを注入したＰ型半導体基板２１に厚さが０．２μｍ～０．８μｍの酸化膜で素子分離部２２を形成する。Ｐ型半導体基板２１の基板濃度は、１×１０１５　／ｃｍ３～１×１０１８　／ｃｍ３である。 [Example 2]
FIG. 3 is a cross-sectional view of the electrostatic discharge protection circuit 20 according to the second embodiment. In the electrostatic discharge protection circuit 20, the element isolation portion 22 is formed of an oxide film having a thickness of 0.2 μm to 0.8 μm on the P-type semiconductor substrate 21 into which boron is implanted. The substrate concentration of the P-type semiconductor substrate 21 is 1 × 10 15 / cm 3 to 1 × 10 18 / cm 3 .
　Ｐ型半導体基板２１の表面２１ａの内側（Ｙ＜０）側に、リンや砒素を注入した、Ｎ型不純物領域２３ａ及びＮ型不純物領域２３ｂ、並びにボロンを注入した、Ｐ型不純物領域２４ａ及びＰ型不純物領域２４ｂを形成する。Ｎ型不純物領域２３ａ及びＮ型不純物領域２３ｂの不純物濃度は、１×１０１８　／ｃｍ３～５×１０２０　／ｃｍ３であり、Ｐ型不純物領域２４ａ及びＰ型不純物領域２４ｂの不純物濃度は、１×１０１８　／ｃｍ３～５×１０２０　／ｃｍ３である。 On the inside (Y <0) side of the surface 21a of the P-type semiconductor substrate 21, N-type impurity regions 23a and N-type impurity regions 23b implanted with phosphorus or arsenic, and P-type impurity regions 24a and P implanted with boron. A type impurity region 24b is formed. The impurity concentration of the N-type impurity region 23a and the N-type impurity region 23b is 1 × 10 18 / cm 3 to 5 × 10 20 / cm 3 , and the impurity concentration of the P-type impurity region 24a and the P-type impurity region 24b is 1 × 10 18 / cm 3 to 5 × 10 20 / cm 3 .
　また、Ｐ型半導体基板２１の表面２１ａ上（Ｙ＞０）に、多層膜２５を形成する。多層膜２５は、厚さが５０ｎｍ～５００ｎｍであり、リンや砒素、ボロンなどを注入した多結晶シリコン膜であるか、または多結晶シリコン膜と高融点金属膜とを積層した膜である。 Further, the multilayer film 25 is formed on the surface 21a (Y> 0) of the P-type semiconductor substrate 21. The multilayer film 25 has a thickness of 50 nm to 500 nm and is a polycrystalline silicon film into which phosphorus, arsenic, boron, or the like is implanted, or a film in which a polycrystalline silicon film and a refractory metal film are stacked.
　その後、Ｐ型半導体基板２１の表面２１ａ上（Ｙ＞０）に、厚さが１００ｎｍ～１５００ｎｍの層間絶縁膜２６を形成し、接続穴を開口後、厚さが１００ｎｍ～１５００ｎｍの、アルミ合金、チタン合金または銅、もしくはアルミ合金、チタン合金及び銅の少なくとも１つを含む多層膜から成るメタル配線２７～メタル配線２９を形成する。 Thereafter, an interlayer insulating film 26 having a thickness of 100 nm to 1500 nm is formed on the surface 21a of the P-type semiconductor substrate 21 (Y> 0), and after opening the connection holes, an aluminum alloy having a thickness of 100 nm to 1500 nm, Metal wiring 27 to metal wiring 29 made of a multilayer film containing at least one of titanium alloy or copper, or aluminum alloy, titanium alloy and copper are formed.
　本実施例２では、Ｎ型不純物領域２３ａ、Ｐ型半導体基板２１及びＰ型不純物領域２４ａが第１のダイオードＤ１を形成しており、Ｎ型不純物領域２３ｂ、Ｐ型半導体基板２１及びＰ型不純物領域２４ｂが第２のダイオードＤ２を形成している。 In the second embodiment, the N-type impurity region 23a, the P-type semiconductor substrate 21 and the P-type impurity region 24a form the first diode D1, and the N-type impurity region 23b, the P-type semiconductor substrate 21 and the P-type impurity are formed. Region 24b forms second diode D2.
　Ｎ型不純物領域２３ａが第１のダイオードＤ１のカソード電極であり、Ｐ型不純物領域２４ａが第１のダイオードＤ１のアノード電極であり、Ｐ型半導体基板２１は、第１のダイオードＤ１の本体を構成する。同様に、Ｎ型不純物領域２３ｂが第２のダイオードＤ２のカソード電極であり、Ｐ型不純物領域２４ｂが第２のダイオードＤ２のアノード電極であり、Ｐ型半導体基板２１は、第２のダイオードＤ２の本体を構成する。 The N-type impurity region 23a is the cathode electrode of the first diode D1, the P-type impurity region 24a is the anode electrode of the first diode D1, and the P-type semiconductor substrate 21 constitutes the main body of the first diode D1. To do. Similarly, the N-type impurity region 23b is the cathode electrode of the second diode D2, the P-type impurity region 24b is the anode electrode of the second diode D2, and the P-type semiconductor substrate 21 is connected to the second diode D2. Configure the body.
　さらに、多結晶シリコン膜、または多結晶シリコン膜と高融点金属膜とを積層した膜である多層膜２５は、抵抗体Ｒを形成している。 Furthermore, the multilayer film 25 which is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated forms a resistor R.
　メタル配線２７は、Ｐ型不純物領域２４ａと、静電気放電保護回路２０が接続される半導体装置のグランド端子とを接続する。メタル配線２８は、Ｎ型不純物領域２３ａ、多層膜２５及び上記半導体装置の電源端子を接続するか、Ｎ型不純物領域２３ａ、多層膜２５及び上記半導体装置の基準電源端子を接続する。メタル配線２９は、多層膜２５、Ｎ型不純物領域２３ｂ及び上記半導体装置の内部回路を接続する。 The metal wiring 27 connects the P-type impurity region 24a and the ground terminal of the semiconductor device to which the electrostatic discharge protection circuit 20 is connected. The metal wiring 28 connects the N-type impurity region 23a, the multilayer film 25, and the power supply terminal of the semiconductor device, or connects the N-type impurity region 23a, the multilayer film 25, and the reference power supply terminal of the semiconductor device. The metal wiring 29 connects the multilayer film 25, the N-type impurity region 23b, and the internal circuit of the semiconductor device.
　なお、図３には図示していないが、Ｐ型不純物領域２４ｂは、Ｐ型不純物領域２４ａと同様に、上記半導体装置のグランド端子に接続される。 Although not shown in FIG. 3, the P-type impurity region 24b is connected to the ground terminal of the semiconductor device in the same manner as the P-type impurity region 24a.
　図４は、静電気放電保護回路２０の等価回路である。図４の等価回路では、電源端子または基準電源端子とグランド端子との間に第１のダイオードＤ１を設け、イミュニティノイズを逃がすと共に、電源端子または基準電源端子と上記半導体装置の内部回路との間に抵抗体Ｒを介することで、上記半導体装置の内部回路に流入する電流を低減させている。 FIG. 4 is an equivalent circuit of the electrostatic discharge protection circuit 20. In the equivalent circuit of FIG. 4, the first diode D1 is provided between the power supply terminal or the reference power supply terminal and the ground terminal to release immunity noise, and between the power supply terminal or the reference power supply terminal and the internal circuit of the semiconductor device. Further, the current flowing into the internal circuit of the semiconductor device is reduced through the resistor R.
　また、静電破壊試験には、試験規格IEC-61000-4-2の他にも、ＨＢＭモデル（human-body model：人体モデル）やＭＭモデル（machine model：マシン・モデル）による規格も存在する。ＨＢＭモデルやＭＭモデルでの静電破壊試験では、グランド端子を基準とした、入力端子や出力端子へのサージ印加試験の項目がある。 In addition to the test standard IEC-61000-4-2, the electrostatic breakdown test includes standards based on the HBM model (human-body model) and MM model (machine model). . In the electrostatic breakdown test in the HBM model and the MM model, there is an item of a surge application test to the input terminal and the output terminal based on the ground terminal.
　入力端子や出力端子へ、静電気などのサージノイズが印加される場合、図１０及び図１１に示されるように、入力端子や出力端子から入ったサージノイズは、入力端子や出力端子に設置された静電気保護素子や内部回路の中を通ってグランド端子へと向かう。 When surge noise such as static electricity is applied to the input terminal and output terminal, as shown in FIG. 10 and FIG. 11, surge noise entered from the input terminal and output terminal is installed at the input terminal and output terminal. It goes to the ground terminal through the electrostatic protection element and internal circuit.
　実施例１の静電気放電保護回路１０を備える場合、図１０に示すように、抵抗体Ｒを通った後にダイオードの逆方向特性を利用してグランド端子にサージノイズが向かうのであるが、抵抗体Ｒを介するのでダイオードの逆方向特性が悪くなり耐量が低下する場合がある。 When the electrostatic discharge protection circuit 10 according to the first embodiment is provided, as shown in FIG. 10, surge noise is directed to the ground terminal using the reverse characteristics of the diode after passing through the resistor R. Therefore, the reverse characteristics of the diode may be deteriorated and the withstand capability may be reduced.
　本実施例２の静電気放電保護回路２０を備える場合、図１１に示すように、電源ラインＰとグランドラインＧとの間に第２のダイオードＤ２を設けており、ＨＢＭモデルやＭＭモデルでの静電破壊試験時のサージノイズは、抵抗体Ｒを介することなく、第２のダイオードＤ２を経由して、グランド端子へ逃げることができる。このため、ＨＢＭモデルやＭＭモデルでの静電破壊試験時の耐量の向上が図られる。 When the electrostatic discharge protection circuit 20 according to the second embodiment is provided, as shown in FIG. 11, a second diode D2 is provided between the power supply line P and the ground line G, and static electricity in the HBM model and the MM model is provided. Surge noise during the electric breakdown test can escape to the ground terminal via the second diode D2 without passing through the resistor R. For this reason, the tolerance of the electrostatic breakdown test in the HBM model and the MM model can be improved.
　抵抗体Ｒの抵抗値は、実施例１と同様に１Ω～１０Ω程度の抵抗値を選ぶことが望ましい。各ダイオードについては、実施例１と同様に、複数に分割したものを並列に接続しても良いが、第１のダイオードＤ１の総周囲長は１０００μｍ～２００００μｍの範囲から選ぶことが望ましく、第２のダイオードＤ２の総周囲長は１０００～１００００ｕｍの範囲から選ぶことが望ましい。 As for the resistance value of the resistor R, it is desirable to select a resistance value of about 1Ω to 10Ω as in the first embodiment. As for each diode, a plurality of divided diodes may be connected in parallel as in the first embodiment, but the total perimeter of the first diode D1 is preferably selected from the range of 1000 μm to 20000 μm, The total perimeter of the diode D2 is preferably selected from the range of 1000 to 10,000 um.
　なお、電極（ダイオードＤ１のカソード電極、ダイオードＤ１のアノード電極、ダイオードＤ２のカソード電極、ダイオードＤ２のアノード電極）は、Ｐ型半導体基板２１の表面２１ａ側にのみ形成できる。これらの理由から、本実施例２に係る静電気放電保護回路２０は、ＣＯＦ（Chip On Film）実装を行う半導体装置に適している。 Note that the electrodes (the cathode electrode of the diode D1, the anode electrode of the diode D1, the cathode electrode of the diode D2, and the anode electrode of the diode D2) can be formed only on the surface 21a side of the P-type semiconductor substrate 21. For these reasons, the electrostatic discharge protection circuit 20 according to the second embodiment is suitable for a semiconductor device in which COF (Chip On On Film) mounting is performed.
　〔実施例３〕
　図５は、本実施例３に係る静電気放電保護回路３０の横断面図である。静電気放電保護回路３０では、ボロンを注入したＰ型半導体基板３１にさらにリンを注入し、Ｎ型不純物ウェル３２をＰ型半導体基板３１内に形成する。また、Ｐ型半導体基板３１には、厚さ（Ｙ方向の長さ）が０．２μｍ～０．８μｍの酸化膜で素子分離部３３を形成する。 Example 3
FIG. 5 is a cross-sectional view of the electrostatic discharge protection circuit 30 according to the third embodiment. In the electrostatic discharge protection circuit 30, phosphorus is further injected into the P-type semiconductor substrate 31 into which boron has been injected, and an N-type impurity well 32 is formed in the P-type semiconductor substrate 31. Further, the element isolation portion 33 is formed on the P-type semiconductor substrate 31 with an oxide film having a thickness (length in the Y direction) of 0.2 μm to 0.8 μm.
　Ｐ型半導体基板３１の基板濃度は、１×１０１５　／ｃｍ３～１×１０１８　／ｃｍ３である。Ｎ型不純物ウェル３２の不純物濃度は、１×１０１５　／ｃｍ３～１×１０１８　／ｃｍ３であり、Ｎ型不純物ウェル３２の深さは（Ｙ方向の長さ）は、０．５μｍ～５μｍである。 The substrate concentration of the P-type semiconductor substrate 31 is 1 × 10 15 / cm 3 to 1 × 10 18 / cm 3 . The impurity concentration of the N-type impurity well 32 is 1 × 10 15 / cm 3 to 1 × 10 18 / cm 3 , and the depth (the length in the Y direction) of the N-type impurity well 32 is 0.5 μm to 5 μm.
　Ｐ型半導体基板３１の表面３１ａ上（Ｙ＞０）に、厚さが１０ｎｍ～１００ｎｍの酸化膜３４と、厚さが５０ｎｍ～５００ｎｍの多層膜３５とでゲート電極を形成する。多層膜３５は、リンや砒素、ボロンなどを注入した多結晶シリコン膜であるか、または多結晶シリコン膜と高融点金属膜とを積層した膜である。 A gate electrode is formed on the surface 31a of the P-type semiconductor substrate 31 (Y> 0) with the oxide film 34 having a thickness of 10 nm to 100 nm and the multilayer film 35 having a thickness of 50 nm to 500 nm. The multilayer film 35 is a polycrystalline silicon film implanted with phosphorus, arsenic, boron, or the like, or a film in which a polycrystalline silicon film and a refractory metal film are stacked.
　Ｐ型半導体基板３１の表面３１ａの内側（Ｙ＜０）側に、ボロンを注入したＰ型不純物領域３６ａでドレイン領域を形成する。同様に、Ｐ型半導体基板３１の表面３１ａの内側（Ｙ＜０）側に、ボロンを注入したＰ型不純物領域３６ｂでソース領域を形成する。Ｐ型不純物領域３６ａ及びＰ型不純物領域３６ｂの不純物濃度は、１×１０１８　／ｃｍ３～５×１０２０　／ｃｍ３である。 On the inner side (Y <0) side of the surface 31a of the P-type semiconductor substrate 31, a drain region is formed by a P-type impurity region 36a into which boron is implanted. Similarly, a source region is formed by a P-type impurity region 36b implanted with boron on the inner side (Y <0) side of the surface 31a of the P-type semiconductor substrate 31. The impurity concentration of the P-type impurity region 36a and the P-type impurity region 36b is 1 × 10 18 / cm 3 to 5 × 10 20 / cm 3 .
　また、リンや砒素を注入したＮ型不純物領域３７でＮウェルコンタクト領域を形成する。Ｎ型不純物領域３７の不純物濃度は、１×１０１８　／ｃｍ３～５×１０２０　／ｃｍ３である。 Further, an N well contact region is formed by an N type impurity region 37 implanted with phosphorus or arsenic. The impurity concentration of the N-type impurity region 37 is 1 × 10 18 / cm 3 to 5 × 10 20 / cm 3 .
　さらに必要に応じて、Ｐ型半導体基板３１の表面３１ａの内側（Ｙ＜０）側の、酸化膜３４と対向する位置に、閾値電圧を調整するためのチャンネル注入領域３８を形成する。 Further, if necessary, a channel injection region 38 for adjusting the threshold voltage is formed at a position facing the oxide film 34 on the inner side (Y <0) side of the surface 31a of the P-type semiconductor substrate 31.
　また、Ｐ型半導体基板３１の表面３１ａ上（Ｙ＞０）に、多層膜３９を形成する。多層膜３９は、厚さが５０ｎｍ～５００ｎｍであり、リンや砒素、ボロンなどを注入した多結晶シリコン膜であるか、または多結晶シリコン膜と高融点金属膜とを積層した膜である。 Also, a multilayer film 39 is formed on the surface 31a of the P-type semiconductor substrate 31 (Y> 0). The multilayer film 39 has a thickness of 50 nm to 500 nm and is a polycrystalline silicon film in which phosphorus, arsenic, boron, or the like is implanted, or a film in which a polycrystalline silicon film and a refractory metal film are stacked.
　その後、Ｐ型半導体基板３１の表面３１ａ上（Ｙ＞０）に、厚さが１００ｎｍ～１５００ｎｍの層間絶縁膜４１を形成し、接続穴を開口後、厚さが１００ｎｍ～１５００ｎｍの、アルミ合金、チタン合金または銅、もしくはアルミ合金、チタン合金及び銅の少なくとも１つを含む多層膜から成るメタル配線４２～メタル配線４４を形成する。 Thereafter, an interlayer insulating film 41 having a thickness of 100 nm to 1500 nm is formed on the surface 31a of the P-type semiconductor substrate 31 (Y> 0), and after opening the connection holes, an aluminum alloy having a thickness of 100 nm to 1500 nm, Metal wiring 42 to metal wiring 44 made of a multilayer film containing at least one of titanium alloy or copper, or aluminum alloy, titanium alloy and copper are formed.
　本実施例３では、Ｎ型不純物ウェル３２、酸化膜３４、多層膜３５、Ｐ型不純物領域３６ａ、Ｐ型不純物領域３６ｂ及びＮ型不純物領域３７がＰＭＯＳトランジスターＭＰを形成している。 In Example 3, N-type impurity well 32, oxide film 34, the multilayer film 35, P-type impurity region 36a, P-type impurity region 36b and the N-type impurity region 37 form a PMOS transistor M P.
　また、Ｐ型不純物領域３６ａはＰＭＯＳトランジスターＭＰのドレイン電極であり、Ｐ型不純物領域３６ｂはＰＭＯＳトランジスターＭＰのソース電極である。Ｎ型不純物領域３７はＰＭＯＳトランジスターＭＰのＮウェルコンタクト電極であり、多層膜３５はＰＭＯＳトランジスターＭＰのゲート電極である。Ｎ型不純物ウェル３２は、ＰＭＯＳトランジスターＭＰのＮウェル領域を構成する。 Further, P-type impurity region 36a is a drain electrode of the PMOS transistor M P, P-type impurity region 36b is the source electrode of the PMOS transistor M P. N-type impurity region 37 is an N-well contact electrode of the PMOS transistor M P, multilayer film 35 is a gate electrode of the PMOS transistor M P. N-type impurity well 32 constitutes the N-well region of the PMOS transistor M P.
　さらに、多結晶シリコン膜、または多結晶シリコン膜と高融点金属膜とを積層した膜である多層膜３９は、抵抗体Ｒを形成している。 Furthermore, the multilayer film 39 which is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated forms a resistor R.
　メタル配線４２は、Ｐ型不純物領域３６ａと、静電気放電保護回路３０が接続される半導体装置のグランド端子とを接続する。メタル配線４３は、Ｐ型不純物領域３６ｂ、Ｎ型不純物領域３７、多層膜３５、多層膜３９及び上記半導体装置の電源端子を接続するか、またはＰ型不純物領域３６ｂ、Ｎ型不純物領域３７、多層膜３５、多層膜３９及び上記半導体装置の基準電源端子を接続する。メタル配線４４は、多層膜３９と上記半導体装置の内部回路とを接続する。 The metal wiring 42 connects the P-type impurity region 36a and the ground terminal of the semiconductor device to which the electrostatic discharge protection circuit 30 is connected. The metal wiring 43 connects the P-type impurity region 36b, the N-type impurity region 37, the multilayer film 35, the multilayer film 39, and the power supply terminal of the semiconductor device, or connects the P-type impurity region 36b, the N-type impurity region 37, and the multilayer. The film 35, the multilayer film 39, and the reference power supply terminal of the semiconductor device are connected. The metal wiring 44 connects the multilayer film 39 and the internal circuit of the semiconductor device.
　図６は、静電気放電保護回路３０の等価回路である。図６の等価回路では、電源端子または基準電源端子とグランド端子との間に、ソース電極、ゲート電極及びＮウェルコンタクト電極を共通に接続したＰＭＯＳトランジスターＭＰを設けている。 FIG. 6 is an equivalent circuit of the electrostatic discharge protection circuit 30. In the equivalent circuit of FIG. 6, between the power supply terminal or the reference power supply terminal and the ground terminal is provided with a PMOS transistor M P connected source electrode, the gate electrode and the N-well contact electrode in common.
　図６の等価回路では、ＰＭＯＳトランジスターＭＰを設けることでイミュニティノイズを逃がすと共に、電源端子または基準電源端子と上記半導体装置の内部回路との間に抵抗体を介することで、上記半導体装置の内部回路に流入する電流を低減させている。 In the equivalent circuit of FIG. 6, by via with escape immunity noise by providing the PMOS transistor M P, a resistor between the internal circuit of the power supply terminal or the reference power terminal and said semiconductor device, the inside of the semiconductor device The current flowing into the circuit is reduced.
　抵抗体Ｒの抵抗値は、実施例１と同様に１Ω～１０Ω程度の抵抗値を選ぶことが望ましい。ＰＭＯＳトランジスターＭＰのチャンネル長は、０．５μｍ～１０μｍの範囲から選ぶことが望ましく、ＰＭＯＳトランジスターＭＰのチャンネル幅は、３００μｍ～７０００μｍの範囲から選ぶことが望ましい。 As for the resistance value of the resistor R, it is desirable to select a resistance value of about 1Ω to 10Ω as in the first embodiment. Channel length of the PMOS transistor M P is desirably chosen from the range of 0.5 [mu] m ~ 10 [mu] m, the channel width of the PMOS transistor M P is preferably selected from the range of 300μm ~ 7000μm.
　また、ＰＭＯＳトランジスターＭＰは、複数のＰＭＯＳトランジスターに分割したものを並列に接続しても良いが、その総チャンネル幅が３００ｕｍ～７０００ｕｍの範囲から選ぶことが望ましい。 Moreover, PMOS transistors M P may be connected to those division into a plurality of PMOS transistors in parallel, but the total channel width is desirably selected within the range of 300um ~ 7000um.
　以上のように、本実施例３に係る静電気放電保護回路３０では、上記半導体装置の内部にイミュニティノイズが流入する場合、ＰＭＯＳトランジスターＭＰのドレイン－ソース間電圧が、ＰＭＯＳトランジスターＭＰのドレイン－ソース間耐圧を上回る。 As described above, in the electrostatic discharge protection circuit 30 according to the third embodiment, when the internal Immunity noise of the semiconductor device flows, the drain of the PMOS transistor M P - source voltage, the drain of the PMOS transistor M P - The breakdown voltage between sources is exceeded.
　この時、ＰＭＯＳトランジスターＭＰのソースからＰＭＯＳトランジスターＭＰのドレインへアバランシェ降伏により大きな電流が流れる。これにより、上記半導体装置の内部に流入するイミュニティノイズを上記接地端子に逃がすことが可能となり、上記半導体装置のイミュニティ耐性を向上させることが可能となる。 In this case, a large current flows due to avalanche breakdown from the source of the PMOS transistor M P to the drain of the PMOS transistor M P. As a result, immunity noise flowing into the semiconductor device can be released to the ground terminal, and the immunity resistance of the semiconductor device can be improved.
　なお、電極（ＰＭＯＳトランジスターＭＰのゲート電極、ＰＭＯＳトランジスターＭＰのソース電極、ＰＭＯＳトランジスターＭＰのドレイン電極、ＰＭＯＳトランジスターＭＰのＮウェルコンタクト電極）は、Ｐ型半導体基板３１の表面３１ａ側にのみ形成できる。これらの理由から、本実施例３に係る静電気放電保護回路３０は、ＣＯＦ（Chip On Film）実装を行う半導体装置に適している。 The electrode (gate electrode of the PMOS transistor M P, the source electrode of the PMOS transistor M P, the drain electrode of the PMOS transistor M P, N well contact electrode of the PMOS transistor M P) is a surface 31a side of the P-type semiconductor substrate 31 Can only be formed. For these reasons, the electrostatic discharge protection circuit 30 according to the third embodiment is suitable for a semiconductor device that performs COF (Chip On Film) mounting.
　〔実施例４〕
　図７は、本実施例４の静電気放電保護回路４０の等価回路である。図７の等価回路では、実施例２の静電気放電保護回路２０と同様に、電源ラインＰとグランドラインＧとの間に、第２のＰＭＯＳトランジスターＭＰ２を設けている。電源端子または基準電源端子とグランド端子との間には、第１のＰＭＯＳトランジスターＭＰ１を設けている。 Example 4
FIG. 7 is an equivalent circuit of the electrostatic discharge protection circuit 40 of the fourth embodiment. In the equivalent circuit of FIG. 7, the second PMOS transistor MP2 is provided between the power supply line P and the ground line G, similarly to the electrostatic discharge protection circuit 20 of the second embodiment. A first PMOS transistor MP1 is provided between the power supply terminal or the reference power supply terminal and the ground terminal.
　静電気放電保護回路４０を備える半導体装置では、ＨＢＭモデルやＭＭモデルにおいて静電破壊試験を行う時のサージノイズは、抵抗体Ｒを介することなく、第２のＰＭＯＳトランジスターＭＰ２を経由して、グランド端子へ逃げることができる。このため、ＨＢＭモデルやＭＭモデルにおいて静電破壊試験を行う時の耐量の向上が図られる。 In a semiconductor device including the electrostatic discharge protection circuit 40, surge noise when performing an electrostatic breakdown test in the HBM model or the MM model passes through the second PMOS transistor MP2 without passing through the resistor R. You can escape to the terminal. For this reason, the tolerance of the electrostatic breakdown test in the HBM model or MM model can be improved.
　抵抗体Ｒの抵抗値は、実施例１と同様に１Ω～１０Ω程度の抵抗値を選ぶことが望ましい。各ＰＭＯＳトランジスターは、実施例３と同様に、複数に分割したものを並列に接続しても良いが、第１のＰＭＯＳトランジスターＭＰ１の総チャンネル幅は、３００μｍ～７０００μｍの範囲から選ぶことが望ましく、第２のＰＭＯＳトランジスターＭＰ２の総チャンネル幅は、３００μｍ～３５００μｍの範囲から選ぶことが望ましい。 As for the resistance value of the resistor R, it is desirable to select a resistance value of about 1Ω to 10Ω as in the first embodiment. Each PMOS transistors, as in Example 3, may be connected to those divided into a plurality in parallel, but the total channel width of the first PMOS transistor M P1 is desirably selected within the range of 300μm ~ 7000μm , the total channel width of the second PMOS transistor M P2, it is desirable to select from a range of 300μm ~ 3500μm.
　〔実施例５〕
　より一般的な静電気放電保護回路の等価回路は、本実施例５の図８、及び後述する実施例６の図９に示されるような等価回路となる。図８は、本実施例５の静電気放電保護回路５０の等価回路である。図８の等価回路では、静電気保護素子（第１回路保護手段）５１を１つ用いており、電源端子または基準電源端子とグランド端子との間に静電気保護素子５１を設けている。 Example 5
An equivalent circuit of a more general electrostatic discharge protection circuit is an equivalent circuit as shown in FIG. 8 of the fifth embodiment and FIG. 9 of the sixth embodiment described later. FIG. 8 is an equivalent circuit of the electrostatic discharge protection circuit 50 of the fifth embodiment. In the equivalent circuit of FIG. 8, one electrostatic protection element (first circuit protection means) 51 is used, and the electrostatic protection element 51 is provided between the power supply terminal or the reference power supply terminal and the ground terminal.
　図８の等価回路では、静電気保護素子５１を設けることで、イミュニティノイズを逃がすと共に、電源端子または基準電源端子と、静電気放電保護回路５０が接続される半導体装置の内部回路との間に、抵抗体Ｒを介することで、上記半導体装置の内部回路に流入する電流を低減させている。 In the equivalent circuit of FIG. 8, by providing the electrostatic protection element 51, immunity noise is released, and a resistance is provided between the power supply terminal or the reference power supply terminal and the internal circuit of the semiconductor device to which the electrostatic discharge protection circuit 50 is connected. By passing through the body R, the current flowing into the internal circuit of the semiconductor device is reduced.
　抵抗体Ｒの抵抗値は、実施例１と同様に１Ω～１０Ω程度の抵抗値を選ぶことが望ましい。 As for the resistance value of the resistor R, it is desirable to select a resistance value of about 1Ω to 10Ω as in the first embodiment.
　〔実施例６〕
　図９は、本実施例６の静電気放電保護回路６０の等価回路である。図９の等価回路では、静電気保護素子を２つ用いており、電源ラインＰとグランドラインＧとの間に第２の静電気保護素子（第２回路保護手段）６２を設けている。電源端子または基準電源端子とグランド端子との間には、第１の静電気保護素子（第１回路保護手段）６１を設けている。 Example 6
FIG. 9 is an equivalent circuit of the electrostatic discharge protection circuit 60 of the sixth embodiment. In the equivalent circuit of FIG. 9, two electrostatic protection elements are used, and a second electrostatic protection element (second circuit protection means) 62 is provided between the power supply line P and the ground line G. A first electrostatic protection element (first circuit protection means) 61 is provided between the power supply terminal or the reference power supply terminal and the ground terminal.
　静電気放電保護回路６０を備える半導体装置では、ＨＢＭモデルやＭＭモデルにおいて静電破壊試験を行う時のサージノイズは、抵抗体Ｒを介することなく、第２の静電気保護素子６２を経由して、グランド端子へ逃げることができる。このため、ＨＢＭモデルやＭＭモデルにおいて静電破壊試験を行う時の耐量の向上が図られる。 In a semiconductor device including the electrostatic discharge protection circuit 60, surge noise when performing an electrostatic breakdown test in the HBM model or the MM model passes through the second electrostatic protection element 62 and does not pass through the resistor R. You can escape to the terminal. For this reason, the tolerance of the electrostatic breakdown test in the HBM model or MM model can be improved.
　抵抗体Ｒの抵抗値は、実施例１と同様に１Ω～１０Ω程度の抵抗値を選ぶことが望ましい。 As for the resistance value of the resistor R, it is desirable to select a resistance value of about 1Ω to 10Ω as in the first embodiment.
　図８及び図９で示される等価回路の、静電気保護素子５１、６１、６２としては、本実施形態の実施例１～４で述べている、ダイオードやＰＭＯＳトランジスターの他にも、ＮＭＯＳトランジスターやバイポーラトランジスター、サイリスター構造を有するものを用いても良い。 As the electrostatic protection elements 51, 61, and 62 in the equivalent circuit shown in FIGS. 8 and 9, in addition to the diode and the PMOS transistor described in Examples 1 to 4 of this embodiment, an NMOS transistor and a bipolar transistor are used. A transistor or a transistor having a thyristor structure may be used.
　〔実施例７〕
　図１２は、本実施例７の静電気放電保護回路７０を備える半導体装置における、ＨＢＭモデルまたはＭＭモデルでのサージノイズの経路を示すブロック図である。上記サージノイズの経路は、グランド端子基準＋印加でのサージノイズ経路である。 Example 7
FIG. 12 is a block diagram illustrating a path of surge noise in the HBM model or the MM model in a semiconductor device including the electrostatic discharge protection circuit 70 according to the seventh embodiment. The surge noise path is a surge noise path with the ground terminal reference + applied.
　図１２のブロック図では、静電気保護素子であるダイオードＤ７は、実施例１と同じ要領で形成されるが、入力端子や出力端子と電源ラインＰとの間に接続されている、静電気保護素子（回路保護装置、第３回路保護手段）７１の一端の接続方法を工夫することにより、実施例２の静電気放電保護回路２０と同様に、ＨＢＭモデルやＭＭモデルでの耐量向上を実現するものである。 In the block diagram of FIG. 12, the diode D7, which is an electrostatic protection element, is formed in the same manner as in the first embodiment, but is connected between the input terminal or output terminal and the power supply line P (an electrostatic protection element ( By devising the connection method of one end of the circuit protection device (third circuit protection means) 71, as in the case of the electrostatic discharge protection circuit 20 of the second embodiment, it is possible to improve the tolerance in the HBM model and the MM model. .
　図１２の、本実施例８の静電気放電保護回路７０を備える半導体装置では、入力端子や出力端子と電源ラインＰとの間に接続されている、静電気保護素子７１の一端Ｅ７１を、ダイオードＤ７のカソード電極と抵抗体Ｒの一端との接続点Ｐ７１に接続している。 In Figure 12, in a semiconductor device comprising an electrostatic discharge protection circuit 70 of the present embodiment 8 is connected between the input terminal and the output terminal and the power supply line P, and one end E 71 of the electrostatic protection element 71, a diode D7 Are connected to a connection point P 71 between the cathode electrode of the resistor and one end of the resistor R.
　静電気放電保護回路７０を備える半導体装置では、ＨＢＭモデルやＭＭモデルにおいて静電破壊試験を行う時のサージノイズは、抵抗体Ｒを介することなく、ダイオードＤ７を経由して、グランド端子へ逃げることができる。このため、ＨＢＭモデルやＭＭモデルでの静電破壊試験時の耐量の向上が図られる。 In a semiconductor device including the electrostatic discharge protection circuit 70, surge noise when performing an electrostatic breakdown test in the HBM model or MM model may escape to the ground terminal via the diode D7 without passing through the resistor R. it can. For this reason, the tolerance of the electrostatic breakdown test in the HBM model and the MM model can be improved.
　抵抗体Ｒの抵抗値は、実施例１と同様に１Ω～１０Ω程度の抵抗値を選ぶことが望ましい。ダイオードＤ７は、実施例１と同様に、複数に分割したものを並列に接続しても良いが、ダイオードの総周囲長は１０００μｍ～２００００μｍの範囲から選ぶことが望ましい。 As for the resistance value of the resistor R, it is desirable to select a resistance value of about 1Ω to 10Ω as in the first embodiment. As in the first embodiment, the diode D7 may be divided into a plurality of diodes connected in parallel, but the total perimeter of the diode is preferably selected from a range of 1000 μm to 20000 μm.
　〔実施例８〕
　図１３は、本実施例８の静電気放電保護回路８０を備える半導体装置における、ＨＢＭモデルまたはＭＭモデルでのサージノイズの経路を示すブロック図である。上記サージノイズの経路は、グランド端子基準＋印加でのサージノイズ経路である。 Example 8
FIG. 13 is a block diagram illustrating a path of surge noise in the HBM model or the MM model in a semiconductor device including the electrostatic discharge protection circuit 80 according to the eighth embodiment. The surge noise path is a surge noise path with the ground terminal reference + applied.
　図１３のブロック図では、静電気保護素子であるＰＭＯＳトランジスターＭＰ８は、実施例３と同じ要領で形成されるが、入力端子や出力端子と電源ラインＰとの間に接続されている、静電気保護素子（回路保護装置、第３回路保護手段）８１の一端の接続方法を工夫することにより、実施例４の静電気放電保護回路４０と同様に、ＨＢＭモデルやＭＭモデルでの耐量向上を実現するものである。 In the block diagram of FIG. 13, the PMOS transistor MP8 , which is an electrostatic protection element, is formed in the same manner as in the third embodiment, but is connected between the input terminal and the output terminal and the power supply line P. By improving the connection method of one end of the element (circuit protection device, third circuit protection means) 81, as in the case of the electrostatic discharge protection circuit 40 of the fourth embodiment, it is possible to improve the tolerance in the HBM model and the MM model. It is.
　図１３の、本実施例８の静電気放電保護回路８０を備える半導体装置では、入力端子や出力端子と電源ラインＰとの間に接続されている、静電気保護素子８１の一端Ｅ８１を、ＰＭＯＳトランジスターＭＰ８のソース電極、ＰＭＯＳトランジスターＭＰ８のゲート電極及び抵抗体Ｒの一端の接続点Ｐ８１に接続している。 In the semiconductor device including the electrostatic discharge protection circuit 80 of the eighth embodiment shown in FIG. 13, one end E 81 of the electrostatic protection element 81 connected between the input terminal or the output terminal and the power supply line P is connected to the PMOS transistor. the source electrode of the M P8, are connected to one end of the connection point P 81 of the gate electrode and the resistor R of the PMOS transistor M P8.
　静電気放電保護回路８０を備える半導体装置では、ＨＢＭモデルやＭＭモデルにおいて静電破壊試験を行う時のサージノイズは、抵抗体Ｒを介することなく、ＰＭＯＳトランジスターＭＰ８を経由して、グランド端子へ逃げることができる。このため、ＨＢＭモデルやＭＭモデルでの静電破壊試験時の耐量の向上が図られる。 In a semiconductor device including the electrostatic discharge protection circuit 80, surge noise when performing an electrostatic breakdown test in the HBM model or MM model escapes to the ground terminal via the PMOS transistor MP8 without passing through the resistor R. be able to. For this reason, the tolerance of the electrostatic breakdown test in the HBM model and the MM model can be improved.
　抵抗体Ｒの抵抗値は、実施例１と同様に１Ω～１０Ω程度の抵抗値を選ぶことが望ましい。ＰＭＯＳトランジスターＭＰ８は、実施例３と同様に、複数に分割したものを並列に接続しても良いが、ＰＭＯＳトランジスターの総チャンネル幅は３００μｍ～７０００μｍの範囲から選ぶことが望ましい。 As for the resistance value of the resistor R, it is desirable to select a resistance value of about 1Ω to 10Ω as in the first embodiment. PMOS transistor M P8, as in Example 3, may be connected to those divided into a plurality in parallel, but the total channel width of the PMOS transistor is desirably selected from the range of 300μm ~ 7000μm.
　〔実施例９〕
　図１４は、本実施例９の静電気放電保護回路９０を備える半導体装置における、ＨＢＭモデルまたはＭＭモデルでのサージノイズの経路を示すブロック図である。上記サージノイズの経路は、グランド端子基準＋印加でのサージノイズ経路である。図１４の半導体装置は、より一般的な静電気放電保護回路９０を備える半導体装置である。 Example 9
FIG. 14 is a block diagram illustrating a path of surge noise in the HBM model or the MM model in a semiconductor device including the electrostatic discharge protection circuit 90 according to the ninth embodiment. The surge noise path is a surge noise path with the ground terminal reference + applied. The semiconductor device of FIG. 14 is a semiconductor device provided with a more general electrostatic discharge protection circuit 90.
　図１４のブロック図では、静電気保護素子（第１回路保護手段）９２は、実施例５と同じ要領で形成されるが、入力端子や出力端子と電源ラインＰとの間に接続されている、静電気保護素子（回路保護装置、第３回路保護手段）９１の一端の接続方法を工夫することにより、実施例６の静電気放電保護回路６０と同様に、ＨＢＭモデルやＭＭモデルでの耐量向上を実現するものである。 In the block diagram of FIG. 14, the electrostatic protection element (first circuit protection means) 92 is formed in the same manner as in the fifth embodiment, but is connected between the input terminal or the output terminal and the power supply line P. By improving the connection method of one end of the electrostatic protection element (circuit protection device, third circuit protection means) 91, as in the case of the electrostatic discharge protection circuit 60 of the sixth embodiment, an improvement in withstand capability in the HBM model and the MM model is realized. To do.
　図１４の、本実施例９の静電気放電保護回路９０を備える半導体装置では、入力端子や出力端子と電源ラインＰとの間に接続されている、静電気保護素子９１の一端Ｅ９１を、電源端子または基準電源端子とグランド端子との間に接続されている、静電気保護素子９２の一端Ｅ９２と、抵抗体Ｒの一端との接続点Ｐ９１に接続している。 In the semiconductor device including the electrostatic discharge protection circuit 90 of the ninth embodiment shown in FIG. 14, one end E 91 of the electrostatic protection element 91 connected between the input terminal or the output terminal and the power supply line P is connected to the power supply terminal. Alternatively, it is connected to a connection point P 91 between one end E 92 of the electrostatic protection element 92 and one end of the resistor R, which is connected between the reference power supply terminal and the ground terminal.
　静電気放電保護回路９０を備える半導体装置では、ＨＢＭモデルやＭＭモデルにおいて静電破壊試験を行う時のサージノイズは、抵抗体Ｒを介することなく、電源端子または基準電源端子とグランド端子との間に接続されている、静電気保護素子９２を経由して、グランド端子へ逃げることができる。このため、ＨＢＭモデルやＭＭモデルでの静電破壊試験時の耐量の向上が図られる。 In a semiconductor device including the electrostatic discharge protection circuit 90, surge noise when performing an electrostatic breakdown test in the HBM model or MM model does not pass through the resistor R and is between the power supply terminal or the reference power supply terminal and the ground terminal. It is possible to escape to the ground terminal via the connected electrostatic protection element 92. For this reason, the tolerance of the electrostatic breakdown test in the HBM model and the MM model can be improved.
　抵抗体Ｒの抵抗値は、実施例１と同様に１Ω～１０Ω程度の抵抗値を選ぶことが望ましい。図１４に示される静電気放電保護回路９０において、電源端子または基準電源端子とグランド端子との間に接続されている、静電気保護素子９２としては、本実施形態の実施例１～実施例４で述べている、ダイオードやＰＭＯＳトランジスターの他にも、ＮＭＯＳトランジスターやバイポーラトランジスター、サイリスター構造を有するものでも良い。 As for the resistance value of the resistor R, it is desirable to select a resistance value of about 1Ω to 10Ω as in the first embodiment. In the electrostatic discharge protection circuit 90 shown in FIG. 14, the electrostatic protection element 92 connected between the power supply terminal or the reference power supply terminal and the ground terminal is described in Examples 1 to 4 of this embodiment. In addition to the diode and the PMOS transistor, an NMOS transistor, a bipolar transistor, or a thyristor structure may be used.
　実施例７～実施例９では、内部回路の両端にさらなる静電気保護素子を追加することなく、ＨＢＭモデルやＭＭモデルでの静電破壊試験時の耐量の向上が図られる。従って、半導体装置の大きさを増加させる必要がないので、チップコストを増加させることなく、ＨＢＭモデルやＭＭモデルにおいて静電破壊試験を行う時の耐量の向上が実現できる。 In Embodiments 7 to 9, the tolerance of the electrostatic breakdown test in the HBM model or MM model can be improved without adding additional electrostatic protection elements at both ends of the internal circuit. Accordingly, since it is not necessary to increase the size of the semiconductor device, it is possible to improve the tolerance when performing the electrostatic breakdown test in the HBM model or the MM model without increasing the chip cost.
　また、実施例７～実施例９では、静電気保護素子７１、８１、９１としては、本実施形態の実施例１～実施例４で述べている、ダイオードやＰＭＯＳトランジスターの他にも、ＮＭＯＳトランジスターやバイポーラトランジスター、サイリスター構造を有するものでも良い。 Further, in Examples 7 to 9, as the electrostatic protection elements 71, 81, 91, in addition to the diodes and PMOS transistors described in Examples 1 to 4 of the present embodiment, NMOS transistors, A bipolar transistor or a thyristor structure may be used.
　なお、本実施の形態において、抵抗体Ｒの両端に複数の静電気放電保護を用いる場合、同じ素子を使用しているが、これに限定されず、異なる素子を組み合わせてもよい。例えば図４において、ダイオードＤ２の代りにＰＭＯＳトランジスターを設けてもよい。 In the present embodiment, when a plurality of electrostatic discharge protections are used at both ends of the resistor R, the same element is used. However, the present invention is not limited to this, and different elements may be combined. For example, in FIG. 4, a PMOS transistor may be provided instead of the diode D2.
　本発明の半導体装置は、内部に流入するイミュニティノイズを接地端子に逃がすことで、イミュニティ耐性を向上させているので、液晶ディスプレイやプラズマディスプレイ等の表示パネル駆動用ＬＳＩに好適に用いることが出来る。 The semiconductor device of the present invention improves the immunity resistance by letting immunity noise flowing into the ground terminal escape to the ground terminal, and therefore can be suitably used for a display panel driving LSI such as a liquid crystal display or a plasma display.
　１、２１、３１　Ｐ型半導体基板
　１ａ、２１ａ、３１ａ　表面
　２、２２、３３　素子分離部
　３、２３ａ、２３ｂ、３７　Ｎ型不純物領域
　４、２４ａ、２４ｂ、３６ａ、３６ｂ　Ｐ型不純物領域
　５、２５、３５、３９　多層膜
　６、２６、４１　層間絶縁膜
　７～９、２７～２９、４２～４４　メタル配線
　１０、２０、３０、４０、５０、６０、７０、８０、９０　静電気放電保護回路
　３２　Ｎ型不純物ウェル
　３８　チャンネル注入領域
　５１、９２　静電気保護素子（第１回路保護手段）
　６１　第１の静電気保護素子（第１回路保護手段）
　６２　第２の静電気保護素子（第２回路保護手段）
　７１、８１、９１　静電気保護素子（第３回路保護手段）
　Ｄ　ダイオード（第１回路保護手段）
　Ｄ１　第１のダイオード（第１回路保護手段）
　Ｄ２　第２のダイオード（第２回路保護手段）
　Ｄ７　ダイオード（第１回路保護手段）
　Ｅ７１、Ｅ８１、Ｅ９１、Ｅ９２　一端
　Ｇ　グランドライン
　ＭＰ、ＭＰ１、ＭＰ８　ＰＭＯＳトランジスター（第１回路保護手段）
　ＭＰ２　ＰＭＯＳトランジスター（第２回路保護手段）
　Ｐ　電源ライン
　Ｐ７１、Ｐ８１、Ｐ９１　接続点
　Ｒ　抵抗体 1, 21, 31 P- type semiconductor substrate 1a, 21a, 31a Surface 2, 22, 33 Element isolation part 3, 23a, 23b, 37 N- type impurity region 4, 24a, 24b, 36a, 36b P- type impurity region 5, 25 , 35, 39 Multilayer film 6, 26, 41 Interlayer insulating film 7-9, 27-29, 42-44 Metal wiring 10, 20, 30, 40, 50, 60, 70, 80, 90 Electrostatic discharge protection circuit 32 N Type impurity well 38 channel injection region 51, 92 electrostatic protection element (first circuit protection means)
61 1st electrostatic protection element (1st circuit protection means)
62 Second electrostatic protection element (second circuit protection means)
71, 81, 91 Static electricity protection element (third circuit protection means)
D diode (first circuit protection means)
D1 first diode (first circuit protection means)
D2 Second diode (second circuit protection means)
D7 diode (first circuit protection means)
E 71 , E 81 , E 91 , E 92 one end G ground line M P , M P1 , M P8 PMOS transistor (first circuit protection means)
MP2 PMOS transistor (second circuit protection means)
P power supply line P 71 , P 81 , P 91 connection point R resistor

Claims (13)

  1. 　半導体装置であって、
    　上記半導体装置の外部から電圧を供給される、電圧供給端子に一端が接続され、上記半導体装置の内部回路に他端が接続される抵抗体と、
    　上記電圧供給端子と、電気的に接地される接地端子との間に接続される第１回路保護手段とを備える半導体装置において、
    　上記第１回路保護手段の一端及び抵抗体の一端は、上記電圧供給端子に接続され、
    　上記第１回路保護手段の他端は、上記接地端子に接続され、
    　上記第１回路保護手段は、ダイオード、ＰＭＯＳトランジスター、ＮＭＯＳトランジスター、バイポーラトランジスター及びサイリスター構造を有するもののいずれか１つであることを特徴とする半導体装置。     A semiconductor device,
    A resistor to which a voltage is supplied from the outside of the semiconductor device, one end connected to a voltage supply terminal, and the other end connected to an internal circuit of the semiconductor device;
    In a semiconductor device comprising the first circuit protection means connected between the voltage supply terminal and a ground terminal that is electrically grounded,
    One end of the first circuit protection means and one end of the resistor are connected to the voltage supply terminal,
    The other end of the first circuit protection means is connected to the ground terminal,
    The semiconductor device according to claim 1, wherein the first circuit protection means is any one of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure.
  2. 　第２回路保護手段をさらに備え、
    　上記第２回路保護手段の一端は、上記抵抗体の上記他端に接続され、上記回路保護手段の他端は、上記接地端子に接続され、
    　上記第２回路保護手段は、ダイオード、ＰＭＯＳトランジスター、ＮＭＯＳトランジスター、バイポーラトランジスター及びサイリスター構造を有するもののいずれか１つであることを特徴とする、請求項１に記載の半導体装置。     A second circuit protection means;
    One end of the second circuit protection means is connected to the other end of the resistor, the other end of the circuit protection means is connected to the ground terminal,
    2. The semiconductor device according to claim 1, wherein the second circuit protection means is any one of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure.
  3. 　上記内部回路の、入力端子または出力端子に一端が接続され、
    　上記第１回路保護手段の一端に他端が接続される第３回路保護手段をさらに備えることを特徴とする、請求項１に記載の半導体装置。     One end of the internal circuit is connected to the input terminal or output terminal,
    The semiconductor device according to claim 1, further comprising third circuit protection means having the other end connected to one end of the first circuit protection means.
  4. 　上記第３回路保護手段は、ダイオード、ＰＭＯＳトランジスター、ＮＭＯＳトランジスター、バイポーラトランジスター及びサイリスター構造を有するもののいずれか１つであることを特徴とする、請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the third circuit protection means is any one of a diode, a PMOS transistor, an NMOS transistor, a bipolar transistor, and a thyristor structure.
  5. 　前記電圧供給端子と、前記接地端子とは、上記半導体装置を形成する、半導体基板の同じ面に形成されることを特徴とする、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the voltage supply terminal and the ground terminal are formed on the same surface of the semiconductor substrate forming the semiconductor device.
  6. 　前記電圧供給端子と、前記接地端子とは、上記半導体装置を形成する、半導体基板の同じ面に形成されることを特徴とする、請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the voltage supply terminal and the ground terminal are formed on the same surface of the semiconductor substrate forming the semiconductor device.
  7. 　前記電圧供給端子と、前記接地端子とは、上記半導体装置を形成する、半導体基板の同じ面に形成されることを特徴とする、請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the voltage supply terminal and the ground terminal are formed on the same surface of the semiconductor substrate forming the semiconductor device.
  8. 　前記電圧供給端子と、前記接地端子とは、上記半導体装置を形成する、半導体基板の同じ面に形成されることを特徴とする、請求項４に記載の半導体装置。 The semiconductor device according to claim 4, wherein the voltage supply terminal and the ground terminal are formed on the same surface of the semiconductor substrate forming the semiconductor device.
  9. 　上記抵抗体は、多結晶シリコン膜、または多結晶シリコン膜と高融点金属膜とを積層した膜であることを特徴とする、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the resistor is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated.
  10. 　上記抵抗体は、多結晶シリコン膜、または多結晶シリコン膜と高融点金属膜とを積層した膜であることを特徴とする、請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the resistor is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated.
  11. 　上記抵抗体は、多結晶シリコン膜、または多結晶シリコン膜と高融点金属膜とを積層した膜であることを特徴とする、請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the resistor is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated.
  12. 　上記抵抗体は、多結晶シリコン膜、または多結晶シリコン膜と高融点金属膜とを積層した膜であることを特徴とする、請求項４に記載の半導体装置。 5. The semiconductor device according to claim 4, wherein the resistor is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated.
  13. 　上記抵抗体は、多結晶シリコン膜、または多結晶シリコン膜と高融点金属膜とを積層した膜であることを特徴とする、請求項５に記載の半導体装置。 6. The semiconductor device according to claim 5, wherein the resistor is a polycrystalline silicon film or a film in which a polycrystalline silicon film and a refractory metal film are laminated.
PCT/JP2009/062114 2008-07-04 2009-07-02 Semiconductor device WO2010001958A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
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KR20150120839A (en) * 2014-08-25 2015-10-28 주식회사 지앤브이 Sealed housing and Embedment heating equipment using this material and its facilities and Manufacturing method thereof
CN108847176A (en) * 2018-07-13 2018-11-20 京东方科技集团股份有限公司 A kind of array substrate, display panel and display device

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JP5402917B2 (en) * 2010-12-20 2014-01-29 株式会社デンソー ESD protection circuit

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JP2000332207A (en) * 1999-05-25 2000-11-30 Hitachi Ltd Overvoltage protective circuit

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JP2000332207A (en) * 1999-05-25 2000-11-30 Hitachi Ltd Overvoltage protective circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150120839A (en) * 2014-08-25 2015-10-28 주식회사 지앤브이 Sealed housing and Embedment heating equipment using this material and its facilities and Manufacturing method thereof
KR101582596B1 (en) 2014-08-25 2016-01-05 주식회사 지앤브이 Sealed housing and Embedment heating equipment using this material and its facilities and Manufacturing method thereof
CN108847176A (en) * 2018-07-13 2018-11-20 京东方科技集团股份有限公司 A kind of array substrate, display panel and display device

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