WO2009152780A1 - 一种时分同步码分多址系统的上行导频搜索装置及方法 - Google Patents
一种时分同步码分多址系统的上行导频搜索装置及方法 Download PDFInfo
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- WO2009152780A1 WO2009152780A1 PCT/CN2009/072359 CN2009072359W WO2009152780A1 WO 2009152780 A1 WO2009152780 A1 WO 2009152780A1 CN 2009072359 W CN2009072359 W CN 2009072359W WO 2009152780 A1 WO2009152780 A1 WO 2009152780A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/709—Correlator structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/70754—Setting of search window, i.e. range of code offsets to be searched
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70701—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation featuring pilot assisted reception
Definitions
- the present invention relates to the field of wireless communications, and in particular, to an uplink pilot search apparatus and a search method for a time division synchronous code division multiple access (TD-SCDMA) communication system.
- TD-SCDMA time division synchronous code division multiple access
- the TD-SCDMA wireless communication system is a synchronous system.
- multiple users mobile stations
- the subframe structure of the TD-SCDMA communication system is shown in Fig. 1.
- Uplink synchronization is established by UpPTS
- uplink pilot time slot to complete.
- the UpPTS will be transmitted.
- the Node B base station
- SYNC_UL uplink synchronization code
- the Node B can successfully detect the SYNC_UL (uplink synchronization code)
- it is on the downlink corresponding FPACH (Fast Physical Access Channel).
- the acknowledgment message is sent to the UE, and then the UE can send the access information to the Node B on the allocated PRACH (Physical Random Access Channel), and finally the Node B sends the necessary information to the UE, and the call setup is completed.
- PRACH Physical Random Access Channel
- the UpPTS is composed of a SYNC-UL of length 128chip and a GP (guard interval) of 32chip length.
- SYNC_UL is a set of PN codes used to distinguish between different UEs during the access procedure.
- the entire system has 256 different SYNC-ULs, divided into 32 groups of 8 each. Since the code group is determined by the Node B, 8 SYNC-ULs are known to both the base station and the UE that has obtained downlink synchronization. When the UE needs to establish uplink synchronization, one of the eight known SYNC-ULs will be randomly selected and transmitted in the UpPTS according to the estimated timing and power.
- the Node B In order to detect whether there is SYNC-UL access on the UpPTS slot, the Node B first needs to perform pilot search on the antenna received signal on the UpPTS slot, which is to calculate the 128 chip (slice) SYNC-UL and receive of the Node B itself.
- the UpPTS time slot search window of the conventional TD-SCDMA communication system has a length of 256 chips (96 + 128 + 32) as shown in FIG.
- the guard interval GP between the DwPTS (downlink pilot time slot) and the UpPTS is 96 chips, and the electromagnetic wave propagation velocity V is about 3 108 m/s, then 96 chips correspond.
- the remote coverage is over (the cell radius is greater than 11.25 km), the synchronization cannot be performed.
- the technical problem to be solved by the present invention is to provide an uplink pilot search apparatus and method for a TD-SCDMA communication system, which is used for synchronization establishment in a case where a distance between a UE and a NodeB is greater than or equal to 11.25 km.
- the present invention is achieved by the following technical solutions:
- An uplink pilot search device for a time division synchronous code division multiple access system, comprising: a local synchronization code memory, a read/write address controller, an antenna data memory, a correlator, an energy seeking module, and an energy combining module, which are sequentially connected, and respectively a clock/reset/controller connected to each of the above modules, wherein the local sync code memory is also connected to the correlator.
- the read/write address controller is used to control the local sync code memory, the read and write of the antenna data memory, the address signal and the read and write enable signals, and the chip select signal for each memory;
- the local sync code memory is used to store all local complex numbers. Uplink synchronization code;
- the clock/reset/controller is configured to provide a clock signal and a reset signal to each of the above modules; provide an operation combining signal for the energy combining module, the energy seeking module, and the correlator; and provide window width information of the search window to the read/write address controller;
- the merging module is configured to sum the antenna energy output by the energy seeking module;
- the energy consuming module is configured to obtain energy for the correlation result complex data output by the correlator;
- the correlator is configured to perform a correlation operation on the received uplink pilot time slot sequence and the local complex uplink synchronization code sequence;
- the antenna data memory is configured to store the received uplink antenna data.
- the correlator specifically includes: a virtual multiplier, a complex adder, and a multiplexer connected in sequence;
- the virtual multiplier is used to solve the complex multiplication of the local sync code memory and the antenna data memory output data sequence; the complex adder is used to accumulate the complex sequence output by the virtual multiplier; the demultiplexer is used to control the start and end of the accumulation operation.
- the energy decision module connected to the energy combining module is further configured to determine whether the uplink synchronization establishment has user equipment access.
- the antenna data memory and the local synchronization code memory are both dual-port RAMs.
- An uplink pilot search method for a time division synchronous code division multiple access system includes the following steps: a: configuring a search window length, and buffering uplink antenna data in an antenna data memory, wherein the local synchronization code is buffered in a local synchronization code memory ;
- the search window length in step b is greater than or equal to 256 chips.
- step b specifically implements the formula as:
- Rx_sync is the antenna uplink pilot data sequence in the search window
- SyncCode is the local complex uplink synchronization code
- Rx_cor is the result of the correlation operation
- ( ⁇ )* indicates the conjugate operation
- the superscript 1 ⁇ 2 indicates the antenna sequence number.
- ka 0 U
- Re ['] means the real part operation
- Im ['] means the imaginary part operation
- the step d further includes determining whether the uplink synchronization establishment has user equipment access, and if yes, continuing the subsequent operation; otherwise, returning to step 1).
- the invention implements correlation operation in pilot search by using a full serial and pipeline structure circuit, and the hardware circuit resource consumption of the correlator device is minimum;
- the search window length of the pilot search device proposed in the present invention is configurable, and can be applied to a long-distance coverage scene or a normal distance coverage scene, and does not require secondary development of an ASIC;
- 1 is a subframe structure of a TD-SCDMA wireless communication system according to the present invention.
- FIG. 2 is a schematic diagram of a pilot slot structure in a subframe of a TD-SCDMA radio communication system according to the present invention
- FIG. 3 is a schematic diagram of a pilot slot search window extended in the case of remote coverage of the present invention
- FIG. 4 is a pilot search implemented by the present invention
- FIG. 5 is a hardware implementation of the correlator of the present invention. detailed description
- the present invention realizes the uplink pilot search of the TD-SCDMA wireless communication system by providing a search window configurable pilot search device and a search method, and implements full hardware implementation with low resource consumption.
- the method includes: a local synchronization code memory 402, a read/write address controller 401, an antenna data memory 407, a correlator 406, an energy seeking module 405, an energy combining module 404, and an energy decision module 408, which are sequentially connected, wherein
- the local sync code memory 402 is also coupled to the correlator 406.
- it also includes a local synchronization code memory 402, a read/write address controller 401, and
- the antenna data memory 407, the correlator 406, the energy seeking module 405, and the energy combining module 404 are connected to the clock reset controller 403, wherein the correlator has 8 sets, the antenna data memory has 8 sets, and the energy module has 8 sets.
- both the antenna data memory 407 and the local synchronization code memory 402 are dual port RAMs.
- the read/write address controller 401 is configured to control the read and write of the local sync code memory 402 and the antenna data memory 407, and provide address signals and read and write enable signals and chip select signals to the respective memories.
- the local sync code memory 402 is used to store all local complexized uplink sync codes.
- the clock/reset/controller 403 is configured to provide a clock signal and a reset signal to all other modules; provide an operation combining signal of the energy combining module 404, the energy modulating module 405, and the correlator 406; and provide a control terminal signal of the multiplexer 503 Providing the read/write address controller 401 with window width information of the search window.
- the energy combining module 404 is used to sum the 8 antenna energies output by the energy seeking module 405.
- the energy seeking module 405 is operative to derive energy from the correlation result complex data output by the correlator 406.
- the correlator 406 is configured to perform a correlation operation on the received uplink pilot time slot sequence and the local complex uplink code sequence.
- Antenna data memory 407 is used to store the received uplink antenna data.
- the virtual multiplier 501 is used to solve the complex multiplication of the output sequence of the local sync code memory 402 and the antenna data memory 407.
- the complex adder 502 is for performing an accumulation operation on the complex sequence output from the virtual multiplier 501.
- Multiplexer 503 is used to control the start and end of the accumulation operation.
- the product of the complex uplink synchronization code can be expressed as:
- the present invention proposes to store the complex local uplink synchronization code si by using a two-bit binary code, that is, to use a simple decoder: '00, denotes 1, '01, denotes -1, '10, denotes j, '11, Represents - j . Therefore, the complex multiplier required in the correlator 406 of the present invention can be replaced by a general decoder and a multiplexer, that is, a virtual multiplier is used, thereby reducing the use of hardware resources.
- the correlator 406 mentioned in the present invention differs from the existing correlator in that: First, the shift register set is not required, but the antenna data memory 407 and the local sync code memory 402 in FIG. 4 are directly used. Second, the existing correlator is mostly a parallel or serial combination, the circuit structure is complex, and the resource consumption is large, and the correlator in the present invention uses a full serial pipeline operation, such as As shown in Figure 5, only one virtual multiplier, complex adder, and one multiplexer are needed here to maximize resource savings. In addition, in the existing TD-SCDMA pilot search implementation scheme, FFT/IDFT is used to solve the correlation operation, and the disadvantage is that it cannot be applied in the search search with variable search window, and at least 4 must be used. A real multiplier performs the operation, and the present invention replaces the FFT/IDFT with a correlator and solves this problem.
- UpPTS will extend to part of TS1, TS1 will no longer be used as a service slot, and TS2 will be configured as a fixed uplink slot, thus allowing SYNC-UL delay to arrive.
- the base station also occupies part of the space of TS1, and the remaining chips of TS1 are idle.
- the search window is appropriately expanded, which can satisfy the pilot search of long-distance coverage, which is equivalent to using system capacity in exchange for performance.
- the SYNC-UL search window must not occupy all the chips of TS1.
- the clock/reset/controller 403 includes a window length register, and the size of the search window can be configured as needed to control the operation of the read/write address controller 401 and the correlator 406, thereby controlling the entire pilot search. process.
- SYNC-UL For each 96chip extension, the cell radius will increase by 11.25 kilometers. Therefore, the search window does not have to be extended to all 864 chips of TS1.
- the length of the search window in this device only affects the operation time of the circuit and does not affect the circuit structure.
- the first step is a first step:
- the search window length in the normal mode is configured as 256chip, as shown in Figure 2, where the configuration registers are in the clock/reset/controller 403.
- the uplink 8 antenna data is buffered in 8 memories of the antenna data memory 407, and the local synchronization code is buffered in the local synchronization code memory 402.
- Each group has 8 local synchronization codes.
- the present invention proposes to use a two-bit binary code to represent the complex local.
- Uplink sync code ie: '00, means 1, '01, means -1, '10, means j, '11, means _j.
- the correlator 406 calculates the correlation sequence of the SYNC-UL and the antenna data, that is, the implementation
- Rx_sync is the antenna uplink pilot data sequence in the search window
- SyncCode is the local complex uplink synchronization code
- Rx_cor is the result of the correlation operation.
- ( ⁇ )* indicates the conjugate operation
- the data of the 8 antennas are processed simultaneously.
- Rx _ pow ⁇ sync ( Re [Rx _ cor]) 2 + (lm [Rx _ cor ⁇ ync)]) 2 equation
- Re [ '] denotes taking the real part calculation
- Im ['] denotes taking the imaginary part operator .
- the energy combining module 404 combines the 8 antenna data and sends it to the subsequent energy decision module to determine whether the synchronization establishment is successful, that is, whether there is UE access. If it is unsuccessful, repeat the above steps 3 to 5 until 8 uplink synchronization codes are calculated.
- the search window is a long-distance coverage (ie, the cell radius is greater than 11.25 km)
- its working principle is as follows:
- the first step is a first step:
- n 96, that is, the search window length of 96 chips is larger than in the normal mode.
- the search can be known.
- the cell radius can reach 22.5 kilometers.
- each of the antennas has 96 chips of buffer data, that is, 96 chips extending to TS1.
- the correlator 406 calculates the correlation sequence of the SYNC-UL and the antenna data, that is, the implementation
- Rx—sync is the uplink pilot data sequence of the antenna in the search window, and SyncCode is local complexization.
- the data of the 8 antennas are processed simultaneously.
- Rx _ pow ⁇ sync) (Re[Rx _ cor ]) 2 + (lm[Rx _ cor ⁇ ync) ]) 2 public Re ['] means real part operation, Im ['] means imaginary part operation .
- the energy combining module 404 combines the 8 antenna data and sends it to the subsequent energy decision module to determine whether the synchronization establishment is successful, that is, whether there is UE access. If it is unsuccessful, repeat the above steps 3 to 5 until 8 uplink synchronization codes are calculated.
- the uplink pilot search apparatus and method disclosed by the present invention implements the correlation operation in the pilot search by using the full serial and pipeline structure circuit, and avoids the use of the multiplier, so the hardware consumption of the correlator device hardware circuit is minimized.
- the search window length of the uplink pilot search device is configurable, and thus can be used for a long-distance coverage scenario or a normal distance coverage scenario without requiring secondary development of an ASIC.
- the uplink pilot search device simultaneously calculates 8 antenna data by using eight correlators with low and medium resource consumption, thereby ensuring high efficiency.
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Description
一种时分同步码分多址系统的上行导频搜索装置及方法 技术领域
本发明涉及无线通信领域, 尤其涉及一种时分同步码分多址 ( TD-SCDMA )通信系统上行导频搜索装置及搜索方法。 背景技术
TD-SCDMA无线通信系统是一种同步系统。在上行链路中,多个用户(移 动台) 向基站发送信号, 为了防止不同用户信号之间的相互干扰, 需要对各 用户进行同步控制, 保证其同时到达基站。
TD-SCDMA通信系统子帧结构如图 1所示。上行同步的建立是靠 UpPTS
(上行导频时隙)来完成的。 当 UE (用户设备)准备建立同步的时候, 将发 射 UpPTS,如果 Node B (基站)能够成功地检测到 SYNC— UL (上行同步码), 则在下行对应的 FPACH (快速物理接入信道)上向 UE发送确认消息, 然后 UE可在分配好的 PRACH (物理随机接入信道 )上向 Node B发送接入信息, 最后 Node B再将必要的信息发送给 UE, 呼叫建立完成。
UpPTS是由长度为 128chip的 SYNC— UL和长度为 32chip的 GP(保护间 隔)组成的。 SYNC— UL是一组 PN码, 用于在接入过程中区分不同的 UE。 整个系统有 256个不同的 SYNC— UL, 分为 32组, 每组 8个。 因为码组是由 Node B确定, 所以 8个 SYNC— UL对基站和已经获得下行同步的 UE来说都 是已知的。 当 UE需要建立上行同步时, 将从 8个已知的 SYNC— UL中随机 选择 1个,并根据估计的定时和功率在 UpPTS发射。 Node B为了检测在 UpPTS 时隙上是否有 SYNC— UL接入, 首先需要对 UpPTS时隙上的天线接收信号进 行导频搜索, 就是要计算 Node B本身的 128chips (码片 ) SYNC— UL与接收 的 UpPTS时隙区间上的天线数据的相关性, 如果二者的数学模式相匹配, 则 表示有 SYNC— UL接入。
常规 TD-SCDMA通信系统的 UpPTS时隙搜索窗长度为 256chip( 96 + 128 + 32 )如图 2所示。 由于系统的码片速率为 1.28MHz, DwPTS (下行导频时 隙)与 UpPTS之间的保护间隔 GP为 96个 chip, 电磁波传播速度 V约为 3 108米 /秒, 则 96个码片对应的电磁波传播距离为 V X 96/ ( 1.28 X 106 ) = 22.5公里, 也就是当 UE与 NodeB的距离小于 11.25公里的时候才能完成上 行同步建立, 远距离覆盖的时候(小区半径大于 11.25公里)无法进行同步 建立, 因为那样会导致 UpPTS时隙延时到达基站, 与 TS1时隙互相干扰, 这 也是 TD-SCDMA通信系统的缺点之一。而且,现有技术中尚无釆用硬件进行 TD-SCDMA通信系统上行导频搜索的方案。 发明内容
本发明所要解决的技术问题是提供一种 TD-SCDMA通信系统上行导频搜 索装置及方法,用于在 UE与 NodeB的距离大于或小于等于 11. 25公里情况下 的同步建立。 为解决上述技术问题, 本发明是通过以下技术方案实现的:
一种时分同步码分多址系统的上行导频搜索装置, 包括: 依次相连的本 地同步码存储器、 读写地址控制器、 天线数据存储器、 相关器、 求能量模块 和能量合并模块,还包括分别与上述各模块相连的时钟 /复位 /控制器, 其中本 地同步码存储器还与相关器相连,
读写地址控制器用于控制本地同步码存储器、天线数据存储器的读和写, 给各个存储器提供地址信号和读、 写使能信号, 片选信号; 本地同步码存储 器用于存储全部本地复数化的上行同步码;
时钟 /复位 /控制器用于对上述各模块提供时钟信号和复位信号;提供能量 合并模块、 求能量模块、 相关器的运算使能信号; 给读写地址控制器提供搜 索窗的窗宽信息; 能量合并模块用于对求能量模块输出的天线能量求和; 求 能量模块用于对相关器输出的相关结果复数数据求能量;
相关器用于对接收到的上行导频时隙序列和本地复数化的上行同步码序 列求相关运算; 天线数据存储器用于存储接收到的上行天线数据。
其中, 所述相关器具体包括: 依次相连的虚拟乘法器、 复数加法器、 多 路选择器;
虚拟乘法器用于求解本地同步码存储器和天线数据存储器输出数据序列 的复数乘法; 复数加法器用于对虚拟乘法器输出的复数序列做累加运算; 多 路选择器用于控制累加运算的开始和结束。
其中, 还包括与所述能量合并模块相连的能量判决模块, 用于判断上行 同步建立是否有用户设备接入。
其中, 所述天线数据存储器与本地同步码存储器均为双口 RAM 。
一种时分同步码分多址系统的上行导频搜索方法, 包括以下步骤: a: 配置搜索窗长度, 并将上行各天线数据緩存在天线数据存储器中, 本 地同步码緩存在本地同步码存储器中;
b: 由相关器计算上行同步码与天线数据的相关序列;
c: 由求能量模块计算各天线对应的相关功率序列;
d: 由能量合并模块进行各天线数据的合并。
其中, 步骤 b中所述搜索窗长度大于或等于 256个码片。
其中, 步骤 b 具体实现公式为:
Rx
其中, Rx— sync为搜索窗内的天线上行导频数据序列, SyncCode为本地 复数化上行同步码, Rx— cor为相关运算的结果, (·)*表示共轭运算, 上标 ½ 表示天线序号, ka = 0U , 上标 ^wc表示本地复数化上行同步码的编号, 即 sync = 0,\,... ,7o
其中, 步骤 c具体实现公式为:
Rx _ pow†a^nc) = (Re[Rx _ cor 。' c) ])2 + (lm[Rx _ Cor 。' c) ])2
其中, Re[']表示取实部运算, Im[']表示取虚部运算。
其中, 步骤 d之后还包括判断上行同步建立是否有用户设备接入, 如果 是, 则继续后续操作; 否则, 返回步骤1)。
本发明具有以下有益效果:
1 )本发明釆用全串行、 流水线结构电路实现导频搜索中的相关运算, 本 相关器装置硬件电路资源消耗最小;
2 )本发明中提出的导频搜索装置搜索窗长度可配置, 可以应用在远距离 覆盖场景或者正常距离覆盖场景, 不需要二次开发 ASIC;
3 )用 8个中低资源消耗的相关器对 8天线数据同时计算, 保证高效率。 附图说明
图 1是本发明 TD-SCDMA无线通信系统子帧结构;
图 2是本发明 TD-SCDMA无线通信系统子帧中导频时隙结构; 图 3是本发明远距离覆盖情况下延伸的导频时隙搜索窗示意图; 图 4是本发明实现的导频搜索的硬件装置;
图 5是本发明中相关器的硬件实现装置。 具体实施方式
本发明通过提供一种搜索窗可配置的导频搜索装置及搜索方法, 实现 TD-SCDMA无线通信系统的上行导频搜索,并且釆用低资源消耗的全硬件实 现。
下面结合附图及具体实施例对本发明作进一步详细的描述:
请参阅图 4所示, 包括: 依次相连的本地同步码存储器 402、 读写地址 控制器 401、 天线数据存储器 407、 相关器 406、 求能量模块 405、 能量合并 模块 404和能量判决模块 408, 其中, 本地同步码存储器 402还与相关器 406 相连。另外,还包括分别与上述本地同步码存储器 402、读写地址控制器 401、
天线数据存储器 407、 相关器 406、 求能量模块 405、 能量合并模块 404相连 的时钟复位控制器 403 , 其中相关器有 8套, 天线数据存储器有 8套, 求能 量模块有 8套。 图 5为相关器装置, 包括依次相连的虚拟乘法器 501、 复数 加法器 502、 多路选择器 503。 本发明中, 天线数据存储器 407与本地同步码 存储器 402均为双口 RAM 。
读写地址控制器 401 : 用于控制本地同步码存储器 402、 天线数据存储器 407的读和写, 给各个存储器提供地址信号和读、 写使能信号, 片选信号。
本地同步码存储器 402用于存储全部本地复数化的上行同步码。
时钟 /复位 /控制器 403用于对其它所有模块提供时钟信号和复位信号;提 供能量合并模块 404、 求能量模块 405、 相关器 406的运算使能信号; 提供多 路选择器 503的控制端信号;给读写地址控制器 401提供搜索窗的窗宽信息。
能量合并模块 404用于对求能量模块 405输出的 8天线能量求和。
求能量模块 405用于对相关器 406输出的相关结果复数数据求能量。 相关器 406用于对接收到的上行导频时隙序列和本地复数化的上行同步 码序列求相关运算。
天线数据存储器 407用于存储接收到的上行天线数据。
虚拟乘法器 501用于求解本地同步码存储器 402和天线数据存储器 407 输出数据序列的复数乘法。
复数加法器 502用于对虚拟乘法器 501输出的复数序列做累加运算。 多路选择器 503用于控制累加运算的开始和结束。
下面是关于本发明提出的虚拟乘法器的说明:
由于本地复数上行同步码序列 § = (-!'-2'-'-128)是由基本上行同步码序列
8 = 0^^". ¾8)通过以下方式得到, 即: ^ = Uy ' s! ^ e {1 -1}, = 1,2,...,128 。
可见, 复数化上行同步码 ^α_ ,__/ = ι,2,···,ΐ28。
因此, 在相关器 406 的运算中, 对于天线复数数据 (a+b*j ) 而言, 与
复数上行同步码的乘积可以表示为:
(a+b*j)*l=a+b*j; (a+b*j)*(-l)=-a-b*j;
(a+b*j)*j=-b+a*j ; (a+b*j)*(-j)=b-a*j 。
另外, 本发明提出用两位二进制编码存储复数化本地上行同步码 si, 即 釆用简单的译码器: '00, 表示 1 , '01, 表示- 1 , '10, 表示 j , '11, 表示- j 。 因此, 本发明相关器 406 中需要的复数乘法器可以由一般的译码 器和多路选择器来替代, 也就是釆用虚拟乘法器, 从而减少硬件资源的使用。
本发明中提及的相关器 406与现有的相关器相比, 其区别在于: 第一, 不需要移位寄存器组, 而是直接釆用图 4中天线数据存储器 407与本地同步 码存储器 402的双口 RAM; 第二, 现有的相关器多是釆用并行或串并结合的 方式, 电路结构复杂, 资源消耗大, 而本发明中的相关器釆用全串行的流水 线操作, 如图 5所示, 这里仅仅需要一个虚拟乘法器、 复数加法器以及一个 多路选择器, 最大限度的节约了资源。 另外, 目前已有的 TD-SCDMA导频搜 索实现方案中,都是釆用 FFT/IDFT来求解相关运算,其缺点在于不能应用在 搜索窗可变的导频搜索中, 并且必须釆用至少 4个实数乘法器进行运算, 而 本发明用相关器来替代 FFT/IDFT, 并且解决了这一问题。
如图 3所示, 在远距离覆盖的时候, UpPTS会延伸到 TS1的部分空间, TS1 将不再作为业务时隙使用, 将 TS2 配置为固定上行时隙, 这样就允许 SYNC— UL延时到达基站并占用 TS1的部分空间, TS1 的剩余码片空闲, 这 时搜索窗适当扩大, 可以满足远距离覆盖的导频搜索, 相当于是用系统容量 来换取性能。 TS1 时隙有 864个 chip, 但是, SYNC— UL搜索窗决不能占用 TS1全部的 chip, 因为那样搜索窗太长, 相关器 406的计算量将过大, 这在 工程上是不可行或得不偿失的, 本发明装置中, 时钟 /复位 /控制器 403里面包 含一个窗长寄存器, 可以根据需要来配置搜索窗的大小, 控制读写地址控制 器 401 , 相关器 406的工作, 从而控制整个导频搜索过程。 另外, SYNC— UL
每延伸 96chip, 小区半径就会增加 11.25公里。 因此, 搜索窗完全没有必要扩 展到 TS1的全部 864个 chip 。
本装置中搜索窗长度仅仅影响电路的运算时间, 不影响电路结构。
下面结合具体实施例, 介绍本发明搜索方法步骤。
实施例 1:
搜索窗正常模式(非远距离覆盖) 时, 其工作原理描述如下:
第一步:
配置正常模式下的搜索窗长度为 256chip, 如图 2所示 , 其中配置寄存 器在时钟 /复位 /控制器 403中。
第二步:
上行 8根天线数据緩存在天线数据存储器 407的 8个存储器中, 本地同 步码緩存在本地同步码存储器 402中, 每组本地同步码有 8个, 本发明提出 用两位二进制编码表示复数化本地上行同步码, 即: '00, 表示 1, '01, 表示 - 1, '10, 表示 j, '11, 表示 _j 。
第三步:
由相关器 406计算 SYNC— UL与天线数据的相关序列, 即实现
/ = 0,1,···, 382
A: = 0,1,·· -,127
« = 0,1,···, 255
Rx— sync为搜索窗内的天线上行导频数据序列, SyncCode为本地复数化 上行同步码, Rx— cor为相关运算的结果。 (·)*表示共轭运算, 上标 ka表示天 线序号, ka = QU。 8根天线的数据同时处理。 SyncCode的上标 ^wc是本 地复数化上行同步码的编号, 即 ^wc = 0, 1 , ... ,7。
每根天线搜索窗内数据的长度为 256, 即 n=0,l,2...,255 。 相关运算数据 结果的长度为 128+256-1 = 383, 即 i=0,l,2...,382。
第四步:
由求能量模块 405计算各天线对应的相关功率序列, 即,
Rx _ pow^sync) = (Re[Rx _ cor ])2 + (lm[Rx _ cor^ync) ])2 公式中 Re[']表示取实部运算, Im[']表示取虚部运算。
第五步:
由能量合并模块 404进行 8天线数据的合并,送往后续的能量判决模块, 判断同步建立是否成功, 也就是判断是否有 UE接入。 如果不成功, 则重复 上述第三步〜第五步, 直到 8个上行同步码都计算完毕。
实施例 2:
搜索窗为远距离覆盖 (即小区半径大于 11.25公里) 时, 其工作原理描 述如下:
第一步:
配置远距离模式下的搜索窗长度为 384chip, 如图 3所示, 图中 n = 96, 即比正常模式下多了 96个 chip的搜索窗长度,通过其对应的电磁波传播距离, 可知道搜索窗增加 96chip后, 小区半径可以达到 22.5公里。
第二步:
与实施例 1的差别在于,每根天线的緩存数据多了 96chip,即延伸到 TS1 的 96个 chip。
第三步:
由相关器 406计算 SYNC— UL与天线数据的相关序列, 即实现
Rx _co a'sync) = ^Rx _syncika) ^SyncCod
k,n ^J
/ = 0,1, · · ·, 478
A: = 0,1, · · -,127
« = 0,1, · · -,351
Rx— sync为搜索窗内的天线上行导频数据序列, SyncCode为本地复数化
上行同步码, Rx— cor为相关运算的结果。 (·)*表示共轭运算, 上标 ka表示天 线序号, ka = QU。 8根天线的数据同时处理。 SyncCode的上标 ^wc是本 地复数化上行同步码的编号, 即 ^wc = 0, 1 , ... ,7。 与实施例 1的差别在于,每根天线搜索窗内数据的长度为 256 + 96 = 352 , 即 n=0,l,2... ,351 。 相关运算数据结果的长度为 128+352-1 = 479 , 即 i=0,l,2... ,478。
第四步:
由求能量模块 405计算各天线对应的相关功率序列, 即,
Rx _ pow^sync) = (Re[Rx _ cor ])2 + (lm[Rx _ cor^ync) ])2 公中 Re[']表示取实部运算, Im[']表示取虚部运算。
第五步:
由能量合并模块 404进行 8天线数据的合并,送往后续的能量判决模块, 判断同步建立是否成功, 也就是判断是否有 UE接入。 如果不成功, 则重复 上述第三步〜第五步, 直到 8个上行同步码都计算完毕。
以上实施例仅用以说明本发明的技术方案而非限制, 仅仅参照较佳实施 例对本发明进行了详细说明。 本领域的普通技术人员应当理解, 可以对本发 明的技术方案进行修改或者等同替换, 而不脱离本发明技术方案的精神和范 围, 这些修改或者等同替换均应涵盖在本发明的权利要求范围当中。
工业实用性
本发明公开的上行导频搜索装置及方法釆用全串行、 流水线结构电路实 现导频搜索中的相关运算, 避开了乘法器的使用, 因此相关器装置硬件电路 资源消耗最小。 此外, 所述上行导频搜索装置的搜索窗长度可配置, 因此可 以用于远距离覆盖场景或者正常距离覆盖场景, 而不需要二次开发 ASIC。 进 一步地, 所述上行导频搜索装置用 8个中低资源消耗的相关器对 8天线数据 同时进行计算, 从而保证了高效率。
Claims
1、 一种时分同步码分多址系统的上行导频搜索装置, 其包括: 依次相连 的本地同步码存储器、 读写地址控制器、 天线数据存储器、 相关器、 求能量 模块和能量合并模块,还包括分别与上述各模块相连的时钟 /复位 /控制器, 其 中本地同步码存储器还与相关器相连,
读写地址控制器用于控制本地同步码存储器、天线数据存储器的读和写, 给各个存储器提供地址信号和读、 写使能信号, 片选信号; 本地同步码存储 器用于存储全部本地复数化的上行同步码;
时钟 /复位 /控制器用于对上述各模块提供时钟信号和复位信号;提供能量 合并模块、 求能量模块、 相关器的运算使能信号; 给读写地址控制器提供搜 索窗的窗宽信息; 能量合并模块用于对求能量模块输出的天线能量求和; 求 能量模块用于对相关器输出的相关结果复数数据求能量;
相关器用于对接收到的上行导频时隙序列和本地复数化的上行同步码序 列求相关运算; 天线数据存储器用于存储接收到的上行天线数据。
2、如权利要求 1所述的时分同步码分多址系统的上行导频搜索装置, 其 中, 所述相关器具体包括: 依次相连的虚拟乘法器、 复数加法器、 多路选择 器;
虚拟乘法器用于求解本地同步码存储器和天线数据存储器输出数据序列 的复数乘法; 复数加法器用于对虚拟乘法器输出的复数序列做累加运算; 多 路选择器用于控制累加运算的开始和结束。
3、如权利要求 1或 2所述的时分同步码分多址系统的上行导频搜索装置, 其还包括与所述能量合并模块相连的能量判决模块, 用于判断上行同步建立 是否有用户设备接入。
4、如权利要求 1或 2所述的时分同步码分多址系统的上行导频搜索装置, 其中, 所述天线数据存储器与本地同步码存储器均为双口 RAM 。
5、 一种时分同步码分多址系统的上行导频搜索方法, 其包括以下步骤:
a: 配置搜索窗长度, 并将上行各天线数据緩存在天线数据存储器中, 本 地同步码緩存在本地同步码存储器中;
b: 由相关器计算上行同步码与天线数据的相关序列;
C : 由求能量模块计算各天线对应的相关功率序列;
d: 由能量合并模块进行各天线数据的合并。
6、如权利要求 5所述的时分同步码分多址系统的上行导频搜索方法, 其 中, 步骤 b中所述搜索窗长度大于或等于 256个码片。
7、如权利要求 5所述的时分同步码分多址系统的上行导频搜索方法, 其 中, 步骤 b 具体实现公式为:
Rx
8、如权利要求 7所述的时分同步码分多址系统的上行导频搜索方法, 其 中, 步骤 c具体实现公式为:
Rx _ pow^sync) = (Re[Rx _ cor ])2 + (lm[Rx _ cor^ync) ])2 其中, Re[']表示取实部运算, Im[']表示取虚部运算。
9、如权利要求 5所述的时分同步码分多址系统的上行导频搜索方法, 其 中, 步骤 d之后还包括判断上行同步建立是否有用户设备接入, 如果是, 则 继续后续操作; 否则, 返回步骤1)。
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