WO2009147753A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2009147753A1
WO2009147753A1 PCT/JP2008/067602 JP2008067602W WO2009147753A1 WO 2009147753 A1 WO2009147753 A1 WO 2009147753A1 JP 2008067602 W JP2008067602 W JP 2008067602W WO 2009147753 A1 WO2009147753 A1 WO 2009147753A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
terminals
semiconductor chips
semiconductor device
electrostatic protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/067602
Other languages
French (fr)
Inventor
Shigehiro Asano
Shinichi Kanno
Junji Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to US12/866,668 priority Critical patent/US8611154B2/en
Publication of WO2009147753A1 publication Critical patent/WO2009147753A1/en
Anticipated expiration legal-status Critical
Priority to US14/085,418 priority patent/US9324653B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/498—Resistive arrangements or effects of, or between, wiring layers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a semiconductor device, and is preferably applied to a electrostatic protection system of a semiconductor device including a plurality of stacked semiconductor chips.
  • some semiconductor chips incorporating an internal circuit include an electrostatic protection circuit on a pad electrode thereof.
  • an electrostatic protection circuit is constituted by a large diode because the circuit is required to be resistant to high current generated due to the discharge of the static electricity. Attributed to the diode, large capacitors are added in parallel to the pad electrode of the semiconductor chip, causing a reduction in operating frequency of the internal circuit formed on the semiconductor chip and an increase in electric power consumption.
  • Patent Document 1 As an alternative external storage device of a hard disk, a solid state drive has attracted attention (Patent Document 1) .
  • a solid state drive employs a NAND flush memory as a nonvolatile storage medium for reading and writing data
  • a mechanical structure such as a hard disk is not required. This brings advantages as achieving a reduction in size and weight, low power consumption, excellent impact resistance, and short access time.
  • An object of the present invention is to provide a semiconductor device capable of reducing the capacitance to be added to external terminals, without degrading the electrostatic protection function of a plurality of semiconductor chips sharing the external terminals.
  • a plurality of semiconductor chips including internal circuits respectively formed thereon; a semiconductor package on which the semiconductor chips are mounted, and which has external terminals shared by pad electrodes of the semiconductor chips; and an electrostatic protection circuit that is formed on a part of the semiconductor chips, and that protects the internal circuits from static electricity.
  • first and second semiconductor chips including internal circuits respectively formed thereon; electrostatic protection circuits that are respectively formed on the first and the second semiconductor chips, and that protect the internal circuits from static electricity; first pad electrodes respectively formed on the first and the second semiconductor chips, and connected to the internal circuits via the electrostatic protection circuits; second pad electrodes respectively formed on the first and the second semiconductor chips, and connected to the internal circuits, not via the electrostatic protection circuits; and a semiconductor package on which the first and the second semiconductor chips are mounted, and which has external terminals shared by the first pad electrode of the first semiconductor chip and by the second pad electrode of the second semiconductor chip.
  • FIG. 1 is a schematic block diagram of a solid state drive to which a semiconductor device according to a first embodiment of the present invention is applied.
  • Fig. 2 is a schematic block diagram of the semiconductor device according to the first embodiment.
  • Fig. 3 is a schematic perspective view of the semiconductor device shown in Fig. 2.
  • Fig. 4 is a schematic diagram of an electrostatic protection circuit applicable to the semiconductor device shown in Fig. 2.
  • Fig. 5 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a second embodiment of the present invention.
  • Fig. 6 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a third embodiment of the present invention.
  • Fig. 7 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a fourth embodiment of the present invention.
  • Fig. 8 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a fifth embodiment of the present invention.
  • Fig. 9 is a schematic block diagram of a solid state drive to which a semiconductor device according to a sixth embodiment of the present invention is applied.
  • Fig. 10 is a schematic block diagram of a drive control circuit shown in Fig. 9.
  • Fig. 11 is a schematic block diagram of a processor shown in Fig. 10.
  • First Embodiment Fig. 1 is a schematic block diagram of a solid state drive to which a semiconductor device according to a first embodiment of the present invention is applied.
  • the solid state drive includes n NAND memories 3-1 to 3-n (n is an integer equal to or greater than 2) , and a controller 1 that controls to drive the NAND memories 3-1 to 3-n.
  • the NAND memories 3-1 to 3-n are connected in parallel to the controller 1 via a bus 2.
  • the NAND memory 3-1 includes m semiconductor chips CPl to CPm (m is an integer equal to or greater than 2) .
  • CPl to CPm On the semiconductor chips CPl to CPm, internal circuits Kl to PCm are respectively mounted, and pad electrodes PDl to PDm connected to the internal circuits Kl to Km are formed, respectively.
  • a semiconductor memory element such as a NAND flush memory
  • a NAND flush memory may include a unit cell array, a decoder, a sense amplifier, a charge pump circuit, and a page buffer.
  • the m semiconductor chips CPl to CPm are mounted on a single semiconductor package PKl, and the semiconductor package PKl has an external terminal T shared by the pad electrodes PDl to PDm on the m semiconductor chips CPl to CPm.
  • the semiconductor chips CPl to CPm may be stacked, or the semiconductor chips CPl to CPm may be arranged in the same plane.
  • the semiconductor chips CPl to CPm may be mounted by face-down mounting or face-up mounting.
  • the m pad electrodes PDl to PDm can be connected to the single external terminal T by bonding wires BW.
  • the pad electrodes PDl to PDm and the external terminal T may be connected to one another via bump electrodes formed on the pad electrodes PDl to PDm.
  • the pad electrodes PDl to PDm and the external terminal T may be connected to one another via the penetrating electrode.
  • an electrostatic protection circuit CD is mounted only on the semiconductor chip CPm.
  • the pad electrode PDm on the semiconductor chip CPm is connected to the internal circuit Km via the electrostatic protection circuit CD.
  • the pad electrodes PDl to PDm-I are respectively connected to the internal circuits Kl to Km-I via no electrostatic protection circuit. This prevents that the capacitance of the m electrostatic protection circuits is added to the external terminal T, even when the single external terminal T is shared by the m pad electrodes PDl to PDm.
  • the pad electrodes PDl to PDm-I of the semiconductor chips CPl to CPm-I can be connected via the bonding wires BW and the pad electrode PDm.
  • This arrangement enables sharing of the electrostatic protection circuit CD on the semiconductor chip CPm, even when no electrostatic protection circuit CD is mounted on the semiconductor chips CPl to CPm-I.
  • the above embodiment describes a method of mounting the electrostatic protection circuit CD only on one semiconductor chip CPm among the m semiconductor chips CPl to CPm.
  • the m semiconductor chips CPl to CPm not greater than (m-1) number of the semiconductor chips may incorporate an electrostatic protection circuit.
  • the above embodiment describes the NAND memories 3-1 to 3-n, as an example of a semiconductor device on which an electrostatic protection circuit is to be mounted.
  • the semiconductor device may be a nonvolatile semiconductor memory such as a NOR memory, or a volatile semiconductor memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) .
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • Examples of such a semiconductor device on which an electrostatic protection circuit is to be mounted may include a processor, a logic circuit, a solid-state image sensor, and a light emitting element such as a light emitting diode or a laser diode, as well as the semiconductor memory.
  • Fig. 2 is a schematic block diagram of the semiconductor device according to the first embodiment of the present invention.
  • the number of the semiconductor chips CPl to CPm shown in Fig. 1 is four as an example.
  • semiconductor chips CPl to CP4 each include, for example, eight address terminals AO to A7, one read/write terminal R/W, one chip select terminal CS, and four data terminals Dl to D4.
  • a semiconductor package PK2 includes 17 external terminals Tl to T17.
  • the four semiconductor chips CPl to CP4 are mounted, and the address terminals AO to A7 of the four semiconductor chips CPl to CP4 are respectively connected to the external terminals Tl to T8.
  • the read/write terminal R/W of each of the four semiconductor chips CPl to CP4 is connected to the external terminal T9.
  • the chip select terminal CS of the semiconductor chip CPl is connected to the external terminal TlO
  • the chip select terminal CS of the semiconductor chip CP2 is connected to the external terminal TIl
  • the chip select terminal CS of the semiconductor chip CP3 is connected to the external terminal T12
  • the chip select terminal CS of the semiconductor chip CP4 is connected to the external terminal T13.
  • the data terminals Dl to D4 of the four semiconductor chips CPl to CP4 are respectively connected to the external terminals T14 to T17.
  • an electrostatic protection circuit may be mounted, for example, on the semiconductor chip CPl among the semiconductor chips CPl to CP4.
  • Fig. 3 is a perspective schematic view of the semiconductor device shown in Fig. 2.
  • the pad electrodes PDl to PD4 are formed as the address terminals AO to A7, the read/write terminals R/W, the chip select terminals CS, and the data terminals Dl to D4 shown in Fig. 2.
  • the semiconductor chips CPl to CP4 can be stacked in a shifted manner so that the pad electrodes PDl to PD4 are exposed.
  • the pad electrodes PDl to PD4 of, for example, the address terminals AO shown in Fig. 2 are commonly connected to the external terminal Tl via the bonding wires BW. In this way, the single external terminal Tl can be shared by the address terminals AO of the four semiconductor chips CPl to CP4.
  • Fig. 4 is a schematic diagram of an electrostatic protection circuit applicable to the semiconductor device shown in Fig. 2.
  • the semiconductor chips CPl to CP4 include the internal circuits Kl to K4, respectively.
  • the pad electrodes PDl to PD4 are respectively connected to the internal circuits Kl to K4 via resistors Rl to R4, and are also commonly connected to the external terminal Tl.
  • a junction between the resistor Rl and the internal circuit Kl is connected to a low voltage potential VSS via a diode Da, and is also connected to a high voltage potential VDD via a diode Db.
  • the diodes Da and Db can constitute an electrostatic protection circuit.
  • the diode Da or the diode Db breaks down, so that the potential of the pad electrode PDl can be maintained in a range between the low voltage potential VSS and the high voltage potential VDD. Accordingly, the internal circuit Kl is protected from electrostatic breakdown. Further, because the pad electrodes PD2 to PD4 are connected to the pad electrode PDl, the potential of the pad electrodes PD2 to PD4 can be maintained at the same potential as the pad electrode PDl. Accordingly, the internal circuits K2 to K4 are protected from electrostatic breakdown even when no electrostatic protection circuit is mounted on the semiconductor chips CP2 to CP4.
  • the pad electrodes PDl to PD4 are commonly connected to the external terminal Tl, only the capacitance of the diodes Da and Db of one semiconductor chip CPl is added. This prevents an increase in capacitance to be added to the external terminal Tl.
  • the foregoing describes a method of mounting an electrostatic protection circuit only on the semiconductor chip CPl among the four semiconductor chips CPl to CP4.
  • This method requires to prepare the semiconductor chip CPl incorporating an electrostatic protection circuit, and the semiconductor chips CP2 to CP4 incorporating no electrostatic protection circuit. This may cause an increase in manufacturing cost and complex management process of the semiconductor chips CPl to CP4.
  • Fig. 5 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a second embodiment of the present invention.
  • semiconductor chips CPU to CP14 include internal circuits KIl to K14, respectively.
  • the semiconductor chips CPU to CP14 include pad electrodes PDIa to PD4a, and PDIb to PD4b, respectively.
  • the pad electrodes PDIa to PD4a are connected to the internal circuits KlI to K14 via resistors RIa to R4a, respectively, and the pad electrodes PDIb to PD4b are connected to the internal circuits KIl to K14 via resistors Rib to R4b and electrostatic protection circuits CDl to CD4, respectively.
  • the electrostatic protection circuits CDl to CD4 include diodes DIa to D4a, and DIb to D4b, respectively.
  • the semiconductor chips CPU to CP14 are commonly mounted on a single semiconductor package, and the pad electrodes PDIb and PD2a to PD4a are commonly connected to an external terminal T21 of the semiconductor package via bonding wires BWl to BW4.
  • the electrostatic protection circuit CDl of the semiconductor chip CPU can be shared by the semiconductor chips CPU to CP14. Accordingly, the electrostatic protection function of the semiconductor chips CPU to CP14 can be secured by using only the electrostatic protection circuit CDl of the semiconductor chip CPU. Further, the pad electrodes PDIb and PD2a to PD4a respectively connected to the internal circuits KIl to K14 can be commonly connected to the external terminal T21. This prevents that the capacitance of the electrostatic protection circuits CD2 to CD4 is added to the external terminal T21, without changing the structure of the semiconductor chips CPU to CP14. It also becomes possible to prevent an increase in manufacturing cost and complex management process of the semiconductor chips CPU to CP14, while preventing a reduction in operating frequency of the internal circuits KIl to K14 and an increase in electric power consumption.
  • Fig. 6 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a third embodiment of the present invention.
  • the semiconductor chip CPU includes pad electrodes PDlIa and PDlIb as input terminals that receive an input to the internal circuit KlI.
  • the pad electrode PDlIa is connected to a first input terminal of an OR circuit ORl via a resistor RlIa, and the first input terminal of the OR circuit ORl is connected to the low voltage potential VSS via a resistor Rl2a.
  • the pad electrode PDlIb is connected to a second input terminal of the OR circuit ORl via a resistor RlIb, and the second input terminal of the OR circuit ORl is connected to the low voltage potential VSS via a resistor R12b.
  • An output terminal of the OR circuit ORl is connected to the internal circuit KlI.
  • a junction between the resistor RlIb and the second input terminal of the OR circuit ORl is connected to the low voltage potential VSS via a diode DlIa, and is also connected to the high voltage potential VDD via a diode DlIb.
  • the pad electrode PDlIb can be connected to an external terminal of the semiconductor package on which the semiconductor chip CPU is mounted.
  • the pad electrode PDlIa can be connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted.
  • wire bonding may be used, for example.
  • the input signal when an input signal is applied to the pad electrode PDlIb, the input signal can be transferred to the internal circuit KlI via the OR circuit ORl.
  • the pad electrode PDlIa When the pad electrode PDlIa is connected to the external terminal of the semiconductor package, the pad electrode PDlIb is open. Because the second input terminal of the OR circuit ORl is connected to the low voltage potential VSS via the resistor R12b, a logical value '0' is input to the second input terminal of the OR circuit ORl. Thus, when an input signal is applied to the pad electrode PDlIa, the input signal can be transferred to the internal circuit KIl via the OR circuit ORl.
  • Fig. 6 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a fourth embodiment of the present invention.
  • Fig. 7 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a fourth embodiment of the present invention.
  • the semiconductor chip CPU includes pad electrodes PD21a and PD21b as output terminals that receive an output from the internal circuit KlI.
  • the internal circuit KIl is connected to the pad electrode PD21a via a buffer B2 and a resistor R21a in order, and is also connected to the pad electrode PD21b via a buffer Bl and a resistor R21b in order.
  • a junction between the resistor R21b and an output terminal of the buffer Bl is connected to the low voltage potential VSS via a diode D21a, and is also connected to the high voltage potential VDD via a diode D21b.
  • the pad electrode PD21b can be connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted.
  • the pad electrode PD21a can be connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted.
  • wire bonding may be used, for example.
  • the capacitance of the pad electrode PD21a can be separated from the capacitances of the diodes D21a and D21b by providing the buffers Bl and B2. This prevents that the capacitances of the diodes D21a and D21b are added to the pad electrode PD21a even when the pad electrodes PD21a and PD21b are commonly connected to the internal circuit KIl.
  • By selecting either the pad electrode PD21a or the pad electrode PD21b it is possible to enable or disable the electrostatic protection function of the output terminals of the semiconductor chip CPU. Further, by selecting the pad electrode PD21a, it is possible to prevent that the capacitance of the electrostatic protection circuit is added to the external terminal via the output terminals of the semiconductor chip CPU.
  • Fifth Embodiment Fig. 8 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a fifth embodiment of the present invention.
  • the semiconductor chip CPU includes, as the internal circuit KIl, an internal circuit input section KlIa, an internal circuit output section KlIb, and an internal circuit OE control section KlIc. Further, the semiconductor chip CPU includes pad electrodes PD31a and PD31b as input-output terminals that receive an input to the internal circuit input section KlIa and an output from the internal circuit output section KlIb.
  • the pad electrode PD31a is connected to a first input terminal of an OR circuit 0R2 via a resistor R31a, and the first input terminal of the OR circuit 0R2 is connected to the low voltage potential VSS via a resistor R32a.
  • the pad electrode PD31b is connected to a second input terminal of the OR circuit 0R2 via a resistor R31b, and the second input terminal of the OR circuit 0R2 is connected to the low voltage potential VSS via a resistor R32b.
  • An output terminal of the OR circuit 0R2 is connected to the internal circuit input section KlIa.
  • the internal circuit output section KlIb is connected to the pad electrode PD31a via a tri-state buffer T2 and the resistor R31a in order, and is also connected to the pad electrode PD31b via a tri-state buffer Tl and the resistor R31b in order.
  • a junction between the resistor R31b and an output terminal of the tri-state buffer Tl is connected to the low voltage potential VSS via a diode D31a, and is also connected to the high voltage potential VDD via a diode D31b.
  • the internal circuit OE control section KlIc is connected to a switching control terminal of the tri-state buffer Tl, and is also connected to a switching control terminal of the tri-state buffer T2.
  • the pad electrode PD31b is connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted.
  • the pad electrode PD31a is connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted.
  • wire bonding may be used, for example.
  • an input signal when an input signal is applied to the pad electrode PD31b, the input signal can be transferred to the internal circuit input section KlIa via the OR circuit OR2.
  • an output enable signal from the internal circuit OE control section KlIc an output signal from the internal circuit output section KlIb is transferred to the pad electrode PD31b via the tri-state buffer Tl, and is also transferred to the pad electrode PD31a via the tri- state buffer T2. This operation does not affect the behavior of the circuit because the pad electrode PD31a is open.
  • the pad electrode PD31a When the pad electrode PD31a is connected to the external terminal of the semiconductor package, the pad electrode PD31b is open. Because the second input terminal of the OR circuit 0R2 is connected to the low voltage potential VSS via the resistor R32b, a logical value f 0' is input to the second input terminal of the OR circuit OR2. Thus, when an input signal is applied to the pad electrode PD31a, the input signal can be transferred to the internal circuit input section KlIa via the OR circuit OR2.
  • an output signal from the internal circuit output section KlIb is transferred to the pad electrode PD31a via the tri-state buffer T2, and is also transferred to the pad electrode PD31b via the tri- state buffer Tl. This operation does not affect the behavior of the circuit because the pad electrode PD31b is open.
  • the foregoing describes a method of providing the tri- state buffers Tl and T2 to connect the internal circuit output section KlIb to the pad electrodes PD31a and PD31b.
  • Circuits other than the tri-state buffers Tl and T2 may be used, as long as a plurality of outputs can be connected to one line as in an open collector.
  • the circuit shown in Fig. 8 may be used, for example, for the data terminals Dl to D4 shown in Fig. 2.
  • Fig. 9 is a schematic block diagram of a solid state drive to which a semiconductor device according to a sixth embodiment of the present invention is applied.
  • a solid state drive 11 includes: a plurality of NAND memories 25a to 25d for data storage; a DRAM 24 for data transfer or as a work area; a temperature sensor 23 that detects an internal temperature of the solid state drive 11; a light emitting diode 12 for status indication; a drive control circuit 21 that controls these components; and a power circuit 22 that supplies power to the components.
  • the semiconductor package PK2 can be used on which the semiconductor chips CPl to CP4 are mounted as shown in Fig. 2.
  • the drive control circuit 21 is connected to the NAND memories 25a to 25d and the DRAM 24.
  • the drive control circuit 21 is connected to a host device 14 such as a personal computer via an advanced technology attachment (ATA) interface IFl, to a debug device 15 via a recommended standard (RS) 232C interface IF2, and to the temperature sensor 23 via an inter-integrated circuit (I 2 C) interface IF3.
  • ATA advanced technology attachment
  • RS recommended standard
  • I 2 C inter-integrated circuit
  • the drive control circuit 21 is connected to the light emitting diode 12 via a parallel interface IF4.
  • the power circuit 22 generates a plurality of internal power signals SD from power supplied from an external power supply 13, and provides them to the components.
  • the power circuit 22 also generates a power-on/off-reset signal SP by detecting the rise and the falling of the external power supply 13, and provides it to the drive control circuit 21.
  • the drive control circuit 21 When writing to the NAND memories 25a to 25d, the drive control circuit 21 temporarily stores in the DRAM 24 the write data supplied from the host device 14. The drive control circuit 21 then transfers the write data stored in the DRAM 24 to the NAND memories 25a to 25d, and writes the write data to the NAND memories 25a to 25d.
  • the drive control circuit 21 When reading out from the NAND memories 25a to 25d, the drive control circuit 21 reads out read data from the NAND memories 25a to 25d, and temporarily stores it in the DRAM 24. The drive control circuit 21 then transfers the read data stored in the DRAM 24 to the host device 14.
  • Fig. 10 is a schematic block diagram of the drive control circuit shown in Fig. 9.
  • the drive control circuit 21 includes circuit control buses Bl and B2, and a data access bus B3.
  • the circuit control bus B2 is connected to a processor 31 that controls the drive control circuit 21.
  • the circuit control bus Bl is connected via a ROM controller 34 to a boot ROM 33 that stores therein a boot program for booting management programs (FW) .
  • the circuit control bus Bl is connected to a clock controller 32 that provides a reset signal CK and a clock signal RS to the components in response to the power- on/off-reset signal SP from the power circuit 22.
  • the circuit control bus Bl is connected to the circuit control bus B2, so that the circuit control bus Bl is connected to an I 2 C circuit 35 that receives data from the temperature sensor 23, to a parallel IO circuit 36 that provides a status indication signal to the light emitting diode 12, and to a serial IO circuit 37 that controls the RS232C interface IF2.
  • Both the data access bus B3 and the circuit control bus B2 are connected to an ATA interface controller 38 that controls the ATA interface IFl, an error detection and correction (ECC) circuit 39 that corrects an error in data read from and written to the NAND memories 25a to 25d, a NAND controller 41 that controls deleting, writing, and reading of the NAND memories 25a to 25d, and a DRAM controller 40 that controls deleting, writing, and reading of the DRAM 24.
  • ECC error detection and correction
  • One side of the ATA interface controller 38 is used for transmitting and receiving data to and from the host device 14 via the ATA interface IFl.
  • the data access bus B3 is connected via an SRAM controller 42 to an SRAM 43 used as a data work area.
  • the NAND controller 41 includes a NAND interface 53 serving as an interface with the four NAND memories 25a to 25d, an ECC circuit section 52 that corrects an error in data read from and written to the NAND memories 25a to 25d, and a direct memory access (DMA) controller 51 that controls DMA transfer between the NAND memories 25a to 25d and the DRAM 24.
  • DMA direct memory access
  • the clock controller 32 Upon receiving the power-on/off-reset signal SP supplied from the power circuit 22, the clock controller 32 provides the reset signal CK and the clock signal RS to the components.
  • the ROM controller 34 reads out the boot program from the boot ROM 33, and transfers it to the processor 31.
  • the processor 31 loads the management programs from the NAND memories 25a to 25d to the SRAM 43.
  • the NAND controller 41 can access the NAND memories 25a to 25d according to a management program loaded to the SRAM 43, and control deleting, writing, and reading of the NAND memories 25a to 25d.
  • Fig. 11 is a schematic block diagram of the processor shown in Fig. 10.
  • the processor 31 includes a data management section 61, an ATA command processing section 62, a security management section 63, a boot loader 64, an initialization control section 65, and a debug support section 66.
  • the data management section 61 controls data transfer between the NAND memories 25a to 25d and the DRAM 24, and various functions of the NAND memories 25a to 25d, via the NAND controller 41, the ECC circuit 39, and the I 2 C circuit 35.
  • the ATA command processing section 62 performs data transfer in cooperation with the data management section 61, via the ATA interface controller 38 and the DRAM controller 40.
  • the security management section 63 manages various kinds of security information, in cooperation with the data management section 61 and the ATA command processing section 62.
  • the boot loader 64 loads the management programs (FW) from the NAND memories 25a to 25d to the SRAM 43 at power- on time.
  • the initialization control section 65 performs initialization of the controllers/circuits on the drive control circuit 21.
  • the debug support section 66 processes the debug data externally supplied via the RS232C interface IF2.
  • the semiconductor package PK2 on which the semiconductor chips CPl to CP4 are mounted as shown in Fig. 2 is used for the NAND memories 25a to 25d.

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Abstract

On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.

Description

DESCRIPTION
SEMICONDUCTOR DEVICE
TECHNICAL FIELD
The present invention relates to a semiconductor device, and is preferably applied to a electrostatic protection system of a semiconductor device including a plurality of stacked semiconductor chips.
BACKGROUND ART
To prevent electrostatic breakdown due to static electricity in an internal circuit, some semiconductor chips incorporating an internal circuit include an electrostatic protection circuit on a pad electrode thereof. In general, such an electrostatic protection circuit is constituted by a large diode because the circuit is required to be resistant to high current generated due to the discharge of the static electricity. Attributed to the diode, large capacitors are added in parallel to the pad electrode of the semiconductor chip, causing a reduction in operating frequency of the internal circuit formed on the semiconductor chip and an increase in electric power consumption. As an alternative external storage device of a hard disk, a solid state drive has attracted attention (Patent Document 1) . Because a solid state drive employs a NAND flush memory as a nonvolatile storage medium for reading and writing data, a mechanical structure such as a hard disk is not required. This brings advantages as achieving a reduction in size and weight, low power consumption, excellent impact resistance, and short access time.
To enable a solid state drive to have an increased data capacitance, there has been a method of stacking on a single semiconductor package a plurality of semiconductor chips incorporating NAND flush memories. In stacking a plurality of semiconductor chips on a single semiconductor package, data lines and address lines of NAND flush memories are not drawn from each semiconductor chip individually on the semiconductor package. Instead, each set of the data lines and of the address lines shares one external terminal among the semiconductor chips, for the purpose of reducing the number of external terminals of the semiconductor package.
In a conventional solid state drive, however, an electrostatic protection circuit is mounted on each semiconductor chip. Thus, when one external terminal is shared among a plurality of semiconductor chips, electrostatic protection circuits as many as the semiconductor chips are connected in parallel to the external terminal. Because only one electrostatic protection circuit adds a large capacitance to the semiconductor chip, much larger capacitances are added to the external terminal in parallel. This causes a further reduction in operating frequency of the internal circuit formed on the semiconductor chip, and a further increase in electric power consumption. [Patent Document 1] Japanese Patent Application Laid-open No. 7-302176
An object of the present invention is to provide a semiconductor device capable of reducing the capacitance to be added to external terminals, without degrading the electrostatic protection function of a plurality of semiconductor chips sharing the external terminals.
DISCLOSURE OF INVENTION To solve the above-described problems, according to an aspect of the present invention, there are provided: a plurality of semiconductor chips including internal circuits respectively formed thereon; a semiconductor package on which the semiconductor chips are mounted, and which has external terminals shared by pad electrodes of the semiconductor chips; and an electrostatic protection circuit that is formed on a part of the semiconductor chips, and that protects the internal circuits from static electricity.
According to another aspect of the present invention, there are provided: first and second semiconductor chips including internal circuits respectively formed thereon; electrostatic protection circuits that are respectively formed on the first and the second semiconductor chips, and that protect the internal circuits from static electricity; first pad electrodes respectively formed on the first and the second semiconductor chips, and connected to the internal circuits via the electrostatic protection circuits; second pad electrodes respectively formed on the first and the second semiconductor chips, and connected to the internal circuits, not via the electrostatic protection circuits; and a semiconductor package on which the first and the second semiconductor chips are mounted, and which has external terminals shared by the first pad electrode of the first semiconductor chip and by the second pad electrode of the second semiconductor chip.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram of a solid state drive to which a semiconductor device according to a first embodiment of the present invention is applied. Fig. 2 is a schematic block diagram of the semiconductor device according to the first embodiment.
Fig. 3 is a schematic perspective view of the semiconductor device shown in Fig. 2.
Fig. 4 is a schematic diagram of an electrostatic protection circuit applicable to the semiconductor device shown in Fig. 2.
Fig. 5 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a second embodiment of the present invention.
Fig. 6 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a third embodiment of the present invention. Fig. 7 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a fourth embodiment of the present invention.
Fig. 8 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a fifth embodiment of the present invention.
Fig. 9 is a schematic block diagram of a solid state drive to which a semiconductor device according to a sixth embodiment of the present invention is applied.
Fig. 10 is a schematic block diagram of a drive control circuit shown in Fig. 9.
Fig. 11 is a schematic block diagram of a processor shown in Fig. 10.
BEST MODE(S) FOR CARRYING OUT THE INVENTION
Exemplary embodiments of a semiconductor device according to the present invention are described with reference to the accompanying drawings. The present invention is not limited by the embodiments. First Embodiment Fig. 1 is a schematic block diagram of a solid state drive to which a semiconductor device according to a first embodiment of the present invention is applied.
In Fig. 1, the solid state drive includes n NAND memories 3-1 to 3-n (n is an integer equal to or greater than 2) , and a controller 1 that controls to drive the NAND memories 3-1 to 3-n. The NAND memories 3-1 to 3-n are connected in parallel to the controller 1 via a bus 2. For example, the NAND memory 3-1 includes m semiconductor chips CPl to CPm (m is an integer equal to or greater than 2) . On the semiconductor chips CPl to CPm, internal circuits Kl to PCm are respectively mounted, and pad electrodes PDl to PDm connected to the internal circuits Kl to Km are formed, respectively. In each of the internal circuits Kl to Km, for example, a semiconductor memory element such as a NAND flush memory can be provided, and such a NAND flush memory may include a unit cell array, a decoder, a sense amplifier, a charge pump circuit, and a page buffer.
The m semiconductor chips CPl to CPm are mounted on a single semiconductor package PKl, and the semiconductor package PKl has an external terminal T shared by the pad electrodes PDl to PDm on the m semiconductor chips CPl to CPm. As a method of mounting the semiconductor chips CPl to CPm on the semiconductor package PKl, the semiconductor chips CPl to CPm may be stacked, or the semiconductor chips CPl to CPm may be arranged in the same plane. The semiconductor chips CPl to CPm may be mounted by face-down mounting or face-up mounting. As a method of allowing the m pad electrodes PDl to PDm to share the single external terminal T, the m pad electrodes PDl to PDm can be connected to the single external terminal T by bonding wires BW. Alternatively, by flip-mounting the semiconductor chips CPl to CPm, the pad electrodes PDl to PDm and the external terminal T may be connected to one another via bump electrodes formed on the pad electrodes PDl to PDm. Alternatively, by forming a penetrating electrode in the semiconductor chips CPl to CPm, the pad electrodes PDl to PDm and the external terminal T may be connected to one another via the penetrating electrode.
Among the m semiconductor chips CPl to CPm, an electrostatic protection circuit CD is mounted only on the semiconductor chip CPm. The pad electrode PDm on the semiconductor chip CPm is connected to the internal circuit Km via the electrostatic protection circuit CD. On the other hand, as to (m-1) number of the semiconductor chips CPl to CPm-I other than the semiconductor chip CPm, the pad electrodes PDl to PDm-I are respectively connected to the internal circuits Kl to Km-I via no electrostatic protection circuit. This prevents that the capacitance of the m electrostatic protection circuits is added to the external terminal T, even when the single external terminal T is shared by the m pad electrodes PDl to PDm. The same applies to the NAND memories 3-2 to 3-n other than the NAND memory 3-1.
As to (m-1) number of the semiconductor chips CPl to CPm-I other than the semiconductor chip CPm, the pad electrodes PDl to PDm-I of the semiconductor chips CPl to CPm-I can be connected via the bonding wires BW and the pad electrode PDm. This arrangement enables sharing of the electrostatic protection circuit CD on the semiconductor chip CPm, even when no electrostatic protection circuit CD is mounted on the semiconductor chips CPl to CPm-I. Thus, it becomes possible to reduce the capacitance to be added to the external terminal T, without degrading the electrostatic protection function of the m semiconductor chips CPl to CPm that share the external terminal T. This prevents a reduction in operating frequency of the internal circuits Kl to Km respectively formed on the semiconductor chips CPl to CPm, and an increase in electric power consumption.
The above embodiment describes a method of mounting the electrostatic protection circuit CD only on one semiconductor chip CPm among the m semiconductor chips CPl to CPm. Among the m semiconductor chips CPl to CPm, not greater than (m-1) number of the semiconductor chips may incorporate an electrostatic protection circuit. The above embodiment describes the NAND memories 3-1 to 3-n, as an example of a semiconductor device on which an electrostatic protection circuit is to be mounted. The semiconductor device may be a nonvolatile semiconductor memory such as a NOR memory, or a volatile semiconductor memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) . Examples of such a semiconductor device on which an electrostatic protection circuit is to be mounted may include a processor, a logic circuit, a solid-state image sensor, and a light emitting element such as a light emitting diode or a laser diode, as well as the semiconductor memory.
Fig. 2 is a schematic block diagram of the semiconductor device according to the first embodiment of the present invention. In the following embodiment, the number of the semiconductor chips CPl to CPm shown in Fig. 1 is four as an example.
In Fig. 2, semiconductor chips CPl to CP4 each include, for example, eight address terminals AO to A7, one read/write terminal R/W, one chip select terminal CS, and four data terminals Dl to D4. A semiconductor package PK2 includes 17 external terminals Tl to T17.
On the semiconductor package PK2, the four semiconductor chips CPl to CP4 are mounted, and the address terminals AO to A7 of the four semiconductor chips CPl to CP4 are respectively connected to the external terminals Tl to T8. The read/write terminal R/W of each of the four semiconductor chips CPl to CP4 is connected to the external terminal T9. The chip select terminal CS of the semiconductor chip CPl is connected to the external terminal TlO, the chip select terminal CS of the semiconductor chip CP2 is connected to the external terminal TIl, the chip select terminal CS of the semiconductor chip CP3 is connected to the external terminal T12, and the chip select terminal CS of the semiconductor chip CP4 is connected to the external terminal T13. The data terminals Dl to D4 of the four semiconductor chips CPl to CP4 are respectively connected to the external terminals T14 to T17.
To each of the address terminals AO to A7, the read/write terminals R/W, the chip select terminals CS, and the data terminals Dl to D4, an electrostatic protection circuit may be mounted, for example, on the semiconductor chip CPl among the semiconductor chips CPl to CP4. Fig. 3 is a perspective schematic view of the semiconductor device shown in Fig. 2.
In Fig. 3, on the semiconductor chips CPl to CP4, the pad electrodes PDl to PD4 are formed as the address terminals AO to A7, the read/write terminals R/W, the chip select terminals CS, and the data terminals Dl to D4 shown in Fig. 2. In stacking and mounting the four semiconductor chips CPl to CP4 on the semiconductor package PK2, the semiconductor chips CPl to CP4 can be stacked in a shifted manner so that the pad electrodes PDl to PD4 are exposed. Further, the pad electrodes PDl to PD4 of, for example, the address terminals AO shown in Fig. 2 are commonly connected to the external terminal Tl via the bonding wires BW. In this way, the single external terminal Tl can be shared by the address terminals AO of the four semiconductor chips CPl to CP4.
Fig. 4 is a schematic diagram of an electrostatic protection circuit applicable to the semiconductor device shown in Fig. 2.
In Fig. 4, the semiconductor chips CPl to CP4 include the internal circuits Kl to K4, respectively. The pad electrodes PDl to PD4 are respectively connected to the internal circuits Kl to K4 via resistors Rl to R4, and are also commonly connected to the external terminal Tl. A junction between the resistor Rl and the internal circuit Kl is connected to a low voltage potential VSS via a diode Da, and is also connected to a high voltage potential VDD via a diode Db. The diodes Da and Db can constitute an electrostatic protection circuit.
When a surge voltage is applied to the external terminal Tl, the diode Da or the diode Db breaks down, so that the potential of the pad electrode PDl can be maintained in a range between the low voltage potential VSS and the high voltage potential VDD. Accordingly, the internal circuit Kl is protected from electrostatic breakdown. Further, because the pad electrodes PD2 to PD4 are connected to the pad electrode PDl, the potential of the pad electrodes PD2 to PD4 can be maintained at the same potential as the pad electrode PDl. Accordingly, the internal circuits K2 to K4 are protected from electrostatic breakdown even when no electrostatic protection circuit is mounted on the semiconductor chips CP2 to CP4. Although the pad electrodes PDl to PD4 are commonly connected to the external terminal Tl, only the capacitance of the diodes Da and Db of one semiconductor chip CPl is added. This prevents an increase in capacitance to be added to the external terminal Tl.
The foregoing describes a method of mounting an electrostatic protection circuit only on the semiconductor chip CPl among the four semiconductor chips CPl to CP4. This method requires to prepare the semiconductor chip CPl incorporating an electrostatic protection circuit, and the semiconductor chips CP2 to CP4 incorporating no electrostatic protection circuit. This may cause an increase in manufacturing cost and complex management process of the semiconductor chips CPl to CP4.
For this reason, by preparing semiconductor chips incorporating an electrostatic protection circuit and by changing external wiring, some semiconductor chips may have an electrostatic protection circuit connected to an external terminal of a semiconductor package, and the other semiconductor chips may have an electrostatic protection circuit not connected to the external terminal of the semiconductor package. The following embodiment describes a method using bonding wires for the external wiring. Second Embodiment
Fig. 5 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a second embodiment of the present invention. In Fig. 5, semiconductor chips CPU to CP14 include internal circuits KIl to K14, respectively. Further, the semiconductor chips CPU to CP14 include pad electrodes PDIa to PD4a, and PDIb to PD4b, respectively. The pad electrodes PDIa to PD4a are connected to the internal circuits KlI to K14 via resistors RIa to R4a, respectively, and the pad electrodes PDIb to PD4b are connected to the internal circuits KIl to K14 via resistors Rib to R4b and electrostatic protection circuits CDl to CD4, respectively. The electrostatic protection circuits CDl to CD4 include diodes DIa to D4a, and DIb to D4b, respectively. The semiconductor chips CPU to CP14 are commonly mounted on a single semiconductor package, and the pad electrodes PDIb and PD2a to PD4a are commonly connected to an external terminal T21 of the semiconductor package via bonding wires BWl to BW4.
This allows the electrostatic protection circuit CDl of the semiconductor chip CPU to be shared by the semiconductor chips CPU to CP14. Accordingly, the electrostatic protection function of the semiconductor chips CPU to CP14 can be secured by using only the electrostatic protection circuit CDl of the semiconductor chip CPU. Further, the pad electrodes PDIb and PD2a to PD4a respectively connected to the internal circuits KIl to K14 can be commonly connected to the external terminal T21. This prevents that the capacitance of the electrostatic protection circuits CD2 to CD4 is added to the external terminal T21, without changing the structure of the semiconductor chips CPU to CP14. It also becomes possible to prevent an increase in manufacturing cost and complex management process of the semiconductor chips CPU to CP14, while preventing a reduction in operating frequency of the internal circuits KIl to K14 and an increase in electric power consumption.
The following describes specific structures of an electrostatic protection circuit separately, in which pad electrodes of the semiconductor chip CPU are used as input terminals, as output terminals, or as input-output terminals . Third Embodiment
Fig. 6 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a third embodiment of the present invention.
In Fig. 6, the semiconductor chip CPU includes pad electrodes PDlIa and PDlIb as input terminals that receive an input to the internal circuit KlI. The pad electrode PDlIa is connected to a first input terminal of an OR circuit ORl via a resistor RlIa, and the first input terminal of the OR circuit ORl is connected to the low voltage potential VSS via a resistor Rl2a. The pad electrode PDlIb is connected to a second input terminal of the OR circuit ORl via a resistor RlIb, and the second input terminal of the OR circuit ORl is connected to the low voltage potential VSS via a resistor R12b. An output terminal of the OR circuit ORl is connected to the internal circuit KlI.
A junction between the resistor RlIb and the second input terminal of the OR circuit ORl is connected to the low voltage potential VSS via a diode DlIa, and is also connected to the high voltage potential VDD via a diode DlIb.
To enable the electrostatic protection function of the input terminals of the semiconductor chip CPU, the pad electrode PDlIb can be connected to an external terminal of the semiconductor package on which the semiconductor chip CPU is mounted. To disable the electrostatic protection function of the input terminals of the semiconductor chip CPU, the pad electrode PDlIa can be connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted. As a method of connecting the pad electrodes PDlIa and PDlIb to the external terminal of the semiconductor package, wire bonding may be used, for example. When the pad electrode PDlIb is connected to the external terminal of the semiconductor package, the pad electrode PDlIa is open. Because the first input terminal of the OR circuit ORl is connected to the low voltage potential VSS via the resistor R12a, a logical value 1O' is input to the first input terminal of the OR circuit ORl.
Thus, when an input signal is applied to the pad electrode PDlIb, the input signal can be transferred to the internal circuit KlI via the OR circuit ORl.
When the pad electrode PDlIa is connected to the external terminal of the semiconductor package, the pad electrode PDlIb is open. Because the second input terminal of the OR circuit ORl is connected to the low voltage potential VSS via the resistor R12b, a logical value '0' is input to the second input terminal of the OR circuit ORl. Thus, when an input signal is applied to the pad electrode PDlIa, the input signal can be transferred to the internal circuit KIl via the OR circuit ORl.
By selecting either the pad electrode PDlIa or the pad electrode PDlIb, it is possible to enable or disable the electrostatic protection function of the input terminals of the semiconductor chip CPU. Further, even by selecting any of the pad electrodes PDlIa and PDlIb, the input signal can be transferred to the internal circuit KIl via the OR circuit ORl. The circuit shown in Fig. 6 may be used, for example, for the address terminals AO to A7 and the read/write terminal R/W shown in Fig. 2. Fourth Embodiment Fig. 7 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a fourth embodiment of the present invention. In Fig. 7, the semiconductor chip CPU includes pad electrodes PD21a and PD21b as output terminals that receive an output from the internal circuit KlI. The internal circuit KIl is connected to the pad electrode PD21a via a buffer B2 and a resistor R21a in order, and is also connected to the pad electrode PD21b via a buffer Bl and a resistor R21b in order.
A junction between the resistor R21b and an output terminal of the buffer Bl is connected to the low voltage potential VSS via a diode D21a, and is also connected to the high voltage potential VDD via a diode D21b.
To enable the electrostatic protection function of the output terminals of the semiconductor chip CPU, the pad electrode PD21b can be connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted. To disable the electrostatic protection function of the output terminals of the semiconductor chip CPU, the pad electrode PD21a can be connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted. As a method of connecting the pad electrodes PD21a and
PD21b to the external terminal of the semiconductor package, wire bonding may be used, for example.
The capacitance of the pad electrode PD21a can be separated from the capacitances of the diodes D21a and D21b by providing the buffers Bl and B2. This prevents that the capacitances of the diodes D21a and D21b are added to the pad electrode PD21a even when the pad electrodes PD21a and PD21b are commonly connected to the internal circuit KIl. By selecting either the pad electrode PD21a or the pad electrode PD21b, it is possible to enable or disable the electrostatic protection function of the output terminals of the semiconductor chip CPU. Further, by selecting the pad electrode PD21a, it is possible to prevent that the capacitance of the electrostatic protection circuit is added to the external terminal via the output terminals of the semiconductor chip CPU. Fifth Embodiment Fig. 8 is a schematic perspective view of an electrostatic protection circuit applicable to a semiconductor device according to a fifth embodiment of the present invention.
In Fig. 8, the semiconductor chip CPU includes, as the internal circuit KIl, an internal circuit input section KlIa, an internal circuit output section KlIb, and an internal circuit OE control section KlIc. Further, the semiconductor chip CPU includes pad electrodes PD31a and PD31b as input-output terminals that receive an input to the internal circuit input section KlIa and an output from the internal circuit output section KlIb.
The pad electrode PD31a is connected to a first input terminal of an OR circuit 0R2 via a resistor R31a, and the first input terminal of the OR circuit 0R2 is connected to the low voltage potential VSS via a resistor R32a.
The pad electrode PD31b is connected to a second input terminal of the OR circuit 0R2 via a resistor R31b, and the second input terminal of the OR circuit 0R2 is connected to the low voltage potential VSS via a resistor R32b. An output terminal of the OR circuit 0R2 is connected to the internal circuit input section KlIa.
The internal circuit output section KlIb is connected to the pad electrode PD31a via a tri-state buffer T2 and the resistor R31a in order, and is also connected to the pad electrode PD31b via a tri-state buffer Tl and the resistor R31b in order.
A junction between the resistor R31b and an output terminal of the tri-state buffer Tl is connected to the low voltage potential VSS via a diode D31a, and is also connected to the high voltage potential VDD via a diode D31b.
The internal circuit OE control section KlIc is connected to a switching control terminal of the tri-state buffer Tl, and is also connected to a switching control terminal of the tri-state buffer T2.
To enable the electrostatic protection function of the input-output terminals of the semiconductor chip CPU, the pad electrode PD31b is connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted. To disable the electrostatic protection function of the input-output terminals of the semiconductor chip CPU, the pad electrode PD31a is connected to the external terminal of the semiconductor package on which the semiconductor chip CPU is mounted. As a method of connecting the pad electrodes PD31a and PD31b to the external terminal of the semiconductor package, wire bonding may be used, for example. When the pad electrode PD31b is connected to the external terminal of the semiconductor package, the pad electrode PD31a is open. Because the first input terminal of the OR circuit 0R2 is connected to the low voltage potential VSS via the resistor R32a, a logical value 1O' is input to the first input terminal of the OR circuit OR2.
Thus, when an input signal is applied to the pad electrode PD31b, the input signal can be transferred to the internal circuit input section KlIa via the OR circuit OR2. According to an output enable signal from the internal circuit OE control section KlIc, an output signal from the internal circuit output section KlIb is transferred to the pad electrode PD31b via the tri-state buffer Tl, and is also transferred to the pad electrode PD31a via the tri- state buffer T2. This operation does not affect the behavior of the circuit because the pad electrode PD31a is open.
When the pad electrode PD31a is connected to the external terminal of the semiconductor package, the pad electrode PD31b is open. Because the second input terminal of the OR circuit 0R2 is connected to the low voltage potential VSS via the resistor R32b, a logical value f0' is input to the second input terminal of the OR circuit OR2. Thus, when an input signal is applied to the pad electrode PD31a, the input signal can be transferred to the internal circuit input section KlIa via the OR circuit OR2.
According to an output enable signal from the internal circuit OE control section KlIc, an output signal from the internal circuit output section KlIb is transferred to the pad electrode PD31a via the tri-state buffer T2, and is also transferred to the pad electrode PD31b via the tri- state buffer Tl. This operation does not affect the behavior of the circuit because the pad electrode PD31b is open.
The foregoing describes a method of providing the tri- state buffers Tl and T2 to connect the internal circuit output section KlIb to the pad electrodes PD31a and PD31b. Circuits other than the tri-state buffers Tl and T2 may be used, as long as a plurality of outputs can be connected to one line as in an open collector.
The circuit shown in Fig. 8 may be used, for example, for the data terminals Dl to D4 shown in Fig. 2. Sixth Embodiment
Fig. 9 is a schematic block diagram of a solid state drive to which a semiconductor device according to a sixth embodiment of the present invention is applied. In Fig. 9, a solid state drive 11 includes: a plurality of NAND memories 25a to 25d for data storage; a DRAM 24 for data transfer or as a work area; a temperature sensor 23 that detects an internal temperature of the solid state drive 11; a light emitting diode 12 for status indication; a drive control circuit 21 that controls these components; and a power circuit 22 that supplies power to the components. As the NAND memories 25a to 25d, the semiconductor package PK2 can be used on which the semiconductor chips CPl to CP4 are mounted as shown in Fig. 2.
The drive control circuit 21 is connected to the NAND memories 25a to 25d and the DRAM 24. The drive control circuit 21 is connected to a host device 14 such as a personal computer via an advanced technology attachment (ATA) interface IFl, to a debug device 15 via a recommended standard (RS) 232C interface IF2, and to the temperature sensor 23 via an inter-integrated circuit (I2C) interface IF3. Further, the drive control circuit 21 is connected to the light emitting diode 12 via a parallel interface IF4. The power circuit 22 generates a plurality of internal power signals SD from power supplied from an external power supply 13, and provides them to the components. The power circuit 22 also generates a power-on/off-reset signal SP by detecting the rise and the falling of the external power supply 13, and provides it to the drive control circuit 21.
When writing to the NAND memories 25a to 25d, the drive control circuit 21 temporarily stores in the DRAM 24 the write data supplied from the host device 14. The drive control circuit 21 then transfers the write data stored in the DRAM 24 to the NAND memories 25a to 25d, and writes the write data to the NAND memories 25a to 25d.
When reading out from the NAND memories 25a to 25d, the drive control circuit 21 reads out read data from the NAND memories 25a to 25d, and temporarily stores it in the DRAM 24. The drive control circuit 21 then transfers the read data stored in the DRAM 24 to the host device 14.
Fig. 10 is a schematic block diagram of the drive control circuit shown in Fig. 9.
In Fig. 10, the drive control circuit 21 includes circuit control buses Bl and B2, and a data access bus B3. The circuit control bus B2 is connected to a processor 31 that controls the drive control circuit 21. Further, the circuit control bus Bl is connected via a ROM controller 34 to a boot ROM 33 that stores therein a boot program for booting management programs (FW) .
The circuit control bus Bl is connected to a clock controller 32 that provides a reset signal CK and a clock signal RS to the components in response to the power- on/off-reset signal SP from the power circuit 22.
The circuit control bus Bl is connected to the circuit control bus B2, so that the circuit control bus Bl is connected to an I2C circuit 35 that receives data from the temperature sensor 23, to a parallel IO circuit 36 that provides a status indication signal to the light emitting diode 12, and to a serial IO circuit 37 that controls the RS232C interface IF2.
Both the data access bus B3 and the circuit control bus B2 are connected to an ATA interface controller 38 that controls the ATA interface IFl, an error detection and correction (ECC) circuit 39 that corrects an error in data read from and written to the NAND memories 25a to 25d, a NAND controller 41 that controls deleting, writing, and reading of the NAND memories 25a to 25d, and a DRAM controller 40 that controls deleting, writing, and reading of the DRAM 24. One side of the ATA interface controller 38 is used for transmitting and receiving data to and from the host device 14 via the ATA interface IFl.
The data access bus B3 is connected via an SRAM controller 42 to an SRAM 43 used as a data work area. The NAND controller 41 includes a NAND interface 53 serving as an interface with the four NAND memories 25a to 25d, an ECC circuit section 52 that corrects an error in data read from and written to the NAND memories 25a to 25d, and a direct memory access (DMA) controller 51 that controls DMA transfer between the NAND memories 25a to 25d and the DRAM 24.
Upon receiving the power-on/off-reset signal SP supplied from the power circuit 22, the clock controller 32 provides the reset signal CK and the clock signal RS to the components. The ROM controller 34 reads out the boot program from the boot ROM 33, and transfers it to the processor 31. The processor 31 loads the management programs from the NAND memories 25a to 25d to the SRAM 43. The NAND controller 41 can access the NAND memories 25a to 25d according to a management program loaded to the SRAM 43, and control deleting, writing, and reading of the NAND memories 25a to 25d.
Fig. 11 is a schematic block diagram of the processor shown in Fig. 10. In Fig. 11, the processor 31 includes a data management section 61, an ATA command processing section 62, a security management section 63, a boot loader 64, an initialization control section 65, and a debug support section 66.
The data management section 61 controls data transfer between the NAND memories 25a to 25d and the DRAM 24, and various functions of the NAND memories 25a to 25d, via the NAND controller 41, the ECC circuit 39, and the I2C circuit 35.
The ATA command processing section 62 performs data transfer in cooperation with the data management section 61, via the ATA interface controller 38 and the DRAM controller 40.
The security management section 63 manages various kinds of security information, in cooperation with the data management section 61 and the ATA command processing section 62. The boot loader 64 loads the management programs (FW) from the NAND memories 25a to 25d to the SRAM 43 at power- on time.
The initialization control section 65 performs initialization of the controllers/circuits on the drive control circuit 21.
The debug support section 66 processes the debug data externally supplied via the RS232C interface IF2.
The semiconductor package PK2 on which the semiconductor chips CPl to CP4 are mounted as shown in Fig. 2 is used for the NAND memories 25a to 25d. This makes it possible to increase the data capacitance of the NAND memories 25a to 25d, while preventing the NAND memories 25a to 25d from electrostatic breakdown and reducing the load capacitance of the NAND controller 41. As described, according to the present invention, it is possible to reduce the capacitance to be added to the external terminals, without degrading the electrostatic protection function of the semiconductor chips sharing the external terminals.

Claims

1. A semiconductor device comprising: a plurality of semiconductor chips including internal circuits respectively formed thereon; a semiconductor package on which the semiconductor chips are mounted, and which has external terminals shared by pad electrodes on the semiconductor chips; and an electrostatic protection circuit that is formed on a part of the semiconductor chips, and that protects the internal circuits from static electricity.
2. The semiconductor device according to claim 1, wherein the electrostatic protection circuit is a diode formed on the semiconductor chips.
3. The semiconductor device according to claim 2, wherein the internal circuits are NAND flush memories.
4. The semiconductor device according to claim 3, wherein the semiconductor chips are staked and mounted on the semiconductor package.
5. The semiconductor device according to claim 4, wherein the semiconductor package on which the semiconductor chips are mounted constitutes a NAND memory.
6. The semiconductor device according to claim 5, wherein the electrostatic protection circuit is connected between a pad electrode and an internal circuit on one of the semiconductor chips.
7. The semiconductor device according to claim 6, wherein the semiconductor chips include address terminals, data terminals, read/write terminals, and chip select terminals, the address terminals, the data terminals, and the read/write terminals are respectively connected to common external terminals of the semiconductor package via bonding wires, and each of the chip select terminals is individually connected to an external terminal of the semiconductor package via a bonding wire.
8. The semiconductor device according to claim 7, further comprising a controller that controls to drive the NAND memory, wherein the NAND memory is a plurality of NAND memories connected in parallel.
9. The semiconductor device according to claim 8, wherein the controller includes: a boot ROM that stores therein a boot program; an SRAM that stores therein a management program stored in the NAND memory; a processor that loads the management program from the NAND memory to the SRAM according to the boot program; and a NAND controller that controls deleting, writing, and reading of data, by accessing the NAND memory according to the management program loaded to the SRAM.
10. A semiconductor device comprising: first and second semiconductor chips including internal circuits respectively formed thereon; electrostatic protection circuits that are respectively formed on the first and the second semiconductor chips, and that protect the internal circuits from static electricity; first pad electrodes respectively formed on the first and the second semiconductor chips, and connected to the internal circuits via the electrostatic protection circuits; second pad electrodes respectively formed on the first and the second semiconductor chips, and connected to the internal circuits, not via the electrostatic protection circuits; and a semiconductor package on which the first and the second semiconductor chips are mounted, and which has external terminals shared by the first pad electrode of the first semiconductor chip and the second pad electrode of the second semiconductor chip.
11. The semiconductor device according to claim 10, wherein the first pad electrode of the first semiconductor chip, the second pad electrode of the second semiconductor chip, and the external terminals of the semiconductor package are connected to one another via bonding wires.
12. The semiconductor device according to claim 11, wherein when the external terminals are input-output terminals, the first and the second pad electrodes are shared by input sections and output sections of the internal circuits, and the output sections of the internal circuits of the first and the second semiconductor chips are connected to the first and the second pad electrodes respectively via first and second tri-state buffers that are switchably controlled according to an output enable signal .
13. The semiconductor device according to claim 10, wherein the electrostatic protection circuits formed on the first and the second semiconductor chips are diodes.
14. The semiconductor device according to claim 13, wherein the internal circuits are NAND flush memories.
15. The semiconductor device according to claim 14, wherein the first and the second semiconductor chips are stacked and mounted on the semiconductor package.
16. The semiconductor device according to claim 15, wherein the semiconductor package on which the first and the second semiconductor chips are mounted constitutes a NAND memory.
17. The semiconductor device according to claim 16, wherein the first and the second semiconductor chips include address terminals, data terminals, read/write terminals, and chip select terminals, the address terminals, the data terminals, and the read/write terminals are respectively connected to common external terminals of the semiconductor package via bonding wires, and each of the chip select terminals is individually connected to an external terminal of the semiconductor package via a bonding wire.
18. The semiconductor device according to claim 17, further comprising a controller that controls to drive the NAND memory, wherein the NAND memory is a plurality of NAND memories connected in parallel.
19. The semiconductor device according to claim 18, wherein the controller includes: a boot ROM that stores therein a boot program; an SRAM that stores therein a management program stored in the NAND memory; a processor that loads the management program from the NAND memory to the SRAM according to the boot program; and a NAND controller that controls deleting, writing, and reading of data, by accessing the NAND memory according to the management program loaded to the SRAM.
PCT/JP2008/067602 2008-06-04 2008-09-22 Semiconductor device Ceased WO2009147753A1 (en)

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US20140082345A1 (en) 2014-03-20
TW200952147A (en) 2009-12-16
TWI419299B (en) 2013-12-11

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