JP2012129395A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable supplying sufficient power to input/output buffer circuits to which power supply voltages of different voltage levels are supplied, in a smaller power-supply wiring space than before.SOLUTION: In a semiconductor device 3, input/output buffer circuits BF convert a voltage level. First power-supply wiring HVL is connected to first circuits HC of the input/output buffer circuits BF and supplies a first power-supply voltage VCC1 to the first circuits HC. Second power-supply wiring LVL is connected to second circuits LC of the input/output buffer circuits BF and supplies a second power-supply voltage VCC2 to the second circuits LC. A plurality of switches SW are provided at a plurality of positions along third power-supply wiring SVL. Each of the plurality of switches connects one power-supply wiring selected from the first power-supply wiring HVL and the second power-supply wiring LVL with the third power-supply wiring SVL in response to control signals output from an internal circuit 10.

Description

  The present invention relates to a semiconductor device in which a plurality of semiconductor elements are integrated on a substrate.

  In a semiconductor integrated circuit, if the current supply capability of the power supply wiring is not sufficient, the delay time of the circuit becomes long due to a drop in the power supply voltage, and as a result, the circuit may malfunction. The current consumption of a semiconductor integrated circuit is usually different for each circuit cell and further depending on the operation mode of each circuit cell. However, in order to operate the circuit reliably, the circuit cell with the largest current consumption has hitherto been The wiring width and the number of wirings of the power supply wiring are determined according to the operation mode. For this reason, the area occupied by the power supply wiring increases, leading to an increase in the chip area. For example, the following patent document discloses a technique for suppressing an increase in chip area while ensuring a power supply capability necessary for reliably operating a semiconductor integrated circuit.

  Japanese Patent Laid-Open No. 6-151713 (Patent Document 1) relates to a semiconductor integrated circuit device that reads a plurality of data from a data storage circuit and outputs the data to the outside via a data output terminal. In this device, when the logic level of one data among a plurality of data read from the data storage circuit is switched, the data is output by the power supplied from the first power supply wiring having a large current supply capability. Output to the terminal. At this time, the data level of other data is held by the second power supply wiring having a small current supply capability. For this reason, even if the voltage of the first power supply wiring fluctuates when the data logic level is switched, other data is not affected.

  A semiconductor device described in Japanese Patent Laying-Open No. 2008-277788 (Patent Document 2) includes a plurality of basic power supply wires wired in a first direction and a plurality of wires wired in a direction intersecting the first direction. A local power supply wiring, a plurality of normal power switch cells, a plurality of circuit cells, and a power enhanced cell with a power switch are provided. The plurality of normal power switch cells are provided corresponding to the intersections of the plurality of basic power supply lines and the plurality of local power supply lines, respectively, and connect the corresponding basic power supply lines and the local power supply lines. The plurality of circuit cells are connected to the local power supply wiring. The power enhancement cell with a power switch is provided corresponding to a specific circuit cell that consumes a large amount of current among a plurality of circuit cells, and supplies power to a local power supply wiring to which the specific circuit cell is connected.

JP-A-6-151713 JP 2008-277788 A

  When the power supply voltage level of the circuit inside the semiconductor chip is different from the external power supply voltage level, it is necessary to convert the voltage level of the input / output signal in the input / output buffer circuit provided in the semiconductor chip. In this case, both the internal power supply voltage used in the circuit inside the semiconductor chip and the external power supply voltage used outside are supplied to the input / output buffer circuit. Normally, when data is output to the outside, the current consumption of the circuit portion to which the external power supply voltage is supplied is greater than the current consumption of the circuit portion to which the internal power supply voltage is supplied. Conversely, when data is input from the outside, the current consumption of the circuit portion to which the internal power supply voltage is supplied is larger than the current consumption of the circuit portion to which the external power supply voltage is supplied.

  In the conventional input / output buffer circuit configured as described above, the width of the power supply wiring for supplying the external power supply voltage is determined based on the power consumption at the time of data output, and the power supply wiring for supplying the internal power supply voltage is determined. Since the width is determined based on the power consumption at the time of data input, a considerable layout area is required for power supply wiring.

  The present invention has been made in consideration of the above-described problems, and an object of the present invention is to provide a sufficient power supply with a smaller power supply wiring space than the conventional one for an input / output buffer circuit to which a plurality of power supply voltages are supplied. It is to provide a semiconductor device that enables supply.

  A semiconductor device according to an embodiment of the present invention includes an internal circuit, an input / output buffer circuit, first to third power supply wirings, and a plurality of switch units. The input / output buffer circuit converts the voltage level signal of the first power supply voltage input from the outside of the semiconductor device into a signal of the voltage level of the second power supply voltage, outputs the signal to the internal circuit, and received from the internal circuit The signal at the voltage level of the second power supply voltage is converted into a signal at the voltage level of the first power supply voltage and output to the outside of the semiconductor device. The input / output buffer circuit includes a first circuit portion that operates at a first power supply voltage and a second circuit portion that operates at a second power supply voltage. The first power supply wiring is connected to the first circuit portion, and supplies the first power supply voltage to the first circuit portion. The second power supply wiring is connected to the second circuit portion, and supplies a second power supply voltage to the second circuit portion. The plurality of switch portions are respectively provided at a plurality of locations along the third power supply wiring. Each of the plurality of switch units connects one power supply line selected from the first and second power supply lines and the third power supply line in accordance with a control signal output from the internal circuit.

  According to the above embodiment, the third power supply wiring can be used by switching between the first power supply voltage supply and the second power supply voltage supply. Therefore, sufficient power supply can be performed with less power wiring space than in the past.

1 is a block diagram conceptually showing the structure of a semiconductor device 3 according to an embodiment of the present invention. 2 is an enlarged plan view schematically showing a portion between an end portion of a semiconductor substrate SUB and an internal circuit 10 in the semiconductor device 3 of FIG. FIG. 3 is a diagram illustrating an example of a configuration of an input / output buffer circuit BF in FIG. 2. FIG. 2 is a timing chart showing an example of the operation of the semiconductor device 3 of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

[Overall configuration of semiconductor device]
FIG. 1 is a block diagram conceptually showing the structure of a semiconductor device 3 according to an embodiment of the present invention.

  Referring to FIG. 1, a semiconductor device 3 is an LSI (Large Scale Integration) chip housed in a package, and is mounted on a printed circuit board 1. In addition to the semiconductor device 3, an SDRAM (Synchronous Dynamic Random Access Memory) device 2 and the like are mounted on the printed circuit board 1. In the example of this embodiment, the SDRAM device 2 has a high-speed data transfer function called a DDR (Double-Data-Rate) mode, and operates with a power supply voltage VCC1 (here, 1.8 V). It shall be. On the other hand, it is assumed that the internal circuit 10 of the semiconductor device 3 operates at a lower power supply voltage VCC2 (here, 1.2V) in order to reduce power consumption. Note that the SDRAM device 2 is shown as an example of a circuit that performs data transfer with the semiconductor device 3, and the present invention is not limited to data transfer with the SDRAM device.

  The semiconductor device 3 is formed on a semiconductor substrate SUB such as silicon. As shown in FIG. 1, the semiconductor device 3 is provided between a plurality of pads PD (PD1 to PD7) provided in the vicinity of the end portion of the semiconductor substrate SUB, the internal circuit 10, and the pad PD and the internal circuit 10. A plurality of input / output buffer circuits BF and a plurality of switch units SW.

  The plurality of pads PD include a pad PD1 for receiving the ground voltage GND (0V), a pad PD2 for receiving the power supply voltage VCC1 (1.8V), and a pad for receiving the power supply voltage VCC2 (1.2V). Pads PD4 to PD7 for inputting / outputting data signals between PD3 and SDRAM device 2 are included.

  The internal circuit 10 includes a CPU (Central Processing Unit) 11, a DMA (Direct Memory Access) controller 12, an SRAM (Static Random Access Memory) device 13, and a memory control circuit 20. Each of these elements is connected to each other via an internal bus 14. The SRAM device 13 is used as a main storage device of the CPU 11. The DMA controller 12 controls data transfer performed between the SDRAM device 2 and the external SRAM device 13 without using the CPU 11.

  The memory control circuit 20 includes a bus interface circuit 23 connected to the internal bus 14, a data control circuit 21 and an I / O control circuit 22 connected to the bus interface circuit 23. The data control circuit 21 transfers write data WD from the SRAM device 13 to the external SDRAM device 2 and transfers read data RD from the external SDRAM device 2 to the SRAM device 13 in accordance with instructions from the CPU 11 and the DMA controller 12. To control. The I / O control circuit 22 controls the input / output buffer circuit BF and each switch unit SW when transferring data between the SRAM device 13 and the external SDRAM device 2.

  The input / output buffer circuit BF performs impedance conversion, voltage level conversion, digital signal shaping, and the like. In the case of FIG. 1, the input / output buffer circuit BF receives a VCC1 (1.8V) voltage level signal (read data signal RD) input from the external SDRAM device 2 via the corresponding pad PD as a VCC2 ( The signal is converted to a signal having a voltage level of 1.2 V) and output to the data control circuit 21. The input / output buffer circuit BF further converts the VCC2 (1.2V) voltage level signal (write data signal WD) output from the data control circuit 21 into a VCC1 (1.8V) voltage level signal. To the external SDRAM device 2 via the corresponding pad PD.

  In order to perform the above voltage level conversion, both the power supply voltage VCC1 (1.8V) and the power supply voltage VCC2 (1.2V) are supplied to the input / output buffer circuit BF. In FIG. 1, the circuit portion that operates at the power supply voltage VCC1 (1.8V) is a region near the end of the semiconductor substrate SUB (the region between the broken line 24 and the broken line 25), and the power supply voltage VCC2 (1.2V). The circuit portion that operates is the inner region (the inner side of the broken line 24).

  When write data WD and read data RD are transferred between semiconductor device 3 and SDRAM device 2, current consumption in input / output buffer circuit BF increases. Therefore, if the current supply capability of the power supply wiring for supplying the power supply voltages VCC1 and VCC2 to the input / output buffer circuit BF is not sufficient, the delay time of the circuit becomes long due to the drop of the power supply voltage, and the circuit may malfunction. In the semiconductor device 3 shown in FIG. 1, in order to enable sufficient power supply with less power supply wiring space than in the prior art, some power supply wirings are used for supplying the power supply voltage VCC1 and supplying the power supply voltage VCC2 by the switch unit SW. It is switched to use. This will be described in detail below.

[Power supply wiring and switch section for input / output buffer circuit BF]
FIG. 2 is a plan view schematically showing an enlarged portion between the end portion of the semiconductor substrate SUB and the internal circuit 10 in the semiconductor device 3 of FIG. In FIG. 2, the direction along the end EG of the semiconductor substrate is defined as the X-axis direction, and the direction perpendicular to the end EG is defined as the Y-axis direction.

  Referring to FIG. 2, the semiconductor device 3 includes power supply wirings HVL1, HVL2, SVL, LVL1, LVL2, and LVL3 extending in the X-axis direction for the input / output buffer circuit BF, and extending in the X-axis direction. Ground wirings GL1 and GL2 are provided. The wirings HVL1, HVL2, SVL, GL1, LVL1, LVL2, LVL3, and GL2 are arranged in this order from the end side of the semiconductor substrate SUB to the inner side.

  The power supply wirings HVL1 and HVL2 are for supplying the power supply voltage VCC1 (1.8V), and are connected to the wiring 72 extending in the Y-axis direction from the pad PD2 in the region 17 on the semiconductor substrate. The power supply lines HVL1 and HVL2 are connected to a circuit portion HC that operates at the power supply voltage VCC1 in each input / output buffer circuit BF.

  The power supply wirings LVL1, LVL2, and LVL3 are for supplying the power supply voltage VCC2 (1.2V), and are connected to the wiring 73 extending in the Y-axis direction from the pad PD3 in the region 18 on the semiconductor substrate. The power supply lines LVL1 to LVL3 are connected to a circuit portion LC that operates at the power supply voltage VCC2 in each input / output buffer circuit BF.

  The ground wirings GL1 and GL2 are connected to a wiring 71 extending in the Y-axis direction from the pad PD1 in the region 16 on the semiconductor substrate. The ground lines GL1 and GL2 are commonly used in the circuit portions HC and LC in each input / output buffer circuit BF.

  The switch units SW (SW1, SW2) are provided at a plurality of locations along the power supply wiring SVL. Each switch unit SW includes semiconductor switch elements Q1 and Q2. The semiconductor switch element Q1 switches between the power supply wiring SVL and the power supply wirings HVL1 and HVL2 between a conductive state and a nonconductive state in accordance with the control signal CTL1 output from the I / O control circuit 22. The semiconductor switch element Q2 switches between the power supply wiring SVL and the power supply wirings LVL1 to LVL3 between a conductive state and a nonconductive state according to the control signal CTL2 output from the I / O control circuit 22. The I / O control circuit 22 outputs control signals CTL1 and CTL2 in accordance with instructions from the CPU 11 and the DMA controller 12. As a result, one power supply wiring group selected from the power supply wiring groups HVL1, HVL2 for supplying the power supply voltage VCC1 and the power supply wiring groups LVL1 to LVL3 for supplying the power supply voltage VCC2 is connected to the power supply wiring SVL.

  Normally, when the write data signal WD is output from the semiconductor device 3 to the external SDRAM device 2, the consumption current of the circuit portion HC to which the power supply voltage VCC1 (1.8 V) is supplied is higher than the power supply voltage VCC2 (1. 2V) is larger than the current consumption of the circuit part LC to which the voltage is supplied. Conversely, when the read data signal RD is input from the external SDRAM device 2 to the semiconductor device 3, the current consumption of the circuit portion LC to which the power supply voltage VCC2 (1.2 V) is supplied is the power supply voltage VCC1 (1 .8V) is greater than the current consumption of the circuit part HC to which is supplied.

  In the conventional input / output buffer circuit BF, the width and the number of power supply lines for supplying the power supply voltage VCC1 to the input / output buffer circuit BF are determined based on the current consumption during data output, and the power supply voltage VCC1 is determined as the input / output buffer circuit. Since the width and number of power supply wirings to be supplied to the BF are determined based on current consumption at the time of data input, a considerable layout area is required for the power supply wiring.

  In the semiconductor device 3 according to this embodiment, the power supply wiring SVL is used for supplying the power supply voltage VCC1 when the write data signal WD is output to the SDRAM device 2 by switching the plurality of switch sections SW. When receiving read data signal RD from device 2, power supply wiring SVL is used for supplying power supply voltage VCC2. As a result, the current supply capability of the power supply wiring can be increased, so that sufficient power supply can be performed to the input / output buffer circuit BF with less power supply wiring space than in the past.

[Example of configuration of input / output buffer circuit BF]
FIG. 3 is a diagram showing an example of the configuration of the input / output buffer circuit BF of FIG. Referring to FIG. 3, input / output buffer circuit BF includes level shifters 41 to 44, ESD (Electro-Static Discharge) protection circuit 30, input buffer 34, output buffer 60, three-state buffer 50, and pre-buffer. 56, 57. Among the above components, each part of the level shifters 41 to 44 is a circuit part LC that operates at the power supply voltage VCC2 (1.2V), and the other part is a circuit part HC that operates at the power supply voltage VCC1 (1.8V). It is.

  The level shifters 41, 43, and 44 convert the voltage level signal of the power supply voltage VCC2 (1.2V) output from the memory control circuit 20 of FIG. 1 into a signal of the voltage level of the power supply voltage VCC1 (1.8V). Output. The level shifter 42 converts the voltage level signal of the power supply voltage VCC1 (1.8V) received from the input buffer 34 into a voltage level signal of the power supply voltage VCC2 (1.2V) and outputs the signal.

  The ESD protection circuit 30 is a circuit for protecting the semiconductor device 3 from static electricity input via the pad PD, and includes a resistance element 33 and diodes 31 and 32. Resistance element 33 is connected between pad PD and internal node ND, and attenuates an ESD surge. Diode 31 is connected in the reverse bias direction between the power supply node (receiving power supply voltage VCC1) and pad PD, and diode 32 is connected in the reverse bias direction between the ground node (receiving ground voltage GND). These diodes 31 and 32 are provided for flowing a high-voltage ESD surge through the power supply wiring and the ground wiring.

  The input buffer 34 becomes active when the read permission signal RE received from the I / O control circuit 22 of FIG. 1 via the level shifter 41 is at a low level (L level). In the active state, input buffer 34 outputs read data signal RD received from external SDRAM device 2 to level shifter 42 via pad PD and node ND. The input buffer 34 becomes inactive when the read permission signal RE is at a high level, and its output becomes high impedance.

  The output buffer 60 includes a PMOS (Positive-channel Metal Oxide Semiconductor) transistor 61 connected between a power supply node (receives the power supply voltage VCC1) and the node ND, a ground node (receives the ground voltage GND), and a node ND. And an NMOS (Negative-channel Metal Oxide Semiconductor) transistor 62 connected between the two transistors. The PMOS transistor 61 and the NMOS transistor 62 are switched to an on state or an off state in accordance with a signal input to the gate.

  Three-state buffer 50 includes a NAND gate 51, a NOR gate 52, and inverters 53-55. A write data signal WD output from the data control circuit 21 is input to each first input node of the NAND gate 51 and the NOR gate 52 via the level shifter 43. A write enable signal WE output from the I / O control circuit 22 is input to the second input node of the NAND gate 51 via the level shifter 44 and the inverter 53. The write enable signal WE output from the I / O control circuit 22 is input to the second input node of the NOR gate 52 via the level shifter 44. The output signal of the NAND gate 51 is input to the gate of the PMOS transistor 61 constituting the output buffer 60 via the inverter 54 and the prebuffer 56. The output signal of the NOR gate 52 is input to the gate of the NMOS transistor 62 constituting the output buffer 60 via the inverter 55 and the prebuffer 57.

  According to the three-state buffer 50 having the above configuration, when the write enable signal WE is at a high level (H level), the signal input to the gate of the PMOS transistor 61 constituting the output buffer 60 is at the H level, and the NMOS transistor Since the signal inputted to the gate 62 becomes L level, the output of the output buffer 60 becomes high impedance. When write enable signal WE is at L level, output buffer 60 is in an active state and outputs a logic level signal corresponding to write data signal WD.

[Example of operation of semiconductor device]
FIG. 4 is a timing chart showing an example of the operation of the semiconductor device 3 of FIG.

  1, 2, and 4, operation from time t <b> 1 to time t <b> 3 in FIG. 4 shows an operation when a write command is output from CPU 11 or DMA controller 12 in FIG. 1. Up to t6 shows the operation when a read command is output from the CPU 11 or the DMA controller 12.

  At time t2 in FIG. 4, in response to the write command, the I / O control circuit 22 sets the control signal CTL1 to H level and the control signal CTL2 to L level. In response to these control signals CTL1 and CTL2, the semiconductor switch element Q1 of each switch unit SW is turned on and the semiconductor switch element Q2 is turned off. Accordingly, the power supply wiring SVL in FIG. 2 is used to supply the power supply voltage VCC1 (1.8V) to the input / output buffer circuit BF. Further, the I / O control circuit 22 sets the write enable signal WE to the L level, whereby the output buffer 60 becomes active, and the write data signal WD is output from the output buffer 60.

  At time t3, the I / O control circuit 22 returns the write enable signal WE to the H level, so that the output buffer 60 becomes inactive, so that the output of the output buffer 60 becomes high impedance (High-Z). Return.

  At time t5, in response to the read command, I / O control circuit 22 sets control signal CTL1 to L level and sets control signal CTL2 to H level. In response to these control signals CTL1 and CTL2, the semiconductor switch element Q1 of each switch unit SW is turned off and the semiconductor switch element Q2 is turned on. Thus, the power supply wiring SVL in FIG. 2 is used to supply the power supply voltage VCC2 (1.2 V) to the input / output buffer circuit BF. Further, in the I / O control circuit 22, the input buffer 34 is activated by setting the read permission signal RE to the L level, and the read data signal RD is output from the input buffer 34.

  At time t6, the I / O control circuit 22 returns the read permission signal RE to the H level, so that the input buffer 34 becomes inactive, so that the output of the input buffer 34 returns to high impedance (High-Z). .

[Modification]
In the above embodiment, the input / output buffer circuit BF shown in FIG. 2 has been described as having no circuit portion directly connected to the power supply wiring SVL. When there are circuit portions SC that are directly connected to the power supply wiring SVL, it is necessary to provide a switch between the circuit portions SC and the power supply wiring SVL. For example, if the circuit portion SC operates with the power supply voltage VCC1 (1.8V), when the power supply wiring SVL is used for supplying the power supply voltage VCC2 (1.2V), the circuit portion SC and the power supply wiring SVL are used. And the connection is switched so that the power supply voltage VCC1 is directly supplied from the power supply wirings HVL1 and HVL2 to the circuit portion SC. On the contrary, if these circuit portions SC operate at the power supply voltage VCC2 (1.2V), the circuit portion SC and the power supply wiring are used when the power supply wiring SVL is used for supplying the power supply voltage VCC1 (1.8V). The connection with the SVL is disconnected, and the connection is switched so that the power supply voltage VCC2 is directly supplied from the power supply wirings LVL1 to LVL3 to the circuit portion SC.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 printed circuit board, 2 SDRAM device, 3 semiconductor device, 10 internal circuit, 11 CPU, 12 DMA controller, 13 SRAM device, 14 internal bus, 20 memory control circuit, 21 data control circuit, 22 I / O control circuit, 23 bus Interface circuit, BF input / output buffer circuit, end of EG semiconductor substrate, GL1, GL2 ground wiring, HC, LC circuit part, HVL1, HVL2 power supply wiring, SVL power supply wiring, LVL1 to LVL3 power supply wiring, PD (PD1 to PD7) Pad, Q1, Q2 semiconductor switch element, SUB semiconductor substrate, SW switch part.

Claims (4)

A semiconductor device,
Internal circuitry,
The voltage level signal of the first power supply voltage input from the outside of the semiconductor device is converted into a signal of the voltage level of the second power supply voltage, output to the internal circuit, and the second signal received from the internal circuit. An input / output buffer circuit that converts a signal at a voltage level of the power supply voltage into a signal at a voltage level of the first power supply voltage and outputs the signal to the outside of the semiconductor device,
The input / output buffer circuit includes:
A first circuit portion operating at the first power supply voltage;
A second circuit portion operating at the second power supply voltage,
The semiconductor device further includes:
A first power supply line connected to the first circuit portion for supplying the first power supply voltage to the first circuit portion;
A second power supply wiring connected to the second circuit portion for supplying the second power supply voltage to the second circuit portion;
A third power supply wiring;
A plurality of switch portions respectively provided at a plurality of locations along the third power supply wiring,
Each of the plurality of switch units connects one power supply line selected from the first and second power supply lines and the third power supply line in accordance with a control signal output from the internal circuit. A semiconductor device. The semiconductor device is formed on a substrate,
Each of the first to third power supply wires extends in a direction along an end portion of the substrate, and the first, third, and second power supply wires are arranged in the order of the first, third, and second power supply wires from the end portion side of the substrate. Placed towards the inside,
The semiconductor device according to claim 1, wherein the internal circuit is provided on an inner side of the substrate than the second power supply wiring. The internal circuit outputs the control signal to each of the plurality of switch units so as to connect the first power supply wiring and the third power supply wiring, and then passes through the input / output buffer circuit. Outputting a signal to the outside of the semiconductor device;
The internal circuit outputs the control signal to each of the plurality of switch units so as to connect the second power supply wiring and the third power supply wiring, and then passes through the input / output buffer circuit. The semiconductor device according to claim 1, wherein a signal is received from outside the semiconductor device. The internal circuit operates with the second power supply voltage;
4. The input / output buffer circuit according to claim 1, wherein the input / output buffer circuit inputs / outputs a signal to / from a circuit that operates at the first power supply voltage provided outside the semiconductor device. 5. Semiconductor device.

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