KR20090130931A - Mode selecting circuit for use in semiconductor memory device - Google Patents

Abstract

PURPOSE: An operation mode selecting circuit in a semiconductor memory device is provided to cut out a current path generated after pad bonding, thereby preventing the current consumption through the current path. CONSTITUTION: An operation mode selecting circuit comprises a floating or bonded bonding pad(100), a buffer(80) connected to the bonding pad, a switching unit(50), and a current path cutout unit(P1,Cap1). The buffer outputs a first operating mode signal. The operation mode selecting circuit comprises the switching unit connected to the input terminal of the buffer. The switching unit is turned on according to the active state of a first operating mode. The current path cutout unit is connected to the switching unit. The current path cutout unit is a power supply voltage and a DC(Direct Current) path to ground connection in the turn-off state of the switching unit. The bonding pad is the pad deciding an x4 or x8 action mode.

Description

Mode selection circuit for use in semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a circuit capable of selecting an operation mode by a bonding option.

In general, semiconductor memory devices, such as dynamic random access memory, tend to be increasingly high-speed and high-density day by day according to the needs of users. Dynamic random access memory devices having one access transistor and one storage capacitor as unit memory cells are commonly employed as main memory devices of electronic systems.

In the case of such a dynamic random access memory device (hereinafter, referred to as DRAM), the X4, X8, X16, and X32 modes depend on how many bits are output from the device in the same cycle in consideration of the use purpose of the memory. It is divided into such forms. In particular, DDR (Double Data Rate) SDRAM of X16 mode is used for high speed memory, and X8 mode is often used as main memory by being assembled into memory modules.

As described above, the classification of the mode types is performed by actually changing the use of the column address in relation to the use of the address. In terms of structure, the X16, X8, and X4 modes are determined using a bonding pad. I'm using the way.

The bonding option pad is for use in selecting a function of the semiconductor device in the bonding step. The reason for such a bonding option pad is that the function of the semiconductor device must be modified according to the function of the mechanism on which the semiconductor device is mounted or its needs. For example, the semiconductor device can be used as a dynamic RAM in a single bit (x bit) configuration by connecting a bonding option pad to one of a power supply side lead (high potential side lead) and a ground lead (low potential side lead). On the other hand, the semiconductor device can be used as a dynamic RAM in an N bit (x 4 bit) configuration by connecting a bonding option pad to another conductor.

As such, a semiconductor device having various functions can be provided by selective connection between the bonding option pad and the high potential or low potential side lead.

Semiconductor devices of this type include high potential and low potential side conductors extending in a predetermined direction with bonding option pads located between the high potential and adjacent low potential side conductors. The bonding option pad is connected to either the high potential side lead or the low potential side lead. In such a semiconductor device, the potential on the bonding option pad is the same as that applied to the high potential or low potential side lead. This configuration avoids level fluctuations at the input of the selective signal generation circuit connected to the bonding option pads.

Referring to Fig. 1, an operation mode selection circuit in a conventional semiconductor memory device is shown.

In FIG. 1, the operation mode selection circuit may be connected to the X4 bonding pads 100 and the X8 bonding pads 110, respectively, to protect the internal circuits from external electrical influences including static electricity. 101,111, the first buffer 120 is connected to the output node of the first antistatic unit 101 and outputs the X4 operation mode signal, the X8 operation mode signal is connected to the output node of the second antistatic unit 111 It has a second buffer 130 for outputting.

The operation mode selection circuit having the configuration as described above is connected to the X4 bonding pad 100 and the X8 bonding pad 110 at the time of package manufacture, that is, to the connection between the internal voltage VDD or the ground VSS. Depending on the state, a particular mode of operation is determined. In addition, since one memory supports two or more operation modes, it is necessary to verify whether the operation of the memory determined as the X16 mode has a specific effect on the X4 and X8 operation modes.

In addition, when the bonding pad is connected to ground, a current path is generated from the power supply voltage terminal of the buffer to the ground, so that a leakage current always exists.

Thus, there is a need for an improved technique that can adequately block current paths for bonding pad options.

Accordingly, it is an object of the present invention to provide an operation mode selection circuit in a semiconductor memory device which can solve the above-mentioned conventional problems.

Another object of the present invention is to provide an operation mode selection circuit in a semiconductor memory device which can prevent generation of a current path in a selection signal output line in a bonding option.

It is still another object of the present invention to provide an operation mode selection circuit in a semiconductor memory device capable of reducing current consumption by cutting off a current path that can be generated to ground at a power supply voltage terminal during ground bonding of an option pad.

According to an aspect of the present invention for achieving the above object of the present invention, the operation mode selection circuit in the semiconductor memory device is:

Bonding pads to be floated or bonded;

A buffer connected to the bonding pad to output a first operation mode signal;

A switching unit connected to an input of the buffer and turned on according to whether the first operation mode is activated;

And a current path blocking unit connected to the switching unit to block a DC path to a power supply voltage and a ground when the switching unit is turned off.

In an embodiment of the present invention, the bonding pad is a pad for determining an x4 or x8 operation mode. Preferably, the first operation mode signal is a signal for performing an x4 operation mode.

According to an embodiment of the present invention, the buffer may be a CMOS inverter, and the switching unit may be a type MOS transistor having a gate connected to ground and a drain connected to an input terminal of the buffer.

Preferably, the current path blocking unit,

A capacitor having one node connected to ground and a gate connected to the other node of the capacitor, a source connected to a power supply voltage supply terminal, and a drain connected to a source of the source MOS transistor may be configured.

A semiconductor memory device applied to an embodiment of the present invention may have a DDR2 type and a DDR3 type memory array structure, and the data processing system equipped with such a semiconductor memory device is a portable electronic device such as a personal computer, a notebook computer, an HHP or a PMP. Device and the like.

According to the exemplary embodiment of the present invention as described above, the current path generated after the pad bonding is blocked, thereby preventing or minimizing the current consumption through the current path.

Hereinafter, according to the present invention, a preferred embodiment of an operation mode selection circuit in a semiconductor memory device capable of blocking a current path generated after pad bonding will be described with reference to the accompanying drawings.

Although many specific details are set forth in the following examples by way of example and in the accompanying drawings, it is noted that this has been described without the intent to assist those of ordinary skill in the art to provide a more thorough understanding of the present invention. shall. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. Functional circuits associated with known DRAM structures, data read and write operations, and pad optional operations have not been described in detail in order not to obscure the subject matter of the present invention.

To better understand the functions and operations of the embodiments of the present invention described below, the generation of the bonding option pads and the current paths generated after the bonding options will first be described with reference to FIGS.

FIG. 2 is a diagram provided to explain bonding options of bonding option pads disposed in the apparatus of FIG. 1.

Referring to FIG. 2, an example of a conventional semiconductor device is illustrated to easily understand the present invention described below. Two or more bonding option pads are aligned in a predetermined direction on the semiconductor chip 10. One of the bonding option pads is labeled BO, which is connected to a high potential side lead (VDD) or a low potential side lead (VSS). One of the remaining bonding option pads is labeled PO and it is connected to the signal lead SL. The high potential and low potential side conductors VDD and VSS are arranged in parallel with each other so as to form like a bus on the semiconductor chip 10, respectively. In other words, the high potential and low potential side leads VDD and VSS extend in the same direction as the alignment of the bonding option pads, respectively. The semiconductor chip 10 is only partially shown in FIG. 2, and the illustrated signal conductor is only a part of the plurality of signal conductors.

When the bonding option pads are arranged parallel to each of the high potential and low potential side conductors, a short bonding wire 11 is required for the connection between the bonding option pad BO and the high potential side conductors, and the bonding wire 12 Is required for the connection between another bonding option pad and the low potential side lead. The bonding wires need to consider the insulation of the bonding wires to avoid electrical contact between the leads. For this reason, the bonding wire 12 should be separated from the low potential side lead Vss by a sufficient distance.

As shown in FIG. 2, one of the first bonding option OP1 and the second bonding option OP2 is selected when the bonding pad BO is selectively connected to the high potential side lead or the low power side lead, for example. The data output operation mode can be set as X4 or X8.

3 and 4 illustrate a pad arrangement form of typical stack packages. 3 illustrates a stack package in the form of a face to face (FF) type in a LOC type stack package in which a pad array is located at the center of a semiconductor integrated circuit. Here, reference numeral 20 in the drawings denotes a pad, and 22 denotes a semiconductor integrated circuit chip. In this case, it can be seen that the pad array is formed to face each other.

4 illustrates a mirror type stack package in a stack package of a semiconductor integrated circuit. Here, reference numeral 26 denotes a pad, 27 an additional circuit, 28 a semiconductor integrated circuit chip, and 32 a lead. Here, the pad arrays are arranged in the form of mirrors looking at each other.

Hereinafter, a circuit for generating an operation mode selection signal through a pad selectively bonded as described above and disposed on the semiconductor chip will be described.

5 and 6 are operating mode selection circuit diagrams with current path generation in conventional technology.

5 and 6 are option circuits in a stack package integrated circuit of a semiconductor integrated circuit using a bonding option, which option circuit selectively operates one of the output modes. The option circuit is installed in the reference chip and the mirror chip, respectively. In the drawing, reference numeral 50 denotes a PMOS transistor, 80 denotes an inverter, and 100 and 110 denote optional pads.

In an unbonded reference chip, an element that does not affect the standby current, for example, a small pull-up transistor is used to prevent a floating state. The drain of the pull-up transistor is connected to a power pad VDD, such as a first power pad VDD, and its gate is connected to a ground power supply VDD, such as a first ground power pad VSS, and the source thereof is an option. It is connected to the input terminal of the pad 100 and the inverter 80.

Therefore, when the bonding pad 100 is in a floating state without bonding, the pull-up transistor 50 is turned off.

In FIG. 6, when the bonding pad 110 is bonded to the ground pad VSS, the ground voltage of the "low level" is applied from the drain of the pull-up transistor 50. Accordingly, the pull-up transistor 50 is turned on so that the "high level" power supply voltage VDD is applied to the ground power supply through the source and drain of the pull-up transistor 50 and the option pad 110, thereby reducing the voltage of the transistor 50. The drain maintains the state of the ground power supply VDD which is "low level".

Thereafter, the voltage VSS of the "low level" is applied to the input terminal of the inverter 80 so that the "high level" option output signal X4OUT is output from the output terminal of the inverter 80.

As described above, when the bonding pad 110 is bonded to the ground voltage, a current path is formed from the source to the drain of the p-type MOS transistor 50 as the switching element. When a small DC current flows through the current path, current consumption is unnecessary. Conventional technology has reduced the current consumption by adjusting the size of the morph transistors so that the current flows on the order of several microamps.

Therefore, there is a need for an improved technique that can fundamentally solve the problem of current path generation in the bonding option.

Hereinafter, a description of solving the problem in which the leakage current is generated as in FIG. 6 will be described with reference to FIGS. 7 and 8.

7 and 8 are operation mode selection circuit diagrams having a current path blocking function according to an embodiment of the present invention.

First, it should be understood that FIG. 7 contrasts with FIG. 5 and FIG. 8 contrasts with FIG. 6.

In the embodiment of the present invention, since neither current path is formed in FIG. 7 or 8, unnecessary current consumption is reduced or prevented.

Reference is now made to FIG. 7. First, the operation mode selection circuit in the semiconductor memory device may include a bonding pad 100 that is floating or bonded, and a buffer 80 connected to the bonding pad 100 to output a first operation mode signal X4OUT. Basically provided. In addition, the operation mode selection circuit includes a switching unit 50 connected to an input terminal of the buffer 80 and turned on according to whether the first operation mode is activated, and connected to the switching unit 50 to perform the switching. Current path blocking units P1 and CAP1 are provided to block DC paths to the power supply voltage and ground when the unit 50 is turned off.

In FIG. 7, the bonding pad is a pad 100 for determining an x4 or x8 operation mode, and the first operation mode signal may be a signal for performing an x4 operation mode.

The buffer 80 may be configured as a CMOS inverter, and the switching unit 50 may be implemented as a type MOS transistor 50 having a gate connected to ground and a drain connected to an input terminal of the buffer. In addition, the current path blocking unit, a capacitor (CAP1) of which one node is connected to ground, a gate is connected to the other node of the capacitor, the source is connected to the power supply voltage supply terminal, the drain is connected to the source of the source Morse transistor It may be configured to include a MOS transistor (90).

Referring to FIG. 8, except for the bonding pad 110 connected to the ground voltage VSS by bonding, the structure of FIG. 7 is the same as in FIG. 7. This is because the level of the generated signal must be the same depending on whether or not to perform bonding.

In the case of the x8 operation in which the bonding pad 100 is floated as shown in FIG. 7, the capacitor 70 maintains the gate terminal of the Morph Transistor 90 at a low level. 90) is turned on. Accordingly, the output of the buffer 80 is at a low level, and the first operation mode signal X4OUT is output at the low level.

On the other hand, in the case of the x4 operation in which the bonding pad 110 is connected to the ground voltage as shown in FIG. 8, the capacitor 70 maintains the gate terminal of the MOS transistor 90 as the high level HIGH. Morse transistor 90 is turned off. As a result, the switching transistor 50 is turned off, the output of the buffer 80 becomes a howe level, and the first operation mode signal X4OUT is output as a high level.

Here, by the blocking role of the current path blocking unit 90, it can be seen that the current path generated as shown in Figure 6 is essentially blocked, there is no current consumption.

8 is a circuit of a conventional memory device including a refresh controller, an address buffer, a bank selector, memory banks, row decoders, and column decoders.

As described above, according to the exemplary embodiment of the present invention, the current path generated after the pad bonding is blocked to prevent or minimize current consumption through the current path.

In the above description, the embodiments of the present invention have been described with reference to the drawings, for example. However, it will be apparent to those skilled in the art that the present invention may be variously modified or changed within the scope of the technical idea of the present invention. . For example, in other cases, a component of the current path blocking unit may be implemented as another switching element in addition to the MOS transistor without departing from the technical spirit of the present invention.

In addition, the semiconductor memory device applied to the embodiment of the present invention may have a DDR2 type, DDR3 type memory array structure, the data processing system equipped with the semiconductor memory device, such as a personal computer, notebook computer, HHP or PMP It can be a portable electronic device, etc.

1 illustrates an operation mode selection circuit in a conventional semiconductor memory device.

FIG. 2 is a diagram provided to explain bonding options of bonding option pads disposed in the apparatus of FIG.

3 and 4 illustrate a pad arrangement form of a typical stack package.

5 and 6 are operating mode selection circuit diagrams with current path generation in conventional technology.

7 and 8 are operation mode selection circuit diagrams having a current path blocking function according to an embodiment of the present invention

Claims (6)

In the operation mode selection circuit in the semiconductor memory device: Bonding pads to be floated or bonded; A buffer connected to the bonding pad to output a first operation mode signal; A switching unit connected to an input of the buffer and turned on according to whether the first operation mode is activated; And a current path blocking unit connected to the switching unit to block a DC path to a power supply voltage and a ground when the switching unit is turned off. The operation mode selection circuit of claim 1, wherein the bonding pad is a pad for determining an x4 or x8 operation mode. The operation mode selection circuit of claim 1, wherein the first operation mode signal is a signal for performing an x4 operation mode. The operation mode selection circuit of claim 1, wherein the buffer is a CMOS inverter. The operation mode selection circuit of claim 1, wherein the switching unit is a type MOS transistor having a gate connected to ground and a drain connected to an input terminal of the buffer. The method of claim 5, wherein the current path blocking unit, A semiconductor memory comprising a capacitor having one node connected to ground, a gate connected to the other node of the capacitor, a source connected to a power supply voltage supply, and a drain connected to a source of the source Morse transistor; Operation mode selection circuit in the device.

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