CN113782070B

CN113782070B - Self-powered nonvolatile programmable chip and memory device

Info

Publication number: CN113782070B
Application number: CN202111028366.6A
Authority: CN
Inventors: 左丰国; 周骏; 郭一欣; 吴勇
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2021-09-02
Filing date: 2021-09-02
Publication date: 2024-05-28
Anticipated expiration: 2041-09-02
Also published as: CN113782070A

Abstract

The application provides a self-powered nonvolatile programmable chip and a storage device. The self-powered nonvolatile programmable chip comprises: the dynamic random storage component is integrated with a dynamic random storage array; the nonvolatile storage component is integrated with a nonvolatile storage array, the nonvolatile storage array is connected with the dynamic random storage array, the capacitance component is integrated with an integrated circuit capacitance array, and the integrated circuit capacitance array is connected with the dynamic random storage array and the nonvolatile storage array; the dynamic random access memory assembly, the nonvolatile memory assembly and the capacitor assembly are arranged in a stacked mode; and responding to a first preset condition, and supplying power to the dynamic random access memory array and the nonvolatile memory array by the integrated circuit capacitor array so that data in the dynamic random access memory array is stored in the nonvolatile memory array and used as backup data of the dynamic random access memory array. Therefore, the data in the dynamic random access memory component can be protected, and the integration density is higher; and simultaneously, self-power supply can be realized.

Description

Self-powered nonvolatile programmable chip and memory device

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a self-powered nonvolatile programmable chip and a memory device.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) uses the magnitude of the stored charge in the capacitor to represent whether a binary bit (bit) is a1 or a 0, and is widely used because of its extremely high storage density. However, in the using process of the DRAM, refresh stop occurs when the system is powered off, so that data are damaged, and the application of the DRAM in high-reliability occasions is greatly limited; such as a memory module on a device such as a server.

The method aims to solve the problem of data damage in the DRAM caused by the power failure problem; currently, a nonvolatile memory chip and a data protection/recovery device are further disposed on a board card of a nonvolatile Dual In-line Memory Module (NVDIMM) memory module to store data In a backup DRAM through the nonvolatile memory chip, and store data In the DRAM to the nonvolatile memory chip or recover data In the nonvolatile memory chip to the DRAM through the data protection/recovery device.

However, the NVDIMM module needs to be matched with a super capacitor module, and after the system is powered down, the power supply of the NVDIMM is maintained through the super capacitor module until the NVDIMM finishes the protection of data in the nonvolatile memory. Each NVDIMM module needs to be matched with a super capacitor module, and the cost is obviously increased.

Disclosure of Invention

The application provides a self-powered nonvolatile programmable chip and a storage device, which can solve the problem of data damage in a dynamic random access memory component caused by the power failure problem and have higher integration density; and simultaneously, self-power supply can be realized.

In order to solve the technical problems, the application adopts a technical scheme that: a self-powered non-volatile programmable chip is provided. The self-powered nonvolatile programmable chip comprises: a dynamic random access memory component, a nonvolatile memory component and a capacitor component; the dynamic random storage component is integrated with a dynamic random storage array; the nonvolatile storage component is integrated with a nonvolatile storage array, the nonvolatile storage array is connected with the dynamic random storage array, the capacitance component is integrated with an integrated circuit capacitance array, and the integrated circuit capacitance array is connected with the dynamic random storage array and the nonvolatile storage array; the dynamic random access memory assembly, the nonvolatile memory assembly and the capacitor assembly are arranged in a stacked mode; and responding to a first preset condition, and supplying power to the dynamic random access memory array and the nonvolatile memory array by the integrated circuit capacitor array so that data in the dynamic random access memory array is stored in the nonvolatile memory array and used as backup data of the dynamic random access memory array.

In order to solve the technical problems, the application adopts another technical scheme that: a storage device is provided. The storage device includes: a memory interface and a plurality of self-powered non-volatile programmable chips; each self-powered nonvolatile programmable chip is connected with the storage interface through the external interface; the self-powered nonvolatile programmable chip is the self-powered nonvolatile programmable chip.

The self-powered nonvolatile programmable chip and the storage device provided by the application are characterized in that a dynamic random storage component is arranged on the self-powered nonvolatile programmable chip and is integrated with a dynamic random storage array; meanwhile, by arranging the nonvolatile storage component, the nonvolatile storage component is integrated with a nonvolatile storage array, and the nonvolatile storage array is connected with the dynamic random storage array; in addition, by arranging the capacitor assembly, the capacitor assembly is integrated with the integrated circuit capacitor array, the integrated circuit capacitor array is connected with the dynamic random access memory array and the nonvolatile memory array, and in response to a first preset condition, the integrated circuit capacitor array supplies power for the dynamic random access memory array and the nonvolatile memory array, so that data in the dynamic random access memory array is stored into the nonvolatile memory array and used as backup data of the dynamic random access memory array, and therefore, when a system is accidentally powered off or breaks down, the data in the dynamic random access memory array can be protected through the nonvolatile memory array, and the problem of data damage in the dynamic random access memory array caused by power failure is avoided; in addition, the dynamic random memory component, the nonvolatile memory component and the capacitor component are arranged in a stacked mode, so that the integration density of the self-powered nonvolatile programmable chip is effectively improved; and enables the chip to be self-powered within the chip.

Drawings

FIG. 1 is a schematic diagram of a prior art memory device;

FIG. 2 is a schematic diagram of a self-powered nonvolatile programmable chip according to a first embodiment of the present application;

FIG. 3 is a schematic diagram of a self-powered nonvolatile programmable chip according to a second embodiment of the present application;

FIG. 4 is a schematic plan view of a self-powered non-volatile programmable chip according to the embodiment of the present application shown in FIG. 3;

FIG. 5 is a schematic diagram of a self-powered nonvolatile programmable chip according to a third embodiment of the present application;

FIG. 6 is a schematic diagram of a self-powered nonvolatile programmable chip according to a fourth embodiment of the present application;

FIG. 7 is a schematic plan view of a self-powered non-volatile programmable chip according to another embodiment of the present application shown in FIG. 3;

FIG. 8 is a schematic diagram illustrating a flow of data protection/recovery in a self-powered non-volatile programmable chip according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a memory device according to an embodiment of the application;

fig. 10 is a schematic structural diagram of a memory device according to an embodiment of the application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," "third," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a storage device in the prior art; currently, a memory device 100a, such as an NVDIMM, includes a circuit board and a DRAM pellet 21, a nonvolatile memory 22, and a data protection controller 23 connected to the circuit board to protect or restore data in the DRAM pellet 21 through the nonvolatile memory 22 and the data protection controller 23. The DRAM particles 21, the nonvolatile memory 22 and the data protection controller 23 are all independent devices and are distributed on the circuit board in a tiled manner, so that the integration level is low. In addition, the signals of the DRAM granule 21 are multiplexed in a time-sharing manner by a multiplexer 24 (MUX) in particular, so that when the data in the DRAM granule 21 needs to be protected or recovered, the signals of the DRAM granule 21 are switched to a data protection controller 23, and when the DRAM granule 21 works normally, the signals of the DRAM granule 21 are switched to a memory module (DIMM) interface 25; however, this is not limited to the use of standard DRRAM granules, but the data protection controller 23 accesses data in the DRRAM granules using standard DRAM interface (JEDEC) protocol (via MUX), is bandwidth limited via DRAM I/O, and consumes significant power. In addition, the interconnection of the data protection controller 23 with the nonvolatile memory 22 is achieved through the I/O on-board, bandwidth is limited, and additional power consumption overhead is generated. In addition, the NVDIMM needs to be collocated with the super capacitor module 26, and after the system is powered down, the power supply of the NVDIMM is maintained through the super capacitor module 26 until the NVDIMM completes the protection of the data in the nonvolatile memory 22. However, each NVDIMM requires a collocation of the super capacitor module, resulting in a significant increase in cost.

The application provides a self-powered nonvolatile programmable chip and a storage device, wherein the self-powered nonvolatile programmable chip combines three-dimensional heterogeneous integration, DRAM particles 21, nonvolatile memory 22 and data protection controller 23 in an NVDIMM are integrated in one chip, and the power consumption of data backup storage access is obviously reduced; the bandwidth of data backup storage access is greatly increased, and the data backup time is reduced, so that the capacity requirement of the self-powered nonvolatile programmable chip on a backup power supply is reduced, and the self-powered nonvolatile programmable chip can be powered by using a capacitor array built in the chip to realize self-power supply of the chip; compared with the prior art, the super capacitor is saved, and the cost is reduced.

The present application will be described in detail with reference to the accompanying drawings and examples.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a self-powered nonvolatile programmable chip according to a first embodiment of the present application; in this embodiment, a self-powered non-volatile programmable chip 10 is provided. The self-powered non-volatile programmable chip 10 is an integrated, single-particle packaged self-powered non-volatile programmable chip 10. Specifically, the self-powered nonvolatile programmable chip 10 includes a dynamic random access memory (DRAM die) component 11, a nonvolatile memory component 12 (Flash die), and a capacitor component 13 (Cap die). The dynamic random access memory assembly 11, the nonvolatile memory assembly 12 and the capacitor assembly 12 are stacked, so as to effectively improve the integration density of the self-powered nonvolatile programmable chip 10; and enables the self-powered non-volatile programmable chip 10 to be self-powered within the chip.

Wherein the dynamic random access memory component 11 is integrated with a dynamic random access memory array 111; the nonvolatile memory component 12 is integrated with a nonvolatile memory array 121, and the nonvolatile memory array 121 is connected with the dynamic random access memory array 111; the capacitor assembly 13 is integrated with an integrated circuit capacitor array 131; the integrated circuit capacitor array 131 is connected to the dynamic random access memory array 111 and the nonvolatile memory array 121. In response to the first preset condition, the integrated circuit capacitor array 131 supplies power to the dynamic random access memory array 111 and the nonvolatile memory array 121, so that data in the dynamic random access memory array 111 is stored in the nonvolatile memory array 121 and is used as backup data of the dynamic random access memory array 111. Therefore, under the first preset condition, the data in the dynamic random access memory array 111 can be protected through the nonvolatile memory array 121, and the problem of data damage in the dynamic random access memory array 111 caused under the first preset condition is avoided. The first preset condition may be a system failure, such as a system power failure or a system crash, where the dynamic random access memory 11 cannot be powered.

Specifically, the nonvolatile memory component 12 is stacked and bonded with the dynamic random access memory component 11 in a three-dimensional heterogeneous integrated bonding manner, so as to improve the integration density of the self-powered nonvolatile programmable chip 10. It can be understood that, the nonvolatile memory array 121 is used for storing backup data corresponding to data in the dynamic random access memory array 111, so that when power is unexpectedly turned off or a system crashes, the data in the dynamic random access memory array 111 can be protected by the nonvolatile memory array 121, and the problem of data damage in the dynamic random access memory array 111 caused by power failure is avoided; of course, in particular embodiments, flash controllers or the like may also be provided on the nonvolatile storage component 12.

Wherein, the data protection and recovery of the dynamic random access memory array 111 is highly regular due to the read, write and erase operations of the nonvolatile memory array 121; therefore, the Flash controller can only comprise the functions of simple verification, counting and/or address mapping, prefetching and the like, and the functions of dirty block recovery, wear balance and the like can be omitted, so that the structure is simpler compared with the Flash controller such as an electronic hard disk and the like.

In a specific embodiment, the nonvolatile memory array 121 and nonvolatile memory component 12 are typically optimized at NAND FLASH; of course, in other embodiments, the nonvolatile memory array 121 may be implemented as Flash, resistive RAM (RRAM or ReRAM), magnetoresistive RAM (MRAM), ferroelectric memory (FeRAM), oxide resistive memory (OxRAM), bridge RAM (CBRAM), phase Change Memory (PCM), spin transfer torque RAM (STT-MRAM), EEPROM, or the like.

In particular embodiments, the number of three-dimensional heterogeneous integration layers, i.e., the stacked bonding of multiple layers of dynamic random access memory elements 11 and/or nonvolatile memory elements 12, may be increased to increase the memory capacity of the self-powered nonvolatile programmable chip 10 for applications that pursue the density of dynamic random access memory elements 11 and/or nonvolatile memory elements 12.

Wherein the capacitor assembly 13 may comprise two, three, four or more layers to form a high capacity capacitor network; and each layer of capacitor assembly 13 can be combined in series/parallel by semiconductor process capacitors in the assembly to integrate a plurality of integrated circuit capacitor arrays 131; the types of the integrated circuit capacitor array 131 include, but are not limited to, metal layer interdigital capacitors (mom), metal plane capacitors (mim), poly layer interdigital capacitors (pipe), mos tube capacitors, trench capacitors, and stacked capacitors, and the integrated circuit capacitor array 131 is formed by lamination and combination.

In particular embodiments, the capacitive component 13 may be further increased in capacitance and reduced in component cost by any one or more of the following five ways. The first mode is as follows: the capacitor density is used as a priority target, and the semiconductor process capacitor is stacked, and other parameters such as precision, temperature drift, dielectric loss, self-discharge and the like are properly compromised. The second mode is as follows: a chip manufacturing process with lower machining precision is used. The third way is: other metal layer processes are used, such as aluminum connections. The fourth mode is: and expanding a low-precision subsequent process to form more metal layers. The fifth mode is as follows: the use of smaller granularity integrated circuit capacitor array 131 and the provision of an inexpensive array access switch, such as a one-time programmable memory (efuse), bypasses the partially disabled integrated circuit capacitor array 131 to improve the yield of the multilayer capacitor assembly 13.

In one embodiment, referring to FIG. 2, the self-powered nonvolatile programmable chip 10 further has integrated thereon a data protection/restoration logic array 141. The data protection/restoration logic array 141 connects the nonvolatile memory array 121, the dynamic random access memory array 111, and the integrated circuit capacitor array 131. In a specific embodiment, in response to the first preset condition, the integrated circuit capacitor array 131 supplies power to the data protection/restoration logic array 141, so that the data protection/restoration logic array 141 stores the data in the dynamic random access memory array 111 to the nonvolatile memory array 121 as backup data. Further, in response to the second preset condition, the data protection/restoration logic array 141 restores the backup data in the nonvolatile memory array 121 to the dynamic random access memory array 111. The second preset condition may be a system power supply or a system recovery condition.

Specifically, after the system is triggered by a protection event such as power failure, the system reads the data in the dynamic random access memory array 111 through the data protection/recovery logic array 141 under the power supply of the integrated circuit capacitor array 131, and then protects the data to the nonvolatile memory array 121 according to the planned interval and sequence, so as to store the data through the nonvolatile memory array 121. And then the system is started for the first time after the triggering of protection events such as power failure, and the like, the backup data stored in the nonvolatile storage array 121 is read out through the data protection/recovery logic array 141 and recovered to the dynamic random storage array 111 according to the planning area and sequence, so that the data protection of the dynamic random storage array 111 is realized. Compared with an I/O interface (input/output interface) and a standard DRAM interface in the prior art, the advantages of high bandwidth and low power consumption of three-dimensional heterogeneous integration are inherited, the backup time is reduced, the backup power consumption is reduced, and the backup power supply capacitance overhead is reduced; in a specific embodiment, after the backup data stored in the nonvolatile memory array 121 is restored to the dynamic random access memory array 111, flash full erase is performed once, and the count is updated to the nonvolatile memory array 121. Wherein, for a sector that fails after erasure, i.e., a subset of the nonvolatile memory array 121, the failed sector can be replaced with a healthy sector by address mapping area modification; and finishing the initialization preparation of the next protection action.

In one embodiment, referring to fig. 2, the data protection/recovery logic module may be integrated with the nonvolatile memory component 12, and connected with the nonvolatile memory array 121 through an internal metal layer, and connected with the dynamic random access memory array 111 through a three-dimensional heterogeneous integrated bonding structure.

In one embodiment, as shown in fig. 2, the nonvolatile memory array 121 and the data protection/recovery logic array 141 are both block-shaped and connected to the second signal bonding area 122 embedded in the nonvolatile memory device 12, which is exemplified in the following embodiments. The layouts of the nonvolatile memory array 121 and the data protection/recovery logic array 141 are not limited, and may be specifically set according to actual requirements. Of course, in other embodiments, the nonvolatile memory array 121 and the data protection/recovery logic array 141 may be integrated in the same block area, i.e., the array indicated by reference numeral 121 or 141 in FIG. 2 is integrated by the nonvolatile memory array 121 and the data protection/recovery logic array 141.

In another embodiment, referring to fig. 3 and fig. 4, fig. 3 is a schematic structural diagram of a self-powered nonvolatile programmable chip according to a second embodiment of the present application; FIG. 4 is a schematic plan view of a self-powered non-volatile programmable chip according to the embodiment of the present application shown in FIG. 3; the self-powered non-volatile programmable chip 10 also includes a Logic component 14 (Logic die); the logic component 14 is stacked and bonded with the dynamic random access memory component 11, the nonvolatile memory component 12 and the capacitor component 13. In this embodiment, the data protection/recovery logic array 141 is specifically integrated in the logic component 14, and is respectively connected to the dynamic random access memory array 111 and the nonvolatile memory array 121 through the three-dimensional heterogeneous integrated bonding structure, so as to store the data in the dynamic random access memory array 111 into the nonvolatile memory array 121 as backup data; or restore the backup data in the nonvolatile memory array 121 to the dynamic random access memory array 111. Thus, when the self-powered nonvolatile programmable chip 10 enters a protection state, the data in the dynamic random access memory array 111 is correspondingly transferred to the nonvolatile memory array 121 in parallel through high-bandwidth interconnection; when the self-powered nonvolatile programmable chip 10 enters a recovery state, the data in the nonvolatile memory array 121 is correspondingly recovered to the dynamic random access memory array 111 through the high-bandwidth interconnection.

Wherein the logic component 14 may be wholly or partially composed of programmable logic modules or embedded programmable logic device modules, i.e., at least a portion of the data protection/restoration logic array 141 of the logic component 14 is composed of programmable logic modules or embedded programmable logic modules to establish the updatability of the functionality of the logic component 14 to accommodate technical protocol upgrades. In a specific embodiment, the logic component 14 is entirely composed of programmable logic modules or embedded programmable logic modules, i.e., all of the data protection/restoration logic arrays 141 on the logic component 14 are composed of programmable logic modules or embedded programmable logic modules to achieve functional reconfigurability of the logic component 14. In another embodiment, portions of the logic component 14 are comprised of embedded programmable logic modules, i.e., portions of the data protection/restoration logic array 141 on the logic component 14 are comprised of embedded programmable logic modules. Specifically, the variable function portion in the data protection/restoration logic array 141 on the logic component 14, such as a portion related to the technical protocol upgrade, is constituted by an embedded programmable logic module; the fixed function parts in the data protection/restoration logic array 141 on the logic element 14, such as parts unrelated to technical protocol upgrades, are implemented by application specific integrated circuits, thereby increasing the functional density of the logic element 14 on the basis of realizing the functional reconfigurability of the logic element 14.

In a specific embodiment, referring to fig. 3, the logic component 14 is specifically disposed between the dynamic random access memory component 11 and the nonvolatile memory component 12, so as to control the data flow between the two components of the dynamic random access memory component 11 and the nonvolatile memory component 12 through the logic component 14. In this embodiment, the dynamic random access memory device 11, the logic device 14, and the nonvolatile memory device 12 form a stacked structure, and the capacitor device 13 may be disposed on a first surface layer and/or a second surface layer opposite to the first surface layer of the stacked structure. The stacking position of the capacitor assembly 13 can be specifically set according to actual requirements, so as to form a three-dimensional heterogeneous integrated structure with optimal data flow. In one embodiment, referring to fig. 3, the capacitor assemblies 13 are all disposed on a first surface layer of the nonvolatile memory assembly 12 facing away from the logic assembly 14; in this embodiment, the stacking order of the four components in the self-powered nonvolatile programmable chip 10 can be, from top to bottom, a dynamic random access memory component 11, a logic component 14, a nonvolatile memory component 12, and a plurality of capacitor components 13; or another stacking order that mirrors the distribution: a plurality of capacitive components 13, a non-volatile storage component 12, a logic component 14 and a dynamic random access memory component 11. Of course, in other embodiments, the capacitor assembly 13 may be disposed on a side of the dynamic random access memory assembly 11 facing away from the logic assembly 14; in this embodiment, the stacking order of the four components in the nonvolatile programmable chip 10 may be from top to bottom, which includes a plurality of capacitor components 13, a dynamic random access memory component 11, a logic component 14 and a nonvolatile memory component 12; or another stacking order that mirrors the distribution: a non-volatile memory component 12, a logic component 14, a dynamic random access memory component 11, and a plurality of capacitive components 13. Of course, in other embodiments, the capacitor element 13 may be disposed between any two of the dynamic random access memory element 11, the logic element 14 and the nonvolatile memory element 12, which is not limited in this regard.

Wherein, in the implementation process, each component related to the application is composed of at least one layer of component stack with corresponding functions; for example, the dynamic random access memory component 11 is formed by stacking two, three, four or more layers of dynamic random access memory components 11; the logic element 14 is stacked from two, three, four or more layers of logic elements 14.

It should be noted that, the stacking order of each component in the self-powered nonvolatile programmable chip 10 and the specific implementation of the switching capacitor component 13 to the top layer or the bottom layer of the nonvolatile programmable chip 10 are the same as or similar to the stacking order of the four components in the present embodiment and the specific implementation of the switching capacitor component 13 to the top layer or the bottom layer of the self-powered nonvolatile programmable chip 10, and the same or similar technical effects may be achieved, and specific reference may be made to this embodiment.

In another embodiment, referring to fig. 5, fig. 5 is a schematic structural diagram of a self-powered nonvolatile programmable chip according to a third embodiment of the present application; the dynamic random access memory component 11 and the nonvolatile memory component 12 are adjacently arranged; this can avoid unnecessary design adjustments of the dynamic random access memory component 11 and the nonvolatile memory component 12 due to design improvements of the data protection/restoration logic array 141.

In this embodiment, the logic component 14 is disposed adjacent to the dynamic random access memory component 11 or the nonvolatile memory component 12 to form a stacked structure. The capacitive component 13 may be disposed on a first skin of the laminate structure and/or a second skin opposite the first skin. Specifically, the stacking order of the four components in the self-powered nonvolatile programmable chip 10 may be, from top to bottom, a dynamic random access memory component 11, a nonvolatile memory component 12, a logic component 14, and a plurality of capacitor components 13; or, a logic component 14, a dynamic random access memory component 11, a nonvolatile memory component 12, and a plurality of capacitive components 13 (see fig. 5); or, a nonvolatile memory component 12, a dynamic random access memory component 11, a logic component 14, and a plurality of capacitive components 13; or, a logic component 14, a non-volatile storage component 12, a dynamic random access memory component 11, and a plurality of capacitive components 13.

In an embodiment, referring to fig. 6, fig. 6 is a schematic structural diagram of a self-powered nonvolatile programmable chip according to a fourth embodiment of the present application; the capacitive assembly 13 comprises a first capacitive assembly 13a and a second capacitive assembly 13b. Wherein the first capacitor assembly 13a is integrated with the first integrated circuit capacitor array 131; the second capacitor assembly 13b is integrated with a second integrated circuit capacitor array 131. The first capacitor element 13a and the second capacitor element 13b are provided on a first surface layer and a second surface layer of a laminated structure formed by laminating and bonding the nonvolatile memory element 12, the dynamic random access memory element 11, and the logic element 14, respectively. In a specific embodiment, the first capacitor element 13a and/or the second capacitor element 13b may be multi-layered to form a high-capacity capacitor network. The active layer and metal layer resources are enriched by splitting the multi-layer capacitor assembly 13, and the nonvolatile programmable chip 10 can be designed on the first capacitor assembly 13a by high-density interconnection of the first capacitor assembly 13a and the core area of the dynamic random access memory assembly 11 shown in fig. 6, so that the redistribution design of the nonvolatile programmable chip 10 for externally leading out the Bump/Pad and the I/O is realized, the related overhead is avoided from occurring in the logic assembly 14, the dynamic random access memory assembly 11 or the nonvolatile memory assembly 12, and the area waste expansion caused by the vertical symmetric design of the related array is effectively avoided.

In this embodiment, the stacking order of the four components in the self-powered nonvolatile programmable chip 10 can be from top to bottom, which is the first capacitor component 13a, the dynamic random access memory component 11, the logic component 14, the nonvolatile memory component 12, and the second capacitor component 13b (see fig. 6); or, a first capacitance component 13a, a logic component 14, a dynamic random access memory component 11, a nonvolatile memory component 12, and a second capacitance component 13b; or, a first capacitance component 13a, a nonvolatile memory component 12, a dynamic random access memory component 11, a logic component 14, and a second capacitance component 13b; or, a first capacitance component 13a, a logic component 14, a nonvolatile memory component 12, a dynamic random access memory component 11, and a second capacitance component 13b. Of course, other capacitive components 13 may be embedded in some or all of the logic component 14, the dynamic random access memory component 11, and the nonvolatile memory component 12; such as: a first capacitive component 13a, a dynamic random access memory component 11, a non-volatile memory component 12, a logic component 14, a second capacitive component 13b, and so on.

Of course, in this embodiment, the capacitor element 13 may be disposed between any two of the dynamic random access memory element 11, the logic element 14 and the nonvolatile memory element 12, which is not limited in this aspect of the application.

In a specific embodiment, the dynamic random access memory device 11, the nonvolatile memory device 12, and the logic device 14 are further integrated with at least one signal bonding area and at least one power bonding area, and the capacitor device 13 is further integrated with at least one power bonding area. The dynamic random access memory component 11, the nonvolatile memory component 12 and the logic component 14 are specifically bonded in a one-to-one correspondence and lamination manner with the signal bonding regions of the adjacent other component through respective signal bonding regions so as to realize signal interconnection between the two components, and are bonded in a one-to-one correspondence and lamination manner with the power bonding regions of the adjacent other component through respective power bonding regions so as to realize power connection of the two components. The signal bonding area and the power bonding area are specifically three-dimensional bonding areas.

The three-dimensional heterogeneous integrated bonding of the self-powered non-volatile programmable chip 10 is described in detail below.

Referring to fig. 6, the dynamic random access memory device 11 further includes an extraction circuit for connecting the dynamic random access memory array 111 to other devices in the self-powered nonvolatile programmable chip 10, such as a first signal bonding region 112 for connecting the data protection/recovery logic array 141 and the extraction circuit of the first capacitor device 13a to three-dimensional high density signals, and a first power bonding region 152 for connecting the dynamic random access memory device 11 to other devices in the self-powered nonvolatile programmable chip 10, such as a logic device 14 and the first capacitor device 13a to three-dimensional power. The nonvolatile memory device 12 also integrates a pull-out circuit for the nonvolatile memory array 121 to other components within the self-powered nonvolatile programmable chip 10, such as a second signal bond area 122 for three-dimensional high density signal connection to the data protection/restoration logic array 141, and a second power bond area 162 for the nonvolatile memory device 12 to other components within the self-powered nonvolatile programmable chip 10, such as a second power bond area 162 for three-dimensional power connection to the logic device 14 and the second capacitor device 13 b. The capacitive assembly 13 also incorporates a third power bond region 132 for three-dimensional power connection of the integrated circuit capacitive array 131. The logic device 14 also integrates a pull-out circuit for the data protection/restoration logic array 141 to other devices within the self-powered nonvolatile programmable chip 10, such as a fourth signal bond area 142 for three-dimensional high density signal connection with the nonvolatile memory array 121 and the data protection/restoration logic array 141, and a fourth power bond area 172 for the logic device 14 to other devices within the self-powered nonvolatile programmable chip 10, such as a third power connection with the dynamic random access memory device 11 and the nonvolatile memory device 12.

Wherein, referring to fig. 2, the dynamic random access memory component 11 and the nonvolatile memory component 12 are bonded together through the first signal bonding region 112 and the second signal bonding region 122 in a stacked manner to realize high-density signal interconnection of the two; wherein the first signal bonding region 112 and the second signal bonding region 122 are connected by an interconnect structure D1. The dynamic random access memory component 11 and the nonvolatile memory component 12 are laminated and bonded together through the first power bonding area 152 and the second power bonding area 162 so as to realize power interconnection of the two; wherein the first and second power bond regions 152 and 162 are connected by an interconnect structure E1. The nonvolatile memory component 12 and the capacitor component 13 are laminated and bonded together through the second power bonding region 162 and the third power bonding region 132 to realize power interconnection of the two; wherein the second and third power bond regions 162 and 132 are connected by an interconnect structure E2.

Referring to fig. 3, the dynamic random access memory component 11 and the logic component 14 are stacked and bonded together by the first signal bonding region 112 and the fourth signal bonding region 142 to realize high-density signal interconnection of the two; wherein the first signal bonding region 112 and the fourth signal bonding region 142 are connected by an interconnect structure D2. The dynamic random access memory component 11 and the logic component 14 are stacked and bonded together through the first power bonding region 152 and the fourth power bonding region 172 to realize power interconnection of the two; wherein the first power bond region 152 and the fourth power bond region 172 are connected by an interconnect structure E3. The logic component 14 and the nonvolatile memory component 12 are stacked and bonded together by the fourth signal bond region 142 and the second signal bond region 122 to achieve high density signal interconnection; wherein the fourth signal bonding region 142 and the second signal bonding region 122 are connected by an interconnect structure D3. The logic component 14 and the nonvolatile memory component 12 are stacked and bonded together by the fourth power bond region 172 and the second power bond region 162 to achieve power interconnection of the two; wherein the fourth power bond region 172 and the second power bond region 162 are connected by an interconnect structure E4. The capacitor assemblies 13 are stacked and bonded together by a third power bond region 132 to provide power interconnection therebetween.

Referring to fig. 5, the dynamic random access memory assembly 11 and the capacitor assembly 13 are laminated and bonded together through the first power bonding region 152 and the third power bonding region 132 to realize power interconnection of the two; wherein the first power bond region 152 and the third power bond region 132 are connected by an interconnect structure E5.

Referring to fig. 5, the number of signal bonding regions integrated on each component may be more than one. For example, the dynamic random access memory component 11 may have a plurality of first signal bonding regions 112 integrated thereon; the nonvolatile memory component 12 may have a plurality of second signal bond areas 122 integrated thereon. And the plurality of signal bond regions on each component are widely distributed within the component to achieve high density interconnection across the component of the corresponding array on each component. Specifically, the number of power bond regions integrated on each component may be multiple. For example, the dynamic random access memory component 11 may have a plurality of first power bonding areas 152 integrated thereon; the nonvolatile memory component 12 may be integrated with a plurality of second power bonding areas 162, and the plurality of power bonding areas on each component may be disposed at an edge position of the corresponding component, so as to reduce occupation of internal resources of the corresponding component, improve distribution density of signal bonding areas, and further realize high-density interconnection between the components.

In a specific embodiment, each signal bonding area may also be provided with a level conversion circuit; two adjacent components can be mutually connected in a bonding way through one signal bonding area, and can also be connected in a bonding way through a plurality of signal bonding areas so as to realize the transmission of different signals; for example, referring to fig. 3, between the dynamic random access memory component 11 and the logic component 14, the first signal bonding area 112 and the fourth bonding area 142 at corresponding positions widely distributed in the component may be bonded to each other, so as to implement signal lamination bonding connection between the dynamic random access memory component 11 and the logic component 14; while the dynamic random access memory component 11 and the power plane of the logic component 14 can be bonded to each other by the first power bonding region 152 at the edge of the component and the fourth bonding region 172 at the corresponding location.

In a specific embodiment, please continue to refer to fig. 5, two adjacent components of the dynamic random access memory component 11, the nonvolatile memory component 12 and the logic component 14 are disposed, wherein a vertical projection of a signal bonding area of one component along a stacking direction thereof coincides with a signal bonding area of the other component; that is, the vertical projection of the first signal bonding region 112 of the dynamic random access memory device 11 bonded to the logic device 14 along the stacking direction of the nonvolatile programmable chip 10 coincides with the fourth signal bonding region 142 of the logic device 14 bonded to the dynamic random access memory device 11; the perpendicular projection of the fourth signal bonding region 142 of the logic element 14 bonded to the nonvolatile memory element 12 along the stacking direction of the nonvolatile programmable chip 10 coincides with the second signal bonding region 122 of the nonvolatile memory element 12 bonded to the logic element 14. Of course, in a specific embodiment, two components of the dynamic random access memory component 11, the nonvolatile memory component 12, the logic component 14 and the capacitor component 13 that are adjacently disposed, wherein the vertical projection of the power bonding area of one component along the stacking direction thereof is also coincident with the power bonding area of the other component.

Specifically, referring to fig. 7, fig. 7 is a schematic plan view of a nonvolatile programmable chip corresponding to fig. 3 according to another embodiment of the present application; each of the dynamic random access memory device 11, the logic device 14, the nonvolatile memory device 12, and the capacitor device 13 may include a substrate, an active layer, an internal metal layer, and a top metal layer, which are sequentially stacked. In a specific bonding process, a thinning process may be performed on the substrate of each component participating in three-dimensional heterogeneous integration to form a thinned substrate, and through silicon vias (Through Silicon Via, TSVs) are formed on the thinned substrate, so as to lead the inner metal layer out of a side surface of the substrate facing away from the active layer. Wherein, the thinning treatment can be specifically carried out by adopting a grinding or polishing mode. In a specific embodiment, the transistors of the array on each component are specifically integrated in the corresponding active layer, i.e. the interconnection signal of the array on each component originates from the active layer of that component. And each assembly and adjacent layer are bonded each other including two ways, wherein one way is that the inter-assembly interconnection signal is interconnected to the three-dimensional heterogeneous integrated bonding structure through the through silicon via of the thinned substrate of the assembly and is laminated and bonded with the adjacent assembly; alternatively, the inter-component interconnect signal is connected to the top metal layer through the component internal metal layer and the holes, interconnected to the three-dimensional heterogeneous integrated bonding structure, and bonded in a stacked manner with the adjacent component.

In a specific embodiment, the nonvolatile programmable chip 10 includes a dynamic random access memory device 11, a logic device 14 and a nonvolatile memory device 12, and the top metal layer of the dynamic random access memory device 11 is bonded to the substrate layer of the logic device 14 through a three-dimensional hetero-integrated bonding structure D2/E3, and the top metal layer of the logic device 14 is bonded to the top metal layer of the nonvolatile memory device 12 through a three-dimensional hetero-integrated bonding structure D3/E4.

As shown in fig. 7, in the embodiment, the data protection/recovery logic array 141 and the dynamic random access memory array 111 are interconnected in a high density manner specifically: the dynamic random access memory array 111 outgoing line of the data protection/recovery logic array 141 is interconnected to the top metal layer of the dynamic random access memory assembly 11 at a high bandwidth through the silicon through hole penetrating through the active layer of the logic assembly 14 and the thinned substrate and the three-dimensional heterogeneous integrated bonding structure of the dynamic random access memory assembly 11 and the logic assembly 14 in the internal metal layer of the logic assembly 14; the top metal layer of the dynamic random access memory 11 is connected to the dynamic random access memory array 111 on the dynamic random access memory 11 through the internal metal layer of the dynamic random access memory 11.

As shown in fig. 7, the data protection/recovery logic array 141 and the nonvolatile memory array 121 are interconnected in a high density manner specifically as follows: the data protection/recovery logic array 141 leads out, at the inner metal layer of the logic component 14, and further connected to the top metal layer of the logic component 14, through the three-dimensional heterogeneous integrated bonding structure of the logic component 14 and the nonvolatile memory component 12, to be interconnected to the top metal layer of the nonvolatile memory component 12 with high bandwidth; at the top metal layer of the non-volatile memory component 12, through the internal metal layer connections of the non-volatile memory component 12, there is a corresponding non-volatile memory array 121 interconnected to the non-volatile memory component 12.

The self-powered nonvolatile programmable chip 10 provided in this embodiment integrates the dynamic random storage component 11, the nonvolatile storage component 12 for storing data in the dynamic random storage component 11, the logic component 14 for carrying data between the dynamic random storage component 11 and the nonvolatile storage component 12 and the capacitor component 13 for supplying power during data protection into a single chip in a three-dimensional heterogeneous integrated bonding manner, so that when power is unexpectedly cut off or a system is crashed, the integrated logic component 14 can store the data stored in the dynamic random storage component 11 in the nonvolatile storage component 12, and the problem of data damage in the dynamic random storage component 11 caused by power failure is avoided; and can continue to power the dynamic random access memory array 111, the nonvolatile memory array 121, and the logic component 14 through the capacitor component 13 during data protection; simultaneously, the interconnection quantity and the interconnection interface frequency of the self-powered nonvolatile programmable chip 10 are effectively increased, and high-bandwidth, high-energy-efficiency ratio and low-delay mass storage access is provided; compared with the scheme that a nonvolatile memory chip and a data protection/recovery device are arranged on a nonvolatile dual in-line memory module (NVDIMM) board card in the prior art, the method has the advantages that a special nonvolatile memory chip and a data protection/recovery device are not needed, the integration density of the self-powered nonvolatile programmable chip 10 can be effectively improved, and the production cost is reduced; in addition, through three-dimensional heterogeneous integrated bonding, metal connection among components is directly established, a physical input/output (I/O) circuit is not needed, physical and electrical parameters of the three-dimensional heterogeneous integrated bonding follow the technological characteristics of a semiconductor manufacturing process, the density (bandwidth) is greatly improved, the power consumption and the data protection time are remarkably reduced, and the capacity requirements of spare power supply devices such as super capacitors are reduced.

In one embodiment, referring to fig. 7, the integrated circuit capacitor array 131 of the at least one layer of capacitor elements 13 in the self-powered nonvolatile programmable chip 10 is specifically connected to the nonvolatile memory array 121, the data protection/recovery logic array 141 and the dynamic random access memory array 111, and is used for supplying power to the nonvolatile memory array 121, the data protection/recovery logic array 141 and the dynamic random access memory array 111 during data protection; the power supply mode of the power supply includes at least one of always supplying power, always powering off and powering off in advance, so as to select to design always powering off or powering off in advance according to the actual protection process, thereby reducing the requirement on the capacity of the multilayer integrated circuit capacitor array 131 on the capacitor assembly 13 and reducing the implementation cost of the capacitor assembly 13.

Specifically, the integrated circuit capacitor array 131 of the at least one layer of capacitor assembly 13 is configured as a plurality of power domains, the plurality of nonvolatile memory arrays 121, the plurality of data protection/recovery logic arrays 141 in the nonvolatile memory assembly 12 and the plurality of dynamic random access memory arrays 111 in the dynamic random access memory assembly 11 form a plurality of power supply ranges, each power supply range is at least connected with one of the power domains, so as to supply power to the power supply ranges connected with the power supply ranges through the power domains, thereby realizing division of the power supply ranges of the integrated circuit capacitor array 131, realizing time-sharing power supply, further reducing the capacity requirement of the multilayer integrated circuit capacitor array 131 on the capacitor assembly 13, reducing power consumption and realizing self-power supply.

Each power domain can be correspondingly connected with a plurality of power supply ranges; for example, each power domain is correspondingly connected with two, three, four or more power supply ranges so as to supply power to the plurality of power supply ranges connected with the power domain through the power domain. Wherein each power range includes at least one non-volatile storage array 121, at least one data protection/restoration logic array 141, and at least one dynamic random access storage array 111 connected to each other; that is, each of the plurality of power domains may be correspondingly connected to one or more nonvolatile memory arrays 121 (or dynamic random access memory arrays 111, or data protection/restoration logic arrays 141) within a power supply range to supply power to one or more data protection/restoration logic arrays 141 connected to the nonvolatile memory arrays 121, and to one or more dynamic random access memory arrays 111 connected to the data protection/restoration logic arrays 141.

It will be appreciated that the connections between the dynamic random access memory array 111, the data protection/recovery logic array 141 and the nonvolatile memory array 121 may be one-to-one or one-to-many or many-to-one within each power range. For example, a data protection/restoration logic array 141 forms a power range with the dynamic random access memory array(s) 111 and nonvolatile memory array(s) 121 and shares a power domain; or the plurality of data protection/restoration logic arrays 141 form a power supply range with the plurality of dynamic random access memory arrays 111 and the plurality of nonvolatile memory arrays 121 and share a power domain.

The following describes in detail a specific scheme of time-sharing power supply of a plurality of power supply domains, taking an example that the integrated circuit capacitor array 131 of at least one layer of capacitor assembly 13 is configured as two power supply domains, and each assembly is integrated with two arrays; referring to fig. 7, the dynamic random access memory assembly 11 is integrated with two dynamic random access memory arrays 111, namely a dynamic random access memory array 1 and a dynamic random access memory array 2; the logic component 14 integrates two data protection/recovery logic arrays 141, namely a data protection/recovery logic array 1 and a data protection/recovery logic array 2; the nonvolatile memory module 12 integrates two nonvolatile memory arrays 121, namely, nonvolatile memory array 1 and nonvolatile memory array 2. The nonvolatile memory array 1 is correspondingly connected with the data protection/recovery logic array 1 and the dynamic random access memory array 1 to form a first power supply range and share a first power domain; the nonvolatile memory array 2 is correspondingly connected with the data protection/recovery logic array 2 and the dynamic random access memory array 2 to form a second power supply range and share a second power domain; that is, a first one of the two power domains is correspondingly connected to the nonvolatile memory array 1 to supply power to the first power supply range; the second power domain is correspondingly connected to the nonvolatile memory array 2 to supply power to the second power supply range. Because each power supply range is powered by different power domains, each power supply range can be controlled to be always powered off, always powered off or powered off in advance by the corresponding power domain according to actual requirements, so that power consumption is saved, and the requirement of the self-powered nonvolatile programmable chip 10 on the capacity of the integrated circuit capacitor array 131 is reduced.

Of course, in other embodiments, the dynamic random access memory array 1 and the dynamic random access memory array 2 and the data protection/recovery logic array 1 and the data protection/recovery logic array 2 and the nonvolatile memory array 1 and the nonvolatile memory array 2 may form three, four, five, or even more power supply ranges, and the integrated circuit capacitor array 131 of the at least one layer of capacitor assembly 13 may also be configured as three, four, five, or even more power supply domains, where the power supply domains are connected in a one-to-one, one-to-many, or many-to-one manner with the formed power supply ranges to supply power.

It should be noted that the above-mentioned dynamic random access memory array 1 and dynamic random access memory array 2, data protection/recovery logic array 1 and data protection/recovery logic array 2, and nonvolatile memory array 1 and nonvolatile memory array 2 are only exemplary illustrations of the arrays in the corresponding components, and in a specific embodiment, each component may further include an array 3 and an array 4 … … n; wherein n is a natural number of 1 or more. In a specific embodiment, the one or more data protection/recovery logic arrays 141, the one or more nonvolatile memory arrays 121, and the one or more dynamic random access memory arrays 111 may be more flexibly organized to form a power supply range, and the one or more power domains may form a self-powered structure of the entire self-powered nonvolatile programmable chip 10.

In one embodiment, referring to fig. 7, the self-powered nonvolatile programmable chip 10 further includes a plurality of control switches, each control switch being connected to at least one of the plurality of power domains to control the power supply or the power interruption of the power domain connected thereto through the control switch. In a specific embodiment, one power domain is correspondingly connected with one control switch, so that the power domain connected with the control switch is independently controlled through the corresponding control switch, and further, the power is always cut off, always power is supplied or power is cut off in advance in a corresponding power supply range; in another specific embodiment, a plurality of power domains are correspondingly connected with a control switch; specifically, the present application may be selected according to practical needs, which is not limited in this respect.

In particular, the control switch may be a power supply, i.e. a power switch; the following examples take this as an example. Of course, in other embodiments, the control switch may be an array integrated on a component, which is not limited by the present application.

A plurality of power sources may be specifically disposed in the nonvolatile memory module 12 and connected to the nonvolatile memory array 121 to perform voltage conversion by the plurality of power sources. Specifically, the multiple power supplies may be DC-DC regulated power supplies, such as Buck-Boost circuits, to stabilize the voltage of the multilayer integrated circuit capacitor array 131 on the capacitor assembly 13 to the core voltage required by the self-powered non-volatile programmable chip 10, support the protection process for power supply, and extend the power supply time by the voltage pump principle of the DC-DC power supply. In a specific embodiment, the power supply network formed by the multi-layer capacitor assembly 13 is concentrated to the three-dimensional heterogeneous integrated bonding structure on the capacitor assembly 13, and is interconnected to the internal metal layer of the nonvolatile memory assembly 12 through the three-dimensional heterogeneous integrated bonding structure of the capacitor assembly 13 and the nonvolatile memory assembly 12 and the through silicon vias penetrating through the active layer and the thinned substrate of the nonvolatile memory assembly 12 to be interconnected to a plurality of power supply networks on the nonvolatile memory assembly 12, and is further interconnected to a plurality of power supply networks on the logic assembly 14 and the dynamic random access memory assembly 11 to realize the self-powered power supply network of the self-powered nonvolatile programmable chip 10.

Specifically, the multiple power supplies may correspond to the internal power supply networks in the nonvolatile memory array 121, the data protection/recovery logic array 141 and the dynamic random access memory array 111 one by one, and form power supply switches of multiple power supply domains to realize controlled power supply; wherein the control signal for the power switch may come from the data protection/restoration logic array 141. Wherein, the internal power supply network refers to a network that related arrays are powered by the multi-layer integrated circuit capacitor array 131 on the capacitor assembly 13 in the self-powered nonvolatile programmable chip 10, and is built in a similar manner to the signal interconnection of the nonvolatile memory array 121, the data protection/recovery logic array 141 and the dynamic random access memory array 111; it will be appreciated that one of the power supply ranges referred to above may be an internal power supply network.

In one embodiment, the number of power supplies may be two, namely, power supply 1 and power supply 2; the power supply 1 is correspondingly connected with a combination of the dynamic random access memory array 1, the data protection/recovery logic array 1 and the nonvolatile memory array 1 in the first power supply range so as to realize independent controlled power supply of the corresponding power supply domain to the first power supply range; the power supply 2 is correspondingly connected with a combination of the dynamic random access memory array 2, the data protection/recovery logic array 2 and the nonvolatile memory array 2 in the second power supply range, so as to realize independent controlled power supply of the corresponding power supply domain to the second power supply range. Of course, in other embodiments, the power supplies 1 and 2 may be in one-to-many or many-to-one correspondence with the data protection/recovery logic array 141, the nonvolatile memory array 121, and the dynamic random access memory array 111, which is not limited in this regard.

It should be noted that the above power source 1 and power source 2 are merely exemplary illustrations of the number of power sources in the self-powered nonvolatile programmable chip 10 according to an embodiment of the present application; in an embodiment, the self-powered nonvolatile programmable chip 10 may further include a power supply 3, a power supply 4 … …, and a power supply n; wherein n is a natural number of 1 or more. Specifically, each power source may be connected to one or more power supply ranges to enable the power domain to independently and controllably power the corresponding power supply range.

In a particular embodiment, at least a portion of the data in the dynamic random access memory array 111 is non-sensitive data; the control switch may be used to control the power domain corresponding to the non-sensitive data to always be powered off. Specifically, by the above scheme of setting multiple power domains to respectively perform controlled power supply, all data of the dynamic random access memory array 111 corresponding to some power domains can be set as non-sensitive data according to real-time application data, and the power domains can be designed to be always closed without protecting the data; and setting partial data of the dynamic random access memory array 111 corresponding to some power domains as non-sensitive data, without protecting the data, that is, the data capacity of the backup needed by each power domain may be different, and for the circuit which has been protected, the power domain may be optionally turned off in advance. It can be understood that when the rest data of the dynamic random access memory array 111 corresponding to some power domains are sensitive data, the control switch controls the power domains corresponding to the sensitive data to supply power to protect the sensitive data.

Of course, in other embodiments, the data protection/recovery function may be provided only for a portion of the dynamic random access memory array 111 by protocol convention without relying on real-time application data, and the data protection/recovery function may not be provided for another portion, and the power domains of the data protection/recovery logic array 141, the nonvolatile memory array 121, the data protection/recovery connection channel, and the multi-layer integrated circuit capacitor array 131 may be omitted to reduce the capacity requirements of the multi-layer integrated circuit capacitor array 131 on the capacitor assembly 13.

In a specific embodiment, referring to fig. 7, the dynamic random access memory assembly 11 is further provided with an external interface 113 and a Multiplexer (MUX) connected to the dynamic random access memory array 111. Wherein the external interface 113 and the multiplexer are integrated in the active layer of the dynamic random access memory assembly 11. The external interface 113 may be a standard DRAM interface. The external interface 113 is connected to the dynamic random access memory array 111 through an internal metal layer. In an embodiment, the external interface 113 does not require internal power to the integrated circuit capacitor array 131, as it is independent of data protection behavior. The number of multiplexers may be plural, such as MUX1 and MUX2. At least a portion of the dynamic random access memory array 111 is designed to be coupled to a multiplexer through the internal metal layers of the dynamic random access memory element 11. The multiplexer selects the dynamic random access memory array 111 to connect with the external interface 113 or the corresponding data protection/recovery logic array 141 respectively, so as to selectively connect the dynamic random access memory array 111 with the external interface 113 for use as a general DRAM; or selectively connecting the dynamic random access memory array 111 with the corresponding data protection/recovery logic array 141 to achieve data protection and recovery, thereby achieving time-division multiplexing of memory signals; the select control signal for the multiplexer may originate from the data protection/restoration logic array 141.

Specifically, when the self-powered nonvolatile programmable chip 10 works normally, the multiplexer is controlled to switch the signals of the dynamic random access memory array 111 to the signals led out from the external interface 113, the signals led out from the external interface 113 pass through the internal metal layer of the dynamic random access memory assembly 11 and through the active layer of the dynamic random access memory assembly 11 and the silicon through holes of the thinned substrate, and the signals led out from the external interface 113 are externally input/output and connected to the outermost interface (bonding interface, PAD/Bump leading-out interface) of the whole self-powered nonvolatile programmable chip 10; when the self-powered nonvolatile programmable chip 10 enters a data protection state, the multiplexer is controlled to switch the signals of the dynamic random access memory array 111 to the data protection/recovery logic array 141, and the data in the dynamic random access memory array 111 is stored to the nonvolatile memory array 121 through the data protection/recovery logic array 141; when the self-powered nonvolatile programmable chip 10 enters a data recovery state, the multiplexer is controlled to switch the signals of the dynamic random access memory array 111 to the data protection/recovery logic array 141, and the protection backup data in the nonvolatile memory array 121 is recovered to the dynamic random access memory array 111 through the data protection/recovery logic array 141; after the recovery is completed, the data protection/recovery logic array 141 controls to erase the corresponding nonvolatile memory array 121 and update the erase record of the corresponding nonvolatile memory array 121, and switches the multiplexer to enter a normal operation mode in which signals of the dynamic random access memory array 111 are communicated with signals led out from the external interface 113.

Specifically, referring to fig. 8, fig. 8 is a schematic flow chart of data protection/recovery in the self-powered nonvolatile programmable chip 10 according to an embodiment of the present application; in particular embodiments, data protection/restoration logic array 141 specifically includes protection circuitry and restoration circuitry; the data protection/recovery logic array 141 specifically stores the data in the dynamic random access memory array 111 to the nonvolatile memory array 121 through a protection circuit; the backup data in the nonvolatile memory array 121 is restored to the dynamic random access memory array 111 by a restoration circuit. In this embodiment, in a normal working state of the upper system, the upper system performs storage access on the dynamic random access memory array 111 through the external interface 113; after the system enters a protection mode, a protection circuit in the data protection/recovery logic array 141 reads data in the dynamic random access memory array 111, and the read data in the dynamic random access memory array 111 is stored to the nonvolatile memory array 121 through a high-bandwidth cross-component connection (protection 1) between the data protection/recovery logic array 141 and the dynamic random access memory array 111, and then the read data in the dynamic random access memory array 111 is stored to the nonvolatile memory array 121 through a high-bandwidth cross-component connection (protection 2) between the data protection/recovery logic array 141 and the nonvolatile memory array 121; after the system enters the protection mode, the recovery circuit in the data protection/recovery logic array 141 reads the backup data in the nonvolatile memory array 121, and the read data in the nonvolatile memory array 121 is recovered to the dynamic random access memory array 111 through the high-bandwidth cross-component connection (recovery 1) between the data protection/recovery logic array 141 and the nonvolatile memory array 121, and further, the recovery circuit in the data protection/recovery logic array 141 recovers the read data in the nonvolatile memory array 121 to the dynamic random access memory array 111 through the high-bandwidth cross-component connection (recovery 2) between the data protection/recovery logic array 141 and the dynamic random access memory array 111.

In this embodiment, the multilayer integrated circuit capacitor array 131 on the capacitor assembly 13 specifically powers the dynamic random access memory array 111, the protection circuit, the recovery circuit, and the nonvolatile memory array 121. That is, during the protection process, the data link is not passed through the circuit, and the power can be always cut off during the protection process, that is, the power supply of the multilayer integrated circuit capacitor array 131 on the capacitor assembly 13 to the related circuit is not designed; for example, the external interface 113, the circuits in the interconnect of the restore circuit (e.g., buffers, etc.), and the circuits in the interconnect between the dynamic random access memory array 111 and the external interface 113 (e.g., buffers, bus, and portions of MUX, etc.) may not be designed to supply power from the capacitive component 13; meanwhile, the protection process data link does not pass through the I/O interconnection in the prior art, so that all I/O circuits in the protection process can not design power supply from the capacitor assembly 13; that is, only a portion of the core voltage in the power domain (power range) of the multi-layer integrated circuit capacitor array 131 on the capacitor element 13 needs to be maintained, and no I/O voltage is needed for power supply, for example, I/O circuit voltage of the external interface 113 (standard DRAM interface voltage or standard DIMM interface voltage), so that the power supply voltage is greatly reduced, so that the capacitor element 13 does not need to maintain a higher voltage, the power supply time is increased, and the capacitance requirement of the capacitor element 13 is reduced.

It will be appreciated that the dynamic random access memory array 111 and external interface 113 of the present application comprise a prior art DRAM granule 21 (see fig. 8 below).

The self-powered nonvolatile programmable chip 10 provided by the application combines three-dimensional heterogeneous integration, designs the multilayer integrated circuit capacitor array 131 in the three-dimensional heterogeneous integrated self-powered nonvolatile programmable chip 10, so that low-power consumption strategies such as power supply voltage management, circuit power supply range division, component internal power supply voltage reduction, time-sharing power supply combined with protection requirements and the like are designed and realized, the power consumption cost of data protection is greatly reduced, and the integrated self-powered nonvolatile programmable chip 10 is obtained.

In an embodiment, referring to fig. 9 and 10, fig. 9 is a schematic structural diagram of a storage device according to an embodiment of the application; FIG. 10 is a schematic plan view of a memory device according to an embodiment of the application; the present application provides a memory device 100b. The memory device 100b may be a nonvolatile dual inline memory module. In particular, the memory device 100b may include a memory interface 20 and a plurality of self-powered nonvolatile programmable chips 10; wherein, each self-powered nonvolatile programmable chip 10 is connected with the storage interface 20 through the external interface 113; and the self-powered non-volatile programmable chip 10 may be specifically the self-powered non-volatile programmable chip 10 according to any of the above embodiments. The memory interface 20 may be, among other things, a DIMM interface.

After the system enters the protection mode, referring to FIG. 9, the array in storage device 100b may be powered, in particular, through storage interface 20. The storage device 100b is a 3D-SP-NVDRAM granule integrating the dynamic random access memory component 11, the logic component 14, the nonvolatile memory component 12 and the multilayer capacitor component 13, namely a three-dimensional self-powered NVDIMM, and all functions of the NVDIMM are realized inside the granule, so that the storage device 100b not only can realize self-power supply, but also does not need to be externally connected with a super capacitor compared with the prior art; meanwhile, the design of the NVDIMM circuit board is greatly simplified, MVDIMM of double-sided mounting particles are easy to realize, and more particles can be contained on the circuit board to provide larger storage capacity; the self-powered nonvolatile programmable chip 10 of the memory device 100b is formed by three-dimensional heterogeneous integrated bonding, so that two or more layers can be stacked, and more self-powered nonvolatile programmable chips 10 can be arranged in the same area to increase the memory capacity.

Wherein the above-mentioned components may include at least one of a die and a wafer; and in particular embodiments, each component may include a plurality of corresponding arrays, each array may include a plurality of corresponding cells. For example, the dynamic random access memory component 11 may include at least one of a dynamic memory array die and a dynamic memory array wafer; and in particular embodiments, dynamic random access memory component 11 may include a plurality of dynamic random access memory arrays 111, each dynamic random access memory array 111 may include a plurality of dynamic random access memory cells.

Referring to fig. 10, in the memory device 100b provided in this embodiment, a self-powered nonvolatile programmable chip 10 is provided with a dynamic random access memory component 11, and the dynamic random access memory component 11 is integrated with a dynamic random access memory array 111; meanwhile, by arranging the nonvolatile memory component 12 and stacking and bonding the nonvolatile memory component 12 and the dynamic random access memory component 11, the integration and interconnection density of the self-powered nonvolatile programmable chip 10 are improved; meanwhile, the nonvolatile memory component 12 is integrated with the nonvolatile memory array 121, so that backup data corresponding to data in the dynamic random access memory array 111 can be stored through the nonvolatile memory array 121, and the data in the dynamic random access memory array 111 can be protected through the nonvolatile memory array 121 when power is unexpectedly cut off or a system is crashed, so that the problem of data damage in the dynamic random access memory array 111 caused by power cut off is avoided; in addition, by providing the capacitor assembly 13, the capacitor assembly 13 is integrated with the integrated circuit capacitor array 131, so that the power is supplied to the dynamic random access memory array 111 and the nonvolatile memory array 121 through the integrated circuit capacitor array 131 when the system is accidentally powered off.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The foregoing is only the embodiments of the present application, and therefore, the patent scope of the application is not limited thereto, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the application.

Claims

1. A self-powered non-volatile programmable chip, the self-powered non-volatile programmable chip comprising:

the dynamic random access memory assembly is integrated with a dynamic random access memory array;

A nonvolatile memory component integrated with a nonvolatile memory array, the nonvolatile memory array being connected with the dynamic random access memory array,

The capacitor assembly is integrated with an integrated circuit capacitor array, and the integrated circuit capacitor array is connected with the dynamic random memory array and the nonvolatile memory array;

The dynamic random access memory component, the nonvolatile memory component and the capacitor component are arranged in a stacked mode;

And responding to a first preset condition, the integrated circuit capacitor array supplies power for the dynamic random storage array and the nonvolatile storage array, so that data in the dynamic random storage array is stored into the nonvolatile storage array and used as backup data of the dynamic random storage array.

2. The self-powered non-volatile programmable chip of claim 1, wherein the backup data is restored to the dynamic random access memory array in response to a second preset condition.

3. The self-powered, non-volatile programmable chip of claim 2,

The nonvolatile memory component is also integrated with a data protection/recovery logic array, and the data protection/recovery logic array is connected with the dynamic random memory array, the nonvolatile memory array and the integrated circuit capacitor array; the integrated circuit capacitor array supplies power to the data protection/recovery logic array in response to the first preset condition, so that the data protection/recovery logic array stores data in the dynamic random access memory array to the nonvolatile memory array; and responding to the second preset condition, and restoring the backup data in the nonvolatile storage array to the dynamic random storage array by the data protection/restoration logic array.

4. The self-powered, non-volatile programmable chip of claim 2,

The self-powered nonvolatile programmable chip further comprises a logic component, wherein the dynamic random storage component, the nonvolatile storage component, the logic component and the capacitor component are arranged in a stacked mode;

The logic component is integrated with a data protection/recovery logic array, and the data protection/recovery logic array is connected with the integrated circuit capacitor array, the dynamic random access memory array and the nonvolatile memory array; the integrated circuit capacitor array supplies power to the data protection/recovery logic array in response to the first preset condition, so that the data protection/recovery logic array stores data in the dynamic random access memory array to the nonvolatile memory array; and responding to the second preset condition, and restoring the backup data in the nonvolatile storage array to the dynamic random storage array by the data protection/restoration logic array.

5. The self-powered, non-volatile programmable chip of claim 3 or 4, wherein the capacitive component is at least one layer, the integrated circuit capacitive array of the capacitive component is configured as a plurality of power domains, the non-volatile memory array and the data protection/recovery logic array and the dynamic random access memory array form a plurality of power ranges, each of the power ranges being connected to at least one of the plurality of power domains for providing power through the power domain.

6. The self-powered, non-volatile programmable chip of claim 5, wherein each of said power ranges includes at least one of said non-volatile memory array, at least one of said data protection/restoration logic array, and at least one of said dynamic random access memory arrays interconnected.

7. The self-powered, non-volatile programmable chip of claim 5, further comprising a plurality of control switches, each of said control switches being connected to at least one of said plurality of power domains, said control switches being configured to control the powering up or powering down of said power domain to which it is connected.

8. The self-powered, non-volatile programmable chip of claim 7, wherein at least a portion of the data in the dynamic random access memory array is non-sensitive data; the control switch is used for controlling the power domain corresponding to the non-sensitive data to be always powered off.

9. The self-powered, nonvolatile programmable chip as claimed in claim 3 or 4, wherein said data protection/recovery logic array comprises a protection circuit and a recovery circuit;

The protection circuit is used for storing data in the dynamic random storage array to the nonvolatile storage array; the recovery circuit is used for recovering the backup data in the nonvolatile memory array to the dynamic random access memory array; the capacitor assembly is used for supplying power to the dynamic random access memory array, the protection circuit, the recovery circuit and the nonvolatile memory array.

10. The self-powered, non-volatile programmable chip of claim 4, wherein at least a portion of the data protection/restoration logic array of the logic component is comprised of a programmable logic module or an embedded programmable logic module.

11. The self-powered, non-volatile programmable chip of claim 10, wherein a portion of the data protection/restoration logic array of the logic component is comprised of programmable logic modules or embedded programmable logic modules for implementing the variable functions of the logic component; the rest of the logic components the data protection/restoration logic array is formed by an application specific integrated circuit for implementing the fixed functions of the logic components.

12. The self-powered, non-volatile programmable chip of claim 4, wherein the dynamic random access memory component, the non-volatile memory component, and the logic component are further integrated with at least one signal bond area and at least one power bond area; the capacitor assembly is also integrated with at least one power bonding region; the dynamic random access memory assembly, the nonvolatile memory assembly and the logic assembly are bonded through the signal bonding area lamination to realize signal connection among all assemblies, and the dynamic random access memory assembly, the nonvolatile memory assembly, the logic assembly and the capacitor assembly are bonded through the power bonding area lamination to realize power connection among all assemblies.

13. The self-powered, non-volatile programmable chip of claim 12, wherein the power bond regions are located at edge locations of corresponding components, and wherein two of the dynamic random access memory components, the non-volatile memory components, and the logic components, and the capacitive components are disposed adjacent to each other, wherein a perpendicular projection of a power bond region of one component along a stacking direction thereof coincides with a power bond region of the other component.

14. The self-powered, non-volatile programmable chip of claim 4, wherein the dynamic random access memory assembly further comprises an external interface and a multiplexer coupled to at least a portion of the dynamic random access memory array; the multiplexer is connected with the external interface and the data protection/recovery logic array, and the multiplexer selects to connect the dynamic random storage array to the external interface or the data protection/recovery logic array.

15. A memory device, comprising:

A storage interface;

Each self-powered nonvolatile programmable chip is connected with the storage interface through an external interface; wherein the self-powered non-volatile programmable chip is a self-powered non-volatile programmable chip as claimed in any one of claims 1 to 14.