WO2009130629A1 - Transistor à effet de champ à ailette et procédé de fabrication associé - Google Patents

Transistor à effet de champ à ailette et procédé de fabrication associé Download PDF

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Publication number
WO2009130629A1
WO2009130629A1 PCT/IB2009/051413 IB2009051413W WO2009130629A1 WO 2009130629 A1 WO2009130629 A1 WO 2009130629A1 IB 2009051413 W IB2009051413 W IB 2009051413W WO 2009130629 A1 WO2009130629 A1 WO 2009130629A1
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WO
WIPO (PCT)
Prior art keywords
fin
spacer
control gate
gate
alignment direction
Prior art date
Application number
PCT/IB2009/051413
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English (en)
Inventor
Bartlomiej Pawlak
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2009130629A1 publication Critical patent/WO2009130629A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the invention relates to a fin FET.
  • the invention relates to a method of manufacturing a fin FET.
  • An illustrated method comprises forming a first insulating layer on a semiconductor substrate, forming a first conductive layer for a fin on the first insulating layer, etching the first conductive layer so that an area of a lower part of the first conductive layer is wider than an area of an upper part of the first conductive layer, forming voltage adjust regions through an ion implantation method, forming a gate insulating layer through a forming gas annealing method, forming a second conductive layer, forming LDD regions by implanting ions into the first conductive layer, forming sidewall spacers adjacent the gate insulating layer, and forming source/drain regions adjacent to the sidewall spacers by implanting ions into the first conductive layer.
  • a fin field effect transistor, and a method of manufacturing a fin field effect transistor according to the independent claims are provided.
  • a fin field effect transistor comprising a substrate (for instance a semiconductor substrate such as a silicon substrate covered by an insulating layer or a substrate on the basis of an SOI substrate), a fin (such as a semiconductor fin) formed on the substrate along a fin alignment direction (for instance extending along a linear direction), a control gate (for instance an electrically conductive member such as a polycrystalline line) formed partially over the fin (for instance separated from the fin by a thin gate insulating layer) and partially on the substrate along a gate alignment direction (for instance extending along a linear direction) which differs from the fin alignment direction (particularly, the both directions may be orthogonal to one another and may be both located essentially within a surface plane of the substrate), and a spacer (for instance made of an electrically insulating material) of a uniform (for instance constant or at least essentially constant) thickness covering a vertical (particularly with respect to a main surface of the substrate) sidewall of the control gate adjacent
  • a substrate for instance a semiconductor substrate such as a silicon substrate
  • a method of manufacturing a fin field effect transistor comprising forming a fin on a substrate along a fin alignment direction, forming a control gate partially over the fin and partially on the substrate along a gate alignment direction which differs from the fin alignment direction, and forming a spacer of a uniform thickness covering a vertical sidewall of the control gate adjacent the fin.
  • fin field effect transistor may denote a field effect transistor in which the conducting channel is wrapped around a thin semiconductor (for instance silicon) "fin", which forms the body of the device.
  • the dimensions of the fin determine the effective channel length of the device.
  • a fin FET may be any fin-based, multigate transistor architecture regardless of number of gates.
  • substrate may denote any suitable material, such as a semiconductor, glass, plastic, etc. According to an exemplary embodiment, the term “substrate” may be used to define generally the elements for layers that underlie and/or overlie a layer or portions of interest. Also, the substrate may be any other base on which a layer is formed, for example a semiconductor wafer such as a silicon wafer or silicon chip.
  • fin alignment direction may denote a straight line in a main surface of the substrate, i.e. in a plane which is formed by the surface of the substrate on which the FET components are subsequently formed. Along this straight line, a linearly extending fin may be formed. In other words, the fin alignment direction may be the direction of the three orthogonal space directions in which the fin has the largest extension.
  • the "gate alignment direction” may be a basically straight direction basically in the surface plane of the main surface of the substrate along which the gate extends, wherein the gate alignment direction is interrupted in a bridge portion at which the gate traverses the fin (or, in a transistor array, traverses a plurality of for instance parallel aligned fins).
  • the gate alignment direction may be the direction of the three orthogonal space directions in which the gate has the largest extension.
  • source/drain region may particularly denote a source region or a drain region. Since the functionality of a source region and a drain region may depend on the operation mode of a transistor, for instance voltages applied thereto, the term source/drain region may denote a structure which can act as a source region or as a drain region.
  • a fin FET may be provided which has a spacer of a constant thickness provided (for instance exclusively) on two opposing sidewalls of a control gate between which spacers a portion of the fin forms a channel region.
  • Such uniformly thick spacers define a constant and reproducible distance between the control gate and source/drain regions implanted in surface portions of the fin which may be located directly next to the spacer.
  • Such spacers may be formed prior to the source/drain implantation by depositing a uniformly thick dielectric layer and selectively removing all portions thereof which do not cover the vertical sidewalls of the control gate which vertical sidewalls have a perpendicular which is parallel to an alignment of the fin.
  • This selective removal procedure for spacer definition may be achieved by directing a damaging agent in an inclined manner on the layer sequence.
  • a damaging agent may be selected to specifically weaken all portions of the conformal dielectric layer with the exception of the portions at the vertical sidewalls of the control gate facing the fin, by shielding only these sidewall portions from the damaging agent. Subsequently, the mechanically weakened portions of this conformal layer which are brought in interaction with the damaging agent can be removed by an etching procedure or similar.
  • Transistors according to exemplary embodiments may have advantageous properties regarding leakage characteristic and may allow for a proper short channel control.
  • Formation of well defined, reproducible, narrow spacers (sub-10nm) positioned next the gate is a technology challenge, of particularly essential importance to form source and drain regions with improved short channel control properties.
  • offset spacer formation may be achieved by silicon oxide liner deposition and a damaging implant followed by a wet etching. Formation of fin FET extensions is one of the main challenges of manufacturing a transistor device. Devices targeting low leakage characteristics for mobile applications require additional optimization.
  • GDL Gate Induced Drain Leakage
  • a fin FET device having symmetric sidewall spacers or symmetric source/drain extensions. Fabricating symmetric source/drain regions using a symmetric sidewall structure can be performed by selective etching off an ion implanted liner layer overlying a gate. Fin FET doping for source and drain regions is a challenge.
  • it may be made possible to form extensions in a multi-gate, vertical device in which leakage currents degrading device performance are efficiently suppressed.
  • a main leakage component is related to gate induced drain lowering. Simulations performed by the present inventor suggest that by using a uniformly thick offset spacer before extension implant it may be possible to significantly reduce the leakage. Leakage current will drop at least by one order of magnitude when introducing narrow offset spacers, before an extension is implanted.
  • a zero degrees twist and a non-zero degrees tilt of the damaging implantation may be set in order to obtain a shadowing effect of a specific vertical part of the gate.
  • the spacers may have a rectangular shape and not a quarter of a circle shape being characteristic for conventional spacers.
  • the rectangular shape may result because the implant and etch may remove all the horizontal layers and may leave only specific ones of the vertical layers.
  • the damaging implant (for defining the gate offset spacer) may be supplied from two sides having non-zero tilt but zero twist (compare Fig. 1).
  • the fin field effect transistor may comprise a source/drain region implanted in an exposed portion of the fin, which exposed portion of the fin is not covered by the spacer; the source/drain region being spaced with regard to the control gate by the spacer. More precisely, a first source/drain region (such as a source region) may be formed in a first exposed portion (i.e. not covered with the spacer) of the fin arranged next to the gate. Accordingly, a second source/drain region (such as a drain region) may be formed in a second exposed portion (i.e.
  • the spacer After formation of the spacer, it is possible to perform the actual source/drain implementation, i.e. implanting p- or n-type dopants in the exposed portions of the fin FET, so that the source region and the drain region may be spaced with regard to the control gate by a distance which depends on the thickness of the spacer. This may allow for a reliable and precise adjustment of the transistor properties and at the same time may prevent leakage effects.
  • the gate alignment direction may be perpendicular to the fin alignment direction.
  • a perpendicular arrangement may allow to manufacture a for instance a matrix-like array of field effect transistors in a space-saving manner which may be used for memory and/or logic purposes, or similar.
  • a control gate may be provided in common for a row or column of the fins.
  • the gate alignment direction and the fin alignment direction enclose an angle which differs from 90°, for instance are arranged in an inclined manner relative to one another enclosing an acute angle.
  • the control gate may form a bridge structure guided over the fin.
  • a gate insulating layer such as a thin silicon oxide layer between the fin and the control gate
  • the field effect of the fin FET transistor may be ensured with a large interaction area between control gate and fin.
  • the (multi) gate may be aligned along three quarters of the surrounding surfaces of the fin, thereby allowing a precise adjustment of the electrical conductivity properties of the fin field effect transistor by applying an electric voltage to the control gate.
  • a storage region such as a floating gate or an ONO structure (silicon oxide-silicon nitride-silicon oxide) may be formed between control gate and fin.
  • the spacer (or more precisely a part of the spacer surrounding the fin) may be U-shaped when viewed from the fin alignment direction (see three-dimensional view of Fig. 3).
  • the fin may be guided through the open portion of the U.
  • the round portions of the U may be angled, for instance may form two right angles.
  • the spacer When viewed from the gate alignment direction (see cross-sectional view of Fig. 3), the spacer may be rectangularly shaped.
  • the rectangular shape of the spacer may result from the constant thickness of the spacer on the sidewall of the control gate.
  • a horizontal surface of the control gate i.e. a surface of the control gate parallel to a main surface of the substrate
  • a horizontal surface of the fin i.e. a surface of the fin parallel to a main surface of the substrate
  • a horizontal surface of the substrate i.e. a surface of the substrate being free of fin and gate
  • Such an architecture may result from a selective removal procedure of portions of a conformally deposited layer deposited over the corresponding layer sequence and removed by the inclined introduction of a damaging agent selectively in specific portions of the conformal layer.
  • a damaging agent selectively in specific portions of the conformal layer.
  • the spacer may have a uniform thickness of less than about 20 nm, particularly of less than about 10 nm, more particularly of less than about 5 nm.
  • the spacer may be formed by forming a conformal layer on the control gate, on the fin and on exposed surface portions of the substrate, and by selectively removing portions of the conformal layer from horizontal surface portions of the control gate and the fin.
  • a conformal layer may be a layer which has an essential constant thickness over the entire (for instance upper) layer surface of the layer sequence.
  • an adjustment of the angular direction under which the damaging implant ions/atoms are directed onto the layer sequence may allow to define which vertical sidewall portions of the gate will be influenced by the damaging implant ions/atoms and which vertical sidewall portions of the gate will be protected against the damaging implant ions/atoms.
  • the conformal layer may be formed by a deposition procedure.
  • a CVD procedure chemical vapour deposition
  • ALD procedure atomic layer deposition
  • the thickness of the conformal layer may be defined with an accuracy in the order of magnitude of an atomic layer thickness (i.e. with an accuracy of a few Angstrom). This may allow to properly improve the leakage properties of the fin FET transistor, define the channel length, etc.
  • the portions of the conformal layer to be removed may be selectively defined by adjusting geometrical parameters of an implanting procedure of implanting a damaging agent into the portions for damaging the portions and by selectively removing the damaged portions.
  • a damaging agent may be any material which is introduced into a wall of the conformal layer and which does not have doping properties (group III or group V materials may have doping properties).
  • a non-doping species such as Ar, Ge or Si may be implemented with a sufficiently high energy into portions of the conformally deposited layer so that the implantation of such molecules has the only effect of destroying the mechanical surface stability of the conformal layer.
  • the weakened portions When being mechanically degraded by the implantation of the non-doping material, the weakened portions may be removed from the layer sequence by an etching procedure, particularly a wet etching procedure, whereas portions of the wall being free of the damaging agent may withstand may better such a doping procedure.
  • the selective mechanical weakening effect of the damaging agent may be precisely defined in a spatial manner by supplying the damaging agent at an incident angle which is inclined with respect to a perpendicular of a main surface of the substrate and which incident angle is at the same time parallel to the vertical sidewall of the control gate which is not to be removed.
  • the damaging agent may be supplied under a fixed incident angle in a range of [10°;45°]. It is also possible that the damaging agent is supplied over a defined angular range of, for instance, [-45°; +45°].
  • non-zero tilt architecture damaging ions may be implemented in a direction parallel to the sidewalls of the gate structure spacing the source/drain regions.
  • a non-zero tilt removes a liner not only from horizontal portions of the layer sequence, but - due to the inclination - also from side walls of the fin and from a part of the sidewalls of the gate. In contrast to this, due to the zero twist, no removal of material from vertical sidewalls of the gate structure facing the fin takes place.
  • the method may comprise implanting the damaging agent by supplying the damaging agent at an incident angle in a manner that the source-drain-distance-defining vertical sidewalls of the control gate are shielded against the damaging agent.
  • the topography of the system may be advantageously used.
  • a shadowing effect by the topographic layer sequence formed by the fin and the control gate may be advantageously used.
  • a vertical surface portion which is in the shadow of the stack with regard to a specific direction of the damaging agent implantation may protect specific surface structures from being mechanically weakened by the damaging agent. It is also possible that specific obstacles are intentionally formed in a layer sequence to serve as specific shadowing members.
  • the damaged portions may be removed by etching, particularly by wet etching. It may be particularly advantageous that a mechanically weakened conformal layer being treated with a damaging agent can be removed selectively by a wet etching procedure. For such a wet etching procedure, such a weakened conformal layer may be much more prone to be removed than a portion of the conformal layer which does not comprise the damaging agent.
  • the method may further comprise implanting a dopant into an exposed portion of the fin which is not covered by the spacer to thereby form a source/drain region being spaced with regard to the control gate by the spacer. More particularly, it is possible to form two source/drain regions on opposing surface portions of the fin between which the control gate is arranged.
  • a p-type dopant such as a semiconductor of the III group (for example boron) may be used, or an n-type dopant such as a semiconductor of the V group (for example arsenide).
  • the gate structure may be manufactured from a metallic material. However, also the usage of poly crystalline silicon material as a gate material is possible.
  • the fin may be manufactured from a semiconductor material such as silicon. The method may be carried out in CMOS technology, since the described procedures are compatible with CMOS technology.
  • Forming layers or components may include deposition techniques like CVD (chemical vapour deposition), PECVD (plasma enhanced chemical vapour deposition), ALD (atomic layer deposition), or sputtering.
  • Removing layers or components may include etching techniques like wet etching, vapour etching, etc., as well as patterning techniques like optical lithography, UV lithography, electron beam lithography, etc.
  • Embodiments of the invention are not bound to specific materials, so that many different materials may be used.
  • conductive structures it may be possible to use metallization structures, suicide structures or polysilicon structures.
  • semiconductor regions or components crystalline silicon may be used.
  • insulating portions silicon oxide or silicon nitride may be used.
  • the structure may be formed on a purely crystalline silicon wafer or on an SOI wafer (Silicon On Insulator).
  • CMOS complementary metal-oxide-semiconductor
  • BIPOLAR BIPOLAR
  • BICMOS BICMOS
  • Fig. 1 shows a fin FET according to an exemplary embodiment of the invention during manufacture illustrating a damage implant or a dopant implant.
  • Fig. 2 illustrates a diagram showing that the leakage current may drop significantly when introducing narrow offset spacers.
  • Fig. 3 shows a three-dimensional view and a cross-sectional view of a fin FET transistor according to an exemplary embodiment of the invention.
  • Fig. 4 to Fig. 8 illustrate plan views (left-hand side) and three-dimensional views (right-hand side) of layer sequences obtained during a method of manufacturing a fin field effect transistor according to an exemplary embodiment of the invention.
  • Fig. 1 shows a layer sequence comprising a silicon fin 102 which is formed on a substrate (not shown) to extend along a fin alignment direction x.
  • a control gate 104 is formed, wherein a (not shown) gate insulating layer may be provided between the fin 102 and the control gate 104 at least in a contact portion therebetween.
  • the control gate 104 is aligned along a gate alignment direction y being perpendicular to the fin alignment direction. Both the gate alignment direction and the fin alignment direction are within a plane corresponding to a main surface of the substrate (not shown) on which main surface the layer sequence is formed.
  • a damaging implant procedure may be used according to an exemplary embodiment of the invention.
  • a damaging agent or implant agent schematically shown with reference numeral 106, is directed onto the layer sequence 100 in an inclined manner to selectively remove portions of the conformal electrically insulating layer.
  • the impingement direction 106 may be tilted by an angle ⁇ O with regard to the z axis with in the yz plane.
  • the impingement direction 106 may also be twisted by an angle ⁇ by a twisting operation in the xy plane.
  • ⁇ O non-zero tilt
  • Fig. 2 shows a diagram 200 having an abscissa 202 along which a gate-source voltage is plotted in V. Along an ordinate 204, a leakage current is plotted in A/ ⁇ m.
  • a first curve 206 relates to a spacer thickness of 0, a second curve 208 relates to a spacer thickness of 5nm and a third curve 210 relates to a spacer thickness of lOnm.
  • the leakage current 204 will drop at least one order of magnitude when introducing narrow offset spacers, before an extension is implanted.
  • a fin field effect transistor 300 according to an exemplary embodiment of the invention will be explained. On the left-hand side of Fig. 3, the fin FET 300 is shown in a three-dimensional view, whereas on the right-hand side of Fig. 3, the fin FET 300 is shown in a cross-sectional view.
  • the fin FET 300 comprises a silicon substrate 302.
  • the substrate 302 comprises a silicon base and a silicon oxide layer provided on top thereof.
  • a fin 304 is formed on the substrate 302 along a fin alignment direction 306.
  • the fin 304 may be formed by a lithography procedure from the upper silicon layer of the SOI substrate.
  • a control gate 308 may be formed from a metallic material or from a polysilicon material partially over the fin 304 and partially on the substrate 302 essentially along a gate alignment direction 310 which is perpendicular to the fin alignment direction 306.
  • a spacer 312 of a uniform thickness d covers two vertical sidewall portions of the control gate 308 adjacent to the fin 304.
  • the structure is symmetrical with regard to a centre of gravity of the control gate 308, so that both vertical sidewalls of the control gate 308 are covered with a silicon oxide spacer 312 of a constant thickness d.
  • the fin FET 300 further comprises a source region 314 and a drain region 314 on opposing sides of the control gate 308 and spaced with regard to the control gate 308 by the uniform spacers 312.
  • Optional contact pads 322 for contacting the source/drain regions 314 are shown as well.
  • the control gate 308 forms a bridge structure guided over the fin 304.
  • the spacer 312 portion next to the fin 304 is essentially U-shaped (more precisely upside-down U-shaped) or horseshoe- shaped.
  • the spacer 312 is rectangularly shaped when viewed from the gate alignment direction 310. This is a consequence of the constant thickness d of the spacers 312.
  • a horizontal surface of the control gate 308, a horizontal surface of the fin 304 and a horizontal surface of the substrate 302 are not covered by the spacer 312. This is of particularly advantage when the exposed portions of the fin 304 shall be implanted with a dopant to form the source/drain regions 314.
  • a method of manufacturing a fin FET according to an exemplary embodiment of the invention will be explained.
  • a plan view is shown on a left-hand side, and a three-dimensional view is shown on a right-hand side.
  • a fin 304 may be formed on a substrate (not shown) along a fin alignment direction which is perpendicular to the paper plane of the drawing on the left-hand side of Fig. 4.
  • a control gate 308 is formed partially over the fin 304 and partially (not shown) on the substrate along a gate alignment direction (horizontally in the right-hand side image of Fig. 4) which is perpendicular to the fin alignment direction.
  • the fin 304 is formed to be surrounded by the gate 308, wherein a gate insulating layer 402 may be formed between the fin 304 and the control gate 308.
  • a vertical sidewall of the control gate 308 facing the fin 304 is denoted with reference numeral 404.
  • a silicon oxide liner 502 is deposited conformally on the entire surface of the layer sequence 400.
  • the layer sequence 500 shown in Fig. 5 it may be desired to remove the major portion of the silicon oxide liner 502 with the exception of a portion on the vertical sidewalls 404 of the control gate 308 adjacent the fin 304, since the maintenance of the silicon oxide liner 502 exclusively on the vertical sidewalls 404 of the control gate 308 adjacent the fin 304 may allow to manufacture source/drain regions in the fin 304 which are spaced with regard to the gate 308 in the fin alignment direction using the liner as a doping prevention mask.
  • a damaging implant procedure is performed, as can be taken from Fig. 6.
  • a non-doping damaging agent 602 for instance silicon or germanium atoms/ions may be directed in an inclined manner onto all surface portions of the silicon oxide liner 502, with the exception of such surface portions of the silicon liner 502 which cover vertical sidewalls 404 of the control gate 308 facing the fin 304. Referring to the plan view of Fig. 6, this may be achieved by directing the non-doping damaging agent 602 onto the layer sequence under a non-zero tilting angle with respect to a perpendicular of the substrate but within the paper plane of Fig. 6, left hand side, i.e. without twisting. All portions of the silicon oxide liner 502 which are hit by the damage implant 602 are mechanically weakened.
  • the offset spacer 312 is formed which intentionally spaces the exposed portion of the fin FET 304 with regard to the control gate 308.
  • a doping procedure may be performed for implanting dopant of the p-type or n-type into exposed portions of the fin 304, thereby forming source/drain regions 314.
  • the dopant 802 is directed for instance in an inclined manner onto the exposed portions of the fin FET, wherein the offset spacer 312 prevents the covered portion of the fin 304 from being implanted.
  • Silicon oxide liner deposition for instance about 5nm to 10 nm around the fin.
  • thin silicon oxide growth around the Si fin with a thickness around between 1 nm and 2 nm.
  • Implantation of a non-doping species like Ar, Ge, Si or any other similar material.
  • the implant elements which can be used may come from the noble element column as well, not limited to Ar.
  • Typical implant conditions may be Ge, 45° tilt, 2 keV energy, 5E14 concentration. This implant is done to create damage on the silicon oxide liner on the top and side wall of the Si fin. Due to the geometrical situation, the side wall of the spacer around the gate is not implanted and therefore clean from damage.
  • Extension implant follows after etch.
  • a B, As or P implant may be used to dope the fin, for instance with the following typical conditions, energies: 0.5 to

Abstract

La présente invention a trait à un transistor à effet de champ à ailette (300). Le transistor à effet de champ à ailette  (300) comprend un substrat (302), une ailette (304) formée sur le substrat (302) dans une direction d’alignement d’ailette (306), une grille de commande (308) formée partiellement au-dessus de l’ailette (304) et partiellement sur le substrat (302) dans une direction d’alignement de grille (310) qui est différente de la direction d’alignement d’ailette (306), et une cale d’espacement (312) d’une épaisseur uniforme recouvrant une paroi latérale verticale de la grille de commande (308) adjacente à l’ailette (304).
PCT/IB2009/051413 2008-04-23 2009-04-03 Transistor à effet de champ à ailette et procédé de fabrication associé WO2009130629A1 (fr)

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Application Number Priority Date Filing Date Title
EP08103681 2008-04-23
EP08103681.6 2008-04-23

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570843B (zh) * 2011-10-18 2017-02-11 英特爾公司 利用非平面佈局的抗熔絲元件

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121138A (en) * 1998-04-28 2000-09-19 Advanced Micro Devices, Inc. Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging
US20040014305A1 (en) * 2002-07-18 2004-01-22 Haselden Barbara A. Two stage etching of silicon nitride to form a nitride spacer
WO2005010994A1 (fr) * 2003-06-27 2005-02-03 Intel Corporation Dispositif a semi-conducteur non planar comportant une electrode de grille enveloppee partiellement ou entierement, et procedes de production
US6969659B1 (en) * 2004-08-12 2005-11-29 International Business Machines Corporation FinFETs (Fin Field Effect Transistors)
US20060154423A1 (en) * 2002-12-19 2006-07-13 Fried David M Methods of forming structure and spacer and related finfet
US20060194381A1 (en) * 2005-02-28 2006-08-31 Andy Wei Gate structure and a transistor having asymmetric spacer elements and methods of forming the same
US20070029624A1 (en) * 2005-08-03 2007-02-08 International Business Machines Corporation Fin-type field effect transistor
WO2008106574A2 (fr) * 2007-02-28 2008-09-04 International Business Machines Corporation Formation d'espaceurs pour transistors à effet de champ (finfet)

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121138A (en) * 1998-04-28 2000-09-19 Advanced Micro Devices, Inc. Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging
US20040014305A1 (en) * 2002-07-18 2004-01-22 Haselden Barbara A. Two stage etching of silicon nitride to form a nitride spacer
US20060154423A1 (en) * 2002-12-19 2006-07-13 Fried David M Methods of forming structure and spacer and related finfet
WO2005010994A1 (fr) * 2003-06-27 2005-02-03 Intel Corporation Dispositif a semi-conducteur non planar comportant une electrode de grille enveloppee partiellement ou entierement, et procedes de production
US6969659B1 (en) * 2004-08-12 2005-11-29 International Business Machines Corporation FinFETs (Fin Field Effect Transistors)
US20060194381A1 (en) * 2005-02-28 2006-08-31 Andy Wei Gate structure and a transistor having asymmetric spacer elements and methods of forming the same
US20070029624A1 (en) * 2005-08-03 2007-02-08 International Business Machines Corporation Fin-type field effect transistor
WO2008106574A2 (fr) * 2007-02-28 2008-09-04 International Business Machines Corporation Formation d'espaceurs pour transistors à effet de champ (finfet)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570843B (zh) * 2011-10-18 2017-02-11 英特爾公司 利用非平面佈局的抗熔絲元件
US9748252B2 (en) 2011-10-18 2017-08-29 Intel Corporation Antifuse element utilizing non-planar topology

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