WO2009113961A1 - Procédé de réduction d'une perte de couplage optique dans un empilement diélectrique - Google Patents

Procédé de réduction d'une perte de couplage optique dans un empilement diélectrique Download PDF

Info

Publication number
WO2009113961A1
WO2009113961A1 PCT/SG2008/000077 SG2008000077W WO2009113961A1 WO 2009113961 A1 WO2009113961 A1 WO 2009113961A1 SG 2008000077 W SG2008000077 W SG 2008000077W WO 2009113961 A1 WO2009113961 A1 WO 2009113961A1
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric stack
dielectric
stack
etch stop
layers
Prior art date
Application number
PCT/SG2008/000077
Other languages
English (en)
Inventor
Rakesh Kumar
Balakumer Subramaniam
Nagarajan Ranganathan
Hong Yu Li
Original Assignee
Agency For Science, Technology And Research
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency For Science, Technology And Research filed Critical Agency For Science, Technology And Research
Priority to PCT/SG2008/000077 priority Critical patent/WO2009113961A1/fr
Publication of WO2009113961A1 publication Critical patent/WO2009113961A1/fr

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12004—Combinations of two or more optical elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Definitions

  • the present invention related broadly to a method for reducing optical coupling loss in a dielectric stack, to a dielectric stack, and to an optical device comprising a dielectric stack.
  • CMOS-based fabrication processes that are used to form electronic devices can be used to form both passive and active silicon-based optical devices, where in many cases a passive optical waveguide can be formed within the same integrated structure as an optical/electrical circuit.
  • the devices that ' perform the pure optical functions, the pure electrical functions and the opto-electronic functions can be produced concurrently, on the same substrate, and using one integrated process flow.
  • CMOS complementary metal-oxide-semiconductor
  • inter-metal dielectric silicon oxide, silicon nitride, silicon carbide and organic or inorganic low- dielectric constant materials layers are used as inter-metal dielectric, copper diffusion barrier and etch-stop layers for performing Cu-damascene process.
  • This multilevel dielectric stack is known to cause dispersion of the optical signal while coupling light from e.g. an optical fiber to on-chip nano-tapered waveguides.
  • the deep trenches for isolation of photons and electrons reaching the active area have a fill material with high extinction coefficient, an optionally a side wall liner with a light absorbent property.
  • a light interceptor slab is provided between adjacent waveguides to hinder the transfer of photons between the first and second waveguides through the inter-waveguides slab portion.
  • the light interceptor region may include a trench region, which is an air gap in one of the embodiments.
  • a method for reducing optical coupling loss in a dielectric stack comprising the steps of removing at least a portion of the dielectric stack associated with one or more metal layers of the dielectric stack in a region where optical losses are to be eliminated; and replacing said portion with a homogenous dielectric material. Said portion may be removed during built-up of the dielectric stack after said one or more associated metal layers have been formed, prior to further built up of the dielectric stack.
  • Said region may extend vertically across the entire dielectric stack.
  • the method may comprise the steps of etching a trench in the dielectric stack corresponding to said region; filling the trench with the homogenous dielectric material; and planarizing the homogenous dielectric material.
  • the planarizing may comprise using a passivation layer of the dielectric stack as a stop layer.
  • the dielectric stack may comprise alternating etch stop or barrier layers and low-k dielectric layers associated with the respective metal layers, and the homogenous dielectric material comprises a low-k organic or inorganic material.
  • the etch stop or barrier layers may comprise one or more of a group consisting of silicon nitride (SiN), silicon carbide (SiC), and silicon carbide nitride (SiCN).
  • the low-k organic or inorganic material may have a dielectric constant in the range of about 1.5 to 3.5 and may comprise one or more of a group consisting of flurorine doped silicon oxides, carbon doped silicon oxides, porous fluorine and carbon doped oxides, deposited using one or more of group consisting of chemical vapour deposition processes, and organic polymer dielectrics deposited using spin- on or spray deposition methods.
  • the method may further comprise removing at least a portion of an etch stop layer associated with a first metal interconnection of the dielectric stack in the region where optical losses are to be eliminated.
  • the removal of the etch stop layer may be performed prior to further built up of the dielectric stack.
  • the method may further comprise using a selective dielectric etch process during a first metal interconnection formation, such that no etch stop layer is required in the first metal interconnection formation.
  • the dielectric stack may comprise a Cu-BEOL stack.
  • a dielectric stack comprising a homogenous dielectric material as a replacement of at least a portion of the dielectric stack associated with one or more metal layers of the dielectric stack in a region where optical losses are to be eliminated
  • Said region may not extend across the entire dielectric stack.
  • Said region may extend vertically across the entire dielectric stack.
  • the dielectric stack may comprise alternating etch stop or barrier layers and low-k dielectric* layers associated with the respective metal layers, and the homogenous dielectric material comprises a low-k organic or inorganic material.
  • the etch stop or barrier layers may comprise one or more of a group consisting of SiN, SiC, and SiCN.
  • the low-k organic or inorganic material may have a dielectric constant in the range of about 1.5 to 3.5 and may comprise one or more of a group consisting flurorine doped silicon oxides, carbon doped silicon oxides, porous fluorine and carbon doped oxides deposited using one or more of a group consisting of chemical vapour deposition processes or organic polymer dielectrics deposited using spin-on or spray deposition methods.
  • the dielectric stack may further comprise a non-continuous etch stop layer associated with a first metal interconnection of the dielectric stack, with at least portions of the etch stop layer removed in the region where optical losses are to be eliminated.
  • the dielectric stack may further Be characterised in that no etch stop layer is present in a first metal interconnection of the dielectric stack.
  • the dielectric stack may comprise a Cu-BEOL stack.
  • an optical device comprising a dielectric stack as defined in the second aspect.
  • Figure 1 shows a schematic cross-sectional drawing illustrating a conventional approach for contact etching to polysilicon or silicon in a first metal interconnection, wherein an etch-stop layer is used to facilitate the contact etch.
  • Figures 2 to 7 show schematic cross-sectional drawings of a Cu-BEOL dielectric stack illustrating the process according to an example embodiment.
  • Figures 8a and b show a plan and cross-sectional views respectively of the dielectric stack after performing the processing steps of figures 2 to 7 according to an example embodiment.
  • Figures 9a and b show a plan and cross-sectional views respectively of a dielectric stack according to another embodiment.
  • Figure 10 shows a schematic cross-sectional drawing illustrating another embodiment wherein the contact etching process does not require any etch stop layers.
  • Figure 11 shows a flowchart illustrating a method for reducing coupling loss in a Cu-BEOL (Back-end of the line) dielectric stack according to an example embodiment.
  • the example embodiments described provide a CMOS compatible process technology that eliminates the optical loss of light during coupling between e.g. an external optical fiber and an on-chip waveguide which could be a uniform, nanotaper or horn type wave guide.
  • the embodiments use formation of deep dielectric trenches and filling the trenches with the a dielectric material which facilitate a formation of a uniform optical cladding layer around the waveguide to eliminate the optical coupling losses due to multilevel dielectric films stacked in a CMOS back-end integration process.
  • the conventional inter-metal dielectric stacks are typically made of alternate layers of plasma deposited silicon oxide and silicon nitride or silicon carbide or silicon carbide nitride.
  • the proposed optical loss elimination embodiments can be readily integrated into standard Cu-BEOL process technology, thus providing an enabling technology that facilitates integration of optical interconnects into a CMOS technology platform.
  • Figure 1 shows a conventional approach for a first metal interconnection to make contact to polysilicon 100 or silicon 102.
  • contact openings 104, 106 are etched to land selectively on silicon 102 and polysilicon 100. This is facilitated by deposition of an etch-stop layer 108 of about 100-500A of SiON or SiN prior to the deposition of inter-metal dielectric 110.
  • the stop layer 108 allows the dielectric etch process to take place without over-etching the respective silicon 102 or polysilicon 100 under-layers.
  • the silicon 102 to which contact is made is in the form of silicon on insulator (SOI), with a burried oxide 112 of a thickness of about 10,000 to 50.000A.
  • SOI silicon on insulator
  • This SOI layer 102 is patterned and a high density plasma (HDP) undoped silicon oxide deposition is used to fill the trenches formed after the patterning. This is followed by chemical mechanical planarization to form a burried silicon oxide layer 103 in the patterned SOI layer 102. This process is known as shallow trench isolation (STI).
  • a gate oxide (GOX) 114 with a thickness of about 10 to 1O ⁇ A is grown or deposited (in case of high dielectric constant gate oxide) on the planarized surface.
  • an etch stop layer 200 for contact etching is removed selectively from the optical areas e.g. 202, 204 and 206.
  • the etch stop layer 200 is removed by masking and etching of an originally deposited continuous etch-stop layer (not shown) to eliminate the optical loss due to the presence of such a continuous etch stop layer, e.g. made from SiN or SiON or a combination of these layers.
  • Figure 10 shows another embodiment wherein the contact etching process does not require any etch stop layers.
  • a selective dielectric etch process is used that selectively stops on silicon 1000 and polysilicon 1002 contact areas. This can eliminate the need for any etch-stop layers that contribute to the optical loss in the optical areas (compare e.g. 202, 204, and 206 in Figure 2). This can be accomplished by e.g. use of a suitable dry etching or wet etching or a combination of both processes and to stop the etch process without overetching of the polysilicon or silicon layers. This means that loss of ploysilicon or silicon during the etch process will be insignificant as compared to loss of dielectric layers that are etched to open the contact window.
  • etch stop layer An example of such a process which does not require an etch stop layer is to first use a flurorine based plasma chemistry to dry etch the dielectric to partially form a part of the contact. This is followed by a wet etching with chemicals such as dilute hydrofluoric acid (HF). HF selectively etches silicon oxide at much higher rate as compared to silicon to complete the formation of the contact without any loss of polysilicon or silicon in the contact area.
  • HF dilute hydrofluoric acid
  • a metal suicide or polycide layer is typically formed in the contact area for reduction of contact resistance to silicon and polysilicon respectively through a series of lithography, etch, deposition and annealing processes.
  • transition metals such as titanium, nickel, cobalt, platinum or tungston are used for formation of suicide or polycide.
  • the silicide/polycide layers are not shown in the example embodiments as described in Figures 1-10.
  • a Cu-BEOL multilevel dielectric stack 300 fabricated using standard Cu-BEOL technology is formed above the first metal interconnection (compare Figure 2).
  • the etch stop layer layer 200 of Figure 2
  • Figure 3 only depicts 4 layers of copper metallization as an illustration, it will be appreciated that the actual number of metal layers may differ in different embodiments depending on technology requirements.
  • the Cu-BEOL multilevel dielectric stack 300 is subjected to an etching step for forming etch trenches 302, 304 in critical regions e.g. 303, 305 where optical losses are to be eliminated.
  • the etching process is performed after the final nitride passivation layer 306 has been deposited.
  • the correct etch depth is maintained in the example embodiment by estimating the correct etching time based on the dielectric etching rate or by using an end-point detection system which triggers the end of the dielectric etching process. Once the etching is completed, the depth can be confirmed by inspection and measurement of depth by using scanning electron microscope, spectroscopy ellipsometry or using a depth profiler.
  • the stack 300 comprises SiN/SiC/SiCN etch stop or barrier layers 312 to 318 with a thickness of about 50 to 800A, and silicon oxide or low-k (low dielectric constant) dielectric layers 321 to 328 with a thickness of about 1 ,000 to 10,000A.
  • the stack 300 further comprises SiN passivation layers 330, 306 with a thickness of about 1 ,000 to 10,000A, copper layers e.g. 332, 334 for electrical contact, where the metallic barrier (Ta/TaN) is not shown in this schematic drawing, and W-pIug or Al filled etch contacts 336, 338.
  • the overall structure in the example embodiment comprises an optical sub assembly consisting of, inter alia, a poly silicon grating 338, active/passive photonics components such as modulators, detectors, light emitters, splitters, resonators, waveguides, couplers etc, schematically indicated at 340 (polysilicon), 342 GOX (gate oxide), and 344 (SOI with thickness of about 500 to 10.000A).
  • the etch trenches 302, 304 in the example embodiment are formed above the poly silicon grating 338 and above a SOI nanotaper 346.
  • the etch trenches 302, 304 are filled with high density plasma (HDP) deposited undoped silicon oxide 400 in the example embodiment.
  • HDP high density plasma
  • the HDP silicon oxide 400 is deposited over the entire dielectric stack 300, resulting in surplus deposits of HDP silicon oxide layer 404 in areas adjacent to the etch trenches 302, 304.
  • a reverse dielectric mask/etch and a chemical-mechanical-polishing (CMP) processing steps are performed to planarise the HDP oxide 400, as shown in Figure 5.
  • the passivation nitride layer 306 is used as the CMP stop layer.
  • pad open masking and etch are next performed to form pad openings 600, 602 above the top layer of copper metallization e.g. 332, 334, as shown in Figure 6.
  • aluminium deposition aluminium layer thickness about 1 ,OO ⁇ A to 20,000A
  • pad masking and etch processing to form aluminium pads 700, 702 extending through the pad openings 600, 602 for electrical contacting, as shown in Figure 7.
  • Micro electro mechanical systems (MEMS) back- end integration processes to integrate thick dielectric contacts, fibre/lens slots and e.g. a laser diode assembly metallization can then be performed in the example embodiment.
  • MEMS micro electro mechanical systems
  • Figures 8a and b show a schematic plan and cross-sectional views respectively of the modified stack 300 after the processing steps described above with reference to Figures 2 to7.
  • FIG. 9a and b show a schematic plan and cross-sectional views respectively of such an example embodiment, in which only the portions 900, 902 associated with the M1 and M2 metal layers e.g. 904, 906 are removed in areas where optical losses are to be eliminated, rather than the (vertically) entire dielectric stack 908.
  • Figure 11 shows a flowchart 1100 illustrating a method for reducing optical coupling loss in a dielectric stack according to an example embodiment.
  • step 1102 at least a portion of the dielectric stack associated with one or more metal layers of the dielectric stack is removed in a region where optical losses are to be eliminated.
  • step 1104 said portion is replaced with a homogenous dielectric material.
  • the example embodiments described can provide a method and dielectric stack for reducing waveguide propagation loss due to coupling to unwanted dielectrics in case of photonics and electronics integration.
  • the example embodiment can eliminate the optical losses while coupling light from optical fiber to silicon nanotaper waveguide structures in a CMOS compatible way.
  • the example embodiments replace one dielectric CMP process for each single or dual damascene stack, while the foundry process for metallization is not changed.
  • the removal of at least a portion of the multi-level dielectric stack in the regions where optical losses are to be eliminated can be performed after e.g. aluminium metallization, as part of the back-end MEMS process.
  • the present invention is not limited to application in Cu-BEOL dielectric stacks, but more generally applies to reducing coupling loss in a dielectric stack.
  • the homogenous dielectric material for filing of the etch trenches is not limited to HDP undoped silicon oxide, but can include other preferably low-dielectric constant (e.g. with a dielectric constant in the range of about 1.5 to 3.5) organic or inorganic dielectric materials, such as, but not limited to, HDP silicon oxide, Plasma enhanced chemical vapor deposited (PECVD) oxide, Phosporous or Boron doped PECVD oxide, TEOS (tetra-ethyl-ortho-silicate) based PECVD oxide, flurorine doped silicon oxides, carbon doped silicon oxides, porous fluorine or carbon doped oxides deposited using chemical vapour deposition processes or organic polymer dielectrics deposited using spin-on or spray deposition methods.
  • PECVD Plasma enhanced chemical vapor deposited
  • TEOS tetra-ethyl-ortho-silicate

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur un procédé de réduction d'une perte de couplage optique dans un empilement diélectrique, sur un empilement diélectrique et sur un dispositif optique. Le procédé comporte les étapes d’élimination d'au moins une partie de l'empilement diélectrique associée à une ou à plusieurs couches métallique de l'empilement diélectrique dans une région où des pertes optiques doivent être éliminées, et de remplacement de ladite partie par un matériau diélectrique homogène.
PCT/SG2008/000077 2008-03-11 2008-03-11 Procédé de réduction d'une perte de couplage optique dans un empilement diélectrique WO2009113961A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/SG2008/000077 WO2009113961A1 (fr) 2008-03-11 2008-03-11 Procédé de réduction d'une perte de couplage optique dans un empilement diélectrique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2008/000077 WO2009113961A1 (fr) 2008-03-11 2008-03-11 Procédé de réduction d'une perte de couplage optique dans un empilement diélectrique

Publications (1)

Publication Number Publication Date
WO2009113961A1 true WO2009113961A1 (fr) 2009-09-17

Family

ID=41065482

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2008/000077 WO2009113961A1 (fr) 2008-03-11 2008-03-11 Procédé de réduction d'une perte de couplage optique dans un empilement diélectrique

Country Status (1)

Country Link
WO (1) WO2009113961A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9202832B2 (en) 2011-04-19 2015-12-01 Infineon Technologies Ag Integrated circuit arrangements
WO2019195367A1 (fr) * 2018-04-05 2019-10-10 The Research Foundation For The State University Of New York Fabrication de régions de transmission de signal lumineux à structure photonique
EP4038426A4 (fr) * 2019-09-30 2023-10-18 California Institute of Technology Dispositifs électroniques-photoniques intégrés, systèmes et leurs procédés de fabrication

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH116928A (ja) * 1997-06-18 1999-01-12 Nippon Telegr & Teleph Corp <Ntt> アレイ導波路格子型波長合分波器
JPH11125750A (ja) * 1997-10-24 1999-05-11 Furukawa Electric Co Ltd:The 光集積回路
US20060163451A1 (en) * 2005-01-25 2006-07-27 Park Young-Hoon Image sensor and method of fabrication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH116928A (ja) * 1997-06-18 1999-01-12 Nippon Telegr & Teleph Corp <Ntt> アレイ導波路格子型波長合分波器
JPH11125750A (ja) * 1997-10-24 1999-05-11 Furukawa Electric Co Ltd:The 光集積回路
US20060163451A1 (en) * 2005-01-25 2006-07-27 Park Young-Hoon Image sensor and method of fabrication

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DATABASE WPI Week 199912, Derwent World Patents Index; Class P81, AN 1999-137738, XP003025506, ACCESSION *
DATABASE WPI Week 199929, Derwent World Patents Index; Class P81, AN 1999-342782, XP003025505, ACCESSION *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9202832B2 (en) 2011-04-19 2015-12-01 Infineon Technologies Ag Integrated circuit arrangements
DE102012103431B4 (de) * 2011-04-19 2018-02-01 Infineon Technologies Ag Integrierte Schaltungsanordnungen
WO2019195367A1 (fr) * 2018-04-05 2019-10-10 The Research Foundation For The State University Of New York Fabrication de régions de transmission de signal lumineux à structure photonique
US10816724B2 (en) 2018-04-05 2020-10-27 The Research Foundation For The State University Of New York Fabricating photonics structure light signal transmission regions
JP2021519948A (ja) * 2018-04-05 2021-08-12 ザ リサーチ ファンデーション フォー ザ ステート ユニバーシティ オブ ニューヨーク フォトニクス構造光信号伝送領域の作製
US11378739B2 (en) 2018-04-05 2022-07-05 The Research Foundation For The State University Of New York Fabricating photonics structure light signal transmission regions
TWI776040B (zh) * 2018-04-05 2022-09-01 美籍紐約州立大學研究基金會 製造光學結構光訊號傳輸區的方法
US11635568B2 (en) 2018-04-05 2023-04-25 The Research Foundation For The State University Of New York Photonics light signal transmission
EP4038426A4 (fr) * 2019-09-30 2023-10-18 California Institute of Technology Dispositifs électroniques-photoniques intégrés, systèmes et leurs procédés de fabrication
US11855119B2 (en) 2019-09-30 2023-12-26 California Institute Of Technology Integrated electronic-photonic devices, systems and methods of making thereof

Similar Documents

Publication Publication Date Title
US9305826B2 (en) Semiconductor substrate for photonic and electronic structures and method of manufacture
US6861347B2 (en) Method for forming metal wiring layer of semiconductor device
US6331479B1 (en) Method to prevent degradation of low dielectric constant material in copper damascene interconnects
EP1560264B1 (fr) Méthode de formation d&#39;une structure pour une ligne d&#39;interconnexion
US8709942B2 (en) Methods for fabricating semiconductor devices
US7790601B1 (en) Forming interconnects with air gaps
US6297149B1 (en) Methods for forming metal interconnects
JP2008198971A (ja) 先端ｃｍｏｓ撮像装置における多重絶縁体構造上の光伝送の改良
US7635650B2 (en) Prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices
US20070232048A1 (en) Damascene interconnection having a SiCOH low k layer
US6815331B2 (en) Method for forming metal wiring layer of semiconductor device
CN114488396B (zh) 不影响互连层的用于光子集成电路的扩大的波导
US20230185024A1 (en) Photonic structure and method for forming the same
WO2009113961A1 (fr) Procédé de réduction d&#39;une perte de couplage optique dans un empilement diélectrique
US6887802B2 (en) Method of manufacturing semiconductor device and semiconductor device
CN102054762B (zh) 双镶嵌结构的形成方法、半导体结构
JP3719672B2 (ja) 半導体装置の製造方法
JP3898669B2 (ja) 半導体装置の製造方法
US20050211664A1 (en) Method of forming optical waveguides in a semiconductor substrate
US20240176067A1 (en) Enlarged multilayer nitride waveguide for photonic integrated circuit
KR20070062026A (ko) 반도체 소자의 컨택홀 형성방법
Winnie et al. Fabrication of High Aspect Ratio Optical Light Pipes
KR20070035201A (ko) 이미지 센서 제조방법
KR20090037553A (ko) 반도체 소자의 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08724341

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08724341

Country of ref document: EP

Kind code of ref document: A1