WO2009110446A1 - Procédé de mappage de mémoire, système de mémoire - Google Patents

Procédé de mappage de mémoire, système de mémoire Download PDF

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Publication number
WO2009110446A1
WO2009110446A1 PCT/JP2009/053923 JP2009053923W WO2009110446A1 WO 2009110446 A1 WO2009110446 A1 WO 2009110446A1 JP 2009053923 W JP2009053923 W JP 2009053923W WO 2009110446 A1 WO2009110446 A1 WO 2009110446A1
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Prior art keywords
memory
address
address conversion
color
areas
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PCT/JP2009/053923
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English (en)
Japanese (ja)
Inventor
一久 石坂
孝 宮崎
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日本電気株式会社
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Priority to JP2010501904A priority Critical patent/JP5293974B2/ja
Publication of WO2009110446A1 publication Critical patent/WO2009110446A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Definitions

  • the present invention relates to a memory system and a memory mapping method in a computer system, and more particularly to a memory system and a memory mapping method for mapping a memory to an address space.
  • a cache memory that temporarily stores data stored in the memory (hereinafter, the cache memory is referred to as a cache) is effectively used.
  • a method of concealing latency due to a memory having a low operation speed is important for improving the performance of application software.
  • the position (index) when data is stored on the cache is determined by the physical address. Mapping of logical addresses and physical addresses by the OS is performed in units called pages (4 KB is often used), and pages stored at the same position on the cache are represented by the same color number (color ID).
  • Figure 1 shows an example of the relationship between the physical address space and the cache.
  • the numbers outside the parentheses in the physical address space of FIG. 1 represent page numbers, and the numbers within the parentheses represent color numbers.
  • the number of colors is the number of color numbers that can be taken in the physical address space.
  • FIG. 1 shows an example in which the number of colors is 8, but the color number indicates the storage position on the cache.
  • the numbers in the cache in FIG. 1 indicate color numbers, and the pages in the physical address space are stored in locations having the same color number on the cache.
  • Non-Patent Document 1 it is possible to improve the use efficiency of the cache when mapping the logical address and the physical address of the process by the OS by using such a characteristic of the physical index cache. It has been known.
  • ⁇ Cache competition between processes is a phenomenon that deteriorates the efficiency of cache usage.
  • FIG. 2 when data accessed by a plurality of processes is stored at the same location on the cache, the data is driven out of the cache.
  • As a method of reducing such cache contention separate the color numbers that can be used for each process and map only the physical pages that have the usable color numbers to the logical pages of each process. There is a way to avoid using the same position.
  • Fig. 3 shows the mapping between logical addresses and physical addresses for reducing cache contention between the two processes A and B.
  • the logical page of process A is mapped only to pages with color numbers 0, 1, 2, 3 and the logical page of process B is mapped only to pages with color numbers 4, 5.
  • the two processes do not utilize the same location on the cache.
  • Patent Document 1 discloses a method for preventing the performance of a real-time task from degrading due to cache contention by separating color numbers between the real-time task and other tasks.
  • Patent Document 2 discloses a free coloring method as a method for solving such a memory size limitation problem.
  • FIG. 5 is a drawing for explaining the Free Coloring method.
  • the CPU bus address width is increased by the number of colors with respect to the memory bus address width.
  • the increment bit (c in the figure) is added to the position where the color is designated when accessing the cache.
  • the correspondence relationship (mapping) between the physical address space and the memory is such that a page in a plurality of physical address spaces corresponds to one page in the memory as shown in FIG.
  • a page on the physical space corresponding to the same page on the memory is called a group.
  • Patent Document 3 divides a memory into a plurality of sections and shares a cache among the sections.
  • the memories in different sections have the same physical address, and the cache tag is an extension called PID (partition identification unit). Bits are used to distinguish different memory locations.
  • PID partition identification unit
  • an index for specifying a set on the cache is determined so as to reduce the probability of a contention miss occurring in the cache with respect to memory access.
  • JP 2000-339220 A Japanese Translation of National Publication No. 09-507599 JP 2001-282617 A Japanese Patent Application Laid-Open No. 09-223069 Kessler et al. "Page Placement Algorithms for Large Real-Indexed Caches" ACM Transactions on Computer Systems, 1992, Vol. 4, No. 10, pp.338-359
  • FIG. 7 shows an example of a process in which the set of colors (color set) that can be used in the case of 8 colors is limited to ⁇ 0, 1 ⁇ .
  • the left side of the figure is the physical address space, and the right side of the figure shows pages that can be mapped to the process logical address space.
  • this process has the problem that only a maximum of 25% of the total memory size is available.
  • Patent Document 3 an extension bit called PID is attached to a tag of a cache to distinguish different memory locations, but there is a problem that different colors on the cache cannot be accessed from the same location on the memory.
  • an index for specifying a set on the cache is determined so as to reduce the probability of a contention miss that occurs in the cache with respect to memory access, but there are a plurality of indexes in the physical address space to which the memory is mapped. There is a problem that different colors on the cache cannot be accessed from the same position on the memory.
  • An exemplary object of the present invention is to increase the memory size that can be used by a process without losing address continuity in a method of controlling the cache usage of a process by mapping the logical address and physical address of an OS.
  • a memory mapping method and a memory system are provided.
  • An exemplary memory mapping method includes: a memory; and a cache memory that temporarily holds data stored in the memory and determines a storage position of the data by a physical address.
  • a method of mapping the physical address space of the memory in a memory system that identifies each page of a certain size, which is a unit of mapping between a logical address and the physical address, by a color ID, Mapping one address of the memory to a plurality of areas of the physical address space; For each access to the memory from each of the plurality of areas, different address conversion is performed, Accessing the one address on the memory with a different color ID from each of the plurality of areas; It is characterized by that.
  • An exemplary memory system includes a memory, a cache memory that temporarily stores data stored in the memory, a storage location of the data is determined by a physical address, and a plurality of physical address spaces.
  • An address conversion unit that performs different address conversion for each access to the memory from each of the areas, and The storage location is identified by a color ID for each page of a certain size, which is a unit of mapping between logical addresses and physical addresses, One address on the memory is mapped to the plurality of areas, and each address conversion unit performs different address conversion for access to the memory from each of the plurality of areas, and each of the plurality of areas The one address is accessed with a different color ID.
  • the exemplary effect of the present invention is that one address on the memory is mapped to multiple areas on the physical address space and each of these areas performs a different address translation for access to the memory. By accessing each of these areas with a different color ID, the mapping between the OS logical page and the physical page is performed without losing the continuity of the address and without reducing the memory size available to the process. It is possible to obtain a memory mapping method and a memory system capable of controlling the cache usage of a process.
  • FIG. 10 is a diagram for explaining a memory size limitation that occurs for cache control according to Patent Document 1.
  • FIG. 8 is a diagram showing an outline of the present invention.
  • the memory 11 is mapped to a plurality of areas 13-0 to 13-N-1 on the physical address space 12, and different address conversion 14- is performed for each area access to the memory.
  • the same address on the memory is accessed from each area with different colors.
  • FIG. 9 is a diagram showing the configuration of the first exemplary embodiment of the present invention.
  • the present embodiment is configured by a physical address space 19 in which the CPU 15, the cache 16, the address conversion unit 17, the memory 18, and the memory 18 are mapped to a plurality of areas.
  • the cache 16 temporarily holds data stored in the memory 18.
  • the cache 16 is a cache memory, and the memory 18 is a main memory.
  • the physical address space 19 has a number of areas mapped to the memory 18 equal to the number of colors.
  • the address conversion unit 17 performs address conversion so as to add an offset to the address so as to shift by one color for each area.
  • Color (x) represents the color at address x and is represented by the following equation.
  • An example of address conversion that satisfies Expression 1 is to apply the following conversion expression f i (x i ) to the address x i on the region i.
  • base i is the start address of area i.
  • FIG. 10 is a diagram showing the operation of the first exemplary embodiment of the present invention, and shows the operation when the address y on the memory is accessed through the address x i on the area i.
  • Memory access in this case is performed in the following order. Since the operation up to the conversion of the logical address and the physical address by the MMU (Memory Management Unit) is clear, it will be described after the conversion to the physical address. Also, let f i be the conversion for the region i in the address conversion unit.
  • the CPU 15 issues a physical address x i (step S11).
  • the cache 16 is accessed with the address x i (step S12).
  • the color at this time is Color (xi).
  • the physical address x i is issued (step S13).
  • the address y is issued to the memory 18 (step S15). It is.
  • FIG. 11 shows a memory map in the first embodiment of the present invention.
  • the memory size is 256 MB (addresses 0x00000000 to 0x0ffffff), the page size is 4 KB, the number of colors and the number of areas are four.
  • the memory is mapped to four areas on the physical address space, and each start address (base i ) is 0x00000000 for area 0, 0x10000000 for area 1 and area 2 is 0x20000000 and area 3 is 0x3000000.
  • address conversion is performed by applying the following address conversion formula of this embodiment.
  • f i (x) x-page size * i? base i * i + size i (base i ⁇ x ⁇ base i + page size * i)
  • f i (x) x-page size * i? base i (base i + page size * i ⁇ x ⁇ base i + size i )
  • size i represents the size of the memory.
  • FIG. 12 shows the configuration of the first embodiment of the present invention.
  • address translation is performed between the cache 16 and the bus.
  • address conversion may be performed between the bus and the memory 18 as shown in FIG.
  • FIG. 14 shows the correspondence between each area and memory in this embodiment.
  • the numbers outside the parentheses in the figure represent page numbers (that is, addresses / page sizes), and the numbers within the parentheses represent color numbers (that is, page number% color number).
  • the color is shifted by 1 in each area by address conversion, and it can be seen that a page in the memory can be accessed in any color by using the four areas.
  • the page on area 0 to which page 0x00000 on the memory is mapped is 0x00000 and the color is 0, whereas the page on area 1 is 0x10001, the color is 1, the page on area 2 is 0x20002, and the color is 2.
  • the page on area 3 is 0x30003 and the color is 3. That is, the set of colors that can access page 0x00000 in memory is ⁇ 0,1,2,3 ⁇ , which includes all colors. Therefore, the page 0x00000 on the memory can be used by any process having the available color set.
  • the available memory size is 256 MB, which is increased to 100% of the total memory.
  • the present embodiment is an example in which the memory size is 256 MB (addresses 0x00000000 to 0x0ffffff), the number of colors and the number of areas are four.
  • the memory is mapped to four areas on the physical address space, and each start address (base i ) is 0x00000000 for area 0, 0x10001000 for area 1 and area 2 is 0x20002000 and area 3 is 0x30003000.
  • the address conversion formula of this embodiment is shown below.
  • FIG. 16 is a diagram showing the configuration of the second exemplary embodiment of the present invention.
  • This embodiment includes a CPU 25, a cache 26, an address conversion unit 27, a memory 28, and a physical address space 29 in which the memory 28 is mapped into a plurality of areas.
  • the number of areas to which the memory 28 is mapped is less than the number of colors.
  • the address conversion unit 27 adds an offset to the address so that the color is shifted by a different constant C i (i is a number representing the area) that is greater than or equal to 0 and smaller than the number of colors for each area. do.
  • N M in Equation 2.
  • the present embodiment is an example in which the memory size is 256 MB (addresses 0x00000000 to 0x0ffffff), the number of colors is 4, and the number of areas is 2.
  • the memory is mapped into two areas on the physical address space, and the start addresses (base i ) of the area 0 are 0x00000000 and the area 1 is 0x10000000. .
  • f i (x) x-page size * 2 * i-base i * i + size i (base i ⁇ x ⁇ base i + page size * 2 * i)
  • f i (x) x-page size * 2 * i-base i (base i + page size * 2 * i ⁇ x ⁇ base i + size i )
  • size i represents the size of the memory.
  • FIG. 18 shows the correspondence between each area and the memory in this embodiment.
  • the color is shifted by 2 in each area by address conversion, and it can be seen that a page on the memory can be accessed in 2 colors by using the 4 areas.
  • the page on area 0 to which page 0x00000 on the memory is mapped is 0x00000 and the color is 0, while the page on area 1 is 0x10001 and the color is 2. Therefore, not only the process including 0 in the usable color set but also the process including 2 can use the page 0x00000 in the memory.
  • it when using a plurality of areas according to the present embodiment, it is 128 MB, and 50% of the memory can be used.
  • the size of some areas or the size of all areas is smaller than the size of the memory. Good.
  • the color set for accessing a specific address on the memory is small, the effect of increasing the memory size that can be allocated to the process is small, but the area occupied by the memory in the physical address space is small. There is.
  • the number of the plurality of areas in which the memory is mapped on the physical address space may be larger than the number of colors.
  • the size of the area is smaller than the memory size, the color set for accessing a specific address on the memory becomes small, but there is an effect of increasing the color set by increasing the number of areas.
  • This embodiment includes a CPU 35, a cache 36, a plurality of address conversion units 37, a memory 38, and a physical address space in which the memory is mapped to a plurality of areas.
  • the present embodiment is characterized in that a plurality of address conversion units 37 continuously perform address conversion and access the memory in different colors from a plurality of areas mapped on the physical address space.
  • FIG. 20 is a diagram illustrating the operation of the third exemplary embodiment of the present invention.
  • the number of address conversion units is n and the address xi on the area i is accessed.
  • the CPU issues a physical address x i (step S21).
  • the cache is accessed at address x i .
  • the color at this time is Color (x i ) (step S22).
  • the physical address x i is issued (step S23).
  • the address y is issued to the memory (step S27). It is.
  • the memory size is 256 MB (addresses 0x00000000 to 0x0ffffff), the number of colors is 4, and the number of areas is 4.
  • the memory is mapped to four areas on the physical space as in the first embodiment, and the start address (base i ) of each area is 0x00000000, region 1 is 0x10001000, region 2 is 0x20002000, and region 3 is 0x30003000.
  • FIG. This embodiment includes two address conversion units.
  • the first address conversion unit 37a is located between the cache and the bus, and the address conversion formula is as follows.
  • f i (x) x-page size * I
  • the second address conversion unit 37b is a bus address decoder.
  • the address decoder outputs a signal indicating that the memory is accessed when the upper 4 bits of the address are 0x0, 0x1, 0x2, and 0x3, and uses the lower 28 bits of the address as an address signal to the memory. It shall operate as follows.
  • the CPU 35 issues an address 0x20006000 (2)
  • the cache 36 is accessed at the address 0x20006000.
  • the physical address 0x20006000 is issued (4)
  • the address ( 0x20006000-4KB * 2) 0x20004000 (5)
  • the second address conversion unit (address decoder) 37b determines that the upper 4 bits of the address 0x20004000 are bits indicating access to the memory, and the memory 38 A signal indicating that it is an access to is issued.
  • the lower 28 bits 0x0004000 of the address are used as an address to be issued to the memory.
  • the address 0x0004000 is issued to the memory 38.
  • the usable memory size increases in the process in which the usable colors are limited.
  • some of the plurality of address conversion units may be common to a plurality of areas.
  • FIG. 22 is a diagram showing the configuration of the fourth exemplary embodiment of the present invention.
  • the present embodiment includes a CPU 45, a cache 46, an address conversion unit 47, an address conversion change unit 47a, a memory 48, and a physical address space 49 in which the memory 48 is mapped into a plurality of areas.
  • the address conversion unit 47 includes an address conversion change unit 47a for changing address conversion from software.
  • changing the address translation means that the address on the memory corresponding to the address x in the physical space is f (x) in the address translation before the change, and the address on the corresponding memory is f (x) after the change. x) is different from f ′ (x).
  • the size of the area on the physical space to which the memory is mapped is smaller than the memory size, or if the number of areas is less than the number of colors, the number of colors that can access the address on the memory is reduced. Even in such a case, in this embodiment, since the color when accessing through each area can be changed, the memory can be accessed with a color that cannot be accessed by the address conversion before the change. Therefore, the effect that the color which can access the address on the memory increases can be obtained.
  • FIG. 1 The configuration of this embodiment is shown in FIG.
  • This embodiment includes a CPU 45, a cache 46, an address conversion unit 47, an address conversion table 50, a physical address space 49, and a memory 48.
  • the memory size is 256 MB.
  • the address conversion unit 47 uses the address conversion table 50 to convert the address on the physical address space 49 into the address on the memory 48, and the range in which the memory on the physical address space 49 is mapped.
  • the size is the same as the memory size.
  • the address conversion table 50 is a table for storing addresses on the physical address space 49 and addresses on the memory 48 to which the addresses are converted.
  • the address conversion unit 47 searches the address conversion table 50 when performing address conversion, and if an address on the physical address space 49 is found, extracts an address on the corresponding memory space as a conversion result.
  • the address conversion table 50 records the address correspondence in units of page size, but this does not limit the unit recorded by the address conversion table 50 to the page size.
  • the address conversion table 50 may be stored on the main memory or may have a dedicated memory. Alternatively, it may be cached with a high-speed memory such as a page table used for conversion between a physical address and a logical address.
  • the CPU 45 issues an address 0x00000010.
  • the cache 46 is accessed at the address 0x00000010.
  • the memory 48 is accessed due to a cache miss or the like, the physical address 0x00000010 is issued.
  • the address conversion unit 47 searches the address conversion table to obtain that the address on the memory 48 corresponding to the page 0x00000 on the physical address space 49 is 0x00003.
  • the address 0x00003010 is issued to the memory 48.
  • pages 0x00000 (color 0) and 0x00001 (color 1) on the physical address space are recorded so as to correspond to pages 0x00000 on the memory. Therefore, it is possible to access page 0x00000 on the memory with color 0 or 1.
  • the present embodiment has an effect of relaxing the restriction on the memory size that can be used by the process when performing cache control using the conversion of the logical address and the physical address by the OS.
  • the address conversion table 50 is an address conversion change unit 47a for changing address conversion. Therefore, the address conversion unit 47 of this embodiment includes an address conversion change unit 47a.
  • this embodiment has a feature that the size of the range for mapping the memory in the physical address space is the same as the memory size. This is because the page on the memory to which a certain physical page corresponds can be changed by changing the recorded contents of the address conversion table. Therefore, the size of the range where the memory in the physical address space is mapped is larger than the size of the memory. This is because all pages on the memory can be accessed without increasing the size.
  • the present embodiment has an effect that it is possible to access the same address on the memory with a plurality of colors while keeping the size of the range for mapping the memory on the physical address space to the same size as the memory size. is there.
  • the present embodiment is also an embodiment corresponding to another form of the first embodiment of the present invention in which the region size is the page size and the number of regions is the number of pages.
  • a computer having a cache memory and a processor that converts a logical address and a physical address, it can be used for a purpose of suppressing a decrease in operation speed due to a cache miss penalty when operating application software. .

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Abstract

L'invention porte sur un procédé de mappage de mémoire dans lequel des pages d'une dimension précise, qui servent d'unité pour le mappage d'adresses logiques et d'adresses physiques, représentent chacune des positions de stockage d'un cache dans une mémoire cache, les pages étant identifiées par un identifiant de couleur. Une adresse de mémoire est mappée à des zones 3-0, 3-1 et 3-N-1 d'un espace d'adresse physique 2; différentes conversions d'adresse 4-0, 4-1, et 4-N-1 sont mises en œuvre pour accéder à la mémoire 1 à partir de chacune des zones 3-0, 3-1 et 3-N-1, et différents identifiants de couleur sont utilisés pour accéder aux adresses dans la mémoire 1 pour chacune des zones 3-0, 3-1 et 3-N-1.
PCT/JP2009/053923 2008-03-04 2009-03-03 Procédé de mappage de mémoire, système de mémoire WO2009110446A1 (fr)

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CN104516826A (zh) * 2013-09-30 2015-04-15 华为技术有限公司 一种虚拟大页面与物理大页面的对应方法及装置

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EP0919927A3 (fr) * 1997-11-26 2000-05-24 Compaq Computer Corporation Technique d'allocation dynamique de mémoire pour maintenir une distribution uniforme d'adresses de pages d'antémémoire dans un espace d'adresse
JP2000339220A (ja) * 1999-05-27 2000-12-08 Nippon Telegr & Teleph Corp <Ntt> キャッシュブロック予約方法およびキャッシュブロック予約機能付きコンピュータシステム
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CN104516826A (zh) * 2013-09-30 2015-04-15 华为技术有限公司 一种虚拟大页面与物理大页面的对应方法及装置

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