WO2009103285A1 - Composant opto-électronique - Google Patents

Composant opto-électronique Download PDF

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Publication number
WO2009103285A1
WO2009103285A1 PCT/DE2009/000251 DE2009000251W WO2009103285A1 WO 2009103285 A1 WO2009103285 A1 WO 2009103285A1 DE 2009000251 W DE2009000251 W DE 2009000251W WO 2009103285 A1 WO2009103285 A1 WO 2009103285A1
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WO
WIPO (PCT)
Prior art keywords
optoelectronic component
semiconductor chip
connection carrier
potting body
connection
Prior art date
Application number
PCT/DE2009/000251
Other languages
German (de)
English (en)
Inventor
Harald Jaeger
Herbert Brunner
Albert Schneider
Original Assignee
Osram Opto Semiconductors Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2009103285A1 publication Critical patent/WO2009103285A1/fr

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0203Containers; Encapsulations, e.g. encapsulation of photodiodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0232Optical elements or arrangements associated with the device
    • H01L31/02325Optical elements or arrangements associated with the device the optical elements not being integrated nor being directly associated with the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0216Coatings
    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02162Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/54Encapsulations having a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • An optoelectronic component with a semiconductor chip and a potting body is specified.
  • Optoelectronic components such as light emitting diodes or photodiodes have found a wide technical use and entry into everyday life. Some aspects that have contributed to the dissemination of such components are their high efficiency, resistance to external environmental influences such as mechanical stress or moisture and heat, long life, compact design and various design options, and this at relatively low production costs. Often crucial for these properties is the house or the housing of the optoelectronic device. In particular, the house is therefore placed great value in the rule.
  • One problem to be solved is to specify an optoelectronic component which is particularly resistant to aging.
  • this comprises at least one optoelectronic semiconductor chip with a thickness of at most 200 ⁇ m.
  • the thickness of the semiconductor chip is at most 150 ⁇ m.
  • the semiconductor chip may be formed, for example, as described in the publication WO 2005 / 081319A1, the disclosure content of which is described with regard to the semiconductor chip described there and to the semiconductor chip described therein manufacturing method hereby incorporated by reference.
  • the contact surfaces of the semiconductor chip for its electrical contacting can be located, for example, on one side of the semiconductor chip, so that the semiconductor chip is designed as a flip-chip, or be mounted on two opposite sides.
  • the semiconductor chip comprises an active layer, which is provided for radiation generation or radiation detection.
  • the active layer of the semiconductor chip may be based on, for example, GaN or GaAs. Likewise, GaP-based active layer sequences are possible.
  • the semiconductor chip can be designed approximately as a light-emitting diode, laser diode or photodiode.
  • the semiconductor chip is configured mechanically self-supporting. That is, it can be handled, for example, with tweezers or another suitable tool, in particular placed on a connection carrier.
  • the latter contains a connection carrier with at least two electrical connection points for electrical contacting of the semiconductor chip.
  • a connection carrier with at least two electrical connection points for electrical contacting of the semiconductor chip.
  • Connection carrier also electrical lines that serve approximately for the power supply of the semiconductor chip.
  • the main body of the connection carrier may be formed, for example, from a ceramic, a glass or a metal. Plastic-based connection carriers are also possible.
  • the connection carrier preferably has a high thermal conductivity in order to be able to dissipate good heat to the outside during the operation of the semiconductor chip.
  • the connection side of the Connection carrier, on which the semiconductor chip can be mounted, may be just designed or structurings, such as acting as a kind of reflector wells, which are provided for receiving the semiconductor chips.
  • this comprises a potting body.
  • the potting body surrounds the semiconductor chip at least in places.
  • the potting body is preferably made of a material which is at least partially permeable in the relevant for the operation of the semiconductor chip electromagnetic spectral range.
  • the potting body may for example be made of a silicone or epoxy resin or a silicone-epoxy hybrid material.
  • the potting body is preferably resistant to aging with respect to the electromagnetic radiation to be emitted or received by the semiconductor chip, and is also resistant to aging with respect to the thermal occurring during operation of the semiconductor chip
  • the potting body may be shaped like a lens, for example.
  • “Lens-like” here means that the potting body does not have to have the exact geometric shape or surface of a lens, but has for example a convex, directed away from the connection carrier curvature.
  • “Lens-like” includes, for example, Fresnel-like structuring of the outer surface of the potting with a ,
  • connection carrier the semiconductor chip is applied directly to the connection carrier. This means that except for a connecting means, such as an electric conductive adhesive or a solder, no other components or materials between the semiconductor chip and electrical connection points of the connection carrier are located.
  • a connecting means such as an electric conductive adhesive or a solder
  • the optoelectronic device of the potting body is in direct contact ⁇ for connection carrier.
  • no further material such as, for example, a film or an adhesive layer is attached between the connection side of the connection carrier and the potting body at at least one point.
  • the potting body is also in direct contact with the semiconductor chip.
  • the potting body is preferably only in direct contact with the connection carrier and the semiconductor chip.
  • the optoelectronic component contains at least one optoelectronic semiconductor chip with a thickness of at most 200 ⁇ m as well as a connection carrier with at least two electrical connection points for the electrical
  • the semiconductor chip is applied directly to the connection carrier and in places surrounded by a potting body.
  • the potting body is also in direct contact with the connection carrier.
  • Such an optoelectronic component is easy to manufacture, inexpensive to produce, has good optical properties and is aging-resistant.
  • the semiconductor chip is designed as a flip chip. That is, the contact surfaces of the semiconductor chip for electrical contacting are located on a main side of the semiconductor chip. Preferably, the two electrical contacts of the chip are located on the side of the semiconductor chip facing the connection carrier. If a flip-chip is used, the electrical contacting of the chip is simplified.
  • the potting body is designed with a material that has a lower hardness than Shore A 90.
  • the hardness of the material forming the potting body is preferably less than Shore A 80.
  • Shore A 0 corresponds to the lowest hardness
  • Shore A 100 corresponds to the highest hardness.
  • the component described here is based inter alia on the following finding.
  • Potting bodies of, for example, silicone have typical thermal expansions in the range from about 150 ppm per Kelvin to 300 ppm per Kelvin.
  • the thermal expansion of the semiconductor chip is on the order of 5 ppm per Kelvin and is therefore considerably lower.
  • the thermal expansion, for example, of a ceramic connection carrier is comparable to that of a semiconductor chip at 15 to 20 ppm per Kelvin, but also deviates significantly from that of a silicone.
  • the temperature difference between the switched-off state and operation of the optoelectronic component can clearly exceed 100 Kelvin. Accordingly, significant thermal stresses can occur between the semiconductor chip and the potting body.
  • hybrid materials such as silicone-epoxy hybrid materials
  • they can also have a greater hardness than Shore A 80, for example between Shore A80 and Shore D 70, since their coefficient of thermal expansion is lower in comparison to silicones.
  • the thermal stresses decrease significantly when the thickness of the semiconductor chips is small, as described, for example, less than 200 microns.
  • the thermal stresses decrease significantly when the thickness of the semiconductor chips is small, as described, for example, less than 200 microns.
  • Semiconductor chips can thus significantly improve the aging stability of an optoelectronic device.
  • the potting body includes at least one
  • Admixture in the form of a reflection agent, filter medium, diffusion agent or conversion agent Admixture in the form of a reflection agent, filter medium, diffusion agent or conversion agent.
  • a reflection means for example in the form of reflective metal particles be added to the potting.
  • Filtering agents may consist of pigments or dyes.
  • Suitable diffusing agents are, for example, light-scattering particles of, for example, titanium dioxide or aluminum oxide.
  • Organic or inorganic luminescent phosphors for example, which convert at least part of the radiation to be emitted or to be received by the semiconductor chip into radiation of a different frequency can be used as the conversion agent.
  • Optically active or photonic crystals can also be used as conversion agents, for example for purposes of frequency doubling or frequency tripling.
  • the admixture is distributed inhomogeneously in the potting body.
  • the admixture is a conversion agent
  • its concentration above the central region of the side of the semiconductor chip facing away from the connection carrier, which, for example, forms a radiation passage area may be higher than at the edge regions.
  • uniform color distributions can be achieved over the entire radiation-emitting surface of a semiconductor chip.
  • the potting body is by means of compression molding, liquid transfer molding, liquid injection molding
  • connection carrier forms a part of the mold.
  • Compression molding is an effective way to create potting bodies for semiconductor chips.
  • the material for the potting body is introduced into the mold and the connection carrier is pressed into the material located in the mold.
  • solid, granular material for example hybrid materials, may also be used.
  • the material can also on the connection carrier and the
  • connection carrier Semiconductor chip are applied before closing the mold.
  • the sealing between the connection carrier and the casting mold can take place, for example, via a sealing film, which is removed after the compression molding process. If solid materials, for example pressed in tablet form, for example hybrid materials, are used, the casting body can also be produced by means of transfer molding.
  • liquid injection molding of semiconductor devices is described in the document WO 2005/017995 A1, casting of semiconductor devices in the document EP 1 589 569 A2 and liquid transfer molding of semiconductor integrated circuits in the document US 2002/0153637 Al.
  • the connection carrier is designed with a ceramic.
  • the connection carrier can be completely made of a ceramic or contain a ceramic ingredient.
  • the ceramic may be made of aluminum nitride or aluminum oxide.
  • the ceramic used has a high thermal conductivity.
  • the ceramic can be configured as a thin-film ceramic with thicknesses of less than 500 .mu.m, preferably less than 400 .mu.m, or designed as multilayer ceramic, in which, for example, different layers of ceramic alternate with different layers of conductive material, such as a metal.
  • a multilayer ceramic has one or more layer sequences, in which a ceramic and a tungsten paste are followed, for example, by 8 ⁇ m nickel and 1 ⁇ m gold.
  • the thin-film ceramic In the case of using a thin-film ceramic, this may be coated with copper. In order to achieve a high thermal conductivity and thus to reduce the thermal loads, the copper can be applied in a thick layer.
  • the thin-film ceramic viewed from the surface of the ceramic in the direction of the connection side or semiconductor chip, have the following layer sequence: about 0.05 ⁇ m to 0.3 ⁇ m titanium, about 50 ⁇ m to 100 ⁇ m, for example 75 ⁇ m copper, about 1, 5 to 4 ⁇ m nickel, and about 0.3 to 1.1 ⁇ m gold.
  • the potting body comprises a plurality of layers. That is, for example, in different compression molding steps, a potting body can be created, the different layers, for example, from different
  • an innermost first layer which surrounds the semiconductor chip directly, may be about a soft silicone having a hardness less than Shore A 90, especially softer than Shore A 80, are used.
  • a conversion agent can be applied approximately in a uniform thickness.
  • a harder silicone with a Shore hardness between, for example, Shore A 80 and Shore D 60 can be used as the outermost layer in order to better protect the optoelectronic component against mechanical damage.
  • the outermost layer is preferably harder than Shore A 80, in particular harder than Shore D 60.
  • intermediate layers which, for example, comprise a further admixture, such as a filter medium, in a uniform layer thickness, or which imparts particular mechanical or chemical properties.
  • a further admixture such as a filter medium
  • the number of layers applied and any intermediate layers as well as the properties of the layers depend on the respective requirements and can be handled flexibly. Over several layers, the scope of an optoelectronic device can therefore be significantly expanded.
  • connection carrier is configured with a printed circuit board, in short PCB, a quad fiat pack, in short QFP or QFN, a flexible printed circuit board or a chip card material.
  • the listed connection carriers are widely used in conventional electronics and often consist of materials which have a comparable thermal expansion with the potting.
  • the use of these embodiments for the connection carrier for an optoelectronic component offers a simple possibility of electromagnetic radiation To connect emitting or receiving components with other non-optoelectronic electronic components and thus achieve a variety of circuit options, and can lead to an increase in the life of the component.
  • connection carrier has electrical vias or plated-through holes which are covered.
  • the covering of the vias can be done by the
  • the vias can be covered by electrically conductive, for example metallically shaped layers or by applied insulator layers. It is also possible that, in the event that the connection carrier is designed from a multilayer ceramic, the vias are located inside the connection carrier. Covered vias enable a robust optoelectronic component to withstand external influences.
  • connection carrier is designed to be at least partially radiation-transmissive.
  • the main body of the connection carrier may for example consist of a glass, a plastic or a ceramic, such as aluminum oxide.
  • electrical connection points or electrical lines this offers the opportunity to create a transparent optoelectronic device.
  • materials for transparent electrical lines, for example transparent conductive oxides, TCO short, such as indium tin oxide, suitable.
  • the connection carrier is designed to be at least partially reflecting. The reflective effect may be via admixtures, such as titanium dioxide particles, or an intrinsic property of the material used.
  • metallic layers or dielectrically reflecting layers, such as Bragg mirrors, applied to the connection carrier are possible. By a reflective acting connection carrier is emitted approximately from the component
  • a plurality of the semiconductor chips are arranged two-dimensionally on a connection carrier.
  • the individual semiconductor chips can each be surrounded by a separate potting body. It is also possible that a plurality of semiconductor chips are surrounded by a common potting body.
  • the two-dimensional arrangement may consist of a regular matrix-like grid or may be more irregular. For example, hexagonal arrangement patterns are possible. It can be identical semiconductor chips or different semiconductor chips use.
  • Semiconductor chips may preferably be used which emit red, green and blue light, for example, so that an overall white-emitting illumination device results, for example, in the backlighting of displays.
  • Component is this except for the connection carrier and the potting body housing-free.
  • the potting body can be designed in this case multilayer and contain admixtures.
  • Such an optoelectronic component comprises few components, is therefore inexpensive to produce and also has low geometric dimensions.
  • this is by means of a
  • connection points are designed so that an assembly of the component can be carried out by means of soldering.
  • optoelectronic components described here can be used are, for example, the backlighting of displays or display devices. Furthermore, the optoelectronic components described here can also be used in illumination devices for projection purposes, in headlights or directional spotlights, or for purposes of general lighting.
  • FIG. 1 is a schematic sectional view of an embodiment
  • FIG. 2 shows a schematic sectional illustration of an exemplary embodiment with Fresnel lens
  • FIG. 3 shows a schematic sectional view of an exemplary embodiment with a multilayer ceramic
  • FIG. 4 shows a schematic sectional representation of an embodiment of a transparent arrangement
  • FIG. 5 shows a schematic sectional representation of a further exemplary embodiment
  • FIG. 6 is a schematic sectional view of an exemplary embodiment with a multilayer casting body
  • Figure 7 is a schematic sectional view (a) and a schematic plan view (b) of an embodiment with a plurality of semiconductor chips, and
  • Figure 8 is a schematic sectional view of an embodiment with a smart card substrate.
  • FIG. 1 shows an exemplary embodiment of an optoelectronic semiconductor component.
  • a connection carrier 4 which is designed for example from a thin-film ceramic having a thickness of 380 microns, electrical conductor tracks 9, which are formed from a metal applied. From the conductor tracks 9 and the electrical connection points 5a, 5b are formed.
  • the side of a semiconductor chip 2 attached to the connection carrier 4 facing the connection carrier 4 is completely occupied by the associated connection point 5 a. That is, the radiation passage area 11 remote from the semiconductor chip 2 is entirely on the connection point 5a.
  • a bonding wire 8 is attached, which is the
  • Semiconductor chip 2 electrically conductively connects to a further connection point 5b.
  • the contacting surfaces of the semiconductor chip are thus located on two opposite sides.
  • the bonding wire 8 occupies only a small portion of the radiation passage area 11.
  • the tracks 9 cover only a small portion of the connection side 10th
  • a potting body 3 is applied such that this in direct contact with the
  • Terminal side 10 is, as well as the semiconductor chip 2 also in direct contact with the radiation passage area 11 and on chip edges 12 surrounds.
  • the chip flanks 12 are in this case formed by the side surfaces of the semiconductor chip 2, which connect the radiation passage area 11 with the side of the semiconductor chip 2 facing the connection carrier 4.
  • the potting body 3 is formed of a soft silicone.
  • connection carrier 4 is a mechanically flexible substrate.
  • the conductor tracks 9 are located in the interior of the connection carrier 4 and connect the optoelectronic semiconductor chip 2, for example, with a further, not shown, semiconductor chip located in the substrate, which can assume the activation of the optoelectronic semiconductor chip 2, for example.
  • the conductor tracks 9 are connected via vias 7 to the optoelectronic semiconductor chip 2.
  • the vias 7 form at the Connection side 10, the electrical connection points 5 off.
  • the optoelectronic semiconductor chip 2 is designed, for example, as a surface emitter, so that the radiation essentially arises at or near the radiation passage area 11 and is emitted precisely at this point.
  • the potting body 3 is formed as a Fresnel lens. As a result, the height of the potting body 3 in the direction perpendicular to the connection side 10 is minimized. About the flat, space-saving design as a Fresnel lens also thermally induced voltages between potting 3 and optoelectronic semiconductor chip 2 can be reduced.
  • connection side 10 of the connection carrier 4 may not be designed flat, but instead have a type of depression in which the optoelectronic semiconductor chip 2 is located.
  • the trough can then from the potting 3 in
  • the conductor tracks 9 can be led to the connection side 10 or to a side of the connection carrier 4 facing away from the connection side.
  • the conductor tracks 9 can be configured for contacting by means of a surface mounting technique, SMT for short.
  • connection carrier 4 is designed from a multilayer ceramic.
  • a conductor 9a on the semiconductor chip 2 side applied a conductor 9b.
  • the conductor tracks 9a and 9b are electrically connected to the semiconductor chip 2 via vias 7a, 7b. Since the interconnects 9a, 9b are integrated into the connection carrier 4 or have no direct contact with the potting body 3, additional thermal stress possibly caused by the interconnects 9a, 9b can be reduced to the potting body 3, precisely by the use of a multilayer ceramic.
  • the semiconductor chip 2 is designed as a contactable by means of surface mount technology component, short SMT component.
  • the semiconductor chip 2 is connected to the electrical connection points 5 formed by the vias 7a, 7b, which are located on the connection side 10, via solder contacts.
  • the likewise lens-like designed potting 3 comprises an admixture 6, for example in the form of a diffuser, a conversion or a filter means. If the semiconductor chip 2 is designed, for example, as a photodiode, the spectral range to be received by the semiconductor chip 2 can be restricted in a simple manner by means of one or more filter media in the potting body 3, as required.
  • the semiconductor chip 2 is, as in the embodiment of Figure 2, designed as a flip-chip. Alternatively, it is also possible that the two not shown electrical contacting points of the semiconductor chip 2 on the side facing away from the connection carrier 4 of the
  • connection carrier 4 is formed from a transparent thermally conductive ceramic such as, for example, aluminum oxide.
  • the conductor tracks 9 and connection points 5 are also formed from a transparent material, such as, for example, indium tin oxide or another TCO or transparent conductive oxides.
  • the designed as a flip-chip semiconductor chip 2 is, for example, a so-called substratlose LED with a thickness of less than 10 microns. Due to the small thickness of the
  • Semiconductor chips 2 can be significantly reduced thermal stress between potting 3 and semiconductor chip 2. This has a positive effect on the aging stability of the optoelectronic component 1.
  • an admixture 6 in the form of a conversion agent is distributed inhomogeneous, indicated in Figure 4 by the hatching distances, so that over the central regions of the
  • Radiation passage area 11 is a higher concentration of the admixture 6 than in the edge regions of the potting body 3. This allows a uniform color radiation of the optoelectronic component 1.
  • connection carrier 4 is formed from a multilayer ceramic. Both conductor tracks 9 are located in the interior of the connection carrier 4, whereby, as in the exemplary embodiment according to FIG. 3, thermal loads on the potting body 3 are prevented by the conductor tracks 9.
  • the conductor tracks 9 are connected to the semiconductor chip 2 via vias 7, which also form the electrical connection points 5 on the connection side 10.
  • Semiconductor chip 2 is designed, for example, as a blue-emitting, GaN-based light-emitting diode.
  • the semiconductor chip 2 comprises one in comparison to the semiconductor chip 2 well thermally conductive ceramic plate 13, which is mixed with a phosphor and is located on the radiation passage area 11.
  • the phosphor converts the blue light emitted by the semiconductor chip 2 during operation at least in part, for example, into white mixed light.
  • Via the thermally conductive ceramic plate 13 a more uniform heat distribution at the radiation passage area 11 of the semiconductor chip 2 is ensured. As a result, thermally induced stresses between chip 2 and potting body 3 are also reduced.
  • the potting body 3 has an admixture 6 in the form of reflective particles, which concentrate on the areas of the potting body 3, which are aligned substantially parallel to the chip flanks 12. This causes approximately radiation emitted by the semiconductor chip 2 to leave the optoelectronic component 1 in a direction perpendicular to the connection side 10.
  • the reflective particles can be, for example, before the injection of the potting body 3 forming material in the corresponding
  • the potting body 3 comprises a plurality of onion-like layers 3a, 3b, 3c.
  • the innermost layer 3a which is in direct contact with the semiconductor chip 2, is formed of a soft silicone having a hardness lower than Shore A 70, for example.
  • the middle layer 3b includes, for example, a conversion agent or another admixture 6 in a uniform thickness.
  • Layer 3c is designed with a silicone of a greater hardness, approximately harder than Shore A 70, around the optoelectronic component 1 against external influences mechanically To make more robust and to achieve less stickiness and better shegles the silicone.
  • connection carrier 4 is made of a printed circuit board. As base material for printed circuit boards, the
  • the conductor tracks 9 are located on the side facing away from the semiconductor chip 2 side of the connection carrier 4.
  • the conductor tracks 9 are connected via vias 7 with the electrical connection points 5, which are located on the connection side 10, conducting.
  • the semiconductor chip 2 is applied to the connection points 5, for example via a conductive adhesive.
  • the connection points 5 are metallic and have a reflective effect on the semiconductor chip 2 to be received or emitted radiation.
  • the connection points 5 occupy a majority of the side of the semiconductor chip 2 facing the connection carrier 4, preferably more than 50%, in particular more than 80%.
  • the connection points 5 can be designed as reflectors with respect to the radiation to be emitted or received by the semiconductor chip 2.
  • the conductor tracks 9 may be covered by an insulator layer 14, for example of a glued-on plastic film or a lacquer layer. It is equally possible that the interconnects 9, depending on the complexity of the desired circuit, are also applied to both main sides of the connection carrier 4.
  • the multi-layer potting body 3 may be designed such that the various layers For example, have different optical refractive index. This can improve the quality of the optical image.
  • the embodiment shown in Figure 7a, 7b includes a plurality of semiconductor chips 2.
  • the non-illustrated electrical contact surfaces of the semiconductor chip 2 are located on the radiation passage area 11 and on the connection carrier 4 facing side of the semiconductor chip 2.
  • the connection carrier has a thickness of approximately 0.7 mm on.
  • the connection points 5 are formed by the ends of the electrical vias 7 located on the connection side 10.
  • the contact surfaces on the radiation passage area 11 are each contacted via a bonding wire 8 with a corresponding connection point 5.
  • the conductor tracks 9 are located on the side facing away from the semiconductor 2 of the connection carrier 4. About the conductor tracks 9, for example, a series connection of the semiconductor chips 2 can be realized.
  • a lens-like molded potting 3 is provided.
  • Potting body 3 each have a diameter of about 2 mm in plan view.
  • the diameters of the potting bodies 3 can also be chosen to be significantly smaller or significantly larger, depending on the specific requirements, in particular with regard to the quality of the optical imaging by the potting bodies 3.
  • a plurality of semiconductor chips 2 may be surrounded by a single potting body 3.
  • the potting body 3 can then have lens-like substructures.
  • Connection carrier 4 is preferably made of a material having a high thermal conductivity, in order to reduce the waste heat arising during operation of the semiconductor chip 2 or dissipate power loss well to the outside.
  • connection carrier 4 is designed as a chip card substrate and formed with an epoxy hard glass fiber fabric.
  • connection side 10 of the connection carrier 4 electrical connection points 5a, 5b are mounted.
  • the connection points 5a, 5b are made of copper and on the side facing away from the connection side 10 two layers coated with nickel and gold.
  • the connection points 5a, 5b can be connected via a surface mounting technique, SMT for short, to an external support or device (not shown in FIG. 8).
  • connection point 5 a the semiconductor chip 2 is attached by means of soldering in a recess of the connection carrier 4. From the radiation passage area 11 of the semiconductor chip 2, an electrical connection to the second connection point 5b is established via a bonding wire 8 and a further recess of the connection carrier 4.
  • a transparent lenticular potting body 3 made of a silicone or a hybrid material which covers the semiconductor chip 2 and the recesses.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

Dans au moins une exécution, le composant opto-électronique (1) comporte au moins une puce à semi-conducteurs opto-électronique (2) ayant une épaisseur maximale de 200 μm, et un support de connexions (4) présentant au moins deux zones de connexion électriques (5a, 5b, 9) pour la mise en contact électrique de la puce à semi-conducteurs (2). La puce à semi-conducteurs (2) est appliquée directement sur le support de connexions (4) et partiellement entourée par un corps de scellement (3). Le corps de scellement (3) se trouve également en contact direct avec le support de connexions (4). Un tel composant opto-électronique (1) est de construction simple et économique, présente de bonnes propriétés optiques et résiste bien au vieillissement.
PCT/DE2009/000251 2008-02-22 2009-02-20 Composant opto-électronique WO2009103285A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102008010509 2008-02-22
DE102008010509.0 2008-02-22
DE102008026841.0 2008-06-05
DE102008026841A DE102008026841A1 (de) 2008-02-22 2008-06-05 Optoelektronisches Bauteil

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WO2009103285A1 true WO2009103285A1 (fr) 2009-08-27

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WO (1) WO2009103285A1 (fr)

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JP5827864B2 (ja) * 2011-06-14 2015-12-02 日東電工株式会社 封止用シートおよび光半導体素子装置
DE102012105176B4 (de) 2012-06-14 2021-08-12 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronischer Halbleiterchip
DE102018105653A1 (de) 2018-03-12 2019-09-12 Osram Opto Semiconductors Gmbh Verfahren zur herstellung einer anordung, anordnung und array

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EP1657758A2 (fr) * 2004-11-15 2006-05-17 LumiLeds Lighting U.S., LLC Diode électroluminescente avec lentille moulée et sa méthode de fabrication
EP1854831A1 (fr) * 2005-02-23 2007-11-14 Mitsubishi Chemical Corporation Element de composant electroluminescent a semiconducteur, son procede de fabrication et composant electroluminescent l'utilisant
WO2006089540A2 (fr) * 2005-02-28 2006-08-31 Osram Opto Semiconductors Gmbh Procede de fabrication d'un composant optique et rayonnant et composant optique et rayonnant
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