WO2009096479A1

WO2009096479A1 - Image display device

Info

Publication number: WO2009096479A1
Application number: PCT/JP2009/051486
Authority: WO
Inventors: Shinji Takasugi; Kohei Ebisuno; Ryosuke Tani
Original assignee: Kyocera Corporation
Priority date: 2008-01-31
Filing date: 2009-01-29
Publication date: 2009-08-06

Abstract

A technique for preventing deterioration of a transistor for controlling the luminance. The image display device comprises first and second pixel circuits each having a light-emitting element the luminance of which is controlled by current and a drive transistor for regulating the current flown through the light-emitting element. The image display device further comprises a potential determining section for determining the potentials given to the drive transistors in the order from the first pixel circuit to the second one and a light emission control section for allowing the light-emitting elements included in the first and second pixel circuits to emit light at the same time. Furthermore the image display device comprises a potential regulating section for regulating the gate voltage of the drive transistor of the first pixel circuit so that the drive transistor of the first pixel circuit may be maintained in a saturation region during the period after the potential determining section determines a potential of the drive transistor of the first pixel circuit until the light emission control section allows the light emitting elements to start to emit light.

Description

Image display device

The present invention relates to an image display device.

Conventionally, an image display apparatus using an organic EL (Electroluminescent) element using electroluminescence has been known. An image display device using this organic EL element is disclosed in, for example, Japanese Patent Application Laid-Open No. 2006-309258.

In the image display device disclosed in Japanese Patent Laid-Open No. 2006-309258, before the light emission of the organic EL element, the gate voltage between the gate and the source in the drive transistor connected in series to the organic EL element is appropriately set. By setting, desired light emission luminance can be obtained. An image display device of a type (voltage control type) that obtains desired light emission luminance by appropriately controlling the gate voltage, and simultaneously emits light from two-dimensionally arranged light emitting elements (simultaneous light emission method). In this image display device, it is necessary to sequentially set the gate potential of the driving transistor for a large number of pixel circuits arranged in the image display device before light emission.

However, in a general voltage control type image display apparatus adopting the simultaneous light emission method, when the gate potential of the driving transistor is sequentially set, the gate potential of another pixel is set in a pixel in which the gate potential has already been set. In the meantime, the driving transistor is driven in a so-called linear region. In such a state, there has been a problem that the threshold voltage of the driving transistor is likely to change, which leads to deterioration of the driving transistor.

The present invention has been made in view of the above problems, and an object thereof is to provide a technique for suppressing deterioration of a transistor that adjusts light emission luminance.

In order to solve the above-described problem, an image display device according to a first aspect is an image display device, wherein a light emitting element whose light emission luminance is adjusted by a flowing current, a drive transistor that adjusts a current flowing through the light emitting element, , Each having first and second pixel circuits. In the image display device, the potential applied to the driving transistor is set in the order of the first pixel circuit and the second pixel circuit, and the potential setting unit and the first and second pixel circuits, respectively. A light emission control unit configured to emit light at the same time. Further, the image display device may be configured such that the potential setting unit sets a potential with respect to the driving transistor of the first pixel circuit before the light emission control unit starts light emission. A potential adjustment unit that adjusts a gate voltage of the drive transistor of the first pixel circuit is provided so that the drive transistor of the first pixel circuit is maintained in a saturation region.

Accordingly, since the state of the driving transistor is maintained in the saturation region from the time when the gate potential of the driving transistor is set to adjust the light emission luminance of the light emitting element until the light emitting element is made to emit light, the state of the driving transistor is linear. The problem of driving while entering the area is avoided as much as possible. As a result, deterioration of the transistor that adjusts the light emission luminance is suppressed.

FIG. 1 is a circuit diagram illustrating the configuration of a pixel circuit included in the image display device according to the first embodiment of the invention. FIG. 2 is a timing chart showing a basic operation example of the pixel circuit. FIG. 3 is a circuit diagram for explaining a basic operation example of the pixel circuit. FIG. 4 is a circuit diagram for explaining a basic operation example of the pixel circuit. FIG. 5 is a circuit diagram for explaining a basic operation example of the pixel circuit. FIG. 6 is a circuit diagram for explaining a basic operation example of the pixel circuit. FIG. 7 is a circuit diagram for explaining a basic operation example of the pixel circuit. FIG. 8 is a circuit diagram for explaining a basic operation example of the pixel circuit. FIG. 9 is a circuit diagram for explaining a basic operation example of the pixel circuit. FIG. 10 is a diagram illustrating a configuration example of the image display device according to the first embodiment of the present invention. FIG. 11 is a timing chart showing an operation example of the pixel circuit according to the first embodiment of the present invention. FIG. 12 is a circuit diagram showing a configuration example of a pixel circuit included in the image display device according to the second embodiment of the present invention. FIG. 13 is a circuit diagram illustrating the configuration of a pixel circuit included in the image display device according to the first modification example of the invention. FIG. 14 is a circuit diagram for explaining a basic operation example of the pixel circuit. FIG. 15 is a timing chart showing an operation example of the pixel circuit according to the first modified example of the present invention. FIG. 16 is a diagram illustrating a circuit that is a premise of the pixel circuit included in the image display device according to the second modification of the present invention. FIG. 17 is a circuit diagram illustrating a configuration example of a pixel circuit included in an image display device according to a second modification of the present invention.

<Terminology>
In the present specification, the term “electrically connected” means that one member and the other member are always connected in a conductive manner via wiring or the like, and one member and the other member Is used in a sense that includes not only conductive wiring and the like, but also a mode of being indirectly connected by other members. In other words, the term “electrically connected” means that one member and the other member are connected to each other depending on the state of other members (for example, a conductive state in which a current can flow between the source and the drain of the transistor). Is used in a meaning including a mode in which the wiring is conductively connected by wiring and other members.

In addition, “gate voltage” in this specification refers to a potential difference between a source and a gate with respect to a source potential with respect to a transistor.

In addition, “threshold voltage” in this specification refers to a threshold voltage of a transistor. The threshold voltage of a transistor refers to a gate voltage that serves as a boundary when the transistor changes from an off state (a state where a drain current does not flow) to an on state (a state where a drain current flows). Note that the “threshold voltage” is abbreviated as “threshold” as appropriate.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Points of interest regarding the first embodiment>
FIG. 1 is a circuit diagram illustrating the configuration of a pixel circuit 7 included in the image display device 100 according to the first embodiment of the invention. In the image display device 100, a plurality of pixel circuits 7 are arranged in a matrix.

As shown in FIG. 1, the pixel circuit 7 includes an organic EL element (OLED) 1, a drive transistor 2, a threshold (V _th ) compensation transistor 3, and a capacitor 4.

The OLED 1 has a first electrode 1a and a second electrode 1b, and is a light emitting element whose light emission luminance is adjusted by the amount of current flowing between the light emitting layer, that is, the first electrode 1a and the second electrode 1b. The first electrode 1a is electrically connected to a power supply line (here, V _DD line L _vd ) that becomes a high potential side when the OLED 1 emits light. On the other hand, the second electrode 1b is electrically connected via the driving transistor 2 to a power supply line (here, the V _SS line L _vs ) that is on the low potential side when the OLED 1 emits light. That is, a potential difference required for light emission of the OLED 1 is given between both poles of the OLED 1 by the V _DD line L _vd and the V _SS line L _vs.

The driving transistor 2 is electrically connected in series to the OLED 1 and controls the light emission luminance of the OLED 1 by adjusting the current flowing through the OLED 1. Here, the driving transistor 2 is a thin film transistor (TFT: Thin Film Transistor) which is a type of field effect transistor (FET: Field Metal Effect Semiconductor) adopting a MIS (Metal Metal Insulator Semiconductor) structure in which carriers are electrons. ), That is, an n-MISFET TFT.

Specifically, the drive transistor 2 has third to fifth electrodes 2ds, 2sd, and 2g. The third electrode 2ds is electrically connected to the second electrode 1b of the OLED 1, and serves as a drain electrode (hereinafter abbreviated as "drain") when the OLED 1 emits light, that is, when a forward current flows through the OLED 1. Function. However, the third electrode 2ds functions as a source electrode (hereinafter abbreviated as “source”) when a current flows in the opposite direction to the OLED 1. The fourth electrode 2sd is electrically connected to the V _SS line L _{vs and} functions as a source when a forward current flows through the OLED 1. However, the fourth electrode 2 sd functions as a drain when a current flows in the opposite direction to the OLED 1. The fifth electrode 2 g is a so-called gate electrode (hereinafter abbreviated as “gate”), and is electrically connected to one electrode (the ninth electrode 4 a) of the capacitor 4.

In the driving transistor 2, when the OLED 1 emits light, the potential applied to the fifth electrode 2g, more specifically, between the third electrode 2ds or the fourth electrode 2sd and the fifth electrode 2g (that is, between the gate and the source). ) Is adjusted, the amount of current flowing between the third electrode 2ds and the fourth electrode 2sd (hereinafter also referred to as “between the third and fourth electrodes”) is adjusted. The Then, the potential applied to the fifth electrode 2g causes the drive transistor 2 to be in a state where current can flow between the third and fourth electrodes (conductive state) and a state where current cannot flow (non-conductive state). Set selectively.

The V _th compensation transistor 3 detects a lower limit value (predetermined threshold voltage V _th ) of the potential of the fifth electrode 2g with respect to the fourth electrode 2sd of the drive transistor 2 when the drive transistor 2 is in a conductive state. The gate voltage of the driving transistor 2 is adjusted to a threshold voltage V _th (hereinafter abbreviated as “threshold V _th ”). Here, the V _th compensation transistor 3 is also composed of an n-MISFET TFT as in the case of the drive transistor 2.

The V _th compensation transistor 3 has sixth to eighth electrodes 3ds, 3sd, and 3g. The sixth electrode 3ds is conductively connected to a wiring that electrically connects the third electrode 2ds of the drive transistor 2 and the second electrode 1b of the OLED 1. The seventh electrode 3sd is conductively connected to a wiring that electrically connects the fifth electrode (gate) 2g of the drive transistor 2 and the ninth electrode 4a of the capacitor 4 at the connection point T1. The eighth electrode 3g is a so-called gate electrode and is electrically connected to the scanning signal line L _ss .

Further, in the V _th compensation transistor 3, the potential applied to the eighth electrode 3g, more specifically, between the sixth electrode 3ds or the seventh electrode 3sd and the eighth electrode 3g (that is, between the gate and the source). By adjusting the applied voltage, the amount of current flowing between the sixth electrode 3ds and the seventh electrode 3sd (hereinafter also referred to as “between the sixth and seventh electrodes”) is adjusted. The potential applied to the eighth electrode 3g causes the V _th compensation transistor 3 to have a state in which a current can flow between the sixth and seventh electrodes (between the drain and the source) (conductive state) and It is selectively set to a state where it cannot flow (non-conducting state).

Here, since the light emission luminance of the OLED 1 is controlled by the current value, the light emission luminance fluctuates sensitively to fluctuations in the gate voltage of the drive transistor 2 during light emission. In particular, when the driving transistor 2 is configured using amorphous silicon, the threshold V _th tends to be different for each driving transistor 2. Therefore, if a function for compensating a different threshold V _th for each pixel (V _th compensation function) is not provided, there is a slight divergence between the desired light emission luminance and the actual light emission luminance, resulting in light emission between pixels. Uneven brightness will occur.

Therefore, the pixel circuit 7 is provided with a V _th compensation transistor 3 that is electrically connected to the drive transistor 2 and compensates the threshold V _th of the drive transistor 2. By V _th compensation transistor 3, before emission by combining once the gate voltage of the driving transistor 2 of each pixel to the threshold V _th, V _th compensation function of compensating for variations in the threshold V _th of the drive transistor 2 is realized Is done.

Capacitor 4 is provided with a ninth electrode 4a is electrically connected to the fifth electrode 2g of the driving transistor 2, and a tenth electrode 4b which is electrically connected to the image signal line L _IS . Here, the retention capacity of the capacitor 4 and the predetermined value C _s.

Incidentally, the OLED 1 functions as a capacitor when a voltage opposite to that during light emission is applied. The capacitance (EL element capacitor) and a predetermined value C _o. The drive transistor 2 includes a parasitic capacitance C _gsTd between the fourth electrode 2sd and the fifth electrode 2g (hereinafter also referred to as “between the fourth and fifth electrodes”), and a third electrode 2ds and a fifth electrode 2g. And a parasitic capacitance C _gdTd (hereinafter also referred to as “between the third and fifth electrodes”). Further, the V _th compensation transistor 3 includes a parasitic capacitance C _gsTth between the seventh electrode 3sd and the eighth electrode 3g (hereinafter also referred to as “between the seventh and eighth electrodes”), the sixth electrode 3ds, and the eighth electrode. And a parasitic capacitance C _gdTth between 3 g (hereinafter also referred to as “between the _sixth and _eighth electrodes”). The parasitic capacitances C _gsTd , C _gdTd , C _gsTth , and C _gdTth are determined by the configurations of the drive transistor 2 and the V _th compensation transistor 3, respectively.

In Figure 1, the circuit configuration of the pixel circuit 7 (described in FIG thick line), the parasitic capacitance _{_{_{C gsTth, C gdTth, C gsTd}}} , the circuit configuration according to the C _GdTd and EL element capacitor C _o (in the figure by a broken line Description) has been added.

As shown in Figure 1, in the pixel circuit 7, there is a capacitor (element capacitor) 1c having an EL element capacitance C _o between both electrodes of OLED1, parasitic between 4-5 electrode of the driving transistor 2 capacitor A capacitor 2gs having C _gsTd exists, a capacitor 2gd having a parasitic capacitance C _gdTd exists between the third and fifth electrodes of the driving transistor 2, and a parasitic between the _seventh and eighth electrodes of the V _th compensation transistor 3 exists. there is a capacitor 3gs with a capacity _C gsTth, is between 6-8 electrode of V _th compensation transistor 3 state equivalent to a state where the capacitor 3gd exists is generated having a parasitic capacitance _C gdTth.

Here, the description has been given focusing on one pixel circuit 7, but there are a large number of pixel circuits 7 in the entire image display apparatus. For this reason, there are a large number of scanning signal lines L _ss . Hereinafter, the multiple scanning signal lines L _ss are appropriately referred to as “Nth scanning signal line (N is a natural number) L _ss ”. Further, a common image signal line L _is is electrically connected for each column to a large number of pixel circuits 7 arranged in a matrix on the image display device, and a common scanning signal line L _ss is electrically connected for each row. Connected.

FIG. 2 is a timing chart illustrating a basic signal waveform (drive waveform) when the OLED 1 emits light. In FIG. 2, the horizontal axis indicates time, and in order from the top, (a) potential applied to the V _DD line L _vd (potential V _d ), (b) potential applied to the V _SS line L _vs (potential V _s ), (c) the potential of the signal applied to the first scanning signal line L _ss (potential V _sc1 ), (d) the potential of the signal applied to the second scanning signal line L _ss (potential V _sc2 ), ( e) A waveform of the potential (potential V _id ) of the signal applied to the image signal line Lis _is shown.

Further, in FIG. 2, there is shown a drive waveform for causing the light emitting once OLED1, duration of the one emission, sequentially time, C _s initialization period P1 (time t1 ~ t2), the preparation period P2 (time t2 to t3), _Vth compensation period P3 (time t3 to t4), writing period P4 (time t4 to t5), element initialization period P5 (time t5 to t6), and light emission period P6 (time t6) To). Since the potential V _id in the writing period P4 is an arbitrary value determined by the light emission luminance of each OLED 1, in FIG. 2, hatched hatching is added for convenience in the range where the potential can exist.

FIGS. 3 to 9 are diagrams illustrating the flow of current generated in the pixel circuit 7 in each period, paying attention to the pixel circuit 7 when driving the image display device according to the drive waveform shown in FIG. . 3 to 9, among the pixel circuits 7, circuits that contribute to the current flow are indicated by thick lines, and circuits that do not substantially contribute to the current flow are indicated by thin lines.

FIG. 3 illustrates the current flow of the pixel circuit 7 in the C _s initialization period P1 (hereinafter, abbreviated as “period P1” where appropriate).

In the period P1, a predetermined positive high potential V _DD (for example, 15V) is applied to the V _DD line L _vd and the V _SS line L _vs , respectively, and a predetermined positive high potential V _gH (for example, to all the scanning signal lines L _ss ). 18V) is applied, a predetermined reference potential to the image signal line L _iS (here, 0V) is applied. At this time, by the application of high voltage V _gH in the scanning signal line L _ss, positive potential corresponding to the high potential V _gH to the eighth electrode (gate) 3 g is applied, V _th compensation transistor 3 is rendered conductive. On the other hand, since the V _DD line L _vd and the V _SS line L _vs have substantially the same potential, the drive transistor 2 is substantially turned off, and the drive transistor 2 is turned off. Therefore, in the period P1, current flows from the V _DD line L _vd to the capacitor 4 via the sixth and seventh electrodes 3ds and 3sd of the V _th compensation transistor 3 as indicated by the white arrow in FIG. The capacitor 4 stores a predetermined amount of charge (for example, a charge amount corresponding to 15V).

FIG. 4 illustrates the current flow of the pixel circuit 7 in the preparation period P2 (hereinafter abbreviated as “period P2” as appropriate).

In the period P2, a negative predetermined potential −V _p (eg, −7 V) is applied to the V _DD line L _vd , a predetermined reference potential (here, 0 V) is applied to the V _SS line L _vs , and the entire scanning signal line L predetermined low potential V _gL (for example, -10 V) is applied to the _ss, given the high potential V _dH to the image signal line L _iS (e.g. 10V) is applied. At this time, by applying the low potential V _{gL to} the scanning signal line L _ss , almost no positive potential is applied to the eighth electrode (gate) 3g, so that the V _th compensation transistor 3 becomes non-conductive. On the other hand, the application of the high potential V _dH in the image signal line L _IS, positive potential corresponding to the high potential V _dH to the fifth electrode (gate) 2 g (e.g. 15 + 10 = 25V) is applied, the driving transistor 2 and the conducting state Become. Then, V for who _DD line L _vd V _SS line L _vs than the potential higher by V _p, as shown by a hollow arrow in FIG. 4, V _SS line fourth drive transistor 2 from L _vs, A current flows toward the OLED 1 through the three electrodes 2sd and 2ds. As a result, a predetermined amount of electric charge (for example, electric charge corresponding to 7V) corresponding to the potential difference between the V _DD line L _vd and the V _SS line L _vs is accumulated in the OLED 1, that is, the element capacitor 1 c.

FIG. 5 illustrates a current flow of the pixel circuit 7 in the _Vth compensation period P3 (hereinafter, abbreviated as “period P3” as appropriate).

In the period P3, a predetermined reference potential (0 V in this case) is applied to the V _DD line L _vd and the V _SS line L _vs , the high potential V _gH is applied to all the scanning signal lines L _ss , and the image signal line L _is A high potential V _dH (for example, 10 V) is applied to. At this time, by the application of high voltage V _gH in the scanning signal line L _ss, positive potential corresponding to the high potential V _gH to the eighth electrode (gate) 3 g is applied, V _th compensation transistor 3 is rendered conductive. When the V _th compensation transistor 3 becomes conductive, the capacitor 4 and the element capacitor 1c are short-circuited. Therefore, a current flows from the capacitor 4 toward the V _SS line L _vs via the sixth and seventh electrodes 3ds and 3sd of the V _th compensation transistor 3 and the third and fourth electrodes 2ds and 2sd of the driving transistor 2. . In addition, a current accompanying the charge accumulated in the element capacitor 1c also flows toward the V _SS line L _vs via the third and fourth electrodes 2ds and 2sd of the drive transistor 2.

However, as the current accompanying the charge accumulated in the capacitor 4 flows from the capacitor 4 toward the V _SS line L _vs , the charge accumulated in the capacitor 4 decreases. When the potential V _gs of the fifth electrode 2g with respect to the fourth electrode 2sd of the drive transistor 2 decreases substantially to the threshold value V _th , the drive transistor 2 becomes non-conductive. At this time, the capacitor 4 is in a state in which charges corresponding to the threshold value V _th are accumulated. As described above, in the period P3, the electric charge corresponding to the threshold value _Vth is accumulated in the capacitor 4, and the variation in the threshold value _Vth that is different for each pixel is compensated.

6 illustrates the current flow of the pixel circuit 7 in the writing period P4 (hereinafter, abbreviated as “period P4” where appropriate).

In the period P4, the reference potential 0V is applied to the V _DD line L _vd and the V _SS line L _vs , respectively, and the pixel to be subjected to processing (writing processing) for accumulating charges according to the gradation indicated by the image signal , The high potential V _gH is applied to the scanning signal line L _ss and the potential (V _dH −V _data ) is applied to the image signal line L _is . Note that the potential V _data is a potential corresponding to the gradation of each pixel indicated by the image signal. At this time, by the application of high voltage V _gH in the scanning signal line L _ss, positive potential corresponding to the high potential V _gH to the eighth electrode 3g is applied, V _th compensation transistor 3 is rendered conductive. On the other hand, since the potential (V _dH −V _data ) equal to or lower than the potential V _dH in the period P3 is applied to the image signal line L _is and the gate voltage becomes equal to or lower than the threshold V _th , the drive transistor 2 is in a non-conductive state. Become. Therefore, in the period P4, as indicated by a white arrow in FIG. 6, a current flows from the OLED 1 (that is, the element capacitor 1c) to the capacitor 4 via the sixth and seventh electrodes 3ds and 3sd of the _Vth compensation transistor 3. Flows. As a result, the charge corresponding to the potential V _data is added and stored on the charge corresponding to the threshold value V _th already stored in the capacitor 4.

Therefore, in the period P4, charges corresponding to the light emission luminance of the OLED 1 are accumulated in the capacitor 4 for each row of the plurality of pixel circuits 7. That is, in the period P4, the application of the high potential V _{gH to} the scanning signal line L _ss and the application of the potential (V _dH −V _data ) to the image signal line L _is cause the fifth electrode 2g in the plurality of pixel circuits 7. Are sequentially set.

In FIG. 7, the current flow when the pixel circuit 7 that has already been subjected to the writing process in the period P <b> 4 is being written in the pixel circuit 7 different from the pixel circuit 7 is illustrated. Yes.

Here, for example, the potential corresponding to the gradation related to the relatively high light emission luminance (for example, light emission luminance corresponding to white) _is applied to the image signal line Lis, and the pixel circuit 7 is written. After that, a potential corresponding to a gradation related to a relatively low light emission luminance (for example, light emission luminance corresponding to black) _is applied to the other pixel circuit 7 to the image signal line Lis, and the pixel circuit 7 is subjected to a writing process. Assume that is performed. At this time, since a relatively high potential close to the high potential V _dH _{is applied} to the image signal line Lis, the drive transistor 2 is connected via the capacitor 4 in the pixel circuit 7 in which the writing process has already been performed. The potential of the fifth electrode 2g is raised, and the driving transistor 2 becomes conductive. At this time, since the reference potential (for example, 0 V) is applied to both the V _DD line L _vd and the V _SS line L _vs , the OLED 1 does not emit light, but as shown by the white arrow in FIG. The electric charge accumulated in the element capacitor 1c is lost to the V _SS line L _vs.

FIG. 8 illustrates the current flow of the pixel circuit 7 in the element initialization period P5 (hereinafter, abbreviated as “period P5” where appropriate).

In the period P5, a predetermined negative potential −V _p is applied to the V _DD line L _vd and the V _SS line L _vs , a low potential V _gL is applied to all the scanning signal lines L _ss , and the image signal line L _is A high potential V _dE (V _dH −V _a , for example, V _a = 1V) is applied. At this time, the V _th compensation transistor 3 is turned off and the drive transistor 2 is turned on. Since there is no potential difference between the V _DD line L _vd and the V _SS line L _vs and the V _SS line L _vs is set to the negative potential −V _p , as shown by the white arrow in FIG. The charge accumulated in the OLED 1 (that is, the element capacitor 1c) passes through the V _SS line L _vs, and the charge accumulated in the OLED 1 is released. At this time, since the common low potential −V _p is applied to the V _DD line L _vd and the V _SS line L _vs , the OLED 1 does not emit light.

FIG. 9 illustrates the current flow of the pixel circuit 7 in the light emission period P6 (hereinafter abbreviated as “period P6” where appropriate).

In the period P6, the positive high potential V _DD is applied to the V _DD line L _vd and the reference potential 0 V is applied to the V _SS line L _vs in the plurality of pixel circuits 7 arranged in the entire image display device. The low potential V _gL is applied to the scanning signal line L _ss , and the high potential V _dE is applied to the image signal line L _is . At this time, the application of the low potential V _{gL to} the scanning signal line L _ss causes the V _th compensation transistor 3 to be turned off. Meanwhile, since the high potential V _dE is applied to the image signal line L _IS, the amount of charge accumulated in the capacitor 4 in the period P4 the potential amount corresponding V _gs corresponding to the (amount of charge corresponding to the potential V _data) It becomes higher than the threshold value _Vth , and the drive transistor 2 becomes conductive. That is, the image signal line L _IS, potential corresponding to the potential V _data corresponding to the gradation of the image signal indicates is given to the fifth electrode (gate) 2 g.

Since the V _DD line L _vd is higher than the V _SS line L _vs by the potential V _DD , the V _DD line L _vd and the V _SS line L _vs cause the first electrode 1a and the fourth electrode 2sd to be connected. A predetermined potential difference is applied between them. At this time, the potential of the fourth electrode 2sd is set relatively lower than the potential of the third electrode 2ds, the driving transistor 2 and a conductive state in which a current flows between the 3-4th electrode according to the potential V _data Become. For this reason, as indicated by a white arrow in FIG. 9, a current corresponding to the potential V _data flows through the OLED 1 and a current is supplied from the V _DD line L _vd to the OLED 1. As a result, the plurality of OLEDs 1 arranged in the entire image display device emit light at a luminance corresponding to an arbitrary potential V _data at the same time.

Here, the gate voltage V _gs of the driving transistor 2 when the OLED 1 emits light is expressed by the following equation (1) using constants α and d.

Further, the current I _ds flowing between the third and fourth electrodes (between the drain and the source) of the driving transistor 2 is expressed by the following equation (2) when a constant β is used.

Since the light emission luminance of the OLED 1 is substantially proportional to the current density (current density) flowing through the OLED 1, a desired light emission luminance can be obtained in each pixel by the control using the drive waveform shown in FIG.

The constant α shown in the above equation (1) _is a coefficient that gives the ratio of the change width of V _{gs to} the change width of the potential applied to the image signal line Lis. Also referred to as “efficiency”. Since the writing efficiency α in the pixel circuit 7 is affected by the parasitic capacitance, it is expressed by the following equation (3).

The constant d shown in the above equation (1) is expressed by the following equation (4), where V _o is the voltage applied between the first electrode 1a and the second electrode 1b of the OLED 1 during light emission. .

By the way, it is known that a TFT using amorphous silicon (amorphous silicon) deteriorates remarkably fast when driven in a linear region. For example, in the case of an n-type TFT, the state in the linear region means that the voltage between the source and the drain with reference to the source is V _ds , and the voltage V _gs between the source and the gate with reference to the source. , And the threshold voltage V _th , the relationship of the following expression (5) is established.

Therefore, in order to suppress the deterioration of the driving transistor 2, the driving transistor 2 should always be in the saturation region when the OLED 1 emits light, that is, the driving transistor 2 should be driven in a state where the relationship of the following expression (6) is satisfied.

However, in the state shown in FIGS. 7 and 8, the state of the driving transistor 2 is in the linear region. This is because the source and drain are at the same potential, whereas the gate is set at a sufficiently high potential to make the drive transistor 2 conductive. For this reason, for example, after a writing process related to a relatively high light emission luminance is performed in the pixel circuit 7 in the M-th row (M is a natural number), the pixel circuit 7 in the M + 1-th row and thereafter is related to a relatively low light emission luminance. When the writing process is performed, specifically, when a white graphic is displayed on a black background, the threshold value _Vth of the drive transistor 2 of the pixel circuit 7 that expresses white rapidly increases. Show a trend.

At this time, if the threshold value V _th exceeds a compensationable setting range, there occurs a problem that the light emission luminance of the pixel circuit 7 that should express white originally decreases. Then, the inventors of the present application can determine whether the driving transistor 2 is driven in the linear region even when the driving transistor 2 is about 1% of the period of one light emission for reproducing one frame. It has been found that the deterioration of is accelerated.

In response to such a problem, the inventors of the present application have created an image display device and a driving method thereof that can suppress deterioration of a transistor that adjusts light emission luminance. This will be described below.

<First Embodiment>
FIG. 10 is a block diagram illustrating a schematic configuration of the image display apparatus 100 according to the first embodiment of the invention.

As shown in FIG. 10, the image display device 100 includes a transmission / reception unit 10, a control unit 20, an operation unit 40, a display panel 50, an X driver X _d , and a dedicated driver S _d . Examples of the image display device 100 include various electronic devices such as a mobile phone having a display screen.

The transmission / reception unit 10 receives an image signal from an external device and sends it to the control unit 20. The image signal includes a signal (pixel data signal) indicating the gradation of each pixel.

The control unit 20 is a part that performs overall control of the operation of the image display apparatus 100. The control unit 20 includes, for example, a CPU, a RAM, and a ROM, and various operations and controls are realized by the CPU reading and executing a program stored in the ROM. The control unit 20 is, for example, a function that performs so-called γ conversion on the image signal (γ conversion function), a function that controls transmission of signals from the X driver X _d , and the dedicated driver S _d (timing control function). have. Note that the various functions of the control unit 20 may be appropriately realized by a dedicated logic circuit.

The operation unit 40 includes various buttons such as a so-called numeric keypad, and sends various signals to the control unit 20 when the various buttons are pressed.

The display panel 50 is configured by arranging a plurality of pixel circuits 7 shown in FIG. 1 in a grid pattern. As shown in FIG. 10, a common image signal line Lis _is electrically connected to the plurality of pixel circuits 7 arranged in the row direction, and the plurality of pixel circuits 7 arranged in the row direction are connected. The common scanning signal line L _ss is electrically connected.

X driver X _d, in response to a signal from the control unit 20 supplies a potential corresponding to the pixel data signals to the image signal line L _IS. Incidentally, the control unit 20, for example, in synchronization with the image signal transmitted from an external device, a signal for controlling the supply timing of the potential corresponding the X driver X _d in the pixel data signals for each image signal line L _IS Send to X driver _Xd .

Here, each image signal line Lis _is a portion (corresponding to a potential setting unit) that sequentially sets the potential of the fifth electrode 2g that adjusts the light emission luminance of the OLED 1 in the plurality of pixel circuits 7 based on the image signal. ). Here, the potential of the fifth electrode 2g of each pixel circuit 7 is sequentially set for each row of the pixel circuits 7 sequentially arranged from the upper part to the lower part of the display panel 50. More specifically, after the potential of the fifth electrode 2g is set in the pixel circuit 7 (corresponding to the first pixel circuit) arranged relatively on the upper side, the pixels arranged relatively on the lower side In the circuit 7 (corresponding to the second pixel circuit), the potential of the fifth electrode 2g is set.

The dedicated driver S _d applies a potential to the V _DD line L _vd , the V _SS line L _vs , and the scanning signal line L _ss with a waveform corresponding to the control signal from the control unit 20. The dedicated driver S _d is configured to include first to third shift registers, and specifically, based on data stored in the first to third shift registers, the V _DD line L _vd , the V _SS line L _vs , And has a function of applying a potential to the scanning signal line L _ss .

Therefore, here, only the driver S _d is, by giving a predetermined potential difference between the first electrode 1a and the fourth electrode 2sd, corresponds to a portion (light emission control unit for emitting a plurality of OLED1 the same time ). Further, the scanning signal line L _ss functions as a part that adjusts the timing at which the potential of the fifth electrode 2g is sequentially set by each image signal line L _is based on the image signal. Here, by the application of a potential difference due to the dedicated driver S _d, and OLED1 contained relatively pixel circuit 7 which is arranged in the upper portion of the display panel 50 (corresponding to the first pixel circuit), relatively The OLED 1 included in the pixel circuit 7 (corresponding to the second pixel circuit) arranged in the lower part emits light at the same time.

FIG. 11 is a timing chart illustrating an operation of the pixel circuit 7 included in the image display device 100 according to the first embodiment of the present invention, specifically, a signal waveform (driving waveform) when the OLED 1 emits light. . In FIG. 11, as in FIG. 2, the horizontal axis indicates time, and in order from the top, (a) the potential V _d applied to the V _DD line L _vd and (b) the potential applied to the V _SS line L _vs. V _s , (c) signal potential V _sc1 applied to the first scanning signal line L _ss , (d) signal potential V _sc2 applied to the second scanning signal line L _ss , (e) image signal line L the potential V _id of the signal applied to the _iS, the waveforms are shown.

In the timing chart shown in FIG. 11, the potential V _d, the potential V _sc1, the signal waveform of the potential V _sc2, and potential V _id, which is the same as that shown in FIG. 2, the time t4 ~ t6 potential V _s The signal waveforms at are different. Specifically, in the period P _u from the end of the V _th compensation period P3 to the start of the emission period P6, the potential V _s is set to a high potential V _DD. Specifically, the potential V _s of the V _SS line L _vs is set to a potential sufficiently higher than the potential V _d of the V _DD line L _ds .

That is, by switching the potential V _s of the V _SS line L _vs, the potential applied to the fourth electrode 2sd is adjusted to be higher than the potential set at the time of light emission, and the first electrode 1a and the second electrode 2sd are adjusted. A potential difference in the opposite direction to that when the OLED 1 emits light is applied between the electrode 1b and the electrode 1b. At this time, the potential difference between the fifth electrode 2g and the fourth electrode 2sd is adjusted to a value different from the potential difference set during light emission.

Then, the gate voltage of the driving transistor is adjusted by the V _SS line L _vs (corresponding to the potential adjustment unit), so that in each pixel circuit 7, after the gate potential is set in the writing period P4, in the light emission period P6. During the period before the light emission of the plurality of OLEDs 1 starts, the state of the drive transistor 2 is maintained in the saturation region. At this time, the state of the driving transistor 2 is maintained in the saturation region when the voltage V _ds between the drain and the source is maintained if the potential of the fourth electrode 2sd is sufficiently higher than the potential of the third electrode 2ds. This is because it becomes sufficiently large and the above equation (6) is always satisfied.

Here, in order to be set to any potential potential V _id of the image signal line L _IS state of the driving transistor 2 does not enter the linear region in the writing period P4, V _th compensation period From the end of P3 to the start of the light emission period P6, the potential V _s of the V _SS line L _vs is set to the high potential V _DD .

Here, the level of sufficiently increasing the potential V _s of the V _SS line L _vs satisfies, for example, the relationship of the following expression (7) when the maximum value of the gate potential V _g of the driving transistor 2 is V _gmax. Degree.

Here, when the above equation (7) is established, the fourth electrode 2sd on the V _SS line L _vs side of the drive transistor 2 functions as a drain, and the state of the drive transistor 2 becomes a saturation region.

In the pixel circuit 7, the gate potential of the driving transistor 2 is maximized when the potential V _id of the image signal line Lis _is set to 0 V in accordance with the maximum gradation (for example, white gradation) for a certain pixel. performs write processing, then, the minimum gradation for the other pixels (e.g., gradation of black) the potential V _id of the image signal line L _iS according to set to a high potential V _dH when performing write processing is there. At this time, V _gmax is expressed by the following equation (8).

In order to satisfy the relationship of the above equation (7), the relationship of the following equations (9) to (11) may be satisfied.

Here, for _{_{example, V dH = 10V, V gL}} = -10V, V gH = 15V, C o = 300fF, C s = 100fF, C gsTth = C gdTth = 10fF, When a _{_C} gsTd = C gdTd = 20fF If the relationship of V _s > 3.5 V is established, the relationships of the above equations (9) to (11) are satisfied. At this time, if the potential of the second electrode 1b of the OLED 1 is less than (V _g −V _th ), a current flows from the V _SS line L _vs to the OLED 1 through the driving transistor 2, but the OLED 1 When a voltage opposite to that at the time of light emission is applied, it functions as a capacitor and therefore does not emit light. That is, sufficiently increasing the potential V _s at the period P _u, does not adversely particularly noticeable negative impact on the emission behavior of OLED1.

As described above, in the image display device 100 according to the first embodiment of the present invention, the driving transistor 2 is driven to adjust the light emission luminance of the OLED 1 by adjusting the potential of the source side during light emission. The state of the driving transistor 2 is maintained in the saturation region from the time when the gate potential V _g of the transistor 2 is set to before the OLED 1 emits light. For this reason, the malfunction which drives in the state in which the state of the drive transistor 2 entered into the linear area | region is avoided as much as possible, and deterioration of the drive transistor 2 which adjusts light-emitting luminance is suppressed.

In addition, by changing the drive waveform without adding a special element or the like, a problem that the state of the drive transistor 2 is driven in a linear region is avoided. For this reason, it is possible to suppress deterioration of the drive transistor 2 that adjusts the light emission luminance with a simple configuration.

Second Embodiment
In the image display device 100 according to the first embodiment, the gate voltage of the drive transistor 2 is adjusted by changing the drive waveform, and the plurality of OLEDs 1 in the light emission period P6 after the gate potential is set in the write period P4. During the period before the start of light emission, the state of the driving transistor 2 was maintained in the saturation region.

On the other hand, in the image display device 100A according to the second embodiment of the present invention, by appropriately adding a capacitor to the pixel circuit 7 shown in FIG. 1, the light emission period after the gate potential is set in the writing period P4. The state of the drive transistor 2 is maintained in the saturation region during the period before the light emission start of the plurality of OLEDs 1 in P6.

Here, the schematic configuration of the image display device 100A according to the second embodiment of the present invention is substantially the same as that of the image display device 100 according to the first embodiment shown in FIG. However, in the image display device 100A, as compared with the image display device 100, the pixel circuit 7 is changed to a pixel circuit 7A to which a capacitor is appropriately added, and the display panel 50 has a plurality of pixel circuits 7A arranged in a matrix. The display panel 50A is changed, and the control unit 20 is changed to a control unit 20A having a different drive waveform control. Therefore, in the following, in the image display device 100A according to the second embodiment, the same parts as those of the image display device 100 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. explain.

FIG. 12 is a circuit diagram illustrating the configuration of a pixel circuit 7A included in the image display device 100A according to the second embodiment of the invention.

As shown in FIG. 12, the pixel circuit 7A is obtained by adding two

capacitors

5 and 6 to the pixel circuit 7 according to the first embodiment shown in FIG.

The capacitor 5 has a predetermined capacitance C _ft and is provided between the fifth electrode (gate) 2g of the driving transistor 2 and the scanning signal line L _ss . The capacitor 5 has an eleventh electrode 5a and a twelfth electrode 5b. The eleventh electrode 5a electrically connects the fifth electrode (gate) 2g of the driving transistor 2 and the ninth electrode 4a of the capacitor 4. It is electrically connected to the wiring to be conducted. That is, the eleventh electrode 5a is electrically connected to the fifth electrode 2g. The twelfth electrode 5b is electrically connected to the scanning signal line L _ss .

The capacitor 6 has a predetermined capacitance C _vdd and is provided between the fifth electrode (gate) 2g of the driving transistor 2 and the V _DD line L _vd . The capacitor 6 has a thirteenth electrode 6a and a fourteenth electrode 6b, and the thirteenth electrode 6a electrically connects the fifth electrode (gate) 2g of the driving transistor 2 and the ninth electrode 4a of the capacitor 4. It is electrically connected to the wiring to be conducted. That is, the thirteenth electrode 6a is electrically connected to the fifth electrode 2g. The fourteenth electrode 6b is electrically connected to the V _DD line L _vd .

Further, in the image display device 100A according to the second embodiment, the signal waveform (drive waveform) when the OLED 1 emits light is the same as that shown in FIG.

Here, the principle that the state of the drive transistor 2 is maintained in the saturation region during the period from the setting of the gate potential in the writing period P4 to the start of light emission of the plurality of OLEDs 1 in the light emission period P6 will be described.

In the image display device 100A, due to the presence of the capacitor 5 provided between the fifth electrode 2g of the drive transistor 2 and the scanning signal line L _ss , each scanning signal line L _ss is set at the end of the V _th compensation period P3. As the potential decreases from the high potential V _gH to the low potential V _gL , the potential (gate potential) of the fifth electrode 2g greatly decreases. In the image display device 100A, the capacitance C _ft is appropriately set, and the potential (gate potential) of the fifth electrode 2g does not exceed the value of the threshold voltage V _th even when the potential V _id at the time of writing processing increases. It has a configuration like this. However, merely lowering the gate potential due to the presence of the capacitor 5 causes a decrease in the light emission luminance of the OLED 1, but in the image display device 100A, the capacitance of the capacitor 6 between the V _DD line L _vd and the fifth electrode 2g. C _vdd is appropriately set, and the gate potential of the driving transistor 2 during light emission is appropriately increased by using the potential V _d of the V _DD line L _vd that rises at the start of the light emission period P6. Yes.

In the plurality of pixel circuits 7A included in the image display device 100A, it is sufficient to always satisfy the relationship of the following expression (12) from the end of the _Vth compensation period P3 to the start of the light emission period P6.

Thus, in the image display device 100A, the capacitor 5 and the capacitor 6 function as a portion (corresponding to a potential adjustment unit) that adjusts the gate voltage of the drive transistor 2 by adjusting the potential of the fifth electrode 2g. To do.

In such a configuration, the maximum value V _gmax of the gate potential of the driving transistor 2 is expressed by the following equation (13).

Note that a in the above equation (13) is represented by the following equation (14).

Here, for _{_{example, V dH = 10V, V gL}} = -10V, V gH = 15V, C o = 300fF, C s = 100fF, C gsTth = C gdTth = 10fF, C gsTd = C gdTd = 20fF, C ft = Assume that 18 fF and V _DD = 15V.

Comparing each potential in the V _th compensation period P3 and each potential in the light emission period P6, the potential of the scanning signal line L _ss decreases from the high potential V _gH to the low potential V _gL , and the potential V of the V _DD line L _vs. _d rises from 0V to the high potential V _DD . At this time, since V _gH = 15V, V _gL = −10V, and V _DD = 15V, the potential change of the scanning signal line L _ss is −25V, and the potential change of the V _DD line L _vs is 15V. Therefore, C _all 'When _{_{= C s + C gsTth + C}} gdTd + C gsTd + C ft + C vdd, the change of the gate potential V _g with the potential change of the scanning signal line L _ss _{_{may, -25 × C ft / C all}} ', The change in the gate potential V _g accompanying the change in the potential of the V _DD line L _vd is 15 × C _vdd / C _all ′. Therefore, in order to match the amount of increase in the gate potential V _g by the reduction amount and the capacitance C _vdd of the gate potential V _g by volume C _ft, if established relationship _{C vdd = (25/15) × C} ft it may may be a _{C vdd = (25/15) × C} ft = 30fF. At this time, V _gmax −V _th = −0.327 V, which satisfies the relationship of the above equation (12).

As described above, in the image display device 100A according to the second embodiment of the present invention, in order to adjust the light emission luminance of the OLED 1 by adjusting the gate potential of the driving transistor 2 due to the presence of the

capacitors

5 and 6. The state of the driving transistor 2 is maintained in the saturation region from the time when the gate potential V _g of the driving transistor 2 is set to before the OLED 1 emits light. For this reason, similarly to the first embodiment, the problem of driving in a state where the state of the driving transistor 2 is in the linear region is avoided as much as possible, and deterioration of the driving transistor 2 that adjusts the light emission luminance is suppressed.

Further, as compared with the first embodiment, the deterioration of the drive transistor 2 that adjusts the light emission luminance is suppressed without performing complicated potential control.

It should be noted that the present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention.

<First Modification>
In the pixel circuit 7 according to the first embodiment, the drive transistor 2 and the _Vth compensation transistor 3 are both n-type transistors, but the present invention is not limited to this. For example, a p-type transistor may be employed instead of an n-type transistor. As the p-type transistor employed here, a thin film transistor (FET) which is a type of field effect transistor (FET) adopting a MIS (Metal Insulator Semiconductor) structure in which a carrier is a hole (p-type). Any TFT (Thin Film Transistor), that is, a p-MISFET TFT may be used.

Hereinafter, a specific example in which a p-type transistor is employed, that is, an image display device 100B according to a first modification of the present invention will be described.

Here, the schematic configuration of the image display device 100B according to the first modification of the present invention is substantially the same as that of the image display device 100 according to the first embodiment shown in FIG. However, the image display device 100B is changed to the pixel circuit 7B in which the transistor type of the pixel circuit 7 is changed as compared with the image display device 100, and the display panel 50 has a plurality of pixel circuits 7B arranged in a matrix. The display panel 50B is changed, and the control unit 20 is changed to a control unit 20B having a different drive waveform control. Therefore, in the following, in the image display device 100B according to the first modification, the same parts as those of the image display device 100 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. explain.

FIG. 13 is a circuit diagram illustrating the configuration of the pixel circuit 7B included in the image display device 100B according to the first modification of the present invention.

As shown in FIG. 13, the pixel circuit 7B is different from the pixel circuit 7 shown in FIG. 1 in that the OLED 1 is changed to the OLED 1B, the drive transistor 2 is changed to the drive transistor 2B, and the V _th compensation transistor 3 is The V _th compensation transistor 3B is changed.

Specifically, in the OLED 1B, the first electrode 1a and the second electrode 1b of the OLED 1 are changed to the first electrode 1aB and the second electrode 1bB, respectively. However, the first electrode 1aB is electrically connected to the V _DD line L _vd that is on the low potential side when the OLED 1B emits light, and the second electrode 1bB is the V _SS line L that is on the high potential side when the OLED 1B emits light. It is electrically connected to _vs via the drive transistor 2B. Incidentally, OLED1b functions as a capacitor (element capacitor) 1CB with the voltage of the light emitting time of the reverse is applied capacitance C _o.

In the driving transistor 2B, the third to fifth electrodes 2ds, 2sd, and 2g of the driving transistor 2 are changed to third to fifth electrodes 2dsB, 2sdB, and 2gB, respectively. The third electrode 2dsB is electrically connected to the second electrode 1bB of the OLED 1B. The fourth electrode 2sdB is electrically connected to the V _SS line L _vs. The fifth electrode 2gB is a gate and is electrically connected to the ninth electrode 4a of the capacitor 4. In the driving transistor 2B, a capacitor 2gsB having a predetermined parasitic capacitance exists between the 4th and 5th electrodes, and this is equivalent to a state where a capacitor 2gs having a predetermined parasitic capacitance exists between the 3rd and 5th electrodes. A condition occurs.

The V _th compensation transistor 3B is obtained by changing the sixth to eighth electrodes 3ds, 3sd, and 3g of the V _th compensation transistor 3 to sixth to eighth electrodes 3dsB, 3sdB, and 3gB, respectively. The sixth electrode 3dsB is electrically connected to the second electrode 1bB of the OLED 1B. The seventh electrode 3sdB is electrically connected to the fifth electrode 2g. The eighth electrode 3gB is a gate and is electrically connected to the scanning signal line L _ss . In the V _th compensation transistor 3B, a capacitor 3gsB having a predetermined parasitic capacitance exists between the seventh and eighth electrodes, and a capacitor 3gdB having a predetermined parasitic capacitance exists between the sixth and eighth electrodes. A state equivalent to the state occurs.

FIG. 14 is a timing chart illustrating a basic signal waveform (drive waveform) when the OLED 1B simply emits light. FIG. 15 is a timing chart illustrating the operation of the pixel circuit 7B included in the image display device 100B according to the first modification of the present invention, specifically, the signal waveform (driving waveform) when the OLED 1B emits light. It is.

14 and 15, as in FIG. 2, the horizontal axis indicates time, and in order from the top, (a) the potential V _d applied to the V _DD line L _vd and (b) the voltage applied to the V _SS line L _vs. Potential V _s , (c) signal potential V _sc1 applied to the first scanning signal line L _ss , (d) signal potential V _sc2 applied to the second scanning signal line L _ss , (e) image the signal line L of the signal applied to _is the potential V _id, the waveforms are respectively shown.

In the timing chart relating to the basic operation shown in FIG. 14, the signal waveforms of the potential V _d , the potential V _s , the potential V _sc1 , the potential V _sc2 , and the potential V _id are changed from those shown in FIG. The signal waveform is simply reversed.

In the timing chart according to the first modification shown in FIG. 15, the signal waveforms of the potential V _d , the potential V _sc1 , the potential V _sc2 , and the potential V _id are the same as those shown in FIG. The signal waveforms at times t4 to t6 of _s are different. Specifically, in the period Pd from the end of the V _th compensation period P3 to the start of the light emission period P6, the potential V _s of the V _SS line L _vs is set to the low potential −V _DD . Specifically, the potential V _s of the V _SS line L _vs is set to a potential sufficiently lower than the potential V _d of the V _DD line L _ds .

By switching the potential V _s of the V _SS line L _{vs in} this way, the potential applied to the fourth electrode 2sdB is adjusted to be lower than the potential set at the time of light emission, and the first electrode 1aB and the first electrode A potential difference in the opposite direction to that when the OLED 1B emits light is applied between the two electrodes 1bB. At this time, the gate voltage of the drive transistor 2B is adjusted to a value different from the potential difference set during light emission.

Then, by adjusting the gate voltage of the driving transistor 2B, driving is performed in each pixel circuit 7B during the period from the setting of the gate potential in the writing period P4 to the start of light emission of the plurality of OLEDs 1B in the light emitting period P6. The state of the transistor 2B is maintained in the saturation region. Therefore, even in the image display device 100B according to the first modification, the same effect as in the first embodiment can be obtained.

<Second Modification>
In the second embodiment, in the pixel circuit in which the OLED 1 is electrically connected between the V _DD line L _vs and the driving transistor 2, the capacitor 5 is interposed between the scanning signal line L _ss and the fifth electrode 2g. And the capacitor 6 is provided between the V _DD line L _vd and the fifth electrode 2g, but is not limited thereto. In the pixel circuit in which the OLED and the drain and source of the driving transistor are connected in series, a capacitor is provided between the signal line electrically connected to the gate of the V _th compensation transistor and the gate of the driving transistor. In addition, other configurations may be used as long as a capacitor is provided between the V _DD line L _vd and the gate of the driving transistor. As another pixel circuit in which the drain and the source of the OLED and the driving transistor are connected in series, for example, a pixel circuit in which the OLED is electrically connected between the V _SS line L _vs and the driving transistor can be considered. .

Hereinafter, an example of a pixel circuit in which the OLED is electrically connected between the V _SS line L _vs and the driving transistor will be described first, and then an image display device including a pixel circuit to which two capacitors are added, that is, An image display device 100C according to a second modification of the present invention will be described.

FIG. 16 is a diagram illustrating a pixel circuit 700 in which the OLED 1C is electrically connected between the V _SS line L _vs and the driving transistor 2C. In FIG. 16, attention is paid to one pixel circuit 700, but a large number of pixel circuits 700 are arranged in a matrix in the image display device. Note that, here, a common image signal line L _is electrically connected to each row and a common scanning signal line L _ss is electrically connected to each column with respect to a large number of pixel circuits 700.

As shown in FIG. 16, the pixel circuit 700 includes an OLED 1C, a driving transistor 2C, a V _th compensation transistor 3C, a capacitor 4C, a scanning transistor 5C, and a capacitor 6C.

The OLED 1C is a light emitting element that includes a first electrode 1bC and a second electrode 1aC, and the light emission luminance is adjusted by the amount of current flowing between the light emitting layer, that is, the first electrode 1bC and the second electrode 1aC. The first electrode 1bC is electrically connected to a power supply line (here, the V _SS line L _vs ) that is on the low potential side when the OLED 1C emits light. On the other hand, the second electrode 1aC is electrically connected via a driving transistor 2C to a power supply line (here, V _DD line L _vd ) that is on the high potential side when the OLED 1C emits light. The OLED 1C functions as a capacitor when a voltage opposite to that during light emission is applied. The capacitance (EL element capacitance) and a predetermined value C _o, 16, the circuit configuration of the pixel circuit 700 with respect to (described in FIG thick line), the circuit arrangement according to the EL element capacitance C _o (described dashed line in the drawing ) Has been added.

The driving transistor 2C is electrically connected in series to the OLED 1C, and controls the light emission luminance of the OLED 1C by adjusting the current flowing through the OLED 1C. Here, the drive transistor 2C is configured by an n-type transistor (for example, n-MISFET TFT).

The drive transistor 2C has third to fifth electrodes 2sdC, 2dsC, and 2gC. The third electrode 2sd is electrically connected to the second electrode 1aC of the OLED 1C, and the fourth electrode 2ds is electrically connected to the V _DD line L _vd . The fifth electrode 2gC is a gate and is electrically connected to one electrode (the ninth electrode 4aC) of the capacitor 4C.

In the driving transistor 2C, the amount of current flowing between the gate and the source is adjusted by adjusting the potential applied to the fifth electrode 2gC, specifically, the gate voltage applied between the gate and the source. Is adjusted. Then, depending on the potential applied to the fifth electrode 2g, the driving transistor 2C selects between a state where current can flow between the gate and the source (conductive state) and a state where current cannot flow (non-conductive state). Is set automatically.

The V _th compensation transistor 3C detects a lower limit value (predetermined threshold voltage V _th ) of the potential of the fifth electrode 2g with respect to the third electrode 2sd of the drive transistor 2C when the drive transistor 2C is in a conductive state. The gate voltage of the drive transistor 2C is adjusted to the threshold voltage V _th (threshold V _th ).

The V _th compensation transistor 3C is electrically connected to the drive transistor 2C and compensates for the threshold V _th of the drive transistor 2C. The _Vth compensation transistor 3C has sixth to eighth electrodes 3sdC, 3dsC, and 3gC. The sixth electrode 3sdC is conductively connected to a wiring that electrically connects the third electrode 2sd of the drive transistor 2C and the second electrode 1aC of the OLED 1C. The seventh electrode 3dsC is conductively connected to a wiring that electrically connects the fifth electrode 2gC of the drive transistor 2C and the ninth electrode 4aC of the capacitor 4C. The eighth electrode 3gC is a gate electrode, and is electrically connected to a signal line (compensation signal line) L _th for applying the gate potential of the V _th compensation transistor 3C.

Capacitor 4C has a predetermined storage capacitor C _s, and a ninth electrode 4aC a tenth electrode 4bc. The ninth electrode 4aC is electrically connected to the fifth electrode 2gC of the drive transistor 2C. On the other hand, the tenth electrode 4bC is electrically connected to the eleventh electrode 5sdC of the scanning transistor 5C and the fifteenth electrode 6bC of the capacitor 6C.

The scanning transistor 5C controls the timing of the writing process in each pixel circuit 700 arranged in the image display device. The scanning transistor 5C includes eleventh to thirteenth electrodes 5sdC, 5dsC, and 5gC. The eleventh electrode 5sdC is electrically connected to the tenth electrode 4bC of the capacitor 4C and the fifteenth electrode 6bC of the capacitor 6C. 12 electrode 5dsC is electrically connected to the image signal line L _IS. The thirteenth electrode 5gC is electrically connected to the scanning signal line L _ss .

The capacitor 6C has a predetermined holding capacity C _s 2 and has a fourteenth electrode 6aC and a fifteenth electrode 6bC. The fourteenth electrode 6aC is electrically connected to the third electrode 2sdC of the drive transistor 2C and the second electrode 1aC of the OLED 1C. On the other hand, the fifteenth electrode 6bC is electrically connected to the tenth electrode 4bC of the capacitor 4C and the eleventh electrode 5sdC of the scanning transistor 5C.

In the pixel circuit 700 having the above-described configuration, as in the case described with reference to FIGS. 1 to 9, the driving is performed after the threshold V _th of the driving transistor 2C is compensated until the OLED 1C emits light. The state of the transistor 2C becomes a linear region, and the drive transistor 2C tends to deteriorate rapidly.

Therefore, in the image display device 100C according to the second modification of the present invention, the compensation signal line L _th and the drive transistor that are electrically connected to the gate of the V _th compensation transistor 3C with respect to the pixel circuit 700. A pixel circuit 7C is employed in which a first adjustment capacitor 8C is provided between the gate of 2C and a second adjustment capacitor 9C is provided between the V _DD line L _vd and the gate of the drive transistor 2C. Yes.

FIG. 17 is a circuit diagram illustrating the configuration of a pixel circuit 7C included in the display panel 50C constituting the image display device 100C according to the second modification of the present invention.

Since the pixel circuit 7C is obtained by adding a first adjustment capacitor 8C and a second adjustment capacitor 9C to the pixel circuit 700 described above, the same portions are denoted by the same reference numerals and described. Omitted.

First adjusting capacitor 8C has a predetermined storage capacitor C _ft, and a second 16 electrode 8aC and the 17 electrode 8bc. The sixteenth electrode 8aC is conductively connected to a wiring that electrically connects the fifth electrode 2gC of the drive transistor 2C and the ninth electrode 4aC of the capacitor 4C. 17 electrode 8bC is electrically connected to the compensation signal line L _th.

Second adjusting capacitor 9C has a predetermined storage capacitor C _vdd, and a second 18 electrode 9aC and the 19 electrode 9bc. The eighteenth electrode 9aC is conductively connected to a wiring that electrically connects the fifth electrode 2gC of the drive transistor 2C and the ninth electrode 4aC of the capacitor 4C. The nineteenth electrode 9bC is electrically connected to the V _DD line L _vs.

Here, the signal waveform of the compensation signal line L _th is controlled by the dedicated driver S _d under the control of the control unit 20C.

Thus, in the image display device 100C according to the second modification of the present invention, the two

adjustment capacitors

8C and 9C are provided. Therefore, similarly to the image display device 100A according to the second embodiment, the gate potential V _g of the drive transistor 2C is set to adjust the light emission luminance of the OLED 1C by adjusting the gate potential of the drive transistor 2C. Until the OLED 1C emits light, the state of the drive transistor 2C is maintained in the saturation region. As a result, the problem of driving in a state where the driving transistor 2C enters the linear region is avoided as much as possible, and deterioration of the driving transistor 2C that adjusts the light emission luminance is suppressed.

<Other variations>
In the second embodiment, the pixel circuit 7A is an n-type transistor. However, the present invention is not limited to this. For example, the drive transistor 2 and the V _th compensation transistor 3 of the pixel circuit 7A may be changed to p-type transistors, respectively, and the direction in which the OLED 1 is connected may be changed in reverse. For example, during the relative pixel circuit 7B according to the modification 1 shown in FIG. 13, a first capacitor having a predetermined capacitance C _ft, fifth electrode 2gB of the driving transistor 2B and the scanning signal line L _ss in providing, a second capacitor having a predetermined capacitance C _vdd, may be adopted that provided between the fifth electrode 2gB and V _DD line L _vd of the driving transistor 2B. In such a configuration, as shown in FIG. 14, the potential of the V _SS line L _vs is relatively lower than the potential of the V _DD line L _vd during light emission. Even when such a configuration is adopted, the gate potential of the driving transistor 2B is adjusted, so that the light emission luminance of the OLED 1B is set, and then the OLED 1B emits light after setting the gate potential V _g of the driving transistor 2B. Until this is done, the state of the drive transistor 2B is maintained in the saturation region. For this reason, the effect similar to 2nd Embodiment is acquired.

In the above embodiment, a mobile phone has been described as an example of an image display device. However, the present invention is not limited to this and includes other image display devices such as a notebook personal computer and a home-use thin television device. The present invention may be applied to image display devices in general.

In the above-described embodiment, the image display device using the organic EL element is described as an example. However, the application target of the present invention is not limited to this. For example, an EL element made of an inorganic material emits light depending on the amount of current. The present invention may be applied to general image display devices in which light emitting elements of a type whose luminance is adjusted (current control type) are arranged.

Note that for a p-type transistor, if the value obtained by subtracting the threshold voltage of the transistor from the potential of the source with respect to the gate of the transistor is greater than the potential of the drain with respect to the source of the transistor, the state of the transistor is It will be in the saturation region.

Claims

An image display device,
First and second pixel circuits each having a light emitting element whose emission luminance is adjusted by a flowing current and a drive transistor for adjusting a current flowing through the light emitting element;
A potential setting unit that sets a potential applied to the driving transistor in the order of the first pixel circuit and the second pixel circuit;
A light emission control unit that causes the light emitting elements included in the first and second pixel circuits to emit light at the same time;
The driving of the first pixel circuit during a period from when the potential setting unit sets a potential to the driving transistor of the first pixel circuit until before the light emission control unit starts light emission. A potential adjusting unit that adjusts a gate voltage of the drive transistor of the first pixel circuit so that the transistor is maintained in a saturation region;
An image display device comprising:
The image display device according to claim 1,
The potential adjusting unit is
An electric wire electrically connected to the driving transistor;
An image display device, wherein the gate voltage is adjusted by switching a potential applied to the electric wire.
The image display device according to claim 2,
The wire is
In the period from the setting of the potential by the potential setting unit to the start of light emission of the light emitting element by the light emission control unit, a potential difference in the opposite direction to that when the light emitting element emits light is given to the light emitting element. An image display device characterized by that.
The image display device according to claim 1,
The potential adjusting unit is
An image display device, wherein the gate voltage is adjusted by adjusting a gate potential of the driving transistor.
The image display device according to claim 1,
The driving transistor is an n-type transistor;
The state of the drive transistor is a saturation region.
An image display apparatus, wherein a value obtained by subtracting a threshold voltage of the drive transistor from a source potential with respect to the gate of the drive transistor is smaller than a drain potential with respect to the source of the drive transistor.
The image display device according to claim 1,
The drive transistor is a p-type transistor;
The state of the drive transistor is a saturation region.
An image display device, wherein a value obtained by subtracting a threshold voltage of the drive transistor from a source potential with respect to the gate of the drive transistor is larger than a drain potential with respect to the source of the drive transistor.