WO2009088123A1 - Template for forming solder bumps, method of manufacturing the template and method of inspecting solder bumps using the template - Google Patents

Template for forming solder bumps, method of manufacturing the template and method of inspecting solder bumps using the template Download PDF

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Publication number
WO2009088123A1
WO2009088123A1 PCT/KR2008/001971 KR2008001971W WO2009088123A1 WO 2009088123 A1 WO2009088123 A1 WO 2009088123A1 KR 2008001971 W KR2008001971 W KR 2008001971W WO 2009088123 A1 WO2009088123 A1 WO 2009088123A1
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WIPO (PCT)
Prior art keywords
cavities
template
openings
transparent substrate
solder bumps
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PCT/KR2008/001971
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French (fr)
Inventor
Pil-Gyu Park
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Secron Co., Ltd.
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Publication date
Application filed by Secron Co., Ltd. filed Critical Secron Co., Ltd.
Publication of WO2009088123A1 publication Critical patent/WO2009088123A1/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3478Applying solder preforms; Transferring prefabricated solder patterns
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01093Neptunium [Np]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0108Transparent
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0104Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0113Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0338Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component

Abstract

A template for forming solder bumps includes a transparent substrate on which a plurality of cavities is formed at surface portions thereof, and an opaque layer formed on the transparent substrate and having a plurality of openings to expose the cavities. Thus, the transparent substrate is prevented from being damaged by a nozzle for injecting a molten solder while injecting the molten solder in the cavities and the openings. The solder bumps formed in the cavities and the openings may be inspected by analyzing light transmitted through edge portions of the cavities.

Description

Description
TEMPLATE FOR FORMING SOLDER BUMPS, METHOD OF MANUFACTURING THE TEMPLATE AND METHOD OF INSPECTING SOLDER BUMPS USING THE TEMPLATE
Technical Field
[1] The present invention relates to a template for forming solder bumps, a method of manufacturing the template and a method of inspecting solder bumps using the template. More particularly, the present invention relates to a template having cavities to form solder bumps in a microelectronic packaging technology, a method of manufacturing the template and a method of inspecting solder bumps formed in the cavities of the template. Background Art
[2] Recently, a microelectronic packaging technology is increasingly moving from wire bonds to solder bumps as the method of interconnection. There are various solder bumping technologies used in volume production. For example, these include electroplating, solder paste printing, evaporation, the direct attachment of preformed solder spheres, and the like.
[3] Particularly, a C4NP (controlled collapse chip connection new process) technology has lately attracted considerable attention by enabling fine pitch bumping at low cost and improving the reliability of semiconductor devices. Examples of the C4NP technology are disclosed in U.S. Patent Nos. 5,607,099, 5,775,569, 6,025,258, etc.
[4] According to the C4NP technology, spherical solder bumps are formed in cavities of a template and then transferred onto bump pads of a semiconductor wafer at a reflow temperature of the solder bumps. The bump pads are connected with metal wires of chips formed on the semiconductor substrate, and under-bump metallurgy (UBM) pads are disposed on the bump pads. The UBM pads may be provided to improve adhesive strength between the solder bumps and the bump pads.
[5] The semiconductor chips of the wafer, onto which the solder bumps are transferred, may be individuated by a dicing process. Each of the semiconductor chips may be attached to a substrate, for example, a printed circuit board (PCB), by a solder reflow process and an underfill process to thereby manufacture a flip chip device.
[6] A molten solder may be injected into the cavities of the template to form the solder bumps. An example of an apparatus for injecting a molten solder is disclosed in U.S. Patent No. 6,231,333. The injected solder may be solidified in the cavities, and the template may be heated to a solder reflow temperature to form spherical solder bumps.
[7] F IGS. 1 and 2 are cross-sectional views illustrating a conventional template for forming solder bumps.
[8] Referring to F IGS. 1 and 2, a plurality of cavities 14 is formed at surface portions of a template 10 to form solder bumps 16a and 16b. The cavities 14 may be formed by a wet etching process. Particularly, a mask may be formed on a substrate 12 to have a plurality of openings and a wet etching process may then be performed using the mask to thereby form the cavities 14. An example of a method of forming the cavities 14 is disclosed in U.S. Patent No. 6,332,569.
[9] It is desirable that the cavities 14 have a hemispherical shape to form spherical solder bumps 16a and 16b on central portions of the cavities. However, bottom surfaces of the cavities 14 may be formed to have a radius of curvature greater than those of side surfaces of the cavities 14 or may be flattened by the wet etching process using the mask. That is, the cavities 14 may have a semielliptical cross-section rather than a semicircular cross-section as shown in F IG. 1. In this case, some solder bumps 16b may not be aligned with the central portions of the cavities 14 as shown in F IG. 2, and further the misaligned solder bumps 16b may be misaligned with bump pads of a semiconductor device.
[10] Meanwhile, the template 10 may be formed of a transparent material to make it easy to align the solder bumps 16a and 16b with the bump pads of the semiconductor device. However, when the solder bumps 16a and 16b are formed in the cavities 14 of the transparent template 10, it is difficult to inspect whether the solder bumps 16a and 16b are normally formed in the cavities 14. Disclosure of Invention
Technical Problem
[11] Example embodiments of the present invention provide a template capable of improving a process of forming solder bumps.
[12] Further, example embodiments of the present invention provide a method of manufacturing the template as mentioned above.
[13] Still further example embodiments of the present invention provide a method of inspecting solder bumps formed in cavities of the template as mentioned above. Technical Solution
[14] According to an aspect of the present invention, a template may include a transparent substrate on which a plurality of cavities is formed at surface portions thereof, and an opaque layer formed on the transparent substrate and having a plurality of openings to expose the cavities.
[15] In some example embodiments of the present invention, examples of a material that may be used for the opaque layer may include metal, metal nitride, silicon nitride, and the like. These materials may be used alone or in a combination thereof. [16] In some example embodiments of the present invention, the ratio of the thickness of the opaque layer to the depth of the cavities may be in a range of about 0.1 to about 0.5.
[17] In a method of manufacturing a template according to another aspect of the present invention, an opaque layer may be formed on a transparent substrate. The opaque layer may be partially removed to form a plurality of openings so as to expose surface portions of the transparent substrate. The exposed surface portions of the transparent substrate may be removed to form a plurality of cavities.
[18] In a method of manufacturing a template according to still another aspect of the present invention, an opaque layer may be formed on a transparent substrate. A first etching mask may be formed on the opaque layer. The first etching mask may have first openings to expose surface portions of the opaque layer. An etching process using the first etching mask may be performed to partially remove the opaque layer so that second openings may be formed to expose surface portions of the transparent substrate. After forming the second openings, the first etching mask may be removed. A second etching mask having third openings may be formed to partially expose the surface portions of the transparent substrate exposed by the second openings. An etching process using the second etching mask may be performed to remove the exposed surface portions of the transparent substrate so as to form a plurality of cavities. After forming the cavities, the second etching mask may be removed.
[19] In some example embodiments of the present invention, each of the third openings may be formed concentrically with each of the second openings.
[20] In some example embodiments of the present invention, the third openings may have a width less than that of the second openings.
[21] In some example embodiments of the present invention, the second openings may have a width equal to that of the cavities.
[22] In some example embodiments of the present invention, examples of a material that may be used for the opaque layer may include metal, metal nitride, silicon nitride, and the like. These materials may be used alone or in a combination thereof.
[23] In some example embodiments of the present invention, an adhesive layer may be formed between the transparent substrate and the opaque layer.
[24] In a method of inspecting solder bumps formed using a template according to still another aspect of the present invention, the template may include a transparent substrate on which a plurality of cavities is formed at surface portions thereof, and an opaque layer formed on the transparent substrate and having a plurality of openings to expose the cavities. Light may be irradiated toward the template. The light transmitted through the template may be detected by a detector. The detected light may be analyzed to ascertain whether the solder bumps are normally formed in the cavities. [25] In some example embodiments of the present invention, an image of the solder bumps may be acquired from the detected light, and it is ascertained whether the solder bumps are normally formed in the cavities from regularities of the image.
[26] In some example embodiments of the present invention, an intensity profile may be acquired from the detected light and it is ascertained whether the solder bumps are normally formed in the cavities from variations in peak values of the intensity profile of the detected light.
Advantageous Effects
[27] According to the example embodiments of the present invention, a template for forming solder bumps may include a transparent substrate having a plurality of cavities and an opaque layer having a plurality of openings to expose the cavities. The opaque layer may be provided to protect the transparent substrate during a relative sliding movement between a nozzle for injecting a molten solder and the template. The lifetime of the template may be increased.
[28] Further, side surfaces of mold cavities for forming the solder bumps may be extended by side surfaces of the openings of the opaque layer, and thus the mold cavities may become closer to a hemispherical shape. Moreover, the opaque layer may have wettability inferior to that of the transparent substrate. Thus, a defective proportion may be improved in a process of forming the solder bumps. Still further, light may be transmitted through portions around the solder bumps, i.e., edge portions of the cavities, and thus an inspection process on the solder bumps may be improved. Brief Description of the Drawings
[29] Example embodiments of the present invention will become readily apparent along with the following detailed description when considered in conjunction with the accompanying drawings, wherein:
[30] F IGS. 1 and 2 are cross-sectional views illustrating a conventional template for forming solder bumps;
[31] F IG. 3 is a cross-sectional view illustrating a template for forming solder bumps in accordance with an example embodiment of the present invention;
[32] F IGS. 4 to 7 are cross-sectional views illustrating a method of manufacturing a template in accordance with an example embodiment of the present invention;
[33] F IGS. 8 to 10 are cross-sectional views illustrating a method of forming solder bumps in mold cavities of the template shown in F IG. 3; and
[34] F IG. 11 is a schematic view illustrating a method of inspecting solder bumps formed in the mold cavities of the template shown in F IG. 3. Best Mode for Carrying Out the Invention
[35] Embodiments of the invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
[36] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
[37] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first thin film could be termed a second thin film, and, similarly, a second thin film could be termed a first thin film without departing from the teachings of the disclosure.
[38] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising" or "includes" and/or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
[39] Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to other elements as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The exemplary term "lower," can therefore, encompass both an orientation of "lower" and "upper" depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary terms "below" or "beneath" can, therefore, encompass both an orientation of above and below.
[40] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[41] Example embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present invention.
[42] F IG. 3 is a cross-sectional view illustrating a template for forming solder bumps in accordance with an example embodiment of the present invention.
[43] Referring to F IG. 3, a template 20 for forming solder bumps may include a transparent substrate 22 and an opaque layer 24. For example, the transparent substrate 22 may be a glass substrate formed of silicon oxide. Particularly, examples of the silicon oxide that may be used for the transparent substrate 22 may include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the like. These silicon oxides may be used alone or in a combination thereof.
[44] The opaque layer 24 may include metal or metal nitride. Examples of the metal that may be used for the opaque layer 24 may include molybdenum (Mo), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), and the like.
[45] In accordance with another example embodiment of the present invention, the opaque layer 24 may include silicon nitride (Si3N4).
[46] In accordance with still another example embodiment of the present invention, the opaque layer 24 may include polymer. For example, the opaque layer 24 may include polyimide.
[47] In accordance with still another example embodiment of the present invention, an adhesive layer may be further provided between the transparent substrate 22 and the opaque layer 24. For example, a chrome layer may be used as the adhesive layer.
[48] A plurality of cavities 22a, into which a molten solder may be injected, may be formed at surface portions of the transparent substrate 22. A plurality of openings 24a may be formed through the opaque layer 24 to expose the cavities 22a of the transparent substrate 22. The cavities 22a may be upwardly exposed by the openings 24a. That is, mold cavities for forming the solder bumps may include the cavities 22a of the transparent substrate 22 and the openings 24a of the opaque layer 24. As a result, the mold cavities may have a shape closer to a hemisphere due to the openings 24a of the opaque layer 24.
[49] F IGS. 4 to 7 are cross-sectional views illustrating a method of manufacturing a template in accordance with an example embodiment of the present invention.
[50] Referring to F IG. 4, an opaque layer 210 may be formed on a transparent substrate
200. For example, a metal layer may be formed on a glass substrate that may be used as the transparent substrate 200. A first mask layer (not shown) may be formed on the opaque layer 210. When the opaque layer includes metal or metal nitride, the first mask layer may include polysilicon, silicon nitride, and the like. Alternatively, when the opaque layer includes silicon nitride, the first mask layer may include polysilicon, metal, metal nitride, and the like.
[51] A first photoresist pattern (not shown) may be formed on the first mask layer. The first mask layer may be patterned by an etching process using the first photoresist pattern as an etching mask. That is, the first mask layer may be partially removed by the etching process to thereby form a first etching mask 220 on the opaque layer 210. Here, the first etching mask 220 may have first openings 222 to expose surface portions of the opaque layer 210.
[52] The first photoresist pattern may be formed by a photolithography process and may be removed by ashing and/or stripping processes after forming the first etching mask 220.
[53] Referring to F IG. 5, second openings 212 may be formed at the surface portions of the opaque layer 210 by an etching processing using the first etching mask 220 to thereby expose surface portions of the transparent substrate 200. The first etching mask 220 may be removed by a wet etching process after forming the second openings 212.
[54] In accordance with another example embodiment of the present invention, in the case that an adhesive layer is formed between the transparent substrate 200 and the opaque layer 210, the adhesive layer may be partially removed by an etching process using the first etching mask 220 to expose surface portions of the transparent substrate 200.
[55] Referring to F IG. 6, a second mask layer (not shown) may be formed on the opaque layer 210 having the second openings 212 and the surface portions of the transparent substrate 200 exposed by the second openings 212. A second photoresist pattern (not shown) may be formed on the second mask layer. The second mask layer may include polysilicon, silicon nitride, and the like.
[56] The second mask layer may be patterned by an etching process using the second photoresist pattern as an etching mask to thereby form a second etching mask 230 having third openings 232 on the opaque layer 210 and the surface portions of the transparent substrate 200 defined by the second openings 212.
[57] The third openings 232 may partially expose the surface portions of the transparent substrate 200 defined by the second openings 212. Particularly, the third openings 232 may be concentrically arranged with the second openings 212. Further, the third openings 232 may have a width or a diameter less than that of the second openings 919
[58] Meanwhile, the second photoresist pattern may be removed by ashing and/or stripping processes after forming the second etching mask 230.
[59] Referring to F IG. 7, the surface portions of the transparent substrate 200 exposed by the third openings 232 may be partially removed by an etching process using the second etching mask 230. For example, the exposed surface portions of the transparent substrate 200 may be removed by a wet etching process using diluted hydrofluoric acid (DHF) to thereby form a plurality of cavities 202 at the surface portions of the transparent substrate 200. The etching process for forming the cavities 202 may be performed such that the width or the diameter of the cavities 202 becomes equal to that of the second openings 212.
[60] The exposed surface portions of the transparent substrate 200 may be isotropically removed by an etching solution, and thus the cavities 202 may have a semielliptical cross-section. However, the cavities 202 of the transparent substrate 200 may upwardly extend through the second openings 212 of the opaque layer 210, and thus mold cavities including the cavities 202 and the second openings 212 may have a generally semicircular shape. The ratio of the thickness of the opaque layer 210 to the depth of the cavities 202 may be determined in a range of about 0.1 to about 0.5 to allow the mold cavities to have the semicircular shape.
[61] The second etching mask 230 may be removed by a wet etching process after forming the cavities 202.
[62] The solder bumps may be formed in the cavities 202 and the second openings 212.
The molten solder may be injected into the cavities 202 and the second openings 212 by an injection nozzle, and a solder reflow process may then be performed to form the solder bumps.
[63] F IGS. 8 to 10 are cross-sectional views illustrating a method of manufacturing solder bumps in the mold cavities of the template shown in F IG. 3.
[64] Referring to F IGS. 8 to 10, a template 20 may be disposed on a chuck (not shown).
The template 20 may include a transparent substrate 22 having a plurality of cavities 22a and an opaque layer 24 having a plurality of openings 24a to expose the cavities 22a. Mold cavities 20a may be defined by the cavities 22a and the openings 24a. [65] A nozzle 300 may be disposed on an upper surface of the template 20 to supply a molten solder 310 into the mold cavities 20a. Here, the nozzle 300 may be heated to a temperature equal to or higher than the melting point of a soldering material. The molten solder 310 may include tin (Sn), silver (Ag), copper (Cu), bismuth (Bi), indium (In), and the like. These materials may be used alone or in a combination thereof.
[66] The template 20 may be heated to a temperature lower than the melting point of the soldering material. Particularly, the template 20 may be heated to a temperature lower than about 30C to about 1O0C; for example, about 50C lower than the melting point of the soldering material. When the template 20 is not sufficiently heated, the temperature of the nozzle 300, which is disposed on the template 20, may vary. On the contrary, when the template of the template 20 is excessively high, molten solders 320 injected in the cavities 22a and the openings 24a may not be solidified.
[67] After disposing the nozzle 300 to make close contact with the upper surface of the template 20, the molten solder 310 may be sequentially injected into the cavities 22a and the openings 24a of the template 20 by a relative sliding movement between the template 20 and the nozzle 300. Particularly, the molten solder 310 may be injected into the cavities 22a and the openings 24a by a differential pressure between the interior and the exterior of the nozzle 300. After injecting the molten solder 310 in the cavities 22a and the openings 24a, the injected molten solder 320 may be solidified because the temperature of template 20 is lower than the melting point of the soldering material.
[68] While the molten solder 310 is injected into the cavities 22a and the openings 24a by the relative sliding movement between the template 20 and the nozzle 300, the surface portions of the transparent substrate 22 may be protected by the opaque layer 24. Thus, the lifetime of the template 20 may be increased.
[69] The solidified solders 320 in the cavities 22a and the openings 24a may be melted by heating the template 20 to a solder reflow temperature, and spherical solder bumps 330 may be formed by surface tension. While performing the solder reflow process to form the solder bumps 330, the melted solders 320 in the cavities 22a and the openings 24a may detached from side surfaces of the openings 24a without difficulty. It is because the wettability of the opaque layer 24 is inferior to that of the transparent substrate 22. That is, the spherical solder bumps 330 may be easily formed in the cavities 22a and the openings 24a because of the poor wettability of the opaque layer 24. Further, the solder bumpers 330 may be arranged on central portions of the cavities 22a, and thus the defective proportion of the solder bumps 330 may be reduced.
[70] After forming the solder bumps 330, an optical inspection process may be performed to ascertain whether the solder bumps 330 are normally formed in the mold cavities 20a. [71] F IG. 11 is a schematic view illustrating a method of inspecting solder bumps formed in the mold cavities of the template shown in F IG. 3.
[72] Referring to F IG. 11 , a light source 400 may be disposed under a template 20 on which a plurality of solder bumps 330a, 330b and 330c is formed. The template 20 may include a transparent substrate 22 having a plurality of cavities 22a and an opaque layer 24 having openings 24a to expose the cavities 22a. Examples of the light source 400 may include a light-emitting diode (LED), a mercury- vapor lamp, and the like.
[73] Light irradiated from the light source 400 may be detected by a detector 410, which may be disposed over the template 20, through the transparent substrate 22. The detector 410 may detect the light transmitted through the template 20 and may produce an image or an intensity profile from the detected light.
[74] The light irradiated from the light source 400 may be transmitted through the cavities
22a of the template 20, as shown is F IG. 11, and may then be detected by the detector 410. In particular, the irradiated light may be transmitted through portions around the solder bumps 330a, 330b and 330c, i.e., through edge portions of the cavities 22a in which the solder bumps 330a, 330b and 330c are formed.
[75] In a case that the solder bump 330a is normally formed in the cavity 22a, a ring- shaped image may be produced from the light transmitted through the portion around the solder bump 330a. However, in a case that the solder bumps 330b and 330b are abnormally formed in the cavities 22a, for example, the solder bumps 330b and 330c are formed at positions apart from centers of the cavities 22a, images produced from the lights transmitted through the portions around the solder bumps 330b and 330c may have an open-ring shape, e.g., a C-shape. Further, the images produced from the lights transmitted through the portions around the abnormally formed solder bumps 330b and 330c may have a ring shape, but may be irregular in width.
[76] Further, an intensity profile produced from the light transmitted through the portion around the solder bump 330a may have two equal peak values. However, intensity profiles produced from the lights transmitted through the portions around the abnormally formed solder bumps 330b and 330c may have one peak value or two peak values different from each other. That is, it may be ascertained whether the solder bumps 330a, 330b and 330c are formed in the cavities 22a from variations in the peak values of the intensity profile.
[77] As a result, it may be ascertained whether the solder bumps 330a, 330b and 330c are normally formed in the cavities 22a and the openings 24a of the template 20 by analyzing the regularities in the image or the intensity profile produced from the light transmitted through the template 20.
[78] Alternatively, the light source 400 may be disposed over the template 20, and the detector 410 may be disposed under the template 20. [79]
Industrial Applicability
[80] According to the example embodiments of the present invention, a template for forming solder bumps may include a transparent substrate having a plurality of cavities and an opaque layer having a plurality of openings to expose the cavities.
[81] The opaque layer may be provided to protect the transparent substrate during a relative sliding movement between a nozzle for injecting a molten solder and the template. The lifetime of the template may be increased.
[82] The openings of the opaque layer may extend side surfaces of mold cavities for forming the solder bumps, and thus the mold cavities may have a hemispherical shape. Further, the opaque layer may have the wettability inferior to that of the transparent substrate. Thus, the defective proportion may be reduced in a process of forming the solder bumps.
[83] Moreover, light may be transmitted through portions around the solder bumps, i.e., edge portions of the cavities, and thus an inspection process on the solder bumps may be improved.
[84] Although the example embodiments of the present invention have been described, it is understood that the present invention should not be limited to these example embodiments but various changes and modifications can be made by those skilled in the art within the spirit and scope of the present invention as hereinafter claimed.
[85]

Claims

Claims
[ 1 ] A template for forming solder bumps comprising: a transparent substrate on which a plurality of cavities is formed at surface portions thereof; and an opaque layer formed on the transparent substrate and having a plurality of openings to expose the cavities. [2] The template of claim 1 , wherein the opaque layer comprises at least one selected from the group consisting of metal, metal nitride and silicon nitride. [3] The template of claim 1, wherein a ratio of a thickness of the opaque layer to a depth of the cavities is in a range of about 0.1 to about 0.5. [4] A method of manufacturing a template comprising: forming an opaque layer on a transparent substrate; partially removing the opaque layer to form a plurality of openings so as to expose surface portions of the transparent substrate; and removing the exposed surface portions of the transparent substrate to form a plurality of cavities. [5] A method of manufacturing a template comprising: forming an opaque layer on a transparent substrate; forming a first etching mask on the opaque layer, the first etching mask having first openings to expose surface portions of the opaque layer; performing an etching process using the first etching mask to partially remove the opaque layer so that second openings are formed to expose surface portions of the transparent substrate; removing the first etching mask; forming a second etching mask having third openings to partially expose the surface portions of the transparent substrate exposed by the second openings; performing an etching process using the second etching mask to remove the exposed surface portions of the transparent substrate so as to form a plurality of cavities; and removing the second etching mask.
[6] The method of claim 5, wherein each of the third openings is formed concentrically with each of the second openings. [7] The method of claim 5, wherein the third openings have a width less than that of the second openings. [8] The method of claim 5, wherein the second openings have a width equal to that of the cavities. [9] The method of claim 5, wherein the opaque layer comprises at least one selected from the group consisting of metal, metal nitride and silicon nitride. [10] The method of claim 5, further comprising forming an adhesive layer between the transparent substrate and the opaque layer. [11] A method of inspecting solder bumps formed using a template comprising a transparent substrate on which a plurality of cavities is formed at surface portions thereof, and an opaque layer formed on the transparent substrate and having a plurality of openings to expose the cavities, comprising: irradiating light toward the template; detecting the light transmitted through the template; and analyzing the detected light to ascertain whether the solder bumps are normally formed in the cavities. [12] The method of claim 11, wherein analyzing the detected light comprises: acquiring an image of the solder bumps from the detected light; and ascertaining whether the solder bumps are normally formed in the cavities from regularities of the image. [13] The method of claim 11, wherein analyzing the detected light comprises: acquiring an intensity profile of the detected light; and ascertaining whether the solder bumps are normally formed in the cavities from variations in peak values of the intensity profile of the detected light.
PCT/KR2008/001971 2008-01-07 2008-04-08 Template for forming solder bumps, method of manufacturing the template and method of inspecting solder bumps using the template WO2009088123A1 (en)

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JPH10256312A (en) * 1997-03-17 1998-09-25 Fujitsu Ltd Ball suction head and ball mounting equipment
JP2000049182A (en) * 1998-07-31 2000-02-18 Fujitsu Ltd Formation of solder bump
US20020004981A1 (en) * 1999-09-02 2002-01-17 Salman Akram Method and apparatus for forming metal contacts on a substrate
KR20030071762A (en) * 2000-10-04 2003-09-06 캠브리지 유니버시티 테크니칼 서비스 리미티드 Solid state embossing of polymer devices
JP2003304057A (en) * 2002-04-11 2003-10-24 Citizen Watch Co Ltd Fine-particle holding plate and its manufacturing method

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JPH10256312A (en) * 1997-03-17 1998-09-25 Fujitsu Ltd Ball suction head and ball mounting equipment
JP2000049182A (en) * 1998-07-31 2000-02-18 Fujitsu Ltd Formation of solder bump
US20020004981A1 (en) * 1999-09-02 2002-01-17 Salman Akram Method and apparatus for forming metal contacts on a substrate
KR20030071762A (en) * 2000-10-04 2003-09-06 캠브리지 유니버시티 테크니칼 서비스 리미티드 Solid state embossing of polymer devices
JP2003304057A (en) * 2002-04-11 2003-10-24 Citizen Watch Co Ltd Fine-particle holding plate and its manufacturing method

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