TW200931610A - Template for forming solder bumps, method of manufacturing the template and method of inspecting solder bumps using the template - Google Patents

Template for forming solder bumps, method of manufacturing the template and method of inspecting solder bumps using the template Download PDF

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TW200931610A
TW200931610A TW097113856A TW97113856A TW200931610A TW 200931610 A TW200931610 A TW 200931610A TW 097113856 A TW097113856 A TW 097113856A TW 97113856 A TW97113856 A TW 97113856A TW 200931610 A TW200931610 A TW 200931610A
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Taiwan
Prior art keywords
template
transparent substrate
opaque layer
recesses
solder bumps
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TW097113856A
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Chinese (zh)
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TWI360206B (en
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Pil-Gyu Park
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Secron Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01093—Neptunium [Np]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0108—Transparent
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0113—Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A template for forming solder bumps includes a transparent substrate on which a plurality of cavities is formed at surface portions thereof, and an opaque layer formed on the transparent substrate and having a plurality of openings to expose the cavities. Thus, the transparent substrate is prevented from being damaged by a nozzle for injecting a molten solder while injecting the molten solder in the cavities and the openings. The solder bumps formed in the cavities and the openings may be inspected by analyzing light transmitted through edge portions of the cavities.

Description

200931610 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種形成銲料凸塊之模板及其製造 方法以及使用此模板之銲料凸塊之檢查方法，且特別是有 .關於一種微電子封裝技術之具有凹處且用以形成銲料凸 塊之模板及其製造方法，以及使用此模板之銲料凸塊之檢 查方法。 © 【先前技術】 近年來微電子封裝技術漸漸以銲料接合取代傳統之 打線接合方式。目前有數種不同之銲料接合方式使用於量 產中，例如包括電鑛（electroplating)、鲜料印刷（solder paste printing)、蒸鍍（evaporation)、直接接合預先形成之銲球或 其他類似方式。 特別值得一提的是近來出現一種稱為C4NP (控制崩 潰晶片接合新製程，controlled collapse chip connection ❹ newprocess)之技術。由於C4NP技術可形成間距微小之 銲料凸塊’其成本低廉，並可改善半導體元件之可靠度， 因此吸引了許多注意力。C4NP技術例如是揭露於美國專 利號碼 5,607,099、5,775,569、6,025,258 等案中。 C4NP技術中，銲球係先形成於模板之凹處中，並於 録料凸塊之迴銲溫度下被轉換為半導體晶圓之凸塊墊 (bump pad)。凸塊墊係與形成於半導體基板上之晶片之金 屬線連接’且凸塊下金屬層（un(jer-bump metallurgy，UBM) 5 200931610 銲墊係配置於凸塊墊上。凸塊下金屬層銲墊係用以改善鮮 料凸塊及凸塊墊間之黏著力。 數個凸塊墊係形成於晶圓之數個半導體晶片上，且此 些半導體晶片可藉由切割製程而分割為獨立的晶片。每一 個半導體晶片可配置於一基板上。舉例來說，在覆晶元件 之製造過程中’半導體晶片可藉由迴銲及底部填充製程而 西己置於一印刷電路板（printed circuit board，PCB)上。 融化的銲料可注入模板之凹處中以形成銲料凸塊。用 0 以注射融化銲料之裝置例如是揭露於美國專利號碼 6,231,333 —案中之裝置。被注射之銲料可於凹處中固化， 真模板可加熱至銲料迴銲溫度，藉以形成球狀之銲料凸 塊。 第1圖及第2圖繪示傳統形成銲料凸塊之模板之剖面 ®。 請參照第1圖及第2圖，數個凹處14係形成於模板 之部分表面’用以形成銲料凸塊16a及16b。凹處14 φ 於〆濕式蝕刻（wet etching)製程中形成。具體來說，。 於裊板12上形成具有數個開口之遮罩，而濕式蝕刻則： 使用此遮罩以形成凹處14。一種形成凹處14之方去疋 霧於美國專利號碼6,332,569 —案中。 係揭 凹處14較佳地為半球狀，使得球狀之銲料凸塊μ 及16b可形成於凹處之中央部分。然而，在形成凹處 時，四處14之底部之曲率半徑可能大於凹處14之=14 之曲率半徑。或者是使用遮罩之濕式蝕刻製程可能=表面 6 200931610 14之底部變平。換句話說，凹處14之剖面形狀可能為半 橢圓而非如第1圖所示之半圓形。如第2圖所示，在此情 況下，某些銲料凸塊16b可能並非對齊於凹處14之中央 部分，進一步造成這些沒有對齊中央部分之銲料凸塊16b 可能無法準確地對齊於半導體元件之凸塊墊。 除此之外，模板10可由一透明材料所製成，使得銲 料凸塊16a及16b較容易對準於半導體元件之凸塊墊。然 而，當銲料凸塊16a及16b形成於透明模板10之凹處14 ❹ 時，檢查銲料凸塊16a及16b是否正常地形成於凹處14 之步驟變得格外困難。 【發明内容】 本發明之一實施例係有關於一種模板，可改善形成銲 料凸塊之製程。 本發明之另一實施例係有關於一種上述模板之製造 方法。 本發明之再一實施例係有關於一種形成於上述模板 之凹處之銲料凸塊之檢查方法。 根據本發明提出一種模板。此模板可包括透明基板及 不透明層。數個凹處係形成於透明基板之部分表面。不透 明層係形成於透明基板上，且具有數個暴露此些凹處之開 π ° 在本發明之實施例中，不透明層之材料例如是包括金 屬、金屬氮化物、氮化石夕及其他類似材料。不透明層之材 7 200931610 料可包括上述材料之一或其任意組合。 在本發明之實施例中，不透明層之厚度及凹處之深度 的比例可介於0.1至0.5之間。 根據本發明提出一種模板之製造方法。不透明層可形 成於透明基板上，且部分之不透明層可被移除以形成數個 開口，用以暴露透明基板之部分表面。透明基板被暴露之 部分表面可被移除以形成數個凹處。 根據本發明提出另一種模板之製造方法。不透明層可 ® 形成於透明基板上。第一蝕刻遮罩可形成於不透明層上， 且第一蝕刻遮罩具有數個第一開口，用以暴露不透明層之 部分表面。部分之不透明層可藉由使用第一触刻遮罩之餘 刻製程而被移除，用以形成數個第二開口。此些第二開口 係用以暴露透明基板之部分表面。第一蝕刻遮罩可在形成 第二開口之後被移除。然後，可形成具有第三開口之第二 蝕刻遮罩，用以暴露透明基板裸露於第二開口之部分表 面。透明基板之被暴露的部分表面可藉由使用第二蝕刻遮 罩之蝕刻製程而被移除，以形成數個凹處。第二蝕刻遮罩 可於形成凹處之後被移除。 在本發明之實施例中，每一個第三開口可對齊於一第 二開口之中央。 在本發明之實施例中，第三開口之寬度可小於第二開 口之寬度。 在本發明之實施例中，第二開口之寬度可等於凹處之 寬度。 8 200931610 在本發明之實施例中，不透明層之材料可包括金屬、 金屬氮化物、氮化石夕或其他類似材料。不透明層之材料可 包括上述材料之一或其組合。 在本發明之實施例中，一黏著層可形成於透明基板及 不透明層之間。 根據本發明提出一種使用模板形成之銲料凸塊之檢 查方法。模板可包括透明基板及不透明層。數個凹處係形 成於透明基板之部分表面。不透明層係形成於透明基板 ® 上，並具有數個用以暴露凹處之開口。光線可照射至模 板。穿透模板之光線可用一檢查裝置檢測。可藉由分析受 檢測之光線，以確認銲料凸塊是否正常地形成於此些凹處 中。 在本發明之實施例中，可由被檢測之光線取得銲料凸 塊之影像。從影像之規則性可得知銲料凸塊是否正常地形 成於凹處中。 在本發明之實施例中，可由被檢測之光線取得亮度 圖。可由被檢測之光線之亮度圖之峰值變化得知銲料凸塊 是否正常地形成於凹處中 根據本發明提出一種用以形成銲料凸塊之模板。此模 板包括透明基板及不透明層。數個凹處係形成於透明基板 上，且不透明層具有數個用以暴露凹處之開口。當喷射融 化之銲料之喷嘴與模板間發生相對位移時，不透明層可用 以保護透明基板，因而增加模板之使用壽命。 此外，用以形成銲料凸塊之模板凹處的側表面可延伸 9 200931610 不透明層之開口的側表面。藉此，模板凹處可更接逆 、狀另外*透明層之可濕性⑽tabiU⑺可低於透明 之可濕性，藉以改善形成銲料凸塊之製程的*良率。二 此之外，光線可穿過銲料凸塊附近之區域，也就是凹： 邊緣部分’藉此可改善銲料凸塊之檢查程序。 為讓本發明之上述内容能更明顯易懂，下文特舉〜較 佳實施例，並配合所附圖式，作詳細說明如下： 乂 ❹【實施方式】 請參考所附圖式，本發明之實施例係更完整地揭露如 下。然而’本發明並非以此為限。本發明之實施例係用以 完整地揭露本發明，使得本發明所屬技術領域中具有通常 知識者可完全了解本發明。於本發明之實施例中，類似之 元件係以類似之符號所標示。 當出現「一元件位於另一元件之上」之敘述時，一元 鲁 件可直接配置於另一元件之上，或有再一元件介於兩者之 間。相對地，當出現「一元件直接位於另一元件之上J之 敘述時，兩者間並無其他元件。此處所使用「且/或」之敘 述係包括所列出項目之全部任意組合。 雖然此處可用第一、第二或其他敘述描述不同元件， 然而元件並不受限於此些敘述，此些敘述僅用以區分不同 的元件。舉例來說，在不脫離本發明揭露之精神下，第一 薄犋可描述為第二薄膜。同樣地，第二薄膜亦可描述為第 一薄膜。 200931610 此處之用詞僅用以敘述本發明之實施例，並非用以限 制本發明。除非特別註明，否則單數形式「一個」亦包括 複數形式「數個」。此處所用之「包含」及「包括」所述 之特徵、範圍、整數、步驟、操作、元件或成份，並非排 除其他之特徵、範圍、整數、步驟、操作、元件、成份或 其組合。 此外，此處之相對用詞，例如是「下」、「底」、「上」 或「頂」等，可用於描述如所附圖式中所繪示之一元件與 ® 另一元件之關係。可了解的是，此些相對用詞係包括其他 方位之描述，並非受限於圖式中之方向。舉例來說，若將 圖式中之裝置上下顛倒，則元件之下側變為元件之上側。 因此，依圖式之方向而定，此處之用詞「下」係包括「上」 和「下」兩種方位。同理，當圖式中之裝置上下翻轉時， 「一元件位於另一元件之下」之敘述則變為「一元件位於 另一元件之上」。因此，此處所舉之用詞「之下」係包括 「之上」與「之下」兩種方位。 參 除非另外定義，此處所使用之所有用詞（包括技術及 科學用詞），係與本發明所屬技術領域中具有通常知識者 所了解之意義相同。除非特別定義，否則此處所使用之用 詞，當與相關技藝及本發明所揭露之範圍内之此用詞之意 義一致，而非指理想化或過度正式之意思。 以下揭露之本發明之實施例之剖面圖係為本發明之 理想化實施例之示意圖。舉例來說，由於製造技術及/或誤 差的關係，將可預期與圖式之形狀有所不同。因此，本發 200931610 明之實施例並不限於圖式中之特定形狀，而包括例如是製 造所造成之差異。舉例來說，描述為平坦之區域，可具有 粗糙;及/或非線性之特徵。此外，描述之銳角可能被變圓。 因此，圖式中所繪示之區域僅為概要式的，其形狀並非精 確地繪示，且並非用以限制本發明之範圍。 第3圖續*示依照本發明之實施例之形成銲料凸塊之 模板之剖面圖。 請參照第3圖’用以形成銲料凸塊之模板20可包括 ❹ 透明基板22及不透明層24。舉例來說，透明基板22可為 由矽氧化物所形成之玻璃基板。具體地來說，形成透明基 板22之珍氧化物可包括蝴咬玻璃（borosilicate glass, BSC)、碟石夕玻璃（phosphosilicate glass, PSG)、爛破石夕玻璃 (borophosphosilicate glass，BPSG)及其他類似材料。此些石夕 氧化物可被單獨使用或混合使用。 不透明層24可包括金屬或金屬氮化物。用以製成不 透明層24之金屬例如包括鉬、鎢、鈦、銅、鋁及其他類 ®似材料。 根據本發明之另一實施例，不透明層24係包括氮化 矽(Si3N4)。 根據本發明之再一實施例，不透明層24係包括聚合 物。舉例來說，不透明層24可包括聚亞醯胺(Polymide) ° 根據本發明之又一實施例，一黏著層可形成於透明基 板22及不透明層24之間。舉例來說，此黏著層可為一鉻 層0 12 200931610 融化之銲料係注入數個凹處22a。此些凹處22a可形 成於透明基板22之部分表面。數個開口 24a可形成於不 透明層22上，用以暴露透明基板22之凹處22a。開口 24a 係，凹處22a之上以暴露此些凹處。也就是說，用以形成 銲料凸塊之模板凹處可包括透明基板22 之凹處22a及不 透月層24之開口 24a。因此，不透明層24之開口 24a可 使得模板凹處之形狀更接近半球狀。 第4圖至第7圖繪示依照本發明之實施例之模板之製 造方法之剖面圖。 請參照第4圖，不透明層210可形成於透明基板200 上。舉例來說，一金屬層可形成於玻璃基板之上，此玻璃 基板可用以當作透明基板2〇〇。第一遮罩層（未顯示於圖 中）可形成於不透明層210之上。當不透明層包括金屬或 金屬氮化物時，第一遮罩層可包括多晶石夕(polysilicon)、氮 化梦及其他類似材料。當不透明層包括說化石夕時，第一遮 ❹罩層可包括多晶矽、金屬、金屬氮化物或其他類似材料。 第一光阻圖案（未顯示於圖中）可形成於第一遮罩層 上。可藉由使用第一光阻圖案為蝕刻遮罩之蝕刻製程而圖 案化第一遮罩層。也就是說，部分之第一遮罩層可於蝕刻 製程中被移除，用以形成第一蝕刻遮罩220於不透明層21〇 上。第一蝕刻遮罩220可具有數個第一開口 222以暴露不 透明層21〇之部分表面。 第一光阻圖案可藉由微影製程而形成。在形成第一蚀 蝕刻遮罩220之後，第一光阻圖案可利用灰化且/或剝除 13 200931610 (stripping)製程而去除。 §月，照第5圖’數個第二開口 212可藉由使用第一钱 刻遮罩22G之14刻製程而形成於不透明層21G之部分表 面。第二開口 212係用以暴露透明基板200之部分表面。 在形成第二開口 212之後’第-蝕刻遮罩220可藉由渴式 蝕刻製程而去除。 八 根據本發明之另—實施例，#黏著層形成於透明基板200931610 IX. Description of the Invention: [Technical Field] The present invention relates to a template for forming a solder bump, a method of manufacturing the same, and a method for inspecting a solder bump using the same, and in particular, a microelectronic A package having a recess and a solder bump for forming a solder bump and a method of fabricating the same, and a solder bump inspection method using the template. © [Prior Art] In recent years, microelectronic packaging technology has gradually replaced the traditional wire bonding method with solder bonding. There are several different solder bonding methods currently used in mass production, including, for example, electroplating, solder paste printing, evaporation, direct bonding of preformed solder balls, or the like. Of particular note is the recent emergence of a technology called C4NP (controlled collapse chip connection ❹ new process). The C4NP technology attracts a lot of attention because it can form solder bumps with a small pitch, which is inexpensive and can improve the reliability of semiconductor components. The C4NP technique is disclosed, for example, in U.S. Patent Nos. 5,607,099, 5,775,569, 6,025,258, and the like. In the C4NP technique, solder balls are first formed in the recesses of the stencil and converted into bump pads of the semiconductor wafer at the reflow temperature of the recording bumps. The bump pad is connected to the metal line of the wafer formed on the semiconductor substrate and the un-bump metallurgy (UBM) 5 200931610 solder pad is disposed on the bump pad. The pad is used to improve the adhesion between the fresh bump and the bump pad. A plurality of bump pads are formed on a plurality of semiconductor wafers of the wafer, and the semiconductor wafers can be divided into independent by a cutting process. Each of the semiconductor wafers may be disposed on a substrate. For example, in the manufacturing process of the flip chip device, the semiconductor wafer may be placed on a printed circuit board by a reflow and underfill process. The molten solder can be injected into the recess of the stencil to form a solder bump. The device for injecting molten solder with 0 is, for example, a device disclosed in U.S. Patent No. 6,231,333. The solder to be injected can be recessed. In the middle curing, the real template can be heated to the solder reflow temperature to form spherical solder bumps. Figures 1 and 2 show the profile of the conventional solder bump forming template. And in Fig. 2, a plurality of recesses 14 are formed on a portion of the surface of the template to form solder bumps 16a and 16b. The recess 14 φ is formed in a wet etching process. A mask having a plurality of openings is formed in the raft 12, and wet etching is used: the mask is used to form the recess 14. A recess 14 is formed to smear in U.S. Patent No. 6,332,569. The recess 14 is preferably hemispherical such that spherical solder bumps μ and 16b can be formed in the central portion of the recess. However, when the recess is formed, the radius of curvature of the bottom of the four portions 14 may be larger than the recess 14 The radius of curvature = 14 or the wet etching process using a mask may = the bottom of the surface 6 200931610 14 flattened. In other words, the cross-sectional shape of the recess 14 may be semi-elliptical rather than as shown in Figure 1. The semicircular shape. As shown in Fig. 2, in this case, some of the solder bumps 16b may not be aligned with the central portion of the recess 14, and further the solder bumps 16b which are not aligned with the central portion may not be accurately Bump pad aligned to a semiconductor component In addition, the template 10 may be made of a transparent material such that the solder bumps 16a and 16b are easier to be aligned with the bump pads of the semiconductor device. However, when the solder bumps 16a and 16b are formed in the transparent template 10 In the case of the recess 14 ,, the step of checking whether the solder bumps 16a and 16b are normally formed in the recess 14 becomes extremely difficult. SUMMARY OF THE INVENTION One embodiment of the present invention relates to a template for improving the formation of solder bumps Another embodiment of the present invention relates to a method of fabricating the above-described template. Still another embodiment of the present invention relates to a method of inspecting a solder bump formed in a recess of the template. A template is proposed in accordance with the invention. The template can include a transparent substrate and an opaque layer. A plurality of recesses are formed on a part of the surface of the transparent substrate. The opaque layer is formed on the transparent substrate and has a plurality of openings π° exposing the recesses. In an embodiment of the invention, the material of the opaque layer includes, for example, a metal, a metal nitride, a nitride, and the like. . The material of the opaque layer 7 200931610 may comprise one of the above materials or any combination thereof. In an embodiment of the invention, the ratio of the thickness of the opaque layer to the depth of the recess may be between 0.1 and 0.5. According to the present invention, a method of manufacturing a template is proposed. The opaque layer can be formed on the transparent substrate, and a portion of the opaque layer can be removed to form a plurality of openings for exposing portions of the surface of the transparent substrate. A portion of the surface on which the transparent substrate is exposed may be removed to form a plurality of recesses. Another method of manufacturing a template is proposed in accordance with the present invention. An opaque layer can be formed on a transparent substrate. A first etch mask can be formed over the opaque layer, and the first etch mask has a plurality of first openings for exposing portions of the surface of the opaque layer. A portion of the opaque layer can be removed by the use of a first etch masking process to form a plurality of second openings. The second openings are for exposing a portion of the surface of the transparent substrate. The first etch mask can be removed after forming the second opening. Then, a second etch mask having a third opening may be formed to expose a portion of the surface of the transparent substrate exposed to the second opening. The exposed portion of the surface of the transparent substrate can be removed by an etching process using a second etch mask to form a plurality of recesses. The second etch mask can be removed after the recess is formed. In an embodiment of the invention, each of the third openings may be aligned with the center of a second opening. In an embodiment of the invention, the width of the third opening may be less than the width of the second opening. In an embodiment of the invention, the width of the second opening may be equal to the width of the recess. 8 200931610 In embodiments of the invention, the material of the opaque layer may comprise a metal, a metal nitride, a nitride nitride or other similar material. The material of the opaque layer may comprise one or a combination of the above materials. In an embodiment of the invention, an adhesive layer can be formed between the transparent substrate and the opaque layer. According to the present invention, a method of inspecting a solder bump formed using a template is proposed. The template can include a transparent substrate and an opaque layer. A plurality of recesses are formed on a part of the surface of the transparent substrate. An opaque layer is formed on the transparent substrate ® and has a plurality of openings for exposing the recesses. Light can be directed onto the template. The light that penetrates the template can be detected by an inspection device. The detected light can be analyzed to confirm whether the solder bumps are properly formed in the recesses. In an embodiment of the invention, an image of the solder bumps can be taken from the detected light. From the regularity of the image, it is known whether the solder bumps are normally formed in the recesses. In an embodiment of the invention, the luminance map can be taken from the detected light. It is known from the peak change in the luminance map of the detected light whether the solder bump is normally formed in the recess. According to the present invention, a template for forming a solder bump is proposed. The template includes a transparent substrate and an opaque layer. A plurality of recesses are formed on the transparent substrate, and the opaque layer has a plurality of openings for exposing the recesses. The opaque layer can be used to protect the transparent substrate when the nozzle of the molten solder is relatively displaced from the stencil, thereby increasing the useful life of the stencil. Furthermore, the side surface of the stencil recess used to form the solder bumps may extend 9 200931610 the side surface of the opening of the opaque layer. Thereby, the template recess can be more reversed, and the wettability of the other transparent layer (10) tabiU (7) can be lower than the wettability of the transparent layer, thereby improving the yield of the process for forming the solder bump. In addition, light can pass through the area near the solder bumps, i.e., the recess: the edge portion, thereby improving the inspection process of the solder bumps. In order to make the above description of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings will be described in detail as follows: 实施 [Embodiment] Referring to the drawings, the present invention The examples are more fully disclosed below. However, the invention is not limited thereto. The embodiments of the present invention are intended to fully disclose the present invention, and those of ordinary skill in the art of the present invention can fully understand the present invention. In the embodiments of the present invention, like elements are designated by like reference numerals. When the phrase "a component is on the other component" is used, the elementary component can be directly disposed on the other component or the other component is in between. In contrast, when the <RTI ID=0.0>" </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Although different elements may be described herein using the first, second or other description, the elements are not limited to the description, and such descriptions are only used to distinguish different elements. For example, the first thin sheet can be described as a second film without departing from the spirit of the present invention. Similarly, the second film can also be described as the first film. 200931610 The words used herein are merely used to describe embodiments of the invention and are not intended to limit the invention. Unless otherwise stated, the singular "a" or "an" The features, ranges, integers, steps, operations, components, or components described in the "comprises" and "comprising" are used herein to exclude other features, ranges, integers, steps, operations, components, components or combinations thereof. In addition, the relative terms herein, such as "lower", "bottom", "upper" or "top", may be used to describe the relationship between one element and another element as illustrated in the drawings. . It will be understood that such relative terms are used to describe other orientations and are not limited by the orientation in the drawings. For example, if the device in the drawing is turned upside down, the lower side of the component becomes the upper side of the component. Therefore, depending on the direction of the drawing, the term "lower" as used herein includes both "upper" and "lower" directions. Similarly, when the device in the drawing is turned upside down, the description of "one component is located under another component" becomes "one component is located on the other component". Therefore, the term "below" as used herein includes both "above" and "below". Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning Terms used herein are intended to be consistent with the meaning of the terms of the art and the scope of the invention, and are not intended to be ideal or overly formal. The cross-sectional views of the embodiments of the invention disclosed below are schematic representations of idealized embodiments of the invention. For example, due to manufacturing techniques and/or error relationships, it can be expected to differ from the shape of the drawings. Therefore, the embodiments of the present invention are not limited to the specific shapes in the drawings, but include, for example, the differences caused by the manufacturing. For example, a region described as flat may have roughness; and/or non-linear characteristics. In addition, the acute angles described may be rounded. Therefore, the regions illustrated in the drawings are merely schematic, and the shapes thereof are not precisely illustrated and are not intended to limit the scope of the invention. Figure 3 is a cross-sectional view showing a template for forming solder bumps in accordance with an embodiment of the present invention. Referring to Figure 3, the template 20 for forming solder bumps may include a transparent substrate 22 and an opaque layer 24. For example, the transparent substrate 22 may be a glass substrate formed of tantalum oxide. Specifically, the rare oxide forming the transparent substrate 22 may include borosilicate glass (BSC), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the like. material. These shixi oxides may be used singly or in combination. The opaque layer 24 can comprise a metal or metal nitride. The metal used to form the opaque layer 24 includes, for example, molybdenum, tungsten, titanium, copper, aluminum, and other like materials. According to another embodiment of the invention, the opaque layer 24 comprises tantalum nitride (Si3N4). According to still another embodiment of the invention, the opaque layer 24 comprises a polymer. For example, the opaque layer 24 can comprise a polymide. According to yet another embodiment of the present invention, an adhesive layer can be formed between the transparent substrate 22 and the opaque layer 24. For example, the adhesive layer can be filled into a plurality of recesses 22a for a chrome layer 0 12 200931610 molten solder. These recesses 22a may be formed on a part of the surface of the transparent substrate 22. A plurality of openings 24a may be formed on the opaque layer 22 to expose the recess 22a of the transparent substrate 22. An opening 24a is formed over the recess 22a to expose the recesses. That is, the template recess for forming the solder bumps may include the recess 22a of the transparent substrate 22 and the opening 24a of the moon-free layer 24. Therefore, the opening 24a of the opaque layer 24 can make the shape of the template recess closer to the hemisphere. 4 to 7 are cross-sectional views showing a method of fabricating a template in accordance with an embodiment of the present invention. Referring to FIG. 4, the opaque layer 210 may be formed on the transparent substrate 200. For example, a metal layer can be formed over the glass substrate, which can be used as a transparent substrate. A first mask layer (not shown) may be formed over the opaque layer 210. When the opaque layer comprises a metal or metal nitride, the first mask layer may comprise polysilicon, nitriding dreams, and the like. When the opaque layer comprises a fossil eve, the first visor layer may comprise polysilicon, metal, metal nitride or other similar material. A first photoresist pattern (not shown) may be formed on the first mask layer. The first mask layer can be patterned by etching the etch mask using the first photoresist pattern. That is, a portion of the first mask layer can be removed during the etching process to form the first etch mask 220 on the opaque layer 21A. The first etch mask 220 can have a plurality of first openings 222 to expose portions of the surface of the opaque layer 21(R). The first photoresist pattern can be formed by a lithography process. After forming the first etch etch mask 220, the first photoresist pattern can be removed using a ashing and/or stripping 13 200931610 (stripping) process. § Month, according to Fig. 5, a plurality of second openings 212 may be formed on a portion of the surface of the opaque layer 21G by using a first etching process of the first mask 22G. The second opening 212 is for exposing a portion of the surface of the transparent substrate 200. After forming the second opening 212, the first etch mask 220 can be removed by a thirst etch process. According to another embodiment of the present invention, the #adhesive layer is formed on a transparent substrate

200及不透明層21〇之間時，部分之黏著層可藉由使用第 一蝕刻遮罩220之蝕刻製程而被移除，用以暴露透明基板 200之表面部分。 請參照第6圖，第二遮罩層（未繪示於圖中）可形成 於具有數個第一開口 212之不透明層210及暴露於第二開 口 212中之透明基板200之部分表面。第二光阻圖案（未 繪示於圖中）可形成於第二遮罩層上。第二遮罩層可包括 多晶石夕、氮化矽及其他類似材料。 可藉由使用第二光阻圖案為蝕刻遮罩之蝕刻製程以 圖案化第二遮罩層，用以形成具有第三開口 232之第二触 刻遮罩230於不透明層210及由第二開口 212所定義之透 明基板200之部分表面。 第三開口 232可暴露透明基板200由第二開口 212所 定義之部分表面。具體來說，第三開口 232係對齊於第二 開口 212之中央。更進一步來說，第三開口 232之寬度或 直經係小於第二開口 212之寬度或直徑。 在形成第二蝕刻遮罩230之後，第二光阻圖案可藉由 200931610 灰化且/或剝除製程而移除。 請參照第7圖，由第三開口 232所暴露之逯明基板 200之部分表面可藉由使用第二蝕刻遮罩23〇之蝕刻製程 而被部分移除。舉例來說，透明基板2〇〇被暴露之部分可 藉由使用稀氫氟酸之濕式蝕刻製程而被移除，用以於透明 基板200之部分表面形成數個凹處2〇2。用以形成凹處2〇2 之蝕刻製程可將凹處202之寬度或直徑變得與第二開口 212之寬度或直徑相同。 透明基板200被暴露之部分表面可藉由蝕刻溶液而 被等向地被移除，使得凹處202可具有半橢圓之剖面形 狀。然而，透明基板200之凹處2〇2可向上延伸至不透明 層210之第二開口 212。因此，模板凹處係包括了凹處2〇2 及第二開口 212而大致上成半球狀。不透明層21〇之厚度 與凹處202之深度之比例可介於〇.1至0 5之間，使得模 板凹處為半球狀。 在形成凹處202之後，第二蝕刻遮罩230可藉由濕式 蝕刻製程而移除。 麵料凸塊可形成於凹處202及第二開口 212中。融化 之鮮料可由喷嘴注射至凹處202及第二開口 212中。之後 可進行迴銲以形成銲料凸塊。 第8圖至第10圖緣示第3圖中位於模板之模板凹處 内之銲料凸塊之製造方法之剖面圖。 請參照第8圖至第10圖。模板20可置於一厚板(chunk) 上。模板20可包括具有數個凹處22a之透明基板22及具 15 200931610 有數個開口 24a之不透明層24。開口 24a係用以暴露凹處 22a °模板凹處20a可由凹處22a及開口 24a而定義。 嘴嘴300可配置於模板20之上表面之上，用以將融 化之銲料310注入模板凹處2〇a中。喷嘴3〇〇可加熱至與 銲料材料之熔點相同或更高之溫度。融化之銲料31〇可包 括錫、銀、銅、鉍、銦及其他類似材料。此些材料可被單 獨使用或混合使用。When between 200 and the opaque layer 21, a portion of the adhesive layer can be removed by an etching process using the first etch mask 220 to expose the surface portion of the transparent substrate 200. Referring to FIG. 6, a second mask layer (not shown) may be formed on the opaque layer 210 having the plurality of first openings 212 and a portion of the surface of the transparent substrate 200 exposed in the second opening 212. A second photoresist pattern (not shown) may be formed on the second mask layer. The second mask layer may comprise polycrystalline spine, tantalum nitride, and the like. The second mask layer can be patterned by using an etching process of the second photoresist pattern as an etch mask to form the second etch mask 230 having the third opening 232 in the opaque layer 210 and the second opening Part of the surface of the transparent substrate 200 defined by 212. The third opening 232 may expose a portion of the surface of the transparent substrate 200 defined by the second opening 212. Specifically, the third opening 232 is aligned with the center of the second opening 212. Furthermore, the width or straightness of the third opening 232 is smaller than the width or diameter of the second opening 212. After forming the second etch mask 230, the second photoresist pattern can be removed by the 200931610 ashing and/or stripping process. Referring to FIG. 7, a portion of the surface of the substrate 200 exposed by the third opening 232 can be partially removed by an etching process using the second etch mask. For example, the exposed portion of the transparent substrate 2 can be removed by a wet etching process using dilute hydrofluoric acid to form a plurality of recesses 2 〇 2 on a part of the surface of the transparent substrate 200. The etching process for forming the recesses 2〇2 can make the width or diameter of the recesses 202 the same as the width or diameter of the second openings 212. A portion of the surface of the transparent substrate 200 that is exposed may be removed isotropically by an etching solution such that the recess 202 may have a semi-elliptical cross-sectional shape. However, the recess 2 2 of the transparent substrate 200 may extend upward to the second opening 212 of the opaque layer 210. Therefore, the template recess includes a recess 2〇2 and a second opening 212 which are substantially hemispherical. The ratio of the thickness of the opaque layer 21 to the depth of the recess 202 may be between 〇.1 and 0 5 such that the recess of the template is hemispherical. After the recess 202 is formed, the second etch mask 230 can be removed by a wet etch process. Fabric bumps may be formed in the recess 202 and the second opening 212. The melted fresh material can be injected into the recess 202 and the second opening 212 by the nozzle. Reflow can then be performed to form solder bumps. Fig. 8 through Fig. 10 are cross-sectional views showing the method of manufacturing the solder bumps in the template recesses of the template in Fig. 3. Please refer to Figure 8 to Figure 10. The template 20 can be placed on a chunk. The template 20 can include a transparent substrate 22 having a plurality of recesses 22a and an opaque layer 24 having a plurality of openings 24a of 15 200931610. The opening 24a is for exposing the recess 22a. The stencil recess 20a can be defined by the recess 22a and the opening 24a. The mouthpiece 300 can be disposed over the upper surface of the template 20 for injecting the molten solder 310 into the template recess 2a. The nozzle 3 can be heated to a temperature equal to or higher than the melting point of the solder material. The molten solder 31 can include tin, silver, copper, bismuth, indium, and the like. These materials can be used alone or in combination.

模板20可加熱至低於銲料熔點之溫度。具體地來 說’模板20可加熱至低於銲料熔點3。€至1〇。〇之溫度。 例如是低於銲料熔點5〇C之溫度。當模板20沒有充分^ 加熱時，配置於模板20之上之喷嘴3〇〇的溫度可能會有 變化。相反地，當模板2〇之溫度過高時，注入凹處22a 及開口 24a之融化的銲料32〇可能無法固化。 在配置喷嘴300於接近模板2〇之上表面之位置後， 藉由模板2G及噴嘴_間的相對滑動，融化的銲料31〇 :連續地被/靖至模板2()之凹處22&amp;及開口 ％。實際上 說、’融化之鲜料310可藉由喷嘴300内部及外部的二 而被=至凹處22a及開口 24a中。當融化之 注入凹處22a及開n u 了 ·Μυ 料之溶點，較射之^之後，由於模板2G之溫度低於銲 當融化之銲C料320可被固化。 滑動而注入凹處22ai 由模板2〇及喷嘴300間之相對 明基板22之表面，^開口⑽時，不透明層24可保護透 舍掇拓因而增加了模板20之使用壽命。 田 口熱至銲料之迴銲溫度時，位於凹處22a 200931610 及開口 24a之固化的銲料320可被融化。此時，表面張力 使得鲜·料凸塊3 3 0變為球狀。當焊料被迴銲以形成録料凸 塊330時，位於凹處22a及開口 24a之融化之銲_料320可 輕易地與開口 24a之側表面分離。這是由於不透明層24 之可濕性低於透明基板22之可濕性。也就是說，由於不 透明層24之低可濕性，球狀之銲料凸塊330可輕易地形 成於凹處22a及開口 24a中。此外，銲料凸塊330可形成 於凹處22a之中央，因而降低了銲料凸塊330之不良率。 φ 在形成銲料凸塊330之後’可執行一光學檢查程序以 確認銲料凸塊330是否正常地形成於模板凹處20a中。 第11圖繪示第3圖中形成於模板之模板凹處之銲料 凸塊之檢查方法。 請參照第η圖，光源400可配置於模板20之下，數 個銲料凸塊330a、330b及330c係形成於模板20上。模板 20可包括具有數個凹處22a之透明基板22及具有數個開 口 24a之不透明層24。光源400例如是包括發光二極體、 Φ 汞蒸汽燈或其他類似光源。 光源400發出之光線可通過透明基板22，並由一檢 查裝置410檢驗。檢查裝置410可配置於模板20之上。 檢查裝置410可檢測穿過模板20之光線，並可由被檢測 之光線產生一影像或亮度圖。 如第11圖所示，光源400產生之光線可穿過模板20 之凹處22a，並可被檢查裝置410所檢測。具體地來說， 光源400發出之光線可穿透銲料凸塊330a、330b及330c 17 200931610 周圍之區域。換句話說，光源400發出之光線可穿過鲜料 凸塊330a、330b及330c之周圍，亦即凹處22a之連说’ &lt;透緣部 分。 ❹The template 20 can be heated to a temperature below the melting point of the solder. Specifically, the template 20 can be heated to below the melting point of the solder 3. From € to 1〇. The temperature of 〇. For example, it is a temperature lower than the melting point of the solder by 5 〇C. When the template 20 is not sufficiently heated, the temperature of the nozzle 3〇〇 disposed above the template 20 may vary. Conversely, when the temperature of the template 2 is too high, the melted solder 32 of the injection recess 22a and the opening 24a may not be cured. After the nozzle 300 is disposed at a position close to the upper surface of the template 2, the molten solder 31〇 is continuously etched into the recess 22&amp; of the template 2() by the relative sliding between the template 2G and the nozzle_ % of opening. In fact, the melted fresh material 310 can be passed into the recess 22a and the opening 24a by the inside and outside of the nozzle 300. When the melting of the injection recess 22a and the opening of the material, the melting point of the coating is improved, since the temperature of the template 2G is lower than that of the welding, the molten material C 320 can be solidified. Sliding into the recess 22ai from the surface of the stencil 2 and the nozzle 300 relative to the surface of the substrate 22, when the opening (10), the opaque layer 24 protects the venting and thus increases the service life of the stencil 20. When the nozzle is hot to the solder reflow temperature, the cured solder 320 located in the recess 22a 200931610 and the opening 24a can be melted. At this time, the surface tension causes the fresh bumps 3 30 to become spherical. When the solder is reflowed to form the recording projection 330, the molten solder material 320 located in the recess 22a and the opening 24a can be easily separated from the side surface of the opening 24a. This is because the wettability of the opaque layer 24 is lower than that of the transparent substrate 22. That is, due to the low wettability of the opaque layer 24, the spherical solder bumps 330 can be easily formed in the recess 22a and the opening 24a. Further, the solder bumps 330 may be formed at the center of the recess 22a, thereby reducing the defective rate of the solder bumps 330. φ After the solder bumps 330 are formed, an optical inspection process can be performed to confirm whether the solder bumps 330 are normally formed in the template recess 20a. Fig. 11 is a view showing a method of inspecting solder bumps formed in the template recesses of the template in Fig. 3. Referring to FIG. 11 , the light source 400 can be disposed under the template 20 , and a plurality of solder bumps 330 a , 330 b , and 330 c are formed on the template 20 . The template 20 can include a transparent substrate 22 having a plurality of recesses 22a and an opaque layer 24 having a plurality of openings 24a. Light source 400 includes, for example, a light emitting diode, a Φ mercury vapor lamp, or other similar light source. Light from source 400 can pass through transparent substrate 22 and be inspected by a inspection device 410. The inspection device 410 can be disposed over the template 20. Inspection device 410 can detect light passing through template 20 and can produce an image or brightness map from the detected light. As shown in FIG. 11, the light generated by the light source 400 can pass through the recess 22a of the template 20 and can be detected by the inspection device 410. In particular, the light emitted by the light source 400 can penetrate the area around the solder bumps 330a, 330b, and 330c 17 200931610. In other words, the light emitted by the light source 400 can pass through the periphery of the fresh bumps 330a, 330b, and 330c, that is, the entangled portion of the recess 22a. ❹

當銲料凸塊330a正常地形成於凹處22a中時，穿透 銲料凸塊330a之周圍區域之光線可產生一環狀影像。然 而，當銲料凸塊330b及330c並非正常地形成於凹處^玨 中時’例如是銲料凸塊330b及330c係形成於偏離凹處22过 中央之位置，穿透銲料凸塊330b及330c之周圍區域之光 線所產生之影像可能為一開口之環狀影像，亦即c形影 像。此外’穿透不正常形成之鋅料凸塊33〇b及330c之門 圍區域之光線亦可能產生寬度不一致之環狀影像。 除此之外’穿透銲料凸塊330a之周圍區域之光線可 產生一亮度圖。此亮度圖可具有兩個相等之峰值。然而， 穿透不正常形成之録料凸塊及330c之周圍區域之光 線所產生之亮度圖可能只具有一個峰值，或是具有兩個不 相等之峰值。也就是說’可藉由亮度圖之峰值變化而確認 形成於凹處22a之銲料凸塊是否正常。 因此，藉由分析穿過模板20之光線之影像或亮度圖 之規則性，即可得知銲料凸塊330a、330b及330c是否正 常地形成於模板20之開口 24a中。 另外’光源400亦可配置於模板20之上，且檢查裝 置410可配置於模板之下。 根據本發明之實施例，用以形成銲料凸塊之模板可包 括具有數個凹處之透明基板及具有數個用以暴露此些凹 18 200931610 處之不透明層。 當用以注射融化之銲料的喷嘴及模板間發生相對滑 動時，不透明層可用以保護透明基板，因而增加模板之使 用壽命。 用以形成銲料凸塊之模板凹處之侧表面可延伸至不 透明層之開口。藉此，模板凹處可為半球狀。進一步地來 說，不透明層之可濕度可低於透明基板之可濕度，藉以減 低銲料凸塊之製程之不良率。 ❹ 此外，光線可穿透銲料凸塊之周圍區域，亦即凹處之 邊緣部分，藉以改善銲料凸塊之檢查方法。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明。本發明所屬技術領域中具有通 常知識者，在不脫離本發明之精神和範圍内，當可作各種 之更動與潤飾。因此，本發明之保護範圍當視後附之申請 專利範圍所界定者為準。 200931610 【圖式簡單說明】 第1圖及第2圖繪示傳統形成銲料凸塊之模板之剖面 圖； 第3圖繪示依照本發明之實施例之形成銲料凸塊之 模板之剖面圖； 第4圖至第7圖繪示依照本發明之實施例之模板製造 方法之剖面圖； 第8圖至第10圖繪示第3圖中位於模板之模板凹處 ® 内之銲料凸塊之製造方法之剖面圖；以及 第11圖繪示第3圖中形成於模板之模板凹處之銲料 凸塊之檢查方法。 【主要元件符號說明】 10、20 :模板 12 :基板 14、22a、202 :凹處 16a、16b、330、330a、330b、330c :銲料凸塊 20a :模板凹處 22、200 :透明基板 24、210 :不透明層 24a :開口 212 :第二開口 220 :第一蝕刻遮罩 222 :第一開口 200931610 230 :第二蝕刻遮罩 232 :第三開口 300 :喷嘴 310 :銲料 400 :光源 410 :檢驗裝置When the solder bump 330a is normally formed in the recess 22a, the light that penetrates the surrounding area of the solder bump 330a produces an annular image. However, when the solder bumps 330b and 330c are not normally formed in the recesses, for example, the solder bumps 330b and 330c are formed at a position offset from the center of the recess 22, penetrating the solder bumps 330b and 330c. The image produced by the light in the surrounding area may be an open circular image, ie a c-shaped image. In addition, the light passing through the surrounding areas of the zinc bumps 33〇b and 330c which are not normally formed may also produce an annular image of inconsistent width. In addition to this, light rays that penetrate the surrounding area of the solder bump 330a can produce a luminance map. This luminance map can have two equal peaks. However, the luminance map produced by penetrating the abnormally formed recording bumps and the area around the 330c may have only one peak or two unequal peaks. That is, it is confirmed by the change in the peak value of the luminance map whether or not the solder bump formed in the recess 22a is normal. Therefore, by analyzing the regularity of the image or luminance map of the light passing through the template 20, it is known whether the solder bumps 330a, 330b, and 330c are normally formed in the opening 24a of the template 20. In addition, the light source 400 can also be disposed on the template 20, and the inspection device 410 can be disposed under the template. In accordance with an embodiment of the present invention, a template for forming solder bumps can include a transparent substrate having a plurality of recesses and a plurality of opaque layers for exposing the recesses 18 200931610. The opaque layer can be used to protect the transparent substrate when relative slip occurs between the nozzle for injecting the melted solder and the stencil, thereby increasing the life of the stencil. The side surface of the stencil recess used to form the solder bump may extend to the opening of the opaque layer. Thereby, the template recess can be hemispherical. Further, the humidity of the opaque layer can be lower than the humidity of the transparent substrate, thereby reducing the defect rate of the solder bump process. ❹ In addition, light can penetrate the surrounding area of the solder bump, that is, the edge portion of the recess, to improve the inspection method of the solder bump. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 200931610 [Simplified Schematic] FIG. 1 and FIG. 2 are cross-sectional views showing a template for forming a solder bump; FIG. 3 is a cross-sectional view showing a template for forming a solder bump according to an embodiment of the present invention; 4 to 7 are cross-sectional views showing a method of fabricating a template in accordance with an embodiment of the present invention; and FIGS. 8 to 10 are diagrams showing a method of manufacturing a solder bump in a template recess of a template in FIG. FIG. 11 is a cross-sectional view showing the solder bump formed in the template recess of the template in FIG. [Main component symbol description] 10, 20: template 12: substrate 14, 22a, 202: recess 16a, 16b, 330, 330a, 330b, 330c: solder bump 20a: template recess 22, 200: transparent substrate 24, 210: opaque layer 24a: opening 212: second opening 220: first etching mask 222: first opening 200931610 230: second etching mask 232: third opening 300: nozzle 310: solder 400: light source 410: inspection device

21twenty one

Claims (1)

200931610 十、申請專利範圍： 1. 一種模板，用以形成複數個銲料凸塊，該模板包 括： 一透明基板，複數個凹處係形成於該透明基板之部分 表面；以及 一不透明層，形成於該透明基板上，並具有複數個開 口以暴露該些凹處。 2. 如申請專利範圍第1項所述之模板，其中該不透 ® 明層包括選自由金屬、金屬氮化物及氮化矽組成之族群至 少其中之一。 3. 如申請專利範圍第1項所述之模板，其中該不透 明層之厚度與該凹處之深度的比例係介於0.1至0.5之間。 4. 一種模板之製造方法，包括： 形成一不透明層於一透明基板上； 移除部分之該不透明層以形成複數個開口，用以暴露 該透明基板之部分表面；以及 ® 移除該透明基板被暴露之部分表面，藉以形成複數個 凹處。 5. —種模板之製造方法，包括： 形成一不透明層於一透明基板上； 形成一第一餘刻遮罩於該不透明層上，該第一蚀刻遮 罩具有複數個第一開口，用以暴露該不透明層之部分表 面； 使用該第一蝕刻遮罩進行蝕刻製程，以移除部分之該 22 Ο ❹ 200931610 不透明層，藉以形成複 — 部分表面； 個第二開口以暴露該透明基板之 移除該第一蝕刻遮罩； 形成具有複數個第三 出該透明基板被該此第-第二蝕刻遮罩，以暴露 使用兮笛； 所暴露之部分表面； 板被暴露二二遮罩:行㈣製程，除該透明基 移除該第二㈣遮罩:以形成複數個凹處；以及 6.,申請專利範圍第5項所述之方法，其中各該些 第一開口係形成於各該些第二開口之中央。 - 7.如申請專利範圍第5項所述之方法，其中各紗 第二開口之寬度係小於各該些第二開口之寬度。 a 一 8. *申請專利範圍第5項所述之方法，其中各該些 弟一開口之寬度係等於各該些凹處之寬度。 9.如申請專利範圍第5項所述之方法，其中該不透 明層包括選自由金屬、金屬氮化物及氮化矽組成之族群至 少其中之一。 10.如申請專利範圍第5項所述之方法更包括形成一 黏著層於該透明基板及該不透明層之間。 11· 一種銲料凸塊之檢查方法，該些銲料凸塊係使用 一模板製成，該模板包括一透明基板及一不透明層，複數 個凹處係形成於該透明基板，且該不透明層係形成於該透 明基板上並具有暴露該些凹處之複數個開口，該方法包 括： 23 200931610 照射一光線至該模板； 檢測穿透該模板之該光線；以及 分析被檢測之該光線，以確認該些銲料凸塊是否正常 地形成於該些凹處之中。 12. 如申請專利範圍第11項所述之方法，其中分析 被檢測之該光線之步驟包括： 由被檢測之該光線取得該些銲料凸塊之一影像；以及 由該影像之規則性確認該些銲料凸塊是否正常地形 ❹成於該些凹處内。 13. 如申請專利範圍第11項所述之方法，其中分析 被檢測之該光線之步驟包括： 取得被檢測之該光線之亮度圖：以及 由被檢測之該光線之該亮度圖之峰值變化確認該些 銲料凸塊是否正常地形成於該些凹處内。 24200931610 X. Patent Application Range: 1. A template for forming a plurality of solder bumps, the template comprising: a transparent substrate, a plurality of recesses formed on a portion of the surface of the transparent substrate; and an opaque layer formed on The transparent substrate has a plurality of openings to expose the recesses. 2. The template of claim 1, wherein the opaque layer comprises at least one selected from the group consisting of metals, metal nitrides, and tantalum nitride. 3. The template of claim 1, wherein the ratio of the thickness of the opaque layer to the depth of the recess is between 0.1 and 0.5. A method of fabricating a template, comprising: forming an opaque layer on a transparent substrate; removing a portion of the opaque layer to form a plurality of openings for exposing a portion of the surface of the transparent substrate; and removing the transparent substrate A portion of the surface that is exposed to form a plurality of recesses. 5. The method of manufacturing a template, comprising: forming an opaque layer on a transparent substrate; forming a first residual mask on the opaque layer, the first etch mask having a plurality of first openings for Exposing a portion of the surface of the opaque layer; etching the portion using the first etch mask to remove portions of the 22 Ο ❹ 200931610 opaque layer to form a complex-partial surface; and a second opening to expose the transparent substrate In addition to the first etch mask; forming a plurality of third out of the transparent substrate by the first-second etch mask to expose the use of the whistle; the exposed portion of the surface; the panel is exposed to the second mask: (4) a process of removing the second (four) mask from the transparent substrate to form a plurality of recesses; and the method of claim 5, wherein each of the first openings is formed in each of the The center of the second openings. 7. The method of claim 5, wherein the width of the second opening of each of the yarns is less than the width of each of the second openings. A. The method of claim 5, wherein the width of each of the openings of the brothers is equal to the width of each of the recesses. 9. The method of claim 5, wherein the opaque layer comprises at least one selected from the group consisting of metals, metal nitrides, and tantalum nitride. 10. The method of claim 5, further comprising forming an adhesive layer between the transparent substrate and the opaque layer. 11 . A method for inspecting solder bumps, wherein the solder bumps are formed using a template, the template includes a transparent substrate and an opaque layer, a plurality of recesses are formed on the transparent substrate, and the opaque layer is formed And a plurality of openings on the transparent substrate and exposing the recesses, the method comprising: 23 200931610 illuminating a light to the template; detecting the light passing through the template; and analyzing the detected light to confirm the Whether or not the solder bumps are normally formed in the recesses. 12. The method of claim 11, wherein the step of analyzing the detected light comprises: obtaining an image of the solder bumps from the detected light; and confirming by the regularity of the image Whether or not the solder bumps are properly formed in the recesses. 13. The method of claim 11, wherein the step of analyzing the detected light comprises: obtaining a brightness map of the detected light: and confirming a peak change of the brightness pattern of the detected light Whether the solder bumps are normally formed in the recesses. twenty four
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