WO2009078574A1 - Dispositif émetteur de lumière et son procédé de fabrication - Google Patents
Dispositif émetteur de lumière et son procédé de fabrication Download PDFInfo
- Publication number
- WO2009078574A1 WO2009078574A1 PCT/KR2008/006266 KR2008006266W WO2009078574A1 WO 2009078574 A1 WO2009078574 A1 WO 2009078574A1 KR 2008006266 W KR2008006266 W KR 2008006266W WO 2009078574 A1 WO2009078574 A1 WO 2009078574A1
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- WO
- WIPO (PCT)
- Prior art keywords
- layer
- type semiconductor
- semiconductor layer
- light emitting
- emitting device
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 339
- 239000010410 layer Substances 0.000 claims description 1147
- 239000000758 substrate Substances 0.000 claims description 122
- 238000000034 method Methods 0.000 claims description 119
- 229910052751 metal Inorganic materials 0.000 claims description 79
- 230000008569 process Effects 0.000 claims description 78
- 239000002184 metal Substances 0.000 claims description 75
- 238000002161 passivation Methods 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 35
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 19
- 238000007788 roughening Methods 0.000 claims description 17
- -1 VO3 Inorganic materials 0.000 claims description 13
- 239000000919 ceramic Substances 0.000 claims description 13
- 239000006023 eutectic alloy Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 239000002356 single layer Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 239000011787 zinc oxide Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 8
- 230000003667 anti-reflective effect Effects 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 8
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 8
- 238000001771 vacuum deposition Methods 0.000 claims description 8
- 239000012298 atmosphere Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 5
- 229910002785 ReO3 Inorganic materials 0.000 claims description 4
- 229910019834 RhO2 Inorganic materials 0.000 claims description 4
- 229910004160 TaO2 Inorganic materials 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052593 corundum Inorganic materials 0.000 claims description 4
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- KZYDBKYFEURFNC-UHFFFAOYSA-N dioxorhodium Chemical compound O=[Rh]=O KZYDBKYFEURFNC-UHFFFAOYSA-N 0.000 claims description 4
- NQKXFODBPINZFK-UHFFFAOYSA-N dioxotantalum Chemical compound O=[Ta]=O NQKXFODBPINZFK-UHFFFAOYSA-N 0.000 claims description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 4
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 4
- HFLAMWCKUFHSAZ-UHFFFAOYSA-N niobium dioxide Inorganic materials O=[Nb]=O HFLAMWCKUFHSAZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- YSZJKUDBYALHQE-UHFFFAOYSA-N rhenium trioxide Chemical compound O=[Re](=O)=O YSZJKUDBYALHQE-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- ZNOKGRXACCSDPY-UHFFFAOYSA-N tungsten(VI) oxide Inorganic materials O=[W](=O)=O ZNOKGRXACCSDPY-UHFFFAOYSA-N 0.000 claims description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 4
- 229910002370 SrTiO3 Inorganic materials 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 229910052594 sapphire Inorganic materials 0.000 description 44
- 239000010980 sapphire Substances 0.000 description 44
- 229910002601 GaN Inorganic materials 0.000 description 30
- 229910052782 aluminium Inorganic materials 0.000 description 14
- 238000000227 grinding Methods 0.000 description 13
- 238000003698 laser cutting Methods 0.000 description 13
- 238000005498 polishing Methods 0.000 description 13
- 239000000126 substance Substances 0.000 description 13
- 230000003287 optical effect Effects 0.000 description 12
- 229910052715 tantalum Inorganic materials 0.000 description 12
- 229910052804 chromium Inorganic materials 0.000 description 10
- 229910052750 molybdenum Inorganic materials 0.000 description 10
- 229910052759 nickel Inorganic materials 0.000 description 10
- 229910052719 titanium Inorganic materials 0.000 description 10
- 229910052721 tungsten Inorganic materials 0.000 description 10
- 229910045601 alloy Inorganic materials 0.000 description 9
- 239000000956 alloy Substances 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- 229910052697 platinum Inorganic materials 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052741 iridium Inorganic materials 0.000 description 4
- 229910052758 niobium Inorganic materials 0.000 description 4
- 239000011368 organic material Substances 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910052703 rhodium Inorganic materials 0.000 description 4
- 229910052707 ruthenium Inorganic materials 0.000 description 4
- 229910052726 zirconium Inorganic materials 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052720 vanadium Inorganic materials 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- 238000007598 dipping method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000879 optical micrograph Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- OTRPZROOJRIMKW-UHFFFAOYSA-N triethylindigane Chemical compound CC[In](CC)CC OTRPZROOJRIMKW-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- QBJCZLXULXFYCK-UHFFFAOYSA-N magnesium;cyclopenta-1,3-diene Chemical compound [Mg+2].C1C=CC=[C-]1.C1C=CC=[C-]1 QBJCZLXULXFYCK-UHFFFAOYSA-N 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
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- 238000013508 migration Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
Definitions
- the present invention relates to a light emitting device and a method of manufacturing the same, and more particularly, to a gallium nitride (hereinafter, referred to as "GaN”)-based light emitting device (LED) having a vertical-type structure and a method of manufacturing the same.
- GaN gallium nitride
- an n-type GaN layer, an undoped InGaN layer, and a p-type GaN layer are sequentially stacked over a nonconductive sapphire substrate, and electrodes are formed over the n-type GaN layer and the p-type GaN layer, respectively.
- the sapphire substrate is nonconductive
- the light emitting device typically has a horizontal-type structure. That is, the electrodes respectively formed over the n-type GaN layer and the p-type GaN layer are horizontally disposed.
- current spreading-resistance is great in a high-power operation, decreasing optical power.
- heat produced in a device operation is not effectively released through the sapphire substrate, there is a limitation that thermal stability of the device is degraded, thereby making a problem in the high-power operation.
- flip-chip-type light emitting devices using a flip-chip package have been proposed.
- an electrode of a vertical-type light emitting device is connected to a heat sink through a solder. Since, in the flip- chip-type light emitting device, light emits from an active layer to the outside through a sapphire substrate, a thick p-type ohmic electrode is applicable instead of a transparent electrode, thus reducing the current spreading-resistance. IHbwever, the flip-chip-type package used for the flip-chip-type light emitting device causes a manufacturing process to be complicated.
- the present invention provides a vertical-type light emitting device and a method of manufacturing the same, which can effectively release heat produced when the device operates and improve optical efficiency characteristics.
- the present invention also provides a light emitting device and a method of manufacturing the same, which can improve heat release and optical efficiency characteristics by stacking a p-type semiconductor layer, an active layer, and an n-type semiconductor layer over a conductive support layer, and allowing light generated in the active layer to emit through the n-type semiconductor layer.
- the present invention also provides a light emitting device and a method of manufacturing the same in which an n-type semiconductor layer, an active layer, and a p- type semiconductor layer are formed over a sapphire substrate, then a conductive substrate is formed over the p-type semiconductor layer, and thereafter the sapphire substrate is removed.
- the p-type electrode layer may be disposed in an entire surface of the p-type semiconductor layer, and the light emitting device may further include a reflective layer disposed on a portion of the p-type electrode layer, and the etch stop layer may be spaced apart from the reflective layer.
- the p-type electrode layer may be formed of a transparent conductive material, and the reflective layer may be formed of a reflective metal. Also, the cover layer may surround the reflective layer.
- the cover layer may be formed of a metal having excellent adhesiveness to the p- type electrode layer and the conductive support layer, and the light emitting device may further include a diffusion barrier layer disposed between the cover layer and the conductive support layer.
- the conductive support layer may have a single-layer or multi-layer structure including one of a metal layer, a conductive ceramic layer, an impurity -doped semiconductor layer and a combination thereof, and the conductive ceramic layer may include one of Nb-doped SrTiC ⁇ , Al-doped ZnO, ITO, IZO and a combination thereof, and the semiconductor layer may include one of B-doped Si, As-doped Si, impurity- doped diamond, impurity -doped Ge and a combination thereof.
- the light emitting device may further include a bonding layer disposed between the cover layer and the conductive support layer.
- the light emitting device may further include a passivation layer disposed on sidewalls of the p-type semiconductor layer, the active layer, and the n-type semiconductor layer and on a portion of the n-type semiconductor layer, and the passivation layer may be further provided on an upper portion and a lower portion of the etch stop layer.
- the light emitting device may further include an anti-reflective layer disposed on an upper or lower portion of the n-type electrode layer.
- a method of manufacturing a light emitting device includes: sequentially forming an n- type semiconductor layer, an active layer, and a p-type semiconductor layer over an insulating substrate; forming a p-type electrode layer and an etch stop layer over the p- type semiconductor layer such that the p-type electrode layer and the etch stop layer are spaced apart from each other; forming a cover layer on the p-type electrode layer to surround the p-type electrode layer; removing the insulating substrate after forming a conductive support layer over the cover layer; etching portions of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer to expose the etch stop layer; forming a passivation layer for surrounding the etched n-type semiconductor layer, the etched active layer, and the etched p-type semiconductor layer; and performing cutting after forming an n-type electrode layer on the etched n-type semiconductor layer.
- the p-type electrode layer may be formed on a portion of the p-type semiconductor layer by stacking an electrode metal and a reflective metal, and the method may further include, after the forming of the p-type electrode layer, heat-treating the p-type electrode layer in a nitrogen atmosphere or an atmosphere containing approximately Q 1 % or more oxygen at a temperature ranging from approximately 250 0 C to approximately 660 0 C for a period of time ranging from approximately 30 seconds to approximately 30 minutes.
- the p-type electrode layer may be formed on an entire surface of the p-type semiconductor layer, and the method may further include forming a reflective layer on the p-type electrode layer.
- the p-type electrode layer may be formed of a transparent conductive material, and the transparent conductive material may be heat-treated at a temperature ranging from approximately 200 0 C to approximately 800 0 C.
- the etch stop layer may be formed of a material having an etch selectivity different from those of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer, and the etch stop layer may be formed of one selected from a group consisting of MgO, Al 2 O 3 , ZrO 2 , IrO 2 , RuO 2 , TaO 2 , WO 3 , VO 3 , HfO 2 , RhO 2 , NbO 2 , YO 3, ReO 3 and a combination thereof.
- the conductive support layer may be formed in a single layer or multi-layer structure including one of a metal layer, a conductive ceramic layer, an impurity -doped semiconductor layer and a combination thereof.
- the metal layer may be formed using an electroplating or vacuum deposition method, and the metal layer, the conductive ceramic layer, or the impurity-doped semiconductor layer may be bonded to the cover layer through a bonding layer.
- the bonding layer may be formed by applying an eutectic alloy containing approximately 80 % of Au and approximately 20 % of Sn on at least one of the cover layer and the conductive support layer, and then heat-treating the eutectic alloy at a temperature ranging from approximately 280 0 C to approximately 400 0 C for a period of time ranging from approximately 1 minute to approximately 120 minutes, or the bonding layer may be formed by applying an eutectic alloy containing approximately 10 % of Au and approximately 90 % of Sn on at least one of the cover layer and the conductive support layer, and then heat-treating the eutectic alloy at a temperature ranging from approximately 220 0 C to approximately 300 0 C for a period of time ranging from approximately 1 minute to approximately 120 minutes.
- the method may further include forming an anti-reflective layer on an upper or lower portion of the n-type electrode layer, and the anti-reflective layer may be formed of one of ITO, ZnO, SiO 2 , Si 3 N 4 , IZO and a combination thereof.
- the method may further include performing a roughening process on a predetermined portion of the n-type semiconductor layer.
- a vertical-type light emitting device is manufactured by stacking an n-type semiconductor layer, an active layer, and a p-type semiconductor layer over a sapphire substrate, forming a p- type electrode layer on the p-type semiconductor layer, forming a cover layer to surround the p-type electrode layer, forming a conductive support layer, removing the sapphire substrate from the resultant structure including the n-type semiconductor layer through a method such as laser irradiation, and forming an n-type electrode layer on the n-type semiconductor layer.
- a vertical- type light emitting device includes a conductive support layer in a lower portion thereof to effectively release heat generated when the device operates. This makes it possible to realize a high-power device.
- a p-type electrode is thickly formed on a p-type semiconductor layer to reduce current density and improve the stability of a device.
- FIG. 1 is a cross-sectional view of a light emitting device in accordance with a first embodiment of the present invention
- FIG. 2 is a cross-sectional view of a light emitting device in accordance with a second embodiment of the present invention.
- FIG. 3 is a cross-sectional view of a light emitting device in accordance with a third embodiment of the present invention
- FIG. 4 is a cross-sectional view of a light emitting device in accordance with a fourth embodiment of the present invention
- FIG. 5 is a cross-sectional view of a light emitting device in accordance with a fifthe embodiment of the present invention
- FIG. 6 is a cross-sectional view of a light emitting device in accordance with a sixth embodiment of the present invention
- FIG. 7 is a cross-sectional view of a light emitting device in accordance with a seventh embodiment of the present invention
- FIG. 8 is a cross-sectional view of a light emitting device in accordance with an eighth embodiment of the present invention
- FIG. 9 is a graph illustrating etch selectivites of GaN and MgO.
- FIGS. 10 through 16 are cross-sectional views illustrating one example of a method of manufacturing the light emitting device in accordance with the first embodiment of the present invention described in FIG. 1 ;
- FIGS. 17 through 20 are cross-sectional views illustrating another example of a method of manufacturing the light emitting device in accordance with the first embodiment of the present invention described in FIG. 1 ;
- FIGS. 21 through 24 are cross-sectional views illustrating still another example of a method of manufacturing the light emitting device in accordance with the first embodiment of the present invention described in FIG. 1 ;
- FIGS. 25 through 28 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the second embodiment of the present invention described in FIG.
- FIGS. 29 through 32 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the third embodiment of the present invention described in FIG. 3;
- FIGS. 33 through 36 are cross-sectional views illustrating one example of a method of manufacturing the light emitting device in accordance with the fourth embodiment of the present invention described in FIG. 4;
- FIGS. 37 through 40 are cross-sectional views illustrating another example of a method of manufacturing the light emitting device in accordance with the fourth embodiment of the present invention described in FIG. 4;
- FIGS. 41 through 44 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the fifth embodiment of the present invention described in FIG. 5;
- FIGS. 45 through 48 are cross-sectional views illustrating another method of manufacturing the light emitting device in accordance with the fifth embodiment of the present invention described in FIG. 5;
- FIGS. 49 through 52 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the sixth embodiment of the present invention described in FIG. 6;
- FIGS. 53 through 56 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the seventh embodiment of the present invention described in FIG. 7 ;
- FIGS. 57 through 60 are cross-sectional views illustrating one example of a method of manufacturing the light emitting device in accordance with the eighth embodiment of the present invention described in FIG. 8;
- FIGS. 61 through 64 are cross-sectional views illustrating another example of a method of manufacturing the light emitting device in accordance with the eighth embodiment of the present invention described in FIG. 8;
- FIG. 65 is an optical microscope image illustrating a light emitting state of a light emitting device in accordance with an exemplary embodiment of the present invention.
- FIGS. 66 and 67 are graphs illustrating comparison in electrical and optical characteristics of a related art horizontal-type light emitting device with a vertical-type light emitting device in accordance with an exemplary embodiment of the present invention.
- FIG. 68 is a graph illustrating comparison in optical power characteristics with respect to input current of a related art horizontal-type light emitting device with a vertical-type light emitting device in accordance with an exemplary embodiment of the present invention. Best Mode for Carrying Out the Invention
- a layer, a film, a region or a plate when referred to as being 'under' another one, it can be directly under the other one, and one or more intervening layers, films, regions or plates may also be present.
- a layer, a film, a region or a plate when referred to as being 'between' two layers, films, regions or plates, it can be the only layer, film, region or plate between the two layers, films, regions or plates, or one or more intervening layers, films, regions or plates may also be present.
- FIG. 1 is a cross-sectional view of a light emitting device in accordance with a first embodiment of the present invention.
- the light emitting device in accordance with the first embodiment includes an n-type semiconductor layer 100, an active layer 200, a p-type semiconductor layer 300, a p-type electrode layer 400, an etch stop layer 500, a cover layer 600, a support layer 700, a passivation layer 800, and an n-type electrode layer 9OQ
- the n-type semiconductor layer 100 for injecting electrons into the active layer 200, may be a GaN layer doped with n-type impurities, e.g., Si, of the concentration ranging from approximately lxlO 19 /cnf to approximately 5xlO 19 /cnf, but the present invention is not limited thereto.
- n-type impurities e.g., Si
- various semi-conductive materials may be used. That is, a nitride such as GaN, InN, or AlN (group IH-V), or a compound having a predetermined ratio of the nitride may be used.
- the n-type semiconductor layer 100 may be formed in a multi-layer structure.
- an n- type clad layer (not shown) may be further formed on the n-type semiconductor layer 100, in which the n-type clad layer may be formed of GaN, AlGaN, or InGaN.
- a roughening process may be performed on a portion of a side of the n-type semiconductor layer 100 where the n-type semiconductor layer 100 does not contact the active layer 200 and the electrode layer 900 is not formed, as shown in FIG. 1.
- the p-type semiconductor layer 300 is formed under the active layer 200, and serves a role of injecting holes into the active layer 2OQ
- the p-type semiconductor layer 300 may be a GaN layer doped with p-type impurities, e.g., with an Mg concentration ranging from approximately lxlO 19 /cnf to approximately 5xlO 19 /cnf, but the present invention is not limited thereto.
- various semi-conducting materials e.g., InGaN may be used.
- the p-type semiconductor layer 300 may be formed in a multi-layer structure.
- a blocking layer may be further provided between the active layer 200 and the p-type semiconductor layer 30Q
- the blocking layer prevents electrons provided from the n-type semiconductor layer 100 from overflowing without being recombined with holes in the active layer 200 and may be an AlGaN layer doped with a p-type impurity.
- the p-type electrode layer 400 acts as an electrode as well as reflecting light emitted from the active layer 200 by stacking an electrode metal and a reflective metal. That is, the p-type electrode layer 400 may be formed in a bilayered or trilayered structure by stacking an electrode metal and a reflective metal.
- the electrode metal includes any one of Ni, Pt, Ru, Ir, Rh, Ta, Mo, Ti, Ag, W, Cu, Cr, Pd, V, Co, Nb, Zr, and an alloy thereof.
- the reflective metal includes Ag or Al.
- the p-type electrode layer 400 may have a bilayered structure of an electrode metal and a reflective metal, or a trilayered structure of a lower electrode metal, a reflective metal, and an upper electrode metal.
- the lower electrode metal may have a thickness ranging from approximately Ql nm to approximately 10 nm
- a reflective metal may have a thickness ranging from approximately 10 nm to approximately 1000 nm
- the upper electrode may have a thickness ranging from approximately 1 nm to approximately 100 nm.
- the p-type electrode layer 400 may be heat-treated in a nitrogen atmosphere or an atmosphere containing approximately Ql% or more oxygen at a temperature ranging from approximately 25O 0 C to approximately 66O 0 C for a period of time ranging from approximately 30 seconds to approximately 30 minutes.
- the etch stop layer 500 has portions formed under the p-type semiconductor layer
- the cover layer 600 fills a space between the p-type electrode layer 400 and the etch stop layer 3)0 and covers the p-type electrode layer 400 and the etch stop layer 3)0
- the cover layer 600 prevents the p-type electrode layer 400 from being exposed to air and minimizes the phenomenon of electromigration where atoms of the p-type electrode layer 400 migrate in response to an electric field while current is applied.
- the cover layer 600 is formed of a metal having excellent adhesiveness to a lower material, and a diffusion barrier layer (not shown) may be further provided on the cover layer 6OQ
- the metal having excellent adhesiveness, forming the cover layer 600 may include Ti or Cr.
- the diffusion barrier layer may be formed of one of Pt, Pd, W, Ni, Ru, Mo, Ir, Rh, Ta, Hf, Ta, Zr, Nb, V, and an alloy thereof.
- the cover layer 600 may be formed in a single-layer or multi-layer structure.
- the metal having excellent adhesiveness such as Ti or Cr may be used.
- the cover layer 600 may be formed by stacking the metal having excellent adhesiveness and the diffusion barrier layer, e.g., in a Ti/Pt or Ti/Pt/W/Pt structure.
- the cover layer 600 may have a thickness ranging from approximately 1 nm to approximately 1000 nm.
- the support layer 700 is formed of a high thermal conductive material under the cover layer 6OQ
- the support layer 700 may be formed of a conductive material including a metal or a conductive ceramic.
- the support layer 700 may be formed in a single layer structure, a bilayered structure including first and second support layers 710 and 720, or a multi-layer structure.
- the support layer 700 may be formed of any one of Au, Ni, W, Mo, Cu, Al, Ta, Ag, Pt, Cr, and an alloy thereof.
- the support layer 700 may be formed by stacking at least two materials different from each other.
- the support layer 700 has a thickness ranging from approximately Q5 nm to approximately 200 nm. The support layer 700 facilitates the release of heat generated during the operation of the device, thus improving the thermal stability of the device, so that a high-power device is realized.
- the n-type electrode layer 900 is formed in a predetermined portion on the n-type semiconductor layer 100 by stacking Cr and Au, or stacking Ti and Al.
- An anti- reflective layer (not shown) may be formed of one of indium tin oxide (ITO), ZnO, SiO 2 , Si 3 N 4 , indium zinc oxide (IZO) and a combination thereof on or under the n-type electrode layer 9OQ
- the light emitting device in accordance with this embodiment includes the conductive support layer 700 disposed in a lower portion thereof, to facilitate the release of heat generated during the operation of the device, so that a high- power device is realized. Also, since photons generated in the active layer 200 are reflected by the p-type electrode layer 400 and emitted through the n-type semiconductor layer 100, an emitting path of the photons is shortened, thus reducing the number of photons absorbed during the emission. Also, the doping concentration of the n-type semiconductor layer 100 can be increased to improve the electric conductivity, thus reducing the current spreading-resistance. As a result, optical power can be enhanced. Also, the p-type electrode layer 400 is thickly formed to reduce current density and improve product stability.
- FIG. 2 is a cross-sectional view of a light emitting device in accordance with a second embodiment of the present invention.
- the light emitting device in accordance with this embodiment includes an n-type semiconductor layer 100, an active layer 200, a p-type semiconductor layer 300, a p-type electrode layer 400, an etch stop layer 3)0, a cover layer 600, a support layer 700, a passivation layer 800, and an n-type electrode layer 9OQ
- the light emitting device in accordance with this embodiment differs from the light emitting device of FIG. 1 in that the cover layer 600 is formed to expose portions of the etch stop layer 3)0, and the passivation layer 800 is further formed on the portions of the etch stop layer 3)0 where the cover layer 600 is not formed.
- FIG. 3 is a cross-sectional view of a light emitting device in accordance with a third embodiment of the present invention.
- the light emitting device in accordance with this embodiment includes an n-type semiconductor layer 100, an active layer 200, a p-type semiconductor layer 300, a p-type electrode layer 400, a reflective layer 43), an etch stop layer 3)0, a cover layer 600, a support layer 700, a passivation layer 800, and an n- type electrode layer 9OQ
- the light emitting device in accordance with this embodiment differs from the light emitting device of FIG. 1 in that the p-type electrode layer 400 is entirely formed on the p-type semiconductor layer 300, and the reflective layer 43) is further formed on a predetermined portion of the p-type electrode layer 40Q That is, the p-type electrode layer 400 of the light emitting device of FIG. 1 includes the electrode metal and the reflective metal that are stacked, but the light emitting device in accordance with this embodiment includes the p-type electrode layer 400 and the reflective layer 43) that are separately formed.
- the p-type electrode layer 400 is formed of a transparent conductive material under the p-type semiconductor layer 30Q
- the transparent conductive material may be a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum doped zinc oxide (AZO), zinc oxide (ZnO) and a combination thereof.
- the reflective layer 43) is formed of a reflective metal under a portion of the p-type electrode layer 4OQ
- the etch stop layer 3)0 is formed under the p-type electrode layer 400 and spaced a predetermined distance from the reflective layer 43)
- the cover layer 600 is formed of a metal to fill a space between the reflective layer 43) and the etch stop layer 3)0 and cover the reflective layer 43) and the etch stop layer 3)Q
- the light emitting device in accordance with this embodiment includes an n-type semiconductor layer 100, an active layer 200, a p-type semiconductor layer 300, a p-type electrode layer 400, a reflective layer 43), an etch stop layer 3)0, a cover layer 600, a support layer 700, a passivation layer 800, and an n- type electrode layer 9OQ
- the light emitting device in accordance with this embodiment differs from the light emitting device of FIG. 3 in that the p-type electrode layer 400 and the reflective layer 43) are stacked in a certain portion under the p-type semiconductor layer 30Q
- the p-type electrode layer 400 is disposed in the certain portion under the p-type semiconductor layer 300, and the reflective layer 43) is disposed under the p-type electrode layer 4OQ
- the etch stop layer 3)0 is spaced apart from the p-type electrode layer 400, partially contacts a lower surface of the p-type semiconductor layer 300 and may have the same thickness as that of the p-type electrode layer 40Q
- the cover layer 600 fills a space between the p-type electrode layer 400 and the etch stop layer 3)0 and covers the etch stop layer 3)0 and the reflective layer 43) to have a planarized surface.
- FIG. 5 is a cross-sectional view of a light emitting device in accordance with a fifthe embodiment of the present invention.
- the light emitting device in accordance with this embodiment includes an n-type semiconductor layer 100, an active layer 330, a p-type semiconductor layer 300, a p-type electrode layer 400, an etch stop layer 3)0, a cover layer 600, a bonding layer 650, a support substrate 750, a passivation layer 800, and an n- type electrode layer 9OQ That is, the light emitting device in accordance with this embodiment differs from the light emitting device of FIG. 1 in that the support substrate 73) instead of the support layer 700 is bonded to the cover layer 600 through the bonding layer 63).
- the bonding layer 63 for bonding the cover layer 600 to the support substrate 73), may be formed of an AuSn-based eutectic alloy containing, e.g., 80 % of Au and 20 % of Sn, or 10 % of Au and 90 % of Sn.
- the bonding layer 63) may be formed in a bilayered structure including first and second bonding layers 651 and 652. The first bonding layer 651 is formed on the cover layer 600, and the second bonding layer 652 is formed on the support substrate 750. Then, the first and second bonding layers 651 and 652 are bonded to each other such that the cover layer 600 and the support substrate 750 are bonded.
- the bonding layer 63 has a thickness ranging from approximately 0.1 ⁇ m to approximately 10 ⁇ m.
- the bonding process is performed through a heat-treating process with a temperature ranging from approximately 280 0 C to approximately 400 0C and a period of time ranging from approximately 1 minute to approximately 120 minutes.
- the bonding process is performed through a heat-treating process with a temperature ranging from approximately 220 0 C to approximately 300 0 C and a period of time ranging from approximately 1 minute to approximately 120 minutes.
- the support substrate 73 includes a conductive substrate such as a metal substrate, a conductive ceramic substrate, or a semiconductor substrate.
- the metal substrate may be formed of single metal elements such as Mo, Ta, Ni, W, Cu, Al, or Ag. Alternatively, the metal substrate may be formed of an alloy of the above metal elements, i.e., Mo, Ta, Ni, W, Cu, Al, or Ag, and other elements.
- the conductive ceramic substrate may be formed of one of a Nb-doped SrTiO 3 , an Al-doped ZnO, indium tin oxide (ITO), indium zinc oxide (IZO) and a combination thereof.
- the semiconductor substrate may be an impurity-doped semiconductor substrate formed of one of B-doped Si, As-doped Si, impurity-doped diamond, impurity-doped Ge and a combination thereof.
- the support substrate 750 has a thickness ranging from approximately 5 ⁇ m to approximately 200 ⁇ m.
- FIG. 6 is a cross-sectional view of a light emitting device in accordance with a sixth embodiment of the present invention.
- the light emitting device in accordance with this embodiment includes an n-type semiconductor layer 100, an active layer 200, a p-type semiconductor layer 300, a p-type electrode layer 400, an etch stop layer 3)0, a cover layer 600, a bonding layer 63), a support substrate 73), a passivation layer 800, and an n- type electrode layer 9OQ
- the cover layer 600 is formed to expose portions of the etch stop layer 3)0
- the passivation layer 800 is further formed on the portions of the etch stop layer 3)0 where the cover layer 600 is not formed. That is, the light emitting device in accordance with this embodiment differs from the light emitting device of FIG. 2 in that the support substrate 73) instead of the support layer 700 is bonded to the cover layer 600 through the bonding layer 63)
- FIG. 7 is a cross-sectional view of a light emitting device in accordance with a seventh embodiment of the present invention.
- the light emitting device in accordance with this embodiment includes an n-type semiconductor layer 100, an active layer 200, a p-type semiconductor layer 300, a p-type electrode layer 4)0, a reflective layer 43), an etch stop layer 3)0, a cover layer 600, a bonding layer 63), a support substrate 73), a passivation layer 800, and an n-type electrode layer 9OQ That is, the light emitting device in accordance with this embodiment differs from the light emitting device of FIG. 3 in that the support substrate 73) instead of the support layer 700 is bonded to the cover layer 600 through the bonding layer 63)
- FIG. 8 is a cross-sectional view of a light emitting device in accordance with an eighth embodiment of the present invention.
- the light emitting device in accordance with this embodiment includes an n-type semiconductor layer 100, an active layer 200, a p-type semiconductor layer 300, a p-type electrode layer 400, a reflective layer 43), an etch stop layer 3)0, a cover layer 600, a bonding layer 63), a support substrate 73), a passivation layer 800, and an n-type electrode layer 9OQ That is, the light emitting device in accordance with this embodiment differs from the light emitting device of FIG. 4 in that the support substrate 73) instead of the support layer 700 is bonded to the cover layer 600 through the bonding layer 63)
- FIG. 9 is a graph illustrating etch selectivities of GaN and MgO.
- MgO is used to form an etch stop layer
- GaN is used to form an n-type semiconductor layer, an active layer, and a p-type semiconductor layer.
- photosensitive patterns were respectively formed on a first substrate where GaN is deposited thereon and a second substrate where GaN and MgO are sequentially deposited thereon, and then etch thickness with respect to etch time was measured by etching the resultant substrates with a mixed etch gas of Cl 2 and BCl 3 .
- a reactive ion etching (RIE) method using an inductive coupled plasma (ICP) apparatus was used as an etching process.
- RIE reactive ion etching
- ICP inductive coupled plasma
- a result of the measurement showed that GaN was etched by approximately 180 nm per minute, but MgO was etched by approximately 45 nm for 18 minutes, i.e., an etch rate of MgO was approximately 2.5 nm per minute. That is, the etch selectivity of GaNiMgO was 721.
- a vertical-type light emitting device can be effectively manufactured using MgO as the etch stop layer in accordance with the present invention.
- FIGS. 10 through 16 are cross-sectional views illustrating one example of a method of manufacturing the light emitting device in accordancd with the first embodiment of the present invention described in FIG. 1.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially stacked on a substrate, e.g., a sapphire substrate 50.
- the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 may be formed of n-type doped GaN, undoped InGaN, and p- type doped GaN, respectively.
- the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 may be formed using various deposition or epitaxy methods including metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) and so on. Also, the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 may be formed in situ.
- MOCVD metal organic chemical vapor deposition
- CVD chemical vapor deposition
- PECVD plasma-enhanced chemical vapor deposition
- MBE molecular beam epitaxy
- HVPE hydride vapor phase epitaxy
- the sapphire substrate 50 is loaded in an MOCVD chamber, the temperature of the chamber is set between approximately 900 0 C and approximately 1000 0 C, and then trimethylgallium (TMGa) as a gallium (Ga) source, ammonia (NH 3 ) as a nitrogen source, and SiH 4 or SiH 6 as n-type impurities are introduced to form a silicon-doped GaN layer.
- TMGa trimethylgallium
- NH 3 ammonia
- SiH 4 or SiH 6 as n-type impurities are introduced to form a silicon-doped GaN layer.
- an indium or aluminum source is introduced to the chamber.
- the temperature of the chamber is set between approximately 700 0 C and approximately 850 0 C, and trimethylindium (TMIn) or triethylindium (TEIn) as an indium source, an gallium source, and a nitrogen source are introduced to form an undoped InGaN layer.
- the temperature of the chamber is set between approximately 900 0 C and approximately 1100 0 C, and an gallium source, a nitrogen source, and biscyclopentadi- enylmagnesium (Cp 2 Mg) as p-type impurities are introduced to form a Mg-doped GaN layer.
- a plurality of p-type electrode layers 400, spaced apart from each other, are formed on the p-type semiconductor layer 300, and then etch stop layers 300 are formed between the p-type electrode layers 40Q
- the p-type electrode layers 400 are formed by forming a metal layer using vacuum deposition, heat-treating the metal layer, and patterning the heated metal layer.
- the p-type electrode layers 400 may be formed of a metal electrode and a reflective metal that are stacked to form a bilayered or trilayered structure.
- the metal electrode is formed of any one of Ni, Pt, Ru, Ir, Rh, Ta, Mo, Ti, Ag, W, Cu, Cr, Pd, V, Co, Nb, Zr, and an alloy thereof and the reflective metal includes Ag or Al.
- a bilayered structure including the metal electrode and the reflective metal, or a trilayered structure including the metal electrode, the reflective metal, and the metal electrode may be formed.
- the p-type electrode layers 400 may be heat-treated in a nitrogen atmosphere or an atmosphere containing approximately Ql% or more oxygen at a temperature ranging from approximately 233 0 C to approximately 660 0 C for a period of time ranging from approximately 30 seconds to approximately 30 minutes. Then, the p-type electrode layers 400 are formed by forming a photosensitive layer (not shown) on the metal layer having a stack structure, patterning the photosensitive layer using photo and exposure processes and patterning the metal layer using the patterned photosensitive layer as a mask
- a photosensitive layer (not shown) is formed on an entire upper portion of a resultant structure, and then the photosensitive layer is patterned through photo and development processes.
- the photosensitive layer is patterned to expose predetermined portions of the p-type semiconductor layer 300 between the p-type electrode layers 40Q
- an etch stop film is formed on an entire upper portion including the patterned photosensitive layer using vacuum deposition.
- the etch stop film is formed of a material having a different etch rate from that of GaN forming the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 30Q
- the etch stop film may be formed of an oxide such as MgO, Al 2 O 3 , ZrO 2 , IrO 2 , RuO 2 , TaO 2 , WO 3 , VO 3 , HfO 2 , RhO 2 , NbO 2 , YO 3 , or ReO 3 .
- dipping is performed with acetone to lift off a photosensitive pattern and portions of the etch stop film on the photosensitive pattern.
- the etch stop layers 300 remain between the p-type electrode layers 400 and are spaced apart from the p- type electrode layers 4OQ
- the etch stop layers 300 may be formed between the p-type electrode layers 400, e.g., by depositing MgO, applying a photosensitive layer, patterning the photosensitive layer through photo and development processes using a predetermined mask, and then etching MgO exposed by a photosensitive pattern using a solution such as HCl.
- a cover layer 600 is formed on the p-type electrode layers 400 and the etch stop layers 3)0 while filling a space between the p-type electrode layers 400 and the etch stop layers 3OQ
- the cover layer 600 prevents the p-type electrode layers 400 from being exposed to air and minimizes the phenomenon of electro- migration, referring that atoms of the p-type electrode layers 400 migrate in response to an electric field while current is applied.
- the cover layer 600 is formed of a metal having excellent adhesiveness to a support layer 700 that will be formed later.
- a diffusion barrier layer (not shown) may be further formed on the cover layer 6OQ
- the cover layer 600 may be formed of a material, e.g., Ti or Cr, having excellent adhesiveness to a metal.
- the diffusion barrier layer on the cover layer 600 may be formed of Pt, Pd, W, Ni, Ru, Mo, Ir, Rh, Ta, Hf, Ta, Zr, Nb, or V.
- the cover layer 600 may be formed in a single layer or multi-layer structure. In case of the single layer structure, the metal having excellent adhesiveness such as Ti or Cr may be used. In case of the multi-layer structure, the cover layer 600 may be formed by stacking the metal having excellent adhesiveness and the diffusion barrier layer, e.g., in a Ti/Pt or Ti/Pt/W/Pt structure.
- the cover layer 600 may have a thickness ranging from approximately 1 nm to approximately 1000 nm.
- the support layer 700 is formed on the cover layer 6OQ
- the support layer 700 may be formed in a single layer or multi-layer structure and may be formed in a bilayered structure by stacking first and second support layers 710 and 720.
- the support layer 700 may be formed of any one of Au, Ni, W, Mo, Cu, Al, Ta, Ag, Pt, Cr, and an alloy thereof.
- the support layer 700 may be formed by stacking at least two materials different from each other.
- the support layer 700 is formed using vacuum deposition such as thermal evaporator, e-beam evaporator and sputter, or electroplating and has a thickness ranging from approximately Q5 nm to approximately 200 nm.
- portions of the second support layer 720 are removed using photo and etching processes. At this point, there remain portions of the second support layer 720 that overlap the p-type electrode layers 400 and portions of the etch stop layers 500 disposed on both sides of the p-type electrode layers 40Q That is, portions of the second support layer 720 over the etch stop layers 500 are mostly removed.
- a laser is irradiated through the sapphire substrate 50 to separate the sapphire substrate 30 from the n-type semiconductor layer 1OQ
- the support layer 700 prevents breakage of the GaN layers when the sapphire substrate 33 is separated through the irradiation of the laser.
- grinding or chemical polishing may be employed to remove the sapphire substrate 50.
- a photosensitive layer is formed on the n-type semiconductor layer 100, and then a photosensitive pattern is formed using photo and development processes.
- the photosensitive pattern is formed to expose portions of the n-type semiconductor layer 100 corresponding to the etch stop layers 50Q
- the n-type semiconductor layer 100, the active layer 200, and the p- type semiconductor layer 300 are etched using dry etching with a Cl 2 gas or a mixed gas of Cl 2 and BCl 3 , thereby exposing the etch stop layers 50Q That is, the etching is performed until the etch stop layers 500 formed of a material, e.g., MgO, is exposed, wherein MgO has an etch rate different from that of GaN forming the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 30Q
- an insulating layer such as a silicon oxide (SiO 2 ) or a silicon nitride (Si 3 N 4 ) is deposited on upper portions and side portions of separated devices to form a passivation layer 80Q
- the passivation layer 800 may have a thickness ranging from approximately 0.05 ⁇ mto approximately 5.0 ⁇ m and may be formed using a plasma-enhanced chemical vapor deposition (PECVD) method.
- PECVD plasma-enhanced chemical vapor deposition
- the passivation layer 800 is selectively removed to expose upper portions of the n-type semiconductor layer 100, and the n-type electrode layer 900 is then formed on the exposed upper portions of the n-type semiconductor layer 1OQ
- the n-type electrode layer 900 is formed in a stack structure including Cr and Au, or Ti and Al.
- FIGS. 17 through 20 are cross-sectional views illustrating another example of a method of manufacturing the light emitting device in accordance with the first embodiment of the present invention described in FIG. 1.
- an n-type semiconductor layer 100, an active layer 230, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 50.
- Predetermined portions of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are etched to expose the sapphire substrate 50 That is, a photosensitive layer (not shown) is formed on an entire structure and patterned using photo and development processes, and then the p-type semiconductor layer 300, the active layer 200, and the n-type semiconductor layer 100 are etched using the patterned photosensitive layer as an etch mask. Etch widths may be less than gaps between light emitting device regions.
- p-type electrode layers 400 are formed on predetermined upper portions of the p-type semiconductor layer 30Q
- etch stop layers 500 are formed on exposed portions of the sapphire substrate 50 and on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the p-type semiconductor layer 30Q
- the etch stop layers 500 on the upper portions of the p-type semiconductor layer 300 are spaced a predetermined distance from the p-type electrode layers 4OQ
- a cover layer 600 is formed on an entire upper portion including the p-type electrode layers 400 and the etch stop layers 500, and then a first support layer 710 and a second support layer 720 are formed on the cover layer 6OQ
- Predetermined portions of the second support layer 720 are removed using certain photo and etching processes. As a result, remainder portions of the second support layer 720 have the same widths as that of the light emitting device.
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. Then, given portions of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are etched to define the light emitting device regions. The etching process is finished on the etch stop layers 500 disposed on the p- type semiconductor layer 30Q At this time, the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are etched inward with respect to portions of the etch stop layers 3)0 formed on the sidewalls thereof, thus the portions of the etch stop layers 3)0 formed on the sidewalls are removed.
- a method such as laser irradiation, grinding, or chemical polishing.
- a passivation layer 800 is formed on sidewalls of the etched n-type semiconductor layer 100, the etched active layer 200, and the etched p-type semiconductor layer 300 and on predetermined upper portions of the etched n-type semiconductor layer 1OQ
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600 and the first support layer 710 are cut between the light emitting device regions using a dicing or laser- cutting process to complete the forming of a chip.
- FIGS. 21 through 24 are cross-sectional views illustrating still another example of a method of manufacturing the light emitting device in accordance with the first embodiment of the present invention described in FIG. 1.
- photosensitive layers 410 or the photosensitive organic material there may be formed a material having a different etch selectivity from those of the n-type semiconductor layer 100, the active layer 200, the p-type semiconductor layer 300, and etch stop layers 3)0.
- the etch stop layers 500 are formed on predetermined upper portions of the p-type semiconductor layer 30Q
- the etch stop layers 500 are spaced a predetermined distance from the p-type electrode layers 400 and disposed on the photosensitive layers 4 IQ Thereafter, a cover layer 600 is formed on an entire upper portion including the p-type electrode layers 400 and the etch stop layers 500, and then a first support layer 710 and a second support layer 720 are formed on the cover layer 6OQ Predetermined portions of the second support layer 720 are removed using predetermined photo and etching processes.
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing.
- a passivation layer 800 is formed on portions where the photosensitive layers 410 are removed, i.e., on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300, which are exposed by the removing of the photosensitive layers 410, and on predetermined upper portions of the n-type semiconductor layer 1OQ
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600 and the first support layer 710 are cut between the light emitting device regions using a dicing or laser- cutting process to complete the forming of a chip.
- FIGS. 25 through 28 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the second embodiment of the present invention described in FIG. 2.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 50. Predetermined portions of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are etched to expose the sapphire substrate 50. The etching process is performed to have widths defining light emitting device regions. Then, p-type electrode layers 400 and etch stop layers 500 are formed on predetermined upper portions of the p-type semiconductor layer 300, wherein the etch stop layers 500 are spaced a predetermined distance from the p-type electrode layers 40Q
- a cover layer 600 is formed on upper portions of the p-type electrode layers 400 and the etch stop layers 500 of the separated light emitting device regions, and then a first support layer 710 and a second support layer 720 are formed on an entire structure. Predetermined portions of the second support layer 720 are removed using predetermined photo and etching processes.
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. Then, a passivation layer 800 is formed on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the n-type semiconductor layer 1OQ The passivation layer 800 is also formed in a space between the etch stop layers 500 and the first support layer 7 IQ
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600 and the first support layer 710 are cut between the light emitting device regions using a dicing or laser- cutting process to complete the forming of a chip.
- FIGS. 29 through 32 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the third embodiment of the present invention described in FIG. 3.
- the transparent conductive oxide is heat-treated in a gas atmosphere containing approximately 10% or more oxygen at a temperature ranging from approximately 200 0 C to approximately 800 0 C for approximately 1 minute or more, thereby forming a transparent conductive oxide layer having ohmic characteristics as the p-type electrode layer 40Q
- reflective layers 450 are formed of a reflective metal such as Ag or Al on predetermined upper portions of the p-type electrode layer 40Q Etch stop layers 500, spaced a predetermined distance from the reflective layers 450, are also formed on the p-type electrode layer 40Q
- a cover layer 600 is formed on an entire upper portion including the reflective layers 450 and the etch stop layers 500, and then a first support layer 710 and a second support layer 720 are formed on the cover layer 600. Predetermined portions of the second support layer 720 are removed using predetermined photo and etching processes.
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600 and the first support layer 710 are cut between the light emitting device regions using a dicing or laser- cutting process to complete the forming of a chip.
- FIGS. 33 through 36 are cross-sectional views illustrating one example of a method of manufacturing the light emitting device in accordance with the fourth embodiment of the present invention described in FIG. 4.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 5Q Then, predetermined portions of the p-type semiconductor layer 300, the active layer 200, and the n-type semiconductor layer 100 are etched to expose the sapphire substrate 5Q Next, p-type electrode layers 400 are formed on predetermined upper portions of the p-type semiconductor layer 30Q That is, a transparent conductive oxide is formed on the p-type semiconductor layer 300, and then selectively removed using photo and etching processes to form the p-type electrode layers 40Q The etching process may be a wet etching process with a HCl diluted solution or a dry etching process with a CF 4 gas.
- reflective layers 43) are formed on upper portions of the p-type electrode layers 40Q
- the reflective layers 43) are formed by forming a photosensitive layer (not shown) on an entire structure, patterning the photosensitive layer to expose the p-type electrode layers 400, depositing a reflective metal, and then removing the photosensitive layer and the reflective metal on the photosensitive layer using a lift-off process.
- the reflective layers 43) may be formed by depositing a reflective metal on the entire structure, forming a photosensitive pattern to expose portions of the reflective metal on the p-type electrode layers 400, and then etching the reflective metal.
- etch stop layers 3)0 are formed on exposed portions of the sapphire substrate 3), on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the p-type semiconductor layer 30Q
- the etch stop layers 3)0 on the upper portions of the p-type semiconductor layer 300 are spaced a predetermined distance from the p-type electrode layers 4OQ
- a cover layer 600 is formed on an entire upper portion of the resultant structure including the p-type electrode layers 400 and the etch stop layers 3)0, and then a first support layer 710 and a second support layer 720 are formed on the cover layer 6OQ
- Predetermined portions of the second support layer 720 are removed using predetermined photo and etching processes, so that remainders of the second support layer 720 have the same widths as that of the light emitting device.
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. Then, predetermined portions of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are removed using an etching process to define the light emitting device regions. The etching process is finished on the etch stop layers 500 disposed on the p-type semiconductor layer 30Q Also, the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are etched inward with respect to portions of the etch stop layers 500 formed on the sidewalls thereof, thus the portions of the etch stop layers 500 formed on the sidewalls are removed. Then, a passivation layer 800 is formed on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the n-type semiconductor layer 1OQ
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600 and the first support layer 710 are cut between the light emitting device regions using a dicing or laser- cutting process to complete the forming of a chip.
- FIGS. 37 through 40 are cross-sectional views illustrating another example of a method of manufacturing the light emitting device in accordance with the fourth embodiment of the present invention described in FIG. 4.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 50. Then, predetermined portions of the p-type semiconductor layer 300, the active layer 200, and the n-type semiconductor layer 100 are etched to expose the sapphire substrate 50. The etching process is performed to have widths defining light emitting device regions. Photosensitive layers 410 or a photosensitive organic material is formed to fill the etched portions.
- etch stop layers 330 are formed on predetermined upper portions of the p-type semiconductor layer 30Q That is, the etch stop layers 500 are spaced a predetermined distance from the p-type electrode layers 400 and disposed on the photosensitive layers 4 IQ
- a cover layer 600 is formed on an entire upper portion of a resultant structure including the p-type electrode layers 400, the reflective layers 450 and the etch stop layers 500, and then a first support layer 710 and a second support layer 720 are formed on the cover layer 6OQ Predetermined portions of the second support layer 720 are removed using predetermined photo and etching processes.
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. After that, the photosensitive layers 410 are removed, and then a passivation layer 800 is formed on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300, which are exposed by the removing of the photosensitive layers 410, and on predetermined upper portions of the n-type semiconductor layer 1OQ
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600 and the first support layer 710 are cut between the light emitting device regions using a dicing or laser- cutting process to complete the forming of a chip.
- FIGS. 41 through 44 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the fifth embodiment of the present invention described in FIG. 5.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 50 After that, p-type electrode layers 400 are formed on predetermined upper portions of the p-type semiconductor layer 300, and etch stop layers 500 are then formed to be spaced a predetermined distance from the p-type electrode layers 400 on given upper portions of the p-type semiconductor layer 30Q
- a cover layer 600 is formed on an entire portion of the resultant structure including the p-type electrode layers 400 and the etch stop layers 500, and then a first bonding layer 651 is formed on the cover layer 6OQ After that, a second bonding layer 652 is formed on a support substrate 750, and then the first and second bonding layers 651 and 652 are bonded to each other to bond the cover layer 600 and the support substrate 750.
- the cover layer 600 and the support substrate 750 are respectively bonded through the first and second bonding layers 651 and 652 while an AuSn based eutectic alloy, e.g., an AuSn-based eutectic alloy containing 80% of Au and 20% of Sn is applied, and the bonding process is performed in a pressure of approximately 1 atm or more and at a temperature ranging from approximately 280 0 C to approximately 400 0 C for a period of time ranging from approximately 5 minutes to approximately 60 minutes.
- an AuSn based eutectic alloy e.g., an AuSn-based eutectic alloy containing 80% of Au and 20% of Sn
- the bonding process is performed through a heat-treating process with a temperature ranging from approximately 220 0 C to approximately 300 0 C for a period of time ranging from approximately 1 minute to approximately 120 minutes.
- the support substrate 750 includes a conductive substrate.
- the support substrate 750 may include a metal substrate, a conductive ceramic substrate, or a semiconductor substrate.
- the metal substrate may be formed of single metal elements such as Mo, Ta, Ni, W, Cu, Al, or Ag.
- the metal substrate may be formed of an alloy of the above metal elements, i.e., Mo, Ta, Ni, W, Cu, Al, or Ag, and other elements.
- the conductive ceramic substrate may be formed of Nb-doped SrTiO 3 , Al- doped ZnO, ITO, or IZO.
- the semiconductor substrate may be an impurity-doped semiconductor substrate formed of one of B-doped Si, As-doped Si, impurity-doped diamond, impurity-doped Ge and a combination thereof.
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. After that, given portions of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are etched to define the light emitting device regions. The etching process is finished on the etch stop layers 500 disposed on the p- type semiconductor layer 30Q. Then, a passivation layer 800 is formed on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300, and on predetermined upper portions of the n-type semiconductor layer 1OQ
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600, the first and second bonding layers 651 and 652, and the support substrate 750 are cut between the light emitting device regions using a dicing or laser-cutting process to complete the forming of a chip.
- FIGS. 45 through 48 are cross-sectional views illustrating another method of manufacturing the light emitting device in accordance with the fifth embodiment of the present invention described in FIG. 5.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 50. Then, predetermined portions of the p-type semiconductor layer 300, the active layer 200, and the n-type semiconductor layer 100 are etched to expose the sapphire substrate 50. Next, p-type electrode layers 400 are formed on predetermined upper portions of the p-type semiconductor layer 30Q
- etch stop layers 500 are formed on exposed portions of the sapphire substrate 50 and on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the p-type semiconductor layer 30Q
- the etch stop layers 500 on the upper portions of the p-type semiconductor layer 300 are spaced a predetermined distance from the p-type electrode layers 4OQ
- a cover layer 600 is formed on an entire portion of a resultant structure including the p-type electrode layers 400 and the etch stop layers 50Q
- a first bonding layer 651 is formed on the cover layer 600 and a second bonding layer 652 is formed on a support substrate 750
- the first and second bonding layers 651 and 652 are bonded to each other to bond the cover layer 600 and the support substrate 750
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. Then, predetermined portions of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are removed using an etching process to define the light emitting device regions. The etching process is finished on the etch stop layers 500 disposed on the p-type semiconductor layer 30Q Also, the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are etched inward with respect to portions of the etch stop layers 500 formed on the sidewalls thereof, thus the portions of the etch stop layers 500 formed on the sidewalls are removed during the etch process. Then, a passivation layer 800 is formed on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the n-type semi- conductor layer 1OQ
- an n-type electrode layer 900 is formed on predetermined upper portion of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600, the first and second bonding layers 651 and 652, and the support substrate 750 are cut between the light emitting device regions using a dicing or laser-cutting process to complete the forming of a chip.
- FIGS. 49 through 52 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the sixth embodiment of the present invention described in FIG. 6.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 50. Then, predetermined portions of the p-type semiconductor layer 300, the active layer 200, and the n-type semiconductor layer 100 are etched to expose the sapphire substrate 50 The etching process is performed to have widths defining light emitting device regions. Next, p-type electrode layers 400 and etch stop layers 500 are formed on predetermined upper portions of the p-type semiconductor layer 300, wherein the etch stop layers 500 are spaced a predetermined distance from the p-type electrode layers 40Q
- cover layers 600 are formed on upper portions including the p- type electrode layers 400 and the etch stop layers 500 of the separated light emitting device regions, and then a first bonding layer 651 is formed on the cover layers 6OQ After that, a second bonding layer 652 is formed on a support substrate 750, and then the first and second bonding layers 651 and 652 are bonded to each other to bond the cover layer 600 and the support substrate 750
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. Then, a passivation layer 800 is formed on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the n-type semiconductor layer 1OQ The passivation layer 800 is also formed to fill a space between the etch stop layers 500 and the first bonding layer 651.
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the first and second bonding layers 651 and 652 and the support substrate 750 are cut between the light emitting device regions using a dicing or laser-cutting process to complete the forming of a chip.
- FIGS. 53 through 56 are cross-sectional views illustrating a method of manufacturing the light emitting device in accordance with the seventh embodiment of the present invention described in FIG. 7.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 50
- a p-type electrode layer 400 is formed on the p-type semiconductor layer 30Q
- the p-type electrode layer 400 is formed of a transparent conductive oxide using a vacuum deposition process, and then is heat-treated in a gas atmosphere containing approximately 10% or more oxygen to have ohmic characteristics.
- Reflective layers 450 are formed of a reflective metal such as Ag or Al on predetermined upper portions of the p-type electrode layer 40Q
- etch stop layers 500, spaced a predetermined distance from the reflective layers 450, are formed on the p-type electrode layer 40Q
- a cover layer 600 is formed on an entire upper portion of a resultant structure including the reflective layers 450 and the etch stop layers 50Q Then a first bonding layer 651 is formed on the cover layer 6OQ After that, a second bonding layer 652 is formed on a support substrate 750, and then the first and second bonding layers 651 and 652 are bonded to each other to bond the cover layer 600 and the support substrate 750
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. Then, given portions of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are removed using an etching process to define the light emitting device regions. The etching process is finished on the etch stop layers 500 disposed on the p-type semiconductor layer 30Q. Then, a passivation layer 800 is formed on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the n-type semiconductor layer 1OQ
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600, the first and second bonding layers 651 and 652 and the support substrate 750 are cut between the light emitting device regions using a dicing or laser-cutting process to complete the forming of a chip.
- FIGS. 57 through 60 are cross-sectional views illustrating one example of a method of manufacturing the light emitting device in accordance with the eighth embodiment of the present invention described in FIG. 8.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 50. Then, predetermined portions of the p-type semiconductor layer 300, the active layer 200, and the n-type semiconductor layer 100 are etched to expose the sapphire substrate 50. Next, p-type electrode layers 400 and reflective layers 450 are formed on predetermined upper portions of the p-type semiconductor layer 30Q
- etch stop layers 500 are formed on exposed portions of the sapphire substrate 50 and on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the p-type semiconductor layer 30Q
- the etch stop layers 500 on the upper portions of the p-type semiconductor layer 300 are spaced a predetermined distance from the p-type electrode layers 4OQ
- a cover layer 600 is formed on an entire upper portion of a resultant structure including the p-type electrode layers 400 and the etch stop layers 500.
- a first bonding layer 651 is formed on the cover layer 600 and a second bonding layer 652 is formed on a support substrate 750 After that, the first and second bonding layers 651 and 652 are bonded to each other to bond the cover layer 600 and the support substrate 750
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. Then, predetermined portions of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are removed using an etching process to define the light emitting device regions. The etching process is finished on the etch stop layers 500 disposed on the p-type semiconductor layer 30Q Also, the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 are etched inward with respect to portions of the etch stop layers 500 formed on the sidewalls thereof, thus the portions of the etch stop layers 500 formed on the sidewalls are removed.
- a method such as laser irradiation, grinding, or chemical polishing.
- a passivation layer 800 is formed on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300 and on predetermined upper portions of the n-type semiconductor layer 1OQ [154]
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed.
- the cover layer 600, a bonding layer 63) including the first and second bonding layers 651 and 652, and the support substrate 750 are cut between the light emitting device regions using a dicing or laser-cutting process to complete the forming of a chip.
- FIGS. 61 through 64 are cross-sectional views illustrating another example of a method of manufacturing the light emitting device in accordance with the eighth embodiment of the present invention described in FIG. 8.
- an n-type semiconductor layer 100, an active layer 200, and a p-type semiconductor layer 300 are sequentially formed on a sapphire substrate 50. Then, predetermined portions of the p-type semiconductor layer 300, the active layer 200, and the n-type semiconductor layer 100 are etched to expose the sapphire substrate 50. The etching process is performed to have widths defining light emitting device regions. Photosensitive layers 410 or a photosensitive organic material is formed to fill the etched portions on the sapphire substrate 50. Next, p-type electrode layers 400 and reflective layers 450 are formed on predetermined upper portions of the p-type semiconductor layer 30Q
- etch stop layers 500 are formed on predetermined upper portions of the p-type semiconductor layer 30Q That is, the etch stop layers 500 are spaced a predetermined distance from the p-type electrode layers 400 and disposed on the photosensitive layers 4 IQ Thereafter, a cover layer 600 is formed on an entire upper portion of a resultant structure including the p-type electrode layers 400, the reflective layers 450 and the etch stop layers 5OQ Then, a first bonding layer 651 is formed on the cover layer 600 and a second bonding layer 652 is formed on a support substrate 750. The first and second bonding layers 651 and 652 are bonded to each other to bond the cover layer 600 and the support substrate 750.
- the substrate 50 is removed from the n-type semiconductor layer 100 using a method such as laser irradiation, grinding, or chemical polishing. After that, the photosensitive layers 410 are removed, and then a passivation layer 800 is formed on sidewalls of the n-type semiconductor layer 100, the active layer 200, and the p-type semiconductor layer 300, which are exposed by the removing of the photosensitive layers 410, and on predetermined upper portions of the n-type semiconductor layer 1OQ [159] Referring to FIG.
- an n-type electrode layer 900 is formed on predetermined upper portions of the n-type semiconductor layer 100, and a roughening process is then performed on portions of the n-type semiconductor layer 100 where the n-type electrode layer 900 is not formed. Thereafter, the cover layer 600, a bonding layer 650 including the first and second bonding layers 651 and 652, and the support substrate 750 are cut between the light emitting device regions using a dicing or laser-cutting process to complete the forming of a chip.
- FIG. 65 is an optical microscope image illustrating a light emitting state of the light emitting device of FIG. 1 when current is applied to the light emitting device, in which the light emitting device is manufactured through the processes of FIGS. 10 through 16. The image shows that the substrate is completely separated from the sapphire substrate and the light emitting devices formed on the substrate are in good condition.
- FIGS. 66 and 67 are graphs illustrating comparison in electrical and optical characteristics of a related art horizontal-type light emitting device B with the vertical-type light emitting device A of FIG. 1.
- FIG. 66 is the graph illustrating comparison in current- voltage characteristics of the horizontal-type light emitting device B with the vertical-type light emitting device A.
- the vertical-type light emitting device A had a forward voltage of approximately 2.8 V that was less than approximately 2.9V of the horizontal-type light emitting device B by approximately QlV, which shows that the vertical-type light emitting device A consumes less power than the horizontal-type light emitting device B.
- FIG. 67 is the graph illustrating comparison in optical power characteristics of the horizontal-type light emitting device B with the vertical-type light emitting device A.
- the vertical-type light emitting device A was 2.5 times or more greater in the optical power characteristics than the horizontal-type light emitting device B, which shows that the vertical-type light emitting device A emits 2.5 times or more light than the horizontal-type light emitting device B for the same power consumption.
- FIG. 68 is a graph illustrating comparison in optical power characteristics with respect to current of a related art horizontal-type light emitting device B with a vertical-type light emitting device A in accordance with an exemplary embodiment.
- the vertical-type light emitting device A emits 2.5 times or more light and is adapted to apply greater current than the horizontal-type light emitting device B, as illustrated in FIG. 68. This is because a metal or conductive substrate of the vertical-type light emitting device A has a heat dissipation coefficient greater than that of a sapphire substrate used for the horizontal-type light emitting device B. Thus, the vertical-type light emitting device A is more suitable as a high-power device.
- the light emitting device and the method of manufacturing the same have been described with reference to the specific embodiments, they are not limited thereto. Therefore, it will be readily understood by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the present invention defined by the appended claims.
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Abstract
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US12/808,333 US8283687B2 (en) | 2007-12-18 | 2008-10-23 | Light emitting device and method of manufacturing the same |
CN2008801212999A CN101904018B (zh) | 2007-12-18 | 2008-10-23 | 发光装置及其制造方法 |
US13/076,075 US8362510B2 (en) | 2007-12-18 | 2011-03-30 | Light emitting device and method of manufacturing the same |
US13/732,759 US8629474B2 (en) | 2007-12-18 | 2013-01-02 | Light emitting device and method of manufacturing the same |
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KR10-2007-0133138 | 2007-12-18 | ||
KR20070133138 | 2007-12-18 | ||
KR1020080034655A KR100975659B1 (ko) | 2007-12-18 | 2008-04-15 | 발광 소자 및 그 제조 방법 |
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US12/808,333 A-371-Of-International US8283687B2 (en) | 2007-12-18 | 2008-10-23 | Light emitting device and method of manufacturing the same |
US13/076,075 Continuation US8362510B2 (en) | 2007-12-18 | 2011-03-30 | Light emitting device and method of manufacturing the same |
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