WO2009071916A1 - Structure de photodiode infrarouge à avalanche à bruit excédentaire faible et son procédé de fabrication - Google Patents

Structure de photodiode infrarouge à avalanche à bruit excédentaire faible et son procédé de fabrication Download PDF

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Publication number
WO2009071916A1
WO2009071916A1 PCT/GB2008/004035 GB2008004035W WO2009071916A1 WO 2009071916 A1 WO2009071916 A1 WO 2009071916A1 GB 2008004035 W GB2008004035 W GB 2008004035W WO 2009071916 A1 WO2009071916 A1 WO 2009071916A1
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Prior art keywords
doped
around
layer
region
type doped
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PCT/GB2008/004035
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English (en)
Inventor
Chee Hing Tan
John David
Andrew Marshall
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The University Of Sheffield
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Priority claimed from GB0723858A external-priority patent/GB0723858D0/en
Priority claimed from GB0812054A external-priority patent/GB0812054D0/en
Application filed by The University Of Sheffield filed Critical The University Of Sheffield
Publication of WO2009071916A1 publication Critical patent/WO2009071916A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP

Definitions

  • the present invention relates to avalanche photodiode structures and to a method of detecting radiation using an avalanche photodiode structure.
  • the invention relates to an avalanche photodiode comprising indium arsenide (InAs).
  • Avalanche photodiode (APD) structures are photodiode structures that have an internal current gain due to impact ionization (known as an "avalanche effect') when operated under appropriate reverse bias conditions.
  • APDs can be used for detecting visible radiation and infrared radiation.
  • High sensitivity APDs for detecting visible radiation may be fabricated from silicon. They are typically operated at reverse-bias voltages in excess of 50V which presents an obstacle to integration of APDs with CMOS IC technology operating at much lower voltages.
  • Some silicon APDs employ bevelling techniques that permit a reverse bias in excess of 200V to be applied in order to enhance performance of the devices, by having a large electron- to-hole ionization coefficient ratio to achieve low avalanche excess noise.
  • InGaAs/lnP APDs are currently the preferred technology due to the poor detection of silicon devices at these wavelengths.
  • the ionization coefficient ratio in InGaAs/lnP APDs is close to unity leading to relatively large avalanche excess noise.
  • CMT APDs suitable for the detection of radiation of wavelengths above 1.55 ⁇ m can be fabricated from cadmium mercury telluride (CMT).
  • CMT APDs suffer from a number of problems.
  • the devices are highly costly to manufacture, particularly when large wafer uniformity is critical.
  • the devices must also be stored at temperatures below 7O 0 C to prevent degradation.
  • the devices must be operated at around 77K, necessitating the use of expensive cooling systems.
  • APDs may be characterised using a range of parameters including quantum efficiency, leakage current, gain and excess noise factors.
  • the quantum efficiency of a device indicates the efficiency with which incident optical photons are absorbed by the structure resulting in the generation of primary charge carriers in the material.
  • Leakage current is given by the sum of the dark current (the current flowing through an APD for a given reverse bias condition in the absence of incident photons) and leakage current flowing through the surface.
  • Sources of noise in photodiodes include shot noise and excess noise.
  • An excess noise factor F(M) describes the noise inherent in the APD multiplication process (a stochastic process) as a function of an avalanche multiplication factor M. F(M) may be written:
  • Conventional silicon APDs are fabricated with a so-called 'reach through' structure in which the electric field increases as a function of distance along the device structure.
  • the region in which avalanche multiplication occurs is located at a pn junction where the peak electric field occurs.
  • an APD structure having a low excess noise factor that overcomes at least one of the above mentioned problems.
  • an avalanche photodiode structure having an avalanche multiplication region comprising InAs.
  • Such a structure has the advantage that an APD may be fabricated having a low excess noise factor and operated at much lower voltages than conventional APDs. This is at least in part because InAs has a lower electron ionization threshold energy for electron- hole pair generation than silicon, and the electron ionization coefficients of InAs are several orders of magnitude higher than those of silicon at the electric fields required to achieve avalanche multiplication in InAs.
  • the electron ionization threshold energy is approximately 0.5eV in InAs and 1.8eV in silicon. Thus for a given avalanche region, a significantly lower voltage is required to achieve avalanche gain in InAs than in silicon.
  • InAs APDs have the potential to detect electromagnetic radiation having a wavelength in the mid-infrared (mid-IR) region of up to 3.5 ⁇ m.
  • the wavelength range from 1.1 - 3.5 ⁇ m is of particular interest in a range of applications such as eye-safe ranging applications, free space optical communication and remote sensing.
  • a number of compounds absorb radiation in this wavelength range, making InAs APDs suitable for applications including carbon dioxide monitoring and glucose sensing in diabetic patients.
  • This range can also be used to monitor heat emission in electronic circuits to identify the existence of faults, in medical thermal imaging and in night vision cameras.
  • InAs material may be grown using molecular beam epitaxy (MBE) or metal organic vapour phase epitaxy (MOVPE) and fabricated using mature Ml-V semiconductor technologies with high yield and at much lower cost than CMT APDs.
  • MBE molecular beam epitaxy
  • MOVPE metal organic vapour phase epitaxy
  • the effective mass of electrons in InAs is 0.023m 0 , where m 0 is the free electron mass. Since the effective mass is low, electrons can gain energy very rapidly and initiate impact ionization when the electron has acquired energy greater than or equal to the ionization threshold energy. Due to the low effective mass, the electron can reach the ionization threshold energy at electric field strengths as low as 10kV/cm or less. Holes in InAs have an effective mass of 0.41 m 0 , which is much higher than that of electrons in InAs. Consequently, the hole ionization coefficient ⁇ is close to zero while the electron ionization coefficient is sufficient to initiate impact ionization events at low electric fields. This leads to a value of k ⁇ 0, yielding negligible excess noise.
  • some embodiments of the invention provide an APD with negligible excess noise.
  • the dead space (being the minimum distance traveled to accumulate sufficient energy to initiate impact ionisation) represents a significant fraction of the mean distance between ionisation events. Consequently in some embodiments of the invention this dead space effect can introduce significant determinism to the ionisation statistics leading to a reduction of the excess noise factor to less than or equal to 2, which is below the limit of a conventional excess noise model.
  • the structure comprises a p-type doped portion and an n-type doped portion, the p-type and n-type doped portions each comprising InAs.
  • one or more portions referred to herein are in the form of layers of material. In other words the portions may be in trie form of one or more coatings.
  • the portions are doped portions or doped layers of a material.
  • the portions are lateral (as opposed to vertical) portions of a single piece of material, such as an InAs substrate.
  • the avalanche region may comprise a junction between the p-type doped portion and the n-type doped portion.
  • the structure is arranged such that incident photons encounter the p-type doped portion before the n-type doped portion.
  • the p-type doped portion may comprise a heavily doped (p + doped) portion or a lightly doped (p " doped) portion.
  • the structure may comprise a p + pn or a pnn + arrangement of doped portions.
  • the structure may comprise a p pn arrangement of doped portions.
  • This structure is also known as a 'reach through' structure.
  • the p pn structure may be configured to absorb photons in the p " portion, whilst avalanche multiplication takes place at the junction between the p doped and n doped portions.
  • the dopant concentration and thickness of the p " portion may be arranged such that in use electrons are injected into the p and n doped portions with energies close to the electron ionization threshold energy.
  • the avalanche region may comprise an intrinsic or undoped portion of a semiconductor material formed between the p-type doped and the n-type doped portion.
  • the device may be fabricated in a relatively straightforward manner and using highly reproducible growth processes.
  • the intrinsic portion preferably comprises substantially undoped InAs.
  • the intrinsic portion may comprise Al x Gai. x As y Sbi. y and InAs.
  • the intrinsic portion has a thickness of from about 1.5 ⁇ m to about 10 ⁇ m.
  • the intrinsic portion may have a thickness of from about 2 ⁇ m to about 4 ⁇ m.
  • the intrinsic region has a width of 2um. In some embodiments the intrinsic region has a width of 3.5um. Other thicknesses are also useful.
  • the structure is arranged to absorb a majority of incident photons in an absorption region.
  • the p-type doped portion comprises the absorption region
  • the absorption region may comprise a p + or p " doped portion.
  • the absorption region may comprise a superlattice portion.
  • thicker intrinsic regions result in device with lower excess noise.
  • thicker intrinsic regions require optimisation of growth to reduce unintentional doping in the intrinsic region.
  • the device is operable to detect incident photons with the superlattice portion within a depletion region, so that carriers generated by incident photons may be extracted in an efficient manner.
  • the superlattice portion comprises a type Il ln x Gai- x As and GaAs x Sb 1 - X superlattice.
  • the superlattice portion comprises a type Il InAs/GaSb superlattice.
  • the superlattice portion comprises alternating layers of InAs and GaSb each layer having a thickness in the range from about 2OA to about 8 ⁇ A.
  • the superlattice portion has a thickness in the range from about 0.5 ⁇ m to about 10 ⁇ m.
  • the superlattice portion may have a thickness in the range from about 2 ⁇ m to about 4 ⁇ m.
  • the superlattice portion may have a thickness of substantially 2 ⁇ m.
  • the structure comprises a blocking region arranged to reduce a number of minority carriers passing from a contact element of the structure to an avalanche region of the structure.
  • a blocking region arranged to reduce a number of minority carriers passing from a contact element of the structure to an avalanche region of the structure. This has the advantage that highly mobile minority electrons are prevented from entering the avalanche region. This reduces the leakage current and hence shot noise.
  • the blocking region may be configured to reduce the number of minority carriers passing from the contact element of the structure through the p-type doped portion to the avalanche region.
  • the blocking region is provided between the contact element and the absorption region.
  • the blocking layer may be provided in the intrinsic region or spaced apart from the intrinsic region.
  • the contact element is provided in ohmic contact with the blocking region.
  • the blocking region may comprise an AI x Ga 1 - X ASySbVy alloy portion.
  • composition of the alloy may be configured to achieve a required minority electron blocking property of the blocking layer.
  • the alloy portion is p doped.
  • AI x Ga 1 . x As y Sbi- y alloy portion is heavily p doped (p + doped).
  • a heavily doped p-type doped (p + doped) portion of InAs is provided between the contact element and the blocking region.
  • a contact region is provided between the contact element and the blocking region, the contact region comprising an InAs portion.
  • the contact region is heavily p-doped (p + doped).
  • the n-type doped portion comprises a heavily doped (n + doped) portion.
  • the structure has a semiconductor surface that has been subjected to an etch process followed by a finishing process, the etch process comprising the steps of exposing the structure to an etching solution comprising a phosphoric acid:hydrogen peroxide:deionised water solution, the finishing process comprising the steps of exposing the structure to a finishing solution comprising a sulphuric acid:hydrogen peroxide:deionised water solution.
  • the etch process comprising the steps of exposing the structure to an etching solution comprising a phosphoric acid:hydrogen peroxide:deionised water solution
  • the finishing process comprising the steps of exposing the structure to a finishing solution comprising a sulphuric acid:hydrogen peroxide:deionised water solution.
  • the etching solution comprises a mixture of a solution of around 85 weight percent phosphoric acid, a solution of around 30 weight percent hydrogen peroxide and deionised water substantially in the volume ratio 0.5-2 : 0.5-2 : 1 , preferably substantially 1 :1 :1.
  • the etching process may be performed for a period of between 1 second and 1 hour at a temperature in the range of from about 5° to about 100 0 C.
  • the finishing solution comprises a mixture of around 98 weight percent sulphuric acid, a solution of around 30 weight percent hydrogen peroxide and deionised water substantially in the volume ratio 1 : 7-10 : 70-100, preferably substantially 1 :8:80.
  • the semiconductor surface is provided with a layer of dielectric medium thereover.
  • the dielectric medium comprises benzocyclobutene.
  • the dielectric medium may have a thickness in the range of from around 0.1 ⁇ m to around 100 ⁇ m, preferably from around 0.1 ⁇ m to around 10 ⁇ m.
  • a method of forming an avalanche photodiode structure comprising the steps of providing a structure according to the first aspect.
  • the method comprises the step of subjecting a semiconductor free surface of the structure to an etch process thereby to form a mesa structure prior to a step of forming electrical contacts to the structure.
  • the method comprises the step of subjecting the surface of the structure to a finishing process following the formation of the mesa structure.
  • the step of exposing the structure to an etch process may comprise the step of exposing the structure to a phosphoric acid:hydrogen peroxide :deionised water solution.
  • the etching solution comprises a mixture of a solution of around 85 weight percent phosphoric acid, a solution of around 30 weight percent hydrogen peroxide and deionised water substantially in the volume ratio 0.5-2 : 0.5-2 : 1 , preferably substantially 1 :1 :1.
  • the method may comprise the step of exposing the structure to the etching solution for a period of between 1 second and 1 hour at a temperature in the range of from about 5° to about 100 0 C.
  • the step of exposing the structure to a finishing process comprises the step of exposing the structure to a finishing solution, the finishing solution comprising a mixture of around 98 weight percent sulphuric acid, a solution of around 30 weight percent hydrogen peroxide and deionised water substantially in the volume ratio 1 : 7-10 : 70- 100, preferably substantially 1 :8:80.
  • a method of detecting particles of electromagnetic radiation comprising the steps of providing an avalanche photodiode structure as claimed in the first aspect of the invention.
  • the method may further comprise the step of applying a reverse bias to the structure sufficient to cause internal current gain.
  • the method comprises the step of establishing a depletion region in the structure having a width in the range from around 1.5 ⁇ m to around 5 ⁇ m.
  • the method may further comprise the step of exposing at least a portion of the structure to particles of electromagnetic radiation.
  • the radiation may have a wavelength in the range from about 1.5 ⁇ m to about 26 ⁇ m.
  • the radiation has a wavelength in the range from about 1.5 ⁇ m to about 3.8 ⁇ m. 2008/004035
  • an InAs APD such that an InAs avalanche region of the APD is sufficiently thick and is subjected to an electric field range of a sufficient size that the APD exhibits large avalanche gain with negligible excess noise.
  • FIGURE 1 is a cross-sectional schematic illustration of a pin APD structure according to an embodiment of the invention
  • FIGURE 2 shows a variation of (a) electric field and (b) dopant concentration as a function of distance in a pin APD structure according to the embodiment of FIG. 1 , the structure having a depletion width w;
  • FIGURE 3 is a cross-sectional schematic illustration of a pin APD structure according to an embodiment of the invention.
  • FIGURE 4 shows (a) the APD structure of FIG. 3 in combination with (b) a corresponding graphical profile of the number of carriers generated by incident photons as a function of position in the structure and (c) is a plot of band structure as a function of position in the material;
  • FIGURE 5 shows the band structure of the APD structure of FIG. 3 under a reverse bias condition
  • FIGURE 6 is a cross-sectional schematic illustration of a p pn APD structure according to an embodiment of the invention.
  • FIGURE 7 shows a variation of (a) electric field and (b) dopant concentration as a function of distance in a p pn APD structure according to the embodiment of FIG. 6, the structure having a depletion width w;
  • FIGURE 8 is a cross-sectional schematic illustration of an APD structure having an absorption region having a superlattice structure; and FIGURE 9 shows a variation of electric field as a function of depletion distance within a structure according to FIG. 8 under normal operating conditions.
  • an avalanche photodiode (APD) structure is fabricated as shown generally at 100 in FIG. 1.
  • the structure has a substrate 101 formed from InAs.
  • the substrate is n-type doped InAs having a dopant concentration greater than 10 18 cm '3 .
  • the dopant concentration is around 10 18 cm "3 .
  • dopant concentrations are also useful.
  • dopant types are also useful.
  • the structure has a GaAs substrate instead of an InAs substrate.
  • a buffer layer may be provided between the GaAs substrate and the structure.
  • n-type doped layer 102 formed from InAs is formed over the substrate 101.
  • the layer is formed to have a thickness of around 2 ⁇ m.
  • the n-type doped layer 102 has a dopant concentration of around 5x10 18 Cm "3 .
  • dopant concentrations are useful.
  • Other layer thicknesses are also useful.
  • the n-type doped layer 102 is formed on an n-type doped sublayer, the n-type doped sub-layer being formed on a GaAs substrate. In some embodiments the n-type doped sublayer is not provided, and the n-type doped layer 102 is provided directly on a buffer layer on a GaAs substrate. In some embodiments, the n- type doped layer is provided directly on a GaAs substrate.
  • a layer of intrinsic semiconductor material (intrinsic layer 104) is formed over the n-type doped layer 102.
  • the intrinsic layer 104 is formed from undoped InAs and has a thickness of about 2 ⁇ m.
  • a p-type doped layer 106 is formed over the intrinsic layer 104.
  • the p-type doped layer 106 has a dopant concentration of around 5x10 18 cm "3 and is formed to have a thickness of around 0.5 ⁇ m. Other dopant concentrations are useful. Other layer thicknesses are also useful.
  • the p-type doped layer 106 provides an absorption region, in which photons incident on the structure are absorbed, creating electron-hole pairs.
  • the p-type doped layer 106 may also be referred to as an 'absorption layer 1 .
  • the structure is subjected to an etch process to define a mesa structure 150 of width W1 (FIG. 1 ) that is less than a width W2 of a basal structure 160 from which the mesa structure 150 protrudes.
  • the mesa structure 150 includes a portion of n-type doped layer 102.
  • the structure is etched from a free surface of the p-type doped layer 106 to the n-type doped layer 102 such that at least a portion of n-type doped layer 102 is exposed. This allows an electrical contact to be formed to the n-type doped layer 102 in some embodiments of the invention.
  • An electrical contact 110 is provided to the p-type doped layer 106.
  • the electrical contact is formed such that the contact does not cover an entire free surface 106A of the p-type doped layer 106. This is to allow optical radiation to pass into the structure along the direction of arrow P (FIG. 1).
  • a back contact 120 may be formed on a reverse side of the substrate 101 with respect to the electrical contact 1 10.
  • the back contact 120 is formed from an InGe/Au bi-layer.
  • the layers are formed to have respective thicknesses of 20nm and 200nm.
  • a 20nm InGe layer is formed first, followed by a 200nm thick Au layer.
  • Other metallization schemes are also useful, for example a Ti/Pt/Au metallization scheme. Other thicknesses are also useful.
  • a p + doped substrate is used.
  • the electrical contact 120 may be formed on the n-type doped layer 102.
  • FIG. 2 is a schematic illustration of the variation of (a) electric field and (b) dopant concentration as a function of distance in a pin APD structure according to the embodiment of FIG. 1. It can be seen from FIG. 2(a) that the electric field is substantially constant in the intrinsic layer 104.
  • Devices fabricated according to the embodiment of FIG. 1 demonstrate high avalanche multiplication in the voltage range from around 10V to around 20V depending on the thickness of the intrinsic layer 104.
  • the intrinsic layer 104 corresponds to an 'avalanche region' in which avalanche multiplication of charge carriers takes place.
  • Devices fabricated according to the embodiment of FIG. 3 exhibit typical values of M of around 50. Values in excess of 50 may be achieved, for example by using higher values of reverse bias.
  • the devices may also be operated at room temperature if relatively high dark current can be tolerated. Optimum performance in devices according to the first embodiment has been observed in the temperature range from about 100K to about 200K.
  • Sensitivity of devices according to embodiments of the invention depends upon the responsivity and the dark current. Responsivity is largely determined by the thickness of the layer configured to absorb incident photons before they reach the avalanche region.
  • This layer may be referred to as an 'absorption layer'.
  • Thicker absorption layers generally provide devices of greater sensitivity.
  • the p-doped layer 106 corresponds to the absorption layer.
  • the p-doped layer 106 is heavily p-doped (p + doped), resulting in improved performance.
  • the absorption layer 106 is formed from p-doped material. This is in order to terminate the depletion region of the structure.
  • the absorption layer may be made relatively thick (for example, around 2 ⁇ m in the case of the embodiment shown in
  • FIG. 3 in order to ensure that the majority of incident photons of the appropriate wavelength are absorbed in the absorption layer. This in turn ensures that carrier injection into the depletion region is substantially only in the form of electron injection and not hole injection. Substantially pure electron injection is a necessary condition in order to achieve a substantial reduction in excess noise.
  • the device For increased absorption efficiency, however, the device should be configured such that photons are absorbed in the depletion region itself. However, this configuration can result in an increase in the level of excess noise. Therefore a balance must be found in order to optimise overall device performance.
  • an APD is provided having a pin structure as shown generally at 200 in FIG. 3.
  • the pin structure of this embodiment has an InAs substrate 201 provided with a series of five semiconductor layer provided thereon.
  • the InAs substrate in the embodiment of FIG. 3 is p- type doped, having a dopant concentration in excess of 10 18 cr ⁇ 3 .
  • the dopant concentration is around 10 18 cm "3 , whilst in some embodiments the dopant concentration is less than 10 18 cm '3 .
  • an n-type doped substrate is used.
  • an n + -type doped InAs layer 202 is first formed over the substrate 201 to a thickness of around 2 ⁇ m.
  • the n + -type doped layer 202 has a dopant concentration of around 5x10 18 cm '3 .
  • dopant concentrations are useful.
  • Other layer thicknesses are also useful.
  • a layer of intrinsic semiconductor material (intrinsic layer 204) is formed over the n + -type doped layer 202.
  • the intrinsic layer 204 is formed from undoped InAs and has a thickness of around 4 ⁇ m.
  • the thickness of the intrinsic layer 204 is in the range from about 1.5 ⁇ m to about 10 ⁇ m. In some embodiments of the invention the intrinsic layer 204 is from 5 ⁇ m to about 6 ⁇ m in thickness.
  • the intrinsic layer 204 provides an avalanche multiplication region, in other words a region in which, during operation of the device, avalanche multiplication of charge carriers can occur.
  • the structure is configured such that the electric field in the avalanche region is sufficiently high for ionization events to take place, providing useful gain, but sufficiently low to prevent band to band tunnelling current. It has been found that an intrinsic layer having a thickness in the range from around 2 ⁇ m to around 4 ⁇ m is useful. Other thicknesses are also useful. For example, a thickness of up to at least
  • a p + -type doped layer 206 is formed over the intrinsic layer 204.
  • the p + -type doped layer has a dopant concentration of around 5x10 18 Cm "3 and is formed to have a thickness of around 2 ⁇ m. Other dopant concentrations are useful. Other layer thicknesses are also useful.
  • the p + -type doped layer 206 is formed to provide an absorption region for incident photons.
  • the structure is configured whereby a substantial proportion of incident photons are absorbed in the p + -type doped layer 206, whereby electron-hole pairs are generated.
  • a blocking layer 209 is formed over the p + -type doped layer 206 in order to reduce diffusion current from an ohmic contact to be formed over the blocking layer to allow the structure to be connected to a circuit.
  • the blocking layer 209 (discussed in more detail below) is in the form of a layer of p-type doped AIAs 0 . ! 6 Sb 0 .84-
  • the blocking layer 209 has a thickness of around 200nm and a dopant concentration of around 1x10 18 cm '3 .
  • a contact layer 210 is formed between the blocking layer and an electrical contact 212.
  • the contact layer 210 is formed from p + -type doped InAs.
  • the contact layer has a thickness of around 100nm and a dopant concentration of around 5x10 18 cr ⁇ 3 .
  • Other dopant cohcentrations are useful for the blocking layer 209 and contact layer 210.
  • Other layer thicknesses are also useful for forming these layers.
  • other alloy compositions are also useful.
  • AI x ASySb 1 - J , alloy compositions are also useful.
  • Other AlxGa ⁇ AS y Sbv y alloy compositions are also useful.
  • the blocking layer has a thickness in the range from around 100nm to around 1 ⁇ m. In some embodiments the blocking layer has a thickness in the range from around 100nm to around 400nm.
  • the contact layer has a thickness in the range from around 50nm to around 1 ⁇ m. In some embodiments the blocking layer has a thickness in the range from around 50nm to around 200nm.
  • Inclusion of a blocking layer above the p + -type doped layer 206 has the advantage of ensuring a low dark current whilst at the same time allowing light absorption that will provide substantially pure electron injection. If the blocking layer is formed next to the intrinsic layer 204, the performance of the structure is found to be inferior.
  • An electrical contact 212 is provided to the contact layer 210.
  • the electrical contact 212 is formed to provide an ohmic contact to the contact layer 210.
  • the contact 212 is formed such that it does not cover an entire free surface 210A of the p + -type doped contact layer 210. Thus, optical radiation is able to pass into the structure along the direction of arrow P (FIG. 3).
  • the structure 200 is provided in the form of a mesa portion 250 and a basal portion 260, similar to the embodiment of FIG. 1.
  • the mesa portion has a width W1 that is less than that of the basal portion W2.
  • the mesa portion is formed by etching portions of the layers formed on the substrate 201 so as to expose a portion 203 of the n + -type doped layer 202.
  • the n + -type doped layer 202 is shared between the mesa portion 250 and the basal portion 260, allowing the formation of a grid contact 220 to the exposed surface 203 of the n + -type doped layer 202 of the basal portion 260.
  • the device is subjected to a reverse bias sufficient to cause avalanche multiplication by applying a potential between electrical contact 212 and the grid contact 220.
  • an electrical contact is formed on a back surface 201 B of the substrate 201 , instead of or in addition to the grid contact 220, and a reverse bias applied between the electrical contact 212 and the electrical contact formed on the back surface 201 B.
  • FIG. 4(a) shows such a structure, with basal contact 240 being formed on the back surface 201 B of substrate 201.
  • the purpose of the blocking layer 209 is to prevent minority electrons from the contact 212 diffusing to the avalanche region (intrinsic layer 204) of the structure. Such electrons will contribute to leakage current and unwanted avalanche multiplication processes, and cause the generation of unwanted noise.
  • FIG. 4 shows (a) an APD structure similar to that of FIG. 3 as discussed above in combination with a corresponding schematic graphical profile (FIG. 4(b)) of the number of carriers generated by incident photons as a function of position in the structure. Incident photons enter the structure from the left hand side of FIG. 4(a) generally along the direction of arrow P.
  • FIG. 4(c) illustrates the band structure of the APD structure of FIG. 4(a) as a function of position in the material.
  • FIG. 5 is a corresponding illustration of the band structure when a reverse bias sufficient to cause avalanche multiplication is applied to the APD structure.
  • the blocking layer 209 presents a substantial potential barrier to the passage of minority electrons from the contact 212 and contact layer 210 to the p7i junction 230.
  • a heterojunction exists between the blocking layer 209 and the p + doped contact layer 210, and between the blocking layer 209 and p + -type doped layer 206.
  • Majority holes returning to the contact layer 210 are able to overcome the valence band offset potential (indicated VBO in FIG. 5) that exists at these heterojunctions either thermionically or by tunnelling. This process is enhanced if the heterojunctions are formed to be abrupt and highly doped.
  • optically generated minority electrons from the p + doped layer 206 are able to reach the high field region of the structure (the intrinsic layer 204) and are subsequently swept towards the n + doped layer 202.
  • a p ' pn APD structure formed from InAs is provided as shown generally at 300 in FIG. 6.
  • This structure is referred to as a 'reach through' structure since in use under reverse bias conditions the electric field increases with position within a depletion region formed at the junction between p and n doped portions of the structure (FIG. 7(a)).
  • the structure has a substrate 301 formed from n-type doped InAs.
  • a contact layer of n- type doped InAs 308 is formed over the substrate 301.
  • the contact layer 308 is formed to be around 2 ⁇ m in thickness. Other thicknesses are also useful.
  • a layer of n-type doped InAs 302 is formed over the contact layer 308.
  • the n doped layer 302 is formed to be around 0.5 ⁇ m in thickness and has a dopant concentration of around 3x10 17 cm "3 .
  • n doped layer 302 Other thicknesses of n doped layer 302 are useful. Other dopant concentrations are also useful.
  • a layer of p-type doped InAs 304 around 1 ⁇ m in thickness is formed, having a dopant concentration also of around 6x10 15 cm “3 .
  • a layer of lightly doped p-type InAs (p " doped InAs) layer 306 is formed, also around 2 ⁇ m in thickness.
  • the p ' doped layer has a dopant concentration lower than that of the p doped layer, the dopant concentration being around 3x10 15 cm '3 in the p " doped layer.
  • a p doped contact layer 307 is formed over the p " doped InAs layer 306.
  • the p doped contact layer is formed to be around 0.2 ⁇ m thick and has a dopant concentration of around 5x10 18 cm “3 .
  • An electrical contact element 310 is formed to the p doped contact layer 307, the contact element 310 forming an ohmic contact with the contact layer 307.
  • a contact element 320 is formed to an underside of the InAs substrate 301.
  • an etching process is performed to define a mesa structure of width W1 as shown in FIG. 6.
  • the contact layer 308 is not etched, but layers above the contact layer 308 are etched as is apparent from FIG. 6.
  • the substrate is also cleaved to form a discrete device having a substrate of width W2, as shown in FIG. 6.
  • FIG. 7 shows a variation of (a) electric field and (b) dopant concentration as a function of distance through a depletion region of width w in a p pn APD structure according to the embodiment of FIG. 6 described above.
  • the p ' -doped layer 306 is replaced by a p + -doped layer having a dopant concentration of around 1 x 10 18 Cm '3 .
  • the p doped layer 304 has a dopant concentration of around 3x10 15 cm "3 and the n doped layer has a dopant concentration of around 5x10 17 cm "3 .
  • the p-doped layer is replaced by an n-doped layer. In each case, however, the device is configured such that avalanche multiplication takes place at the junction between p-type and n-type doped InAs.
  • layer 306 is heavily p-type doped (p + doped), layer 304 is p doped and layer 302 is n doped. In some embodiments, layer 306 is p + doped, layer 304 is n doped and layer 302 is also n doped.
  • the ordering of layers on the substrate according to embodiments of the invention has been described in the context of radiation incident from a side of the device structure opposite the substrate, it will be appreciated that the device may alternatively be formed to detect radiation passing through the substrate to the avalanche region, for example in focal plane array structures. In the case of a focal plane array structure, a n + ip + structure may be more appropriate since light will enter from the lower side of the structure with respect to the orientation of the structure of FIG.
  • the structure is formed having a substrate having a wider bandgap than InAs, whereby incident radiation is not absorbed by the substrate, but rather is able to pass through the substrate to the avalanche region.
  • the substrate is thinned or a portion substantially removed in order to reduce absorption of photons by the substrate.
  • some embodiments of the invention are provided in the form of layers formed over one another on a substrate. Doping of one or more of the layers may be performed in-situ. In some embodiments, doping of one or more of the layers is performed ex-situ.
  • structures are formed in a lateral manner in a semiconductor substrate.
  • regions of the substrate are doped, for example by ion implantation or other suitable technique, in a lateral configuration over the substrate.
  • a structure is provided as shown in FIG. 8.
  • the structure has a substrate 401 formed from n-type doped InAs.
  • the cladding layer 402 is formed to be around 200nm in thickness. Other thicknesses are also useful. Other cladding materials are also useful.
  • a layer of intrinsic semiconductor material (substantially undoped InAs) is formed over the cladding layer 402, providing an avalanche multiplication layer 404.
  • the avalanche layer 404 is formed to be around 2.5 ⁇ m in thickness. Other thicknesses are also useful. 04035
  • a charge sheet layer 405 is formed over the avalanche multiplication layer 404.
  • the charge sheet layer 405 is formed to be around 100nm in thickness.
  • the charge sheet layer 405 is formed from InAs.
  • the charge sheet layer 405 is formed from a AI x Ga 1 . x AsySbi-y alloy.
  • the value of x may be in the range from 0 to 1 , whilst the value of y may also be in the range from 0 to 1.
  • the value of x is in the range of from 0.2 to 0.8 and the value of y is in the range of from 0.2 to 0.8.
  • An absorption layer 406 is formed above the charge sheet layer 405.
  • the absorption layer is formed from a type Il InAs/GaSb superlattice structure.
  • the structure has a series of alternating layers of InAs and GaSb.
  • each of the layers has a thickness of around 2OA.
  • the thickness of the layers may be adjusted in order to tune the wavelength of radiation absorbed by the absorption layer.
  • the layers have a thickness of from around 2OA to around 8OA. In general, the thicker the layers the longer the absorption wavelength will be.
  • a heavily doped p-type doped (p + -doped) cladding layer 407 is formed above the absorption layer 406.
  • the p + -doped cladding layer 407 is formed to have a thickness of around 200nm. Other thicknesses are also useful. Other materials are also useful for forming the cladding layer.
  • a contact element 410 is formed over the p + -doped cladding layer 407 and is configured to form an ohmic contact to the cladding layer 407.
  • the contact element is formed over a portion of the p + -doped cladding layer 407, such that a portion of the cladding layer 407 is not covered by the contact element 410.
  • a further electrical contact 420 is made to the substrate 401.
  • the contact 420 is formed on a back surface of the substrate opposite the surface on which the n + -doped cladding layer 402 is formed.
  • a structure according to the embodiment of FIG. 8 is operable to generate electron-hole pairs in the absorption layer 406 when the structure is irradiated with infra-red radiation in the range from around 3 ⁇ m to around 26 ⁇ m. Under applied reverse bias conditions, electrons generated by absorption of radiation drift to the InAs avalanche multiplication layer 404, where impact ionization events are generated resulting in the formation of new electron-hole pairs.
  • the embodiment shown in FIG. 8 is provided with the further feature of a blocking layer as described with respect to the embodiments of FIGs. 3 to 5.
  • FIG. 9 shows the variation of electric field as a function of position within a depletion region of a structure according to FIG. 8 under normal operating conditions. It can be seen that the structure is configured to have a larger electric field in the avalanche layer 404 (labelled 'A 1 in FIG. 9) compared with the absorption layer 406 (labelled 'S' in FIG. 9).
  • processing steps are introduced in order to reduce surface leakage current.
  • the processing steps are performed before the formation of metal contact elements to the structure (such as contacts 1 10, 120, 212, 220).
  • the structure is subjected to an etch process in order to form a mesa structure (as shown schematically for example in FIGs 1 , 3 and 6).
  • the structure is etched using an etching solution comprising a mixture of a solution of around 85 weight percent phosphoric acid, a solution of around 30 weight percent hydrogen peroxide and deionised water substantially in the volume ratio 1 :1 :1.
  • Etching is performed until individual mesa devices (or pixels) are isolated from one another, that is to say until the etch has removed unmasked areas of material down to a level beyond the electrical junction between p and n type material (or p, i and n type material in the case of a pin structure).
  • etching is preferably performed until at least a portion of n-type doped layer 102 has been etched so that depletion under an operating reverse bias occurs in intrinsic layer 104, at least a portion of p-doped layer 106 and at least a portion of the etched potion of n-type doped layer 102.
  • the time duration of the first etch process will therefore depend on the nature of the structure being etched. In some embodiments, etch rates at 20 0 C of around 1.1 ⁇ m per minute may be used. Other etch rates are also useful. It will be appreciated that variations of the first etch process may be used, such as etch processes in which a structure is etched to a greater or lesser extent.
  • composition of the etchant solution is not limited strictly to a 1 :1 :1 ratio, and that solutions having a composition that is a variation of this ratio are also useful, such as 5:5:6 or ratios in the range generally 0.5-2 : 0.5-2 : 1.
  • a second etch process (a 'finishing' process) is performed whereby the structure is immersed in a finishing solution.
  • the finishing solution comprises a mixture of around 98 weight percent sulphuric acid, a solution of around 30 weight percent hydrogen peroxide and deionised water substantially in the volume ratio 1 :8:80.
  • Other ratios are also useful, such as a solution having these solutions generally in the volume ratio 1 : 7-10 : 70-100.
  • the structure is exposed to the finishing solution for a period typically from around 5 to around 60 seconds, preferably from around 20 to around 30 seconds, at 2O 0 C.
  • finishing process temperatures are also useful.
  • the two-step sequential etching process described above provides a structure having a reduced surface leakage current and hence improved device performance compared with a single step etching process and other known multiple-step processes.
  • a dielectric layer is formed over the structure to passivate the structure.
  • the dielectric is benzocyclobutene (BCB).
  • BCB benzocyclobutene
  • the dielectric is formed to a thickness such that, after curing of the dielectric, the mesa structures are effectively buried.
  • the dielectric is formed such that a free surface of the dielectric layer is substantially flat.
  • the dielectric is formed to have a thickness such that an upper portion of a mesa is around 1 ⁇ m to around 2 ⁇ m below a surface of the dielectric.
  • the thickness of the dielectric layer is in the range from around 0.1 ⁇ m to around 100 ⁇ m.
  • the dielectric is cured at around 300 0 C.
  • surface passivation is achieved by overgrowth of a wider band gap material (having high resistivity) over the structure.
  • An alternative method of surface passivation is to perform ion implantation to increase surface resistance.
  • implantation of Fe and/or Ti is used to increase surface resistivity.
  • implantation of Fe and/or Ti is used to increase surface resistivity of InGaAs.
  • ion implantation is performed to render the surface substantially non-conducting thereby to reduce surface leakage current substantially.
  • a combination of techniques are used to increase surface resistivity. For example, in some embodiments a combination of ion implantation and overgrowth is performed, ion implantation being performed before overgrowth in some embodiments and after overgrowth in some other embodiments.
  • Metal contacts may then be formed to the structure in order to allow the structure to be connected to a circuit. Portions of the dielectric layer may be removed by an etching process in order to form the contacts.
  • the metal contacts are formed from an alloy of titanium and gold (TiAu).
  • a depletion region in the range of from about 2 ⁇ m to about 4 ⁇ m wide provides useful gain whilst at the same time keeping the dark current low and avoiding band to band tunnelling current.
  • a depletion region in the range up to about 10 ⁇ m wide also provides useful gain whilst at the same time keeping the dark current low and avoiding band to band tunnelling current.

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Abstract

La présente invention concerne une structure de photodiode à avalanche pour la plage des infrarouges. Ladite photodiode présente une région de multiplication par avalanche (104) comprenant de l'InAs. Ainsi, un bruit excédentaire faible de la structure de photodiode à avalanche est obtenu. L'invention concerne également un procédé de formation d'une structure mesa (150) à partir d'InAs.
PCT/GB2008/004035 2007-12-06 2008-12-08 Structure de photodiode infrarouge à avalanche à bruit excédentaire faible et son procédé de fabrication WO2009071916A1 (fr)

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GB0723858A GB0723858D0 (en) 2007-12-06 2007-12-06 Avalance photodiode structure and method
GB0723858.7 2007-12-06
GB0812054A GB0812054D0 (en) 2008-07-02 2008-07-02 Avalanche photodiode structure and method
GB0812054.5 2008-07-02

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WO2011144938A3 (fr) * 2010-05-19 2012-08-23 The University Of Sheffield Structure de photodiode à avalanche et procédé
CN103022218A (zh) * 2012-12-26 2013-04-03 华中科技大学 一种InAs雪崩光电二极管及其制造方法
WO2014165228A1 (fr) * 2013-03-12 2014-10-09 The Regents Of The University Of California Dispositifs de conversion optique/électrique de haute efficacité
US20160005887A1 (en) * 2013-03-12 2016-01-07 The Regents Of The University Of California Highly efficient optical to electrical conversion devices and methods
CN107749424A (zh) * 2017-10-24 2018-03-02 江门市奥伦德光电有限公司 一种雪崩光电二极管及其制备方法
CN114300574A (zh) * 2021-11-25 2022-04-08 中国电子科技集团公司第十一研究所 一种基于InAs的APD结构的制备方法

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Cited By (10)

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Publication number Priority date Publication date Assignee Title
WO2011144938A3 (fr) * 2010-05-19 2012-08-23 The University Of Sheffield Structure de photodiode à avalanche et procédé
CN103022218A (zh) * 2012-12-26 2013-04-03 华中科技大学 一种InAs雪崩光电二极管及其制造方法
WO2014165228A1 (fr) * 2013-03-12 2014-10-09 The Regents Of The University Of California Dispositifs de conversion optique/électrique de haute efficacité
KR20150144317A (ko) * 2013-03-12 2015-12-24 더 리젠츠 오브 더 유니버시티 오브 캘리포니아 매우 효율적인 광-전기 변환 디바이스들
US20160005887A1 (en) * 2013-03-12 2016-01-07 The Regents Of The University Of California Highly efficient optical to electrical conversion devices and methods
KR102279914B1 (ko) * 2013-03-12 2021-07-22 더 리젠츠 오브 더 유니버시티 오브 캘리포니아 매우 효율적인 광-전기 변환 디바이스들
US11637216B2 (en) 2013-03-12 2023-04-25 The Regents Of The University Of California Highly efficient optical to electrical conversion devices and MElHODS
CN107749424A (zh) * 2017-10-24 2018-03-02 江门市奥伦德光电有限公司 一种雪崩光电二极管及其制备方法
CN107749424B (zh) * 2017-10-24 2023-11-07 江门市奥伦德光电有限公司 一种雪崩光电二极管及其制备方法
CN114300574A (zh) * 2021-11-25 2022-04-08 中国电子科技集团公司第十一研究所 一种基于InAs的APD结构的制备方法

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