WO2009063853A1 - チップ内およびチップ間通信回路と通信方法及び３次元ｌｓｉ装置 - Google Patents

チップ内およびチップ間通信回路と通信方法及び３次元ｌｓｉ装置 Download PDF

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Publication number
WO2009063853A1
WO2009063853A1 PCT/JP2008/070482 JP2008070482W WO2009063853A1 WO 2009063853 A1 WO2009063853 A1 WO 2009063853A1 JP 2008070482 W JP2008070482 W JP 2008070482W WO 2009063853 A1 WO2009063853 A1 WO 2009063853A1
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WO
WIPO (PCT)
Prior art keywords
circuit
transmitting
clock
time difference
clock time
Prior art date
Application number
PCT/JP2008/070482
Other languages
English (en)
French (fr)
Inventor
Yasuhiko Hagihara
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Publication of WO2009063853A1 publication Critical patent/WO2009063853A1/ja

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

　本発明は、レイテンシを固定できる通信回路と通信方法を提供する。送受信回路６と送受信回路５には、クロック発生回路２、１からクロック分配回路１１、１０を経由したクロック３００、２００が分配され、送受信回路５において、送受信回路６から送信された信号３０１は、オーバーサンプリング回路・位相発生回路１２３で、送信回路と受信回路のクロックの時間差の高周波成分（クロック時間差が高い周波数で変動）に相当する時間調整を行い、可変レイテンシバッファ１２２に送られ、低周波位相差検出回路１２１で検出したクロック時間差の低周波成分（クロック時間差が低い周波数で変動）が何サイクルに相当するかを検出し、予め取り決めた時間とクロック時間差の低周波成分の差をサイクル数に換算し可変レイテンシバッファ１２２で時間調整をしてフリップフロップ１０１へ送られる（図１）。
PCT/JP2008/070482 2007-11-12 2008-11-11 チップ内およびチップ間通信回路と通信方法及び３次元ｌｓｉ装置 WO2009063853A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-293518 2007-11-12
JP2007293518 2007-11-12

Publications (1)

Publication Number Publication Date
WO2009063853A1 true WO2009063853A1 (ja) 2009-05-22

Family

ID=40638702

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/070482 WO2009063853A1 (ja) 2007-11-12 2008-11-11 チップ内およびチップ間通信回路と通信方法及び３次元ｌｓｉ装置

Country Status (1)

Country Link
WO (1) WO2009063853A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117713983A (zh) * 2024-02-05 2024-03-15 浙江华创视讯科技有限公司 时钟同步监测方法、装置、级联系统和计算机设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213895A (ja) * 1995-02-08 1996-08-20 Kawasaki Steel Corp 信号タイミング調整回路
JPH10135938A (ja) * 1996-10-30 1998-05-22 Matsushita Electric Ind Co Ltd 非同期信号同期化回路
JPH11243405A (ja) * 1998-02-26 1999-09-07 Nec Ic Microcomput Syst Ltd 非同期式シリアル通信方式
JP2007109773A (ja) * 2005-10-12 2007-04-26 Sharp Corp 大規模半導体集積回路装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213895A (ja) * 1995-02-08 1996-08-20 Kawasaki Steel Corp 信号タイミング調整回路
JPH10135938A (ja) * 1996-10-30 1998-05-22 Matsushita Electric Ind Co Ltd 非同期信号同期化回路
JPH11243405A (ja) * 1998-02-26 1999-09-07 Nec Ic Microcomput Syst Ltd 非同期式シリアル通信方式
JP2007109773A (ja) * 2005-10-12 2007-04-26 Sharp Corp 大規模半導体集積回路装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117713983A (zh) * 2024-02-05 2024-03-15 浙江华创视讯科技有限公司 时钟同步监测方法、装置、级联系统和计算机设备
CN117713983B (zh) * 2024-02-05 2024-05-07 浙江华创视讯科技有限公司 时钟同步监测方法、装置、级联系统和计算机设备

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