WO2009063584A1 - プログラマブルデバイス、デバイス制御方法及び情報処理システム - Google Patents

プログラマブルデバイス、デバイス制御方法及び情報処理システム Download PDF

Info

Publication number
WO2009063584A1
WO2009063584A1 PCT/JP2008/002567 JP2008002567W WO2009063584A1 WO 2009063584 A1 WO2009063584 A1 WO 2009063584A1 JP 2008002567 W JP2008002567 W JP 2008002567W WO 2009063584 A1 WO2009063584 A1 WO 2009063584A1
Authority
WO
WIPO (PCT)
Prior art keywords
core logic
constitution
programmable device
power
information processing
Prior art date
Application number
PCT/JP2008/002567
Other languages
English (en)
French (fr)
Inventor
Shinichiro Nishioka
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to US12/598,099 priority Critical patent/US7863930B2/en
Priority to CN2008800160535A priority patent/CN101971500A/zh
Priority to JP2009541021A priority patent/JP5204123B2/ja
Publication of WO2009063584A1 publication Critical patent/WO2009063584A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17772—Structural details of configuration resources for powering on or off
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Programmable Controllers (AREA)

Abstract

　消費電力を低減しつつ高速に動作することができるプログラマブルデバイスを提供する。 　プログラマブルデバイス２は、構成メモリ２１とコアロジック２２を含む複数のプロセッシングタイル１１と、それらをプログラミングする構成制御手段１３と、それらの動作状態に応じて電力供給を遮断する電力制御手段１２とを備え、コアロジック２２の内部状態を構成メモリ１１に退避してからコアロジック２２の電源を遮断し、またコアロジック２２の電源を再度供給し、前記内部状態を構成メモリ２１からコアロジック２２へ復帰することで、内部状態を維持しつつ省電力化される。
PCT/JP2008/002567 2007-11-13 2008-09-18 プログラマブルデバイス、デバイス制御方法及び情報処理システム WO2009063584A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/598,099 US7863930B2 (en) 2007-11-13 2008-09-18 Programmable device, control method of device and information processing system
CN2008800160535A CN101971500A (zh) 2007-11-13 2008-09-18 可编程设备、设备控制方法及信息处理系统
JP2009541021A JP5204123B2 (ja) 2007-11-13 2008-09-18 プログラマブルデバイス、デバイス制御方法及び情報処理システム

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-293926 2007-11-13
JP2007293926 2007-11-13

Publications (1)

Publication Number Publication Date
WO2009063584A1 true WO2009063584A1 (ja) 2009-05-22

Family

ID=40638440

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/002567 WO2009063584A1 (ja) 2007-11-13 2008-09-18 プログラマブルデバイス、デバイス制御方法及び情報処理システム

Country Status (4)

Country Link
US (1) US7863930B2 (ja)
JP (1) JP5204123B2 (ja)
CN (1) CN101971500A (ja)
WO (1) WO2009063584A1 (ja)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102714496A (zh) * 2010-01-20 2012-10-03 株式会社半导体能源研究所 半导体装置
JP2013013067A (ja) * 2011-05-31 2013-01-17 Semiconductor Energy Lab Co Ltd プログラマブルロジックデバイス
JP2013178770A (ja) * 2012-02-28 2013-09-09 Samsung Electronics Co Ltd 再構成可能プロセッサ及びそのコード変換装置及び方法
JP2014506073A (ja) * 2011-01-13 2014-03-06 ザイリンクス インコーポレイテッド 集積回路における電力マネジメント
JP2014099843A (ja) * 2012-10-17 2014-05-29 Semiconductor Energy Lab Co Ltd プログラマブルロジックデバイスの駆動方法
KR20140147045A (ko) * 2013-06-18 2014-12-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2016516363A (ja) * 2013-03-15 2016-06-02 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア Ｆｐｇａインターコネクトにおける細粒度型パワーゲーティング
JP2018107799A (ja) * 2016-12-27 2018-07-05 株式会社半導体エネルギー研究所 撮像装置および電子機器
WO2018180536A1 (ja) * 2017-03-28 2018-10-04 日本電気株式会社 プログラマブル論理集積回路とそのプログラミング方法及びそのプログラム
JP2020018007A (ja) * 2011-05-20 2020-01-30 株式会社半導体エネルギー研究所 半導体装置
US10564698B2 (en) 2016-08-19 2020-02-18 Semiconductor Energy Laboratory Co., Ltd. Method for controlling power supply in semiconductor device

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7551508B2 (en) * 2007-11-16 2009-06-23 International Business Machines Corporation Energy efficient storage device using per-element selectable power supply voltages
US8341582B2 (en) * 2009-01-30 2012-12-25 Active-Semi, Inc. Programmable analog tile configuration tool
US8219956B2 (en) * 2009-01-30 2012-07-10 Active-Semi, Inc. Analog tile selection, placement, configuration and programming tool
US8079007B2 (en) * 2009-01-30 2011-12-13 Active-Semi, Inc. Programmable analog tile programming tool
US8225260B2 (en) * 2009-01-30 2012-07-17 Active-Semi, Inc. Programmable analog tile placement tool
US9003340B2 (en) 2009-01-30 2015-04-07 Active-Semi, Inc. Communicating configuration information across a programmable analog tile to another tile
US8117428B2 (en) * 2009-06-04 2012-02-14 Texas Instruments Incorporated Apparatus and method for automatically saving and restoring pad configuration registers implemented in a core power domain
US8503264B1 (en) * 2011-11-18 2013-08-06 Xilinx, Inc. Reducing power consumption in a segmented memory
US8743653B1 (en) 2012-06-20 2014-06-03 Xilinx, Inc. Reducing dynamic power consumption of a memory circuit
JP6254834B2 (ja) * 2012-12-06 2017-12-27 株式会社半導体エネルギー研究所 半導体装置
US8860457B2 (en) * 2013-03-05 2014-10-14 Qualcomm Incorporated Parallel configuration of a reconfigurable instruction cell array
CN103746942B (zh) * 2013-11-26 2017-06-27 苏州智汇谱电子科技有限公司 一种门控开关装置
US10331201B2 (en) * 2016-07-20 2019-06-25 Imec Vzw Power control in integrated circuits
JP6618455B2 (ja) * 2016-11-28 2019-12-11 日立オートモティブシステムズ株式会社 電子制御装置、車載システム、および電源制御方法
US10079054B1 (en) * 2017-06-05 2018-09-18 Lattice Semiconductor Corporation Selective power gating of routing resource configuration memory bits for programmable logic devices
US10529412B1 (en) 2019-04-09 2020-01-07 Micron Technology, Inc. Output buffer circuit with non-target ODT function
KR20220000587A (ko) * 2020-06-26 2022-01-04 에스케이하이닉스 주식회사 파워 게이팅 제어 회로 및 이를 포함하는 반도체 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001093275A (ja) * 1999-09-20 2001-04-06 Mitsubishi Electric Corp 半導体集積回路装置
JP2001284530A (ja) * 2000-03-29 2001-10-12 Matsushita Electric Ind Co Ltd 半導体集積回路
JP2005005611A (ja) * 2003-06-13 2005-01-06 Matsushita Electric Ind Co Ltd 半導体集積回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548228A (en) * 1994-09-28 1996-08-20 Altera Corporation Reconfigurable programmable logic device having static and non-volatile memory
US5778439A (en) * 1995-08-18 1998-07-07 Xilinx, Inc. Programmable logic device with hierarchical confiquration and state storage
JP3106998B2 (ja) 1997-04-11 2000-11-06 日本電気株式会社 メモリ付加型プログラマブルロジックｌｓｉ
US7098689B1 (en) * 2003-09-19 2006-08-29 Xilinx, Inc. Disabling unused/inactive resources in programmable logic devices for static power reduction
US20060119382A1 (en) * 2004-12-07 2006-06-08 Shumarayev Sergey Y Apparatus and methods for adjusting performance characteristics of programmable logic devices
US7620926B1 (en) * 2007-03-20 2009-11-17 Xilinx, Inc. Methods and structures for flexible power management in integrated circuits
US7675317B2 (en) * 2007-09-14 2010-03-09 Altera Corporation Integrated circuits with adjustable body bias and power supply circuitry

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001093275A (ja) * 1999-09-20 2001-04-06 Mitsubishi Electric Corp 半導体集積回路装置
JP2001284530A (ja) * 2000-03-29 2001-10-12 Matsushita Electric Ind Co Ltd 半導体集積回路
JP2005005611A (ja) * 2003-06-13 2005-01-06 Matsushita Electric Ind Co Ltd 半導体集積回路

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9614097B2 (en) 2010-01-20 2017-04-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2021002849A (ja) * 2010-01-20 2021-01-07 株式会社半導体エネルギー研究所 プログラマブル回路及びｆｐｇａ
US10454475B2 (en) 2010-01-20 2019-10-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2022081601A (ja) * 2010-01-20 2022-05-31 株式会社半導体エネルギー研究所 プログラマブル回路
TWI512899B (zh) * 2010-01-20 2015-12-11 Semiconductor Energy Lab 半導體裝置
CN102714496A (zh) * 2010-01-20 2012-10-03 株式会社半导体能源研究所 半导体装置
KR101606247B1 (ko) * 2011-01-13 2016-03-24 자일링크스 인코포레이티드 집적 회로 내에서의 전력 관리
JP2014506073A (ja) * 2011-01-13 2014-03-06 ザイリンクス インコーポレイテッド 集積回路における電力マネジメント
US10897258B2 (en) 2011-05-20 2021-01-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11750194B2 (en) 2011-05-20 2023-09-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2022023123A (ja) * 2011-05-20 2022-02-07 株式会社半導体エネルギー研究所 半導体装置
JP2020018007A (ja) * 2011-05-20 2020-01-30 株式会社半導体エネルギー研究所 半導体装置
JP2013013067A (ja) * 2011-05-31 2013-01-17 Semiconductor Energy Lab Co Ltd プログラマブルロジックデバイス
JP2013178770A (ja) * 2012-02-28 2013-09-09 Samsung Electronics Co Ltd 再構成可能プロセッサ及びそのコード変換装置及び方法
JP2014099843A (ja) * 2012-10-17 2014-05-29 Semiconductor Energy Lab Co Ltd プログラマブルロジックデバイスの駆動方法
JP2016516363A (ja) * 2013-03-15 2016-06-02 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア Ｆｐｇａインターコネクトにおける細粒度型パワーゲーティング
KR20140147045A (ko) * 2013-06-18 2014-12-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR102270580B1 (ko) * 2013-06-18 2021-06-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US10564698B2 (en) 2016-08-19 2020-02-18 Semiconductor Energy Laboratory Co., Ltd. Method for controlling power supply in semiconductor device
US11281285B2 (en) 2016-08-19 2022-03-22 Semiconductor Energy Laboratory Co., Ltd. Method for controlling power supply in semiconductor device
JP2018107799A (ja) * 2016-12-27 2018-07-05 株式会社半導体エネルギー研究所 撮像装置および電子機器
WO2018180536A1 (ja) * 2017-03-28 2018-10-04 日本電気株式会社 プログラマブル論理集積回路とそのプログラミング方法及びそのプログラム

Also Published As

Publication number Publication date
JP5204123B2 (ja) 2013-06-05
US20100148820A1 (en) 2010-06-17
JPWO2009063584A1 (ja) 2011-03-31
US7863930B2 (en) 2011-01-04
CN101971500A (zh) 2011-02-09

Similar Documents

Publication Publication Date Title
WO2009063584A1 (ja) プログラマブルデバイス、デバイス制御方法及び情報処理システム
EP2003534A3 (en) Method of and apparatus for reducing power consumption within an integrated circuit.
TW200736899A (en) Method and apparatus for controlling power supply in a computer system
TW200943046A (en) System and method for fast platform hibernate and resume
WO2006077561A3 (en) System and method of configuring a control system for a plurality of devices
TW200801924A (en) A power management system, controller, method with multiple power sources and media player thereof
EP2242058A3 (en) Flash memory system control scheme
TW200733558A (en) Instantaneous data-driven clock-gating device and hard-wired streaming processing system including the same
TW200629054A (en) Apparatus and method of controlling power in a portable system
WO2013165786A3 (en) Power management for a system having non-volatile memory
WO2007113766A3 (en) Method and system for i2c clock generation
WO2010085340A3 (en) Host controller
WO2012096528A3 (ko) 저전력 무선 통신 모듈을 이용한 ｌｅｄ 조명 제어 방법 및 시스템
WO2007002381A3 (en) Multi-channel ldpc decoder architecture
EP2064797A4 (en) INSULATION CONTROL HIGH-SPEED TRANSFORMER SWITCH FOR AN UNIMBURBABLE POWER SUPPLY, SWITCH USING THE POWER SUPPLY SYSTEM, AND INSULATION CONTROL HIGH-SPEED TRANSMISSION PROCESS
EP2897005B1 (en) Control device, control system, control method, program, and medium for recording same
EP3699912A3 (en) Semiconductor device
WO2004109436A3 (en) Uninterrupted system operation
WO2008056293A3 (en) Fast adaptive voltage scaling
WO2009001514A1 (ja) メモリコントローラ、不揮発性記憶装置、ファイルシステム、不揮発性記憶システム、データ書き込み方法及びデータ書き込みプログラム
JP2013073318A5 (ja)
WO2007103219A3 (en) Firmware extendable commands for a microcontroller based flash memory digital controller
JP2013168028A5 (ja) 情報処理装置及びその制御方法とプログラム
ZA200805503B (en) Method for storing a data block containing data for controlling a technical process, and control and automation apparatus
TW200702988A (en) Command process method for RAID

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880016053.5

Country of ref document: CN

DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08849516

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009541021

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 12598099

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08849516

Country of ref document: EP

Kind code of ref document: A1