WO2009060514A1 - 半導体装置の製造方法、ウエハおよびウエハの製造方法 - Google Patents
半導体装置の製造方法、ウエハおよびウエハの製造方法 Download PDFInfo
- Publication number
- WO2009060514A1 WO2009060514A1 PCT/JP2007/071565 JP2007071565W WO2009060514A1 WO 2009060514 A1 WO2009060514 A1 WO 2009060514A1 JP 2007071565 W JP2007071565 W JP 2007071565W WO 2009060514 A1 WO2009060514 A1 WO 2009060514A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chips
- wafer
- dicing
- manufacturing
- pieces
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
1枚のウエハから異なる平面サイズのチップを一定数、効率的に取得する。 平面サイズが整数倍異なるチップ(A),(B),(C)について、最大のチップ(C)をウエハ(1)の中央部にその直径方向に整列配置し、その外側に中間のチップ(B)を整列配置し、さらにその外側に最小のチップ(A)を整列配置する。各チップ(A),(B),(C)を配置したウエハ(1)について、まず最大のチップ(C)を個片化するダイシングを行ってチップ(C)を取得し、続いて中間のチップ(B)を個片化するダイシングを行ってチップ(B)を取得し、最後に最小のチップ(A)を個片化するダイシングを行ってチップ(A)を取得する。これにより、ウエハ(1)からチップ(A),(B),(C)を、それぞれ一定の取得数を確保しつつ、ダイシング時にスクライブラインのT字交差位置での破壊を回避して、取得することができる。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/071565 WO2009060514A1 (ja) | 2007-11-06 | 2007-11-06 | 半導体装置の製造方法、ウエハおよびウエハの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/071565 WO2009060514A1 (ja) | 2007-11-06 | 2007-11-06 | 半導体装置の製造方法、ウエハおよびウエハの製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009060514A1 true WO2009060514A1 (ja) | 2009-05-14 |
Family
ID=40625429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/071565 WO2009060514A1 (ja) | 2007-11-06 | 2007-11-06 | 半導体装置の製造方法、ウエハおよびウエハの製造方法 |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2009060514A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018015114A1 (en) * | 2016-07-19 | 2018-01-25 | Asml Netherlands B.V. | Determining the combination of patterns to be applied to a substrate in a lithography step |
US20180158788A1 (en) * | 2016-12-01 | 2018-06-07 | Avery Dennison Retail Information Services, Llc | Mixed structure method of layout of different size elements to optimize the area usage on a wafer |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0737766A (ja) * | 1993-07-19 | 1995-02-07 | Sony Corp | ウエハ上のチップ割り当て方法 |
JPH08186064A (ja) * | 1994-12-28 | 1996-07-16 | Nec Kyushu Ltd | 半導体ウエハおよび半導体ペレットの分割方法 |
JPH09199377A (ja) * | 1996-01-22 | 1997-07-31 | Mitsubishi Electric Corp | チップ製造方法 |
JP2001148358A (ja) * | 1999-11-19 | 2001-05-29 | Disco Abrasive Syst Ltd | 半導体ウェーハ及び該半導体ウェーハの分割方法 |
-
2007
- 2007-11-06 WO PCT/JP2007/071565 patent/WO2009060514A1/ja active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0737766A (ja) * | 1993-07-19 | 1995-02-07 | Sony Corp | ウエハ上のチップ割り当て方法 |
JPH08186064A (ja) * | 1994-12-28 | 1996-07-16 | Nec Kyushu Ltd | 半導体ウエハおよび半導体ペレットの分割方法 |
JPH09199377A (ja) * | 1996-01-22 | 1997-07-31 | Mitsubishi Electric Corp | チップ製造方法 |
JP2001148358A (ja) * | 1999-11-19 | 2001-05-29 | Disco Abrasive Syst Ltd | 半導体ウェーハ及び該半導体ウェーハの分割方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018015114A1 (en) * | 2016-07-19 | 2018-01-25 | Asml Netherlands B.V. | Determining the combination of patterns to be applied to a substrate in a lithography step |
JP2019522820A (ja) * | 2016-07-19 | 2019-08-15 | エーエスエムエル ネザーランズ ビー.ブイ. | リソグラフィステップにおける基板に施されるべきパターンの組み合わせの決定 |
US11747738B2 (en) | 2016-07-19 | 2023-09-05 | Asml Netherlands B.V. | Determining the combination of patterns to be applied to a substrate in a lithography step |
US20180158788A1 (en) * | 2016-12-01 | 2018-06-07 | Avery Dennison Retail Information Services, Llc | Mixed structure method of layout of different size elements to optimize the area usage on a wafer |
CN110023961A (zh) * | 2016-12-01 | 2019-07-16 | 艾利丹尼森零售信息服务公司 | 不同尺寸元件布局的混合结构方法以优化晶圆的面积使用 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2007035234A3 (en) | Semiconductor stacked die/wafer configuration and packaging and method thereof | |
SG155133A1 (en) | Semiconductor package and method of making the same | |
TWI368311B (en) | Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package | |
WO2008135905A3 (en) | A photosensitive device and a method of manufacturing a photosensitive device | |
WO2008105315A1 (ja) | 磁気メモリチップ装置の製造方法 | |
TW200729390A (en) | Method for making semiconductor wafer | |
AU2003235902A1 (en) | Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods | |
EP1975998A3 (en) | Method for manufacturing a plurality of island-shaped SOI structures | |
TWI372439B (en) | Semiconductor wafer positioning method, and apparatus using the same | |
WO2006075725A3 (en) | Manufacturing method for semiconductor chips and semiconductor wafer | |
EP3879011A4 (en) | SIC SEMICONDUCTOR SUBSTRATE, METHOD AND DEVICE FOR MAKING IT | |
WO2009020245A3 (en) | Method of segmenting semiconductor wafer | |
WO2007028074A3 (en) | Workpiece transfer device | |
EP1744376A3 (en) | Semiconductor device and manufacturing method thereof | |
WO2009128786A3 (en) | A system and process for dicing integrated circuits | |
WO2008085495A3 (en) | Micromirror manufacturing method | |
EP3933892A4 (en) | DRY ETCHING METHOD, METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND ETCHING DEVICE | |
WO2010025231A3 (en) | Methods, apparatus and articles of manufacture for testing a plurality of singulated die | |
EP2846353A3 (en) | Complementary metal oxide semiconductor device and method of manufacturing the same | |
EP4131346A4 (en) | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MAKING IT | |
EP3862132A4 (en) | INDIUM PHOSPHIDE SUBSTRATE, EPITACTIC SEMICONDUCTOR WAFER AND METHOD OF MAKING AN INDIUM PHOSPHIDE SUBSTRATE | |
SG153008A1 (en) | Integrated circuit and method of fabrication thereof | |
WO2009060514A1 (ja) | 半導体装置の製造方法、ウエハおよびウエハの製造方法 | |
EP4203000A4 (en) | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE | |
EP3916759A4 (en) | WAFER AND METHOD FOR MAKING IT, AND SEMICONDUCTOR DEVICE |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07831297 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 07831297 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: JP |