WO2009054413A1 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

Info

Publication number
WO2009054413A1
WO2009054413A1 PCT/JP2008/069148 JP2008069148W WO2009054413A1 WO 2009054413 A1 WO2009054413 A1 WO 2009054413A1 JP 2008069148 W JP2008069148 W JP 2008069148W WO 2009054413 A1 WO2009054413 A1 WO 2009054413A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
pattern
forming
lower layer
semiconductor device
Prior art date
Application number
PCT/JP2008/069148
Other languages
French (fr)
Japanese (ja)
Inventor
Bangching Ho
Yasushi Sakaida
Daisuke Maruyama
Original Assignee
Nissan Chemical Industries, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Chemical Industries, Ltd. filed Critical Nissan Chemical Industries, Ltd.
Priority to JP2009538234A priority Critical patent/JPWO2009054413A1/en
Publication of WO2009054413A1 publication Critical patent/WO2009054413A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Materials For Photolithography (AREA)

Abstract

Provided is a semiconductor device manufacturing method by which a fine pattern different from conventional patterns is manufactured. The semiconductor manufacturing method is provided with a step of forming a film to be etched on a substrate; a step of forming a lower layer film composed of at least one layer on the film to be etched; a step of forming a first pattern by forming a photosensitive film on the lower layer film and patterning the photosensitive film; a step of forming a film, which may be photosensitive, on the lower layer film to cover a side wall or a gap of the first pattern and the upper surface of the first pattern; a stepof forming a second pattern, which covers at least a part of the side wall or the gap of the first pattern and the upper surface of the first pattern, by patterning the film; a step of etching the lower layer film by partially or entirely removing the first pattern and using the second pattern as a mask; and a step of etching the film to be etched by using the lower layer film after etching.
PCT/JP2008/069148 2007-10-25 2008-10-22 Semiconductor device manufacturing method WO2009054413A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009538234A JPWO2009054413A1 (en) 2007-10-25 2008-10-22 Method for manufacturing semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007277588 2007-10-25
JP2007-277588 2007-10-25

Publications (1)

Publication Number Publication Date
WO2009054413A1 true WO2009054413A1 (en) 2009-04-30

Family

ID=40579517

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/069148 WO2009054413A1 (en) 2007-10-25 2008-10-22 Semiconductor device manufacturing method

Country Status (3)

Country Link
JP (1) JPWO2009054413A1 (en)
TW (1) TW200937496A (en)
WO (1) WO2009054413A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009218556A (en) * 2008-03-12 2009-09-24 Taiwan Semiconductor Manufacturing Co Ltd Method of lithography patterning
JP2010050384A (en) * 2008-08-25 2010-03-04 Elpida Memory Inc Method of manufacturing semiconductor device
US7935477B2 (en) 2007-11-30 2011-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Double patterning strategy for contact hole and trench
WO2012111459A1 (en) * 2011-02-17 2012-08-23 Fujifilm Corporation Gap embedding composition, method of embedding gap and method of producing semiconductor device by using the composition
JP2015149473A (en) * 2013-12-23 2015-08-20 マイクロン テクノロジー， インク． Methods of forming patterns
WO2016017346A1 (en) * 2014-08-01 2016-02-04 富士フイルム株式会社 Pattern formation method and production method for electronic device using same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03270227A (en) * 1990-03-20 1991-12-02 Mitsubishi Electric Corp Formation of fine pattern
JPH07130631A (en) * 1993-11-05 1995-05-19 Sanyo Electric Co Ltd Pattern formation and manufacture of semiconductor storage device utilizing same
JPH07335670A (en) * 1994-06-07 1995-12-22 Mitsubishi Electric Corp Pattern forming method and pattern forming method for t-type gate electrode
JP2001343757A (en) * 2000-03-28 2001-12-14 Toshiba Corp Forming method for resist pattern
WO2005121019A1 (en) * 2004-06-08 2005-12-22 Riken Method for manufacturing nanostructure and nanostructure
JP2007081403A (en) * 2005-09-14 2007-03-29 Hynix Semiconductor Inc Method of forming fine pattern in semiconductor element
JP2008072101A (en) * 2006-09-12 2008-03-27 Hynix Semiconductor Inc Method for forming fine pattern of semiconductor device
JP2008227465A (en) * 2007-02-14 2008-09-25 Renesas Technology Corp Method of manufacturing a semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03270227A (en) * 1990-03-20 1991-12-02 Mitsubishi Electric Corp Formation of fine pattern
JPH07130631A (en) * 1993-11-05 1995-05-19 Sanyo Electric Co Ltd Pattern formation and manufacture of semiconductor storage device utilizing same
JPH07335670A (en) * 1994-06-07 1995-12-22 Mitsubishi Electric Corp Pattern forming method and pattern forming method for t-type gate electrode
JP2001343757A (en) * 2000-03-28 2001-12-14 Toshiba Corp Forming method for resist pattern
WO2005121019A1 (en) * 2004-06-08 2005-12-22 Riken Method for manufacturing nanostructure and nanostructure
JP2007081403A (en) * 2005-09-14 2007-03-29 Hynix Semiconductor Inc Method of forming fine pattern in semiconductor element
JP2008072101A (en) * 2006-09-12 2008-03-27 Hynix Semiconductor Inc Method for forming fine pattern of semiconductor device
JP2008227465A (en) * 2007-02-14 2008-09-25 Renesas Technology Corp Method of manufacturing a semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7935477B2 (en) 2007-11-30 2011-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Double patterning strategy for contact hole and trench
JP2009218556A (en) * 2008-03-12 2009-09-24 Taiwan Semiconductor Manufacturing Co Ltd Method of lithography patterning
US8048616B2 (en) 2008-03-12 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Double patterning strategy for contact hole and trench in photolithography
JP2010050384A (en) * 2008-08-25 2010-03-04 Elpida Memory Inc Method of manufacturing semiconductor device
WO2012111459A1 (en) * 2011-02-17 2012-08-23 Fujifilm Corporation Gap embedding composition, method of embedding gap and method of producing semiconductor device by using the composition
US8906253B2 (en) 2011-02-17 2014-12-09 Fujifilm Corporation Gap embedding composition, method of embedding gap and method of producing semiconductor device by using the composition
KR101609592B1 (en) 2011-02-17 2016-04-06 후지필름 가부시키가이샤 Gap embedding composition, method of embedding gap and method of producing semiconductor device by using the composition
JP2015149473A (en) * 2013-12-23 2015-08-20 マイクロン テクノロジー， インク． Methods of forming patterns
WO2016017346A1 (en) * 2014-08-01 2016-02-04 富士フイルム株式会社 Pattern formation method and production method for electronic device using same
JPWO2016017346A1 (en) * 2014-08-01 2017-04-27 富士フイルム株式会社 Pattern forming method and electronic device manufacturing method using the same

Also Published As

Publication number Publication date
TW200937496A (en) 2009-09-01
JPWO2009054413A1 (en) 2011-03-03

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