JP2001343757A - Forming method for resist pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce errors in the measurement of a resist pattern in a multilayer resist patterning process, and to simplify rework process. SOLUTION: An upper layer resist pattern 4 is formed on a lower layer resist 3. A polysilsesquioxane film 5, that is filled with the recessed part of the pattern 4 and has a flat surface, is formed on the resist 3 and on the pattern 4. The whole surface of the film 5 is etched, to selectively leave the film 5 in the recessed part of the pattern 4. The resist 3 and the pattern 4 are then etched, using the left film 5 as a mask, to form the multilayer resist pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a resist pattern used in a lithography step of a semiconductor process, and more particularly to an improvement in a method for forming a multilayer resist pattern such as laminating a coating film.

[0002]

2. Description of the Related Art In a conventional method for forming a multilayer resist pattern, first, as shown in FIGS. 3A to 3C, a lower resist is formed on a substrate to be processed (silicon substrate 51, silicon oxide film 52). 53, SOG film 54, upper resist 5
5 are sequentially formed. Next, as shown in FIGS. 3D to 3F, the upper resist 55 is patterned to form an upper resist pattern, and the SOG film 5 is formed using the upper resist pattern as a mask.
4. A multilayer resist pattern is obtained by sequentially etching the lower resist 53.

However, the conventional method of forming a multilayer resist pattern has a problem that when the upper resist 55 is patterned, the dimension of the upper resist pattern fluctuates due to a change in the thickness of the SOG film 54.

In a normal lithography process, a dimension inspection of a pattern and an overlay inspection for checking a relative position with respect to a previous process pattern are performed after a resist pattern is formed. You need to start the process over again.

In the conventional method of forming a multilayer resist pattern, when performing lithography again, it is necessary to first peel off and remove the upper resist 55 / SOG film 54 / lower resist 53 stepwise by a processing method corresponding to each film. There is a problem that the redo process becomes very complicated.

On the other hand, in a conventional method of forming a multilayer resist pattern, there is a method of forming a two-layer structure in which Si is included in an upper-layer resist to provide resistance to etching of a lower-layer resist, instead of such a three-layer structure. .

According to this method, the upper resist pattern can be formed directly on the lower resist, and the SOG film becomes unnecessary. In such a two-layer resist process, the problem of dimensional fluctuation in the three-layer resist process is solved, but the complexity of the above-described lithography restart still remains.

Further, in this method, if the added amount of Si is increased in order to impart sufficient lower layer resist etching resistance to the upper layer resist, the lithography performance of the upper layer resist represented by resolution is often impaired. As a result, there is a problem that the dimensional error increases.

[0009]

As described above, the conventional 3
The method of forming the layer resist pattern is such that the size of the upper layer resist fluctuates due to the influence of the SOG film which is the base of the upper layer resist, or a rework in the lithography process (rework)
There was a problem that it became very complicated.

Further, the conventional method of forming a two-layer resist pattern has a problem in that if the upper resist is allowed to have sufficient lower-layer resist etching resistance, the lithography performance of the upper resist is impaired and a dimensional error is increased. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of forming a multi-layer resist pattern that enables a reduction in a dimensional error of a resist pattern and simplification of a rework process. Is to do.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows. That is, in order to achieve the above object, a method for forming a resist pattern according to the present invention comprises the steps of: forming a lower resist as a first film on a substrate to be processed; and forming a second film on the lower resist film as a second film. Forming an upper-layer resist, patterning the upper-layer resist to form an upper-layer resist pattern, and using a casting solvent containing at least one of water, alcohol, anisole and an aliphatic hydrocarbon-based solvent. Forming a third film on the upper resist pattern by a casting method.

Here, it is preferable to form an intermediate film made of an organic polymer on the lower resist before forming the upper resist. Further, the film serving as a mask of the lower resist is preferably a polymer film containing silicon.

With this structure, the upper resist pattern and the lower resist can be simultaneously etched using the third film left in the concave portion of the upper resist pattern as a mask. And a complicated three-layer structure (lower-layer resist / SOG / upper-layer resist) is not required. In addition, it is unnecessary to add Si to the upper layer resist, which has caused a decrease in resolution in the conventional two-layer resist process. Therefore, according to the present invention, it is possible to reduce the dimensional error of the resist pattern and to simplify the rework process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 7 is a process cross-sectional view illustrating the method for forming the multilayer resist pattern according to the embodiment.

First, as shown in FIG. 1A, a substrate to be processed having a silicon oxide film 2 having a thickness of 1 μm formed on a silicon substrate 1 is prepared. The silicon oxide film 2 is used, for example, as an interlayer insulating film.

Next, as shown in FIG. 1 (b), a solution obtained by dissolving poly (2,6-biphenylylene ethylene) (Mw = 10000, hereinafter referred to as polyarylene) having a solid content of 10% by weight in a cyclohexanone solvent is used. 3,000 rpm by spin coating method, one of the casting methods
Then, a lower resist (polyarylene film: first film) 3 having a thickness of 900 nm is formed on the silicon oxide film 2 by spin-drying.

Next, as shown in FIG. 1C, a chemically amplified positive resist JSRKrFM20G is formed on the lower resist 3.
(Thickness: 200 nm), a coating film (upper layer resist: second film) is formed, and a KrF excimer laser exposure apparatus (NS
RS203B: Nikon Corporation). 68, σ =
Under the conditions of 0.75, 2/3 orbicular zone illumination and exposure amount of 17 mJ / cm2, using a halftone mask having a transmittance of 6%,
0.13 μmL / S is transferred to the upper resist to form an upper resist pattern 4.

Next, an aqueous solution of polysilsesquioxane having a solid content of 6% by weight was rotated at a rotation speed (25
(00 rpm), spin-coating is performed on the upper resist pattern 4, and then heat treatment is performed at 120 ° C. for 2 minutes on a hot plate. The atmosphere in the heat treatment was air at a humidity of 40%.

As a result, as shown in FIG. 1D, a policy having a film thickness on the lower resist 3 and the upper resist pattern 4 which is larger than the thickness of the concave portion of the upper resist pattern 4 and having a flat surface is obtained. A sesquioxane film 5 (third film: a film made of an organic silicon-based polymer) is formed.

Here, a solvent containing water is used as the casting solvent, but any solvent containing at least one of water, alcohol, anisole and an aliphatic hydrocarbon solvent may be used. The third film is a film containing Si, but may be any film containing at least one of Si, Al and Ti.

Next, as shown in FIG. 1E, the CDE (ch
The polysilsesquioxane film 5 is etched using a plasma of a mixed gas of CF4 / 02 in an apparatus for etching the polysilsesquioxane film 5 until the surface of the upper resist pattern 4 is exposed. Only the polysilsesquioxane film 5 is left.

The remaining film thickness of the polysilsesquioxane film 5 after this etching step was about 100 nm. CD
Reactive ion etching (RI) instead of E
E: Etchback using Reactive Ion Etching, or chemical mechanical polishing method (CMP: Chem)
Alternatively, the polysilsesquioxane film 5 may be selectively left by polishing using ical mechanical polishing.

Finally, as shown in FIG. 1 (f), using the polysilsesquioxane film 5 as a mask, the upper resist pattern 4, By dry-etching the lower resist 3, the lower resist pattern 3 that is inverted from the upper resist pattern 4 is formed. Thus, a multilayer resist pattern including the lower resist pattern 3 and the polysilsesquioxane film 5 is obtained. The remaining film thickness of the polysilsesquioxane film 5 after this etching step was about 30 nm.

The processed multilayer resist pattern had a high aspect ratio and a good shape, and the dimensional conversion difference (upper resist size−lower resist size after etching) was 5 nm or less.

In the present embodiment, since the upper resist pattern 4 is formed before the polysilsesquioxane film 5 is formed, the size of the upper resist pattern 4 is affected by the thickness of the polysilsesquioxane film 5. This is because the dimensions can be controlled with high precision as a result.

Furthermore, in the case of this embodiment, the upper resist pattern 4 and the lower resist 3 are dry-etched using the polysilsesquioxane film 5 as a mask to form a resist pattern. In order to impart resist etching resistance, means such as increasing the amount of Si added to the upper resist pattern is not required, and there is no problem that the lithography performance of the upper resist represented by resolution is impaired.

Next, a description will be given of an embodiment of the present invention and the prior art in the case where the dimensions are out of the standard in the dimensional inspection, that is, when the lithography step needs to be repeated.

First, in the present invention, since the polysilsesquioxane film 5 has not been formed yet at the stage of forming the upper resist pattern 4, the upper resist pattern 4 is treated with a mixed solution of sulfuric acid and hydrogen peroxide. And the lower resist 3 could be easily peeled off. In the wet processing, badge processing (collective processing) can be used, and the time required for removing the resist on one lot (25 sheets) of the substrate to be processed was 30 minutes.

On the other hand, when the multilayer resist pattern formed by the prior art is stripped, the SOG insoluble in a mixed aqueous solution of sulfuric acid and hydrogen peroxide is present between the lower resist and the upper resist.
Since the film exists, the above-described resist stripping method by wet processing cannot be used. Therefore, in the single-wafer ashing apparatus, it is necessary to peel off the upper resist in a stepwise manner using an oxygen-based gas, the SOG film using a fluorine-based gas, and the lower resist using an oxygen-based gas again. The time required to remove the resist on one lot (25 sheets) of the substrate to be processed by this method was 100 minutes. That is, it took twice as long as the present invention.

(Second Embodiment) Next, a method of forming a multilayer resist pattern according to a second embodiment of the present invention will be described.

In the first embodiment, the etching process of the polysilsesquioxane film 5 in FIG. 1E is performed by the CDE method. In the present embodiment, the etching process is performed by the wet etching method using an HF-based aqueous solution. Do. The remaining film thickness of the polysilsesquioxane film 5 after the wet etching was about 60 nm, almost as in the case of CDE.

It has been confirmed that similar effects (reduction of dimensional error and simplification of rework) can be obtained by using such wet etching. Steps before and after FIG. 1E are the same as those in the first embodiment.

(Third Embodiment) FIG. 2 shows a third embodiment of the present invention.
FIG. 7 is a process cross-sectional view illustrating the method for forming the multilayer resist pattern according to the embodiment.

First, as shown in FIG. 2A, a substrate to be processed having a silicon oxide film 12 having a thickness of 1 μm formed on a silicon substrate 11 is prepared. Up to this point, the operation is the same as in the first embodiment.

Next, as shown in FIG. 2B, on the silicon oxide film 12, a lower resist (polyacenaphthene film) made of a solution of polyacenaphthene (Mw = 1500) having a solid content of 1 wt% in cyclohexanone. 13) film thickness 5
It is formed to have a thickness of 00 nm.

Next, as shown in FIG. 2C, an antireflection film AR for DUV manufactured by Ship1ey is formed on the lower resist 13.
5 (hereinafter simply referred to as an antireflection film) 14 is formed by a coating method. At this time, the thickness of the antireflection film 14 is 70 nm.
The rotation speed and the baking conditions are determined so that

Next, as shown in FIG. 2D, a chemically amplified positive resist JSRKrFM20 is formed on the antireflection film 14.
An upper resist pattern 15 of 0.13 μmL / S is formed using G (film thickness 200 nm).

The antireflection film 14 used here is made of DUV
In addition to the anti-reflection effect against exposure light, the lower resist 1
3 has an effect of increasing the adhesion between the upper resist pattern 15 and the upper resist pattern 15.

Next, as shown in FIG. 2 (e), a 300 nm-thick policy with a flat surface is formed on the lower resist 13 and the upper resist pattern 15 so as to fill the recesses of the upper resist pattern 15. A sesquioxane film 16 is formed. In the first embodiment, the polysilsesquioxane film 5 is formed by using a spin coating method. In the second embodiment, the polysilsesquioxane film 16 is formed by a scan type coating method. With this scan coating method, a uniform coating film without defects was obtained even on a resist pattern having a step.

Next, as shown in FIG. 2F, similarly to the first embodiment, the surface of the upper resist pattern 4 is exposed by using a plasma composed of a mixed gas of CF 4 / O 2 in a CDE apparatus. The polysilsesquioxane film 16 is etched until the polysilsesquioxane film 16 is left only in the concave portions of the upper resist pattern 4. Note that this step may be performed using a wet etching method as in the second embodiment.

Finally, as shown in FIG. 2 (g), similarly to the first embodiment, using the polysilsesquioxane film 16 as a mask, a plasma made of a mixed gas of N 2/02 in an RIE apparatus. Using the upper resist pattern 15,
By dry-etching the antireflection film 14 and the lower-layer resist 13, the lower-layer resist pattern 13 inverted from the upper-layer resist pattern 15 is formed. As a result, a multilayer resist pattern including the lower resist pattern 13, the antireflection film 14, and the polysilsesquioxane film 16 is formed.

As in the first and second embodiments, the processed resist pattern shows a good shape with a high aspect ratio and a dimensional conversion difference (upper resist size−lower resist size after etching). It was a very small value. In addition, since the antireflection film 14 exists but is easily removed, the rework in the lithography process is easier than in the past.

The present invention is not limited to the above embodiment. For example, in the above embodiment, a silicon oxide film (film to be processed) is formed on a silicon substrate as a substrate to be processed.
Was used, but the film to be processed may be another film such as a polycrystalline silicon film or a metal film used for a gate electrode or the like. The film to be processed is not limited to a single-layer film, and may be, for example, a laminated film of a polysilicon film and a W film used for a gate electrode. Further, the substrate to be processed may be a substrate. As a process in which the substrate to be processed becomes a substrate, for example, there is a process of forming an element isolation groove or a trench capacitor.

The semiconductor substrate is not limited to a bulk silicon substrate, but may be, for example, an SOI substrate or a semiconductor substrate other than a silicon substrate.

Further, in the above embodiment, the case where the KrF excimer laser device is used as the exposure light source has been described. However, the present invention may use an ArF, Xe or F2 excimer laser device.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0049]

As described above in detail, according to the present invention, it is possible to realize a method of forming a multilayer resist pattern capable of reducing a dimensional error of a resist pattern and simplifying a rework process.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a method for forming a multilayer resist pattern according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a method for forming a multilayer resist pattern according to a second embodiment of the present invention.

FIG. 3 is a process sectional view showing a conventional method of forming a multilayer resist pattern.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 silicon oxide film 3 lower resist (polyarylene film) 4 upper resist pattern 5 polysilsesquioxane film 11 silicon substrate 12 silicon oxide film 13 lower resist (polyacenaphthene film) 14 antireflection film 15 upper resist pattern 16 polysilsesquioxane film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/3205 H01L 21/302 J 21/88 B F Term (Reference) 2H025 AA02 AA03 AA09 AB16 AC08 AD03 BE00 BE10 BG00 DA11 FA28 FA41 2H096 AA25 BA11 EA05 HA23 HA30 KA02 KA06 KA30 LA06 5F004 AA04 BA03 BA04 DA01 DA26 DB24 EA02 EA06 5F033 HH04 HH07 MM05 QQ01 QQ08 QQ09 QQ13 QQ28 QQ29 QQ31 RR04 RR04 RRXXRR

Claims (4)

[Claims] A step of forming a lower resist as a first film on a substrate to be processed; a step of forming an upper resist as a second film on the lower resist film; and patterning the upper resist. A step of forming an upper resist pattern, and using a casting solvent containing at least one of water, alcohol, anisole and an aliphatic hydrocarbon solvent, and forming a third film on the upper resist pattern by a casting method. Forming a resist pattern. 2. The method according to claim 1, wherein the third film contains at least one of Si, Al, and Ti. 3. The method according to claim 1, wherein the third film has a hydroxyl group and an amino group in its skeleton. 4. The upper resist pattern by etching back or polishing the surface of the third film using a reactive ion etching method or a chemical mechanical polishing method until the surface of the upper resist pattern is exposed. And selectively processing the upper resist pattern and the lower resist by RIE using the remaining third film as a mask. The method of forming a resist pattern according to claim 1.