JP4004014B2 - Method for forming resist pattern - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a resist pattern used in a lithography process of a semiconductor process, and more particularly to improvement of a method for forming a multilayer resist pattern in which a coating film is laminated.
[0002]
[Prior art]
In the conventional multilayer resist pattern forming method, first, as shown in FIGS. 3A to 3C, a lower layer resist 53 and an SOG film 54 are formed on a substrate to be processed (silicon substrate 51 and silicon oxide film 52). The upper layer resist 55 is sequentially formed. Next, as shown in FIGS. 3D to 3F, the upper resist 55 is patterned to form an upper resist pattern, and the SOG film 54 and the lower resist 53 are sequentially etched using this as a mask. A multilayer resist pattern is obtained.
[0003]
However, this conventional method for forming a multilayer resist pattern has a problem that when the upper resist 55 is patterned, the dimension of the upper resist pattern varies due to the change in the film thickness of the SOG film 54.
[0004]
Moreover, in the normal lithography process, after the resist pattern is formed, a pattern dimension inspection and an overlay inspection to check the relative position with the previous process pattern are performed. If the inspection process is out of specification, the lithography process is performed once again. I need to start over.
[0005]
In the conventional method for forming a multilayer resist pattern, when lithography is performed again, it is necessary to first remove and remove the upper layer resist 55 / SOG film 54 / lower layer resist 53 stepwise by a processing method corresponding to each film. There was a problem that the process became very complicated.
[0006]
On the other hand, some conventional multilayer resist pattern forming methods have a two-layer structure in which Si is contained in the upper layer resist instead of such a three-layer structure to provide resistance to etching of the lower layer resist.
[0007]
In this method, the upper layer resist pattern can be formed directly on the lower layer resist, and the SOG film becomes unnecessary. In such a two-layer resist process, the problem of dimensional variation in the three-layer resist process is solved, but the complexity of the above-described lithography rework still remains.
[0008]
Furthermore, in this method, if the amount of Si added is increased in order to give the upper resist sufficient etching resistance to the lower resist, the lithography performance of the upper resist represented by resolution is often impaired, resulting in dimensional errors. There was a problem that became larger.
[0009]
[Problems to be solved by the invention]
As described above, the conventional method for forming a three-layer resist pattern has a problem in that the size of the upper resist varies due to the influence of the SOG film that is the base of the upper resist, and the rework (rework) in the lithography process becomes very complicated. was there.
[0010]
Further, the conventional method for forming a two-layer resist pattern has a problem that if the upper layer resist is made to have sufficient lower layer resist etching resistance, the lithography performance of the upper layer resist is impaired and the dimensional error is increased. The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a method for forming a multilayer resist pattern that can reduce the dimensional error of the resist pattern and simplify the rework process. is there.
[0011]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows. That is, in order to achieve the above object, a resist pattern forming method according to the present invention includes a step of forming a lower layer resist as a first film on a substrate to be processed, and a second film as a second film on the lower layer resist film. A step of forming an upper layer resist, a step of patterning the upper layer resist to form an upper layer resist pattern, and a film containing water as a casting solvent are used, and a third film is formed on the upper layer resist pattern by a casting method. And a step of forming a resist pattern.
[0012]
Here, it is preferable to form an intermediate film made of an organic polymer on the lower resist before forming the upper resist. Further, the film serving as a mask for the lower resist is preferably a polymer film containing silicon.
[0013]
With such a configuration, it is possible to simultaneously etch the upper layer resist pattern and the lower layer resist using the third film left in the recess of the upper layer resist pattern as a mask. A complicated three-layer structure (lower layer resist / SOG / upper layer resist) is not required. Further, it is not necessary to add Si to the upper layer resist, which is a cause of a decrease in resolution in the conventional two layer resist process. Therefore, according to the present invention, it is possible to reduce the dimensional error of the resist pattern and simplify the rework process.
[0014]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0016]
(First embodiment)
FIG. 1 is a process sectional view showing a multilayer resist pattern forming method according to the first embodiment of the present invention.
[0017]
First, as shown in FIG. 1A, a substrate to be processed in which a silicon oxide film 2 having a thickness of 1 μm is formed on a silicon substrate 1 is prepared. The silicon oxide film 2 is used for an interlayer insulating film, for example.
[0018]
Next, as shown in FIG. 1B, a solution obtained by dissolving poly (2,6-biphenylylene ethylene) (Mw = 10000, hereinafter referred to as polyarylene) having a solid content of 10 wt% in a cyclohexanone solvent is cast. The lower layer resist (polyarylene film: first film) 3 having a film thickness of 900 nm is applied on the silicon oxide film 2 by applying onto the wafer at a rotational speed of 3000 rpm by a spin coating method, which is one of the above. Form.
[0019]
Next, as shown in FIG. 1C, a coating film (upper layer resist: second film) of a chemically amplified positive resist JSRKrFM20G (thickness 200 nm) is formed on the lower layer resist 3, and a KrF excimer laser exposure apparatus (NSRS203B) is formed. : Nikon Corporation) NA = O. 68, σ = 0.75, 2/3 annular illumination, exposure amount 17 mJ / cm 2, using a halftone mask with a transmittance of 6%, 0.13 μmL / S was transferred to the upper resist, A resist pattern 4 is formed.
[0020]
Next, a polysilsesquioxane aqueous solution having a solid content concentration of 6 wt% was applied on the upper resist pattern 4 by a spin coating method at a rotation speed (2500 rpm) with a film thickness of 300 nm, and then at 120 ° C. for 2 minutes on a hot plate. Perform a heat treatment. The atmosphere in the heat treatment was in the air with a humidity of 40%.
[0021]
As a result, as shown in FIG. 1D, on the lower resist 3 and the upper resist pattern 4, a polysilsesquioxide having a thickness larger than that for embedding the recesses of the upper resist pattern 4 and having a flat surface. A sun film 5 (third film: a film made of an organic silicon polymer) is formed.
[0022]
Here, although the thing containing water was used as a casting solvent, what is necessary is just to contain at least 1 of water, alcohol, anisole, and an aliphatic hydrocarbon solvent. The third film is a film containing Si, but may be any film containing at least one of Si, Al, and Ti.
[0023]
Next, as shown in FIG. 1E, a polysilsesquioxane film is used until the surface of the upper resist pattern 4 is exposed by using plasma made of a mixed gas of CF4 / 02 in a CDE (chemical dry etching) apparatus. By etching 5, the polysilsesquioxane film 5 is left only in the concave portion of the upper resist pattern 4.
[0024]
The remaining film thickness of the polysilsesquioxane film 5 after this etching process was about 100 nm. The polysilsesquioxane film 5 is obtained by etching back using reactive ion etching (RIE) instead of CDE, or by polishing using chemical mechanical polishing (CMP). It is also possible to leave the selection.
[0025]
Finally, as shown in FIG. 1 (f), using the polysilsesquioxane film 5 as a mask, plasma composed of a mixed gas of N 2/02 is used in the RIE apparatus to form the upper resist pattern 4 and the lower resist 3 Is dry-etched to form the lower resist pattern 3 that is the reverse of the upper resist pattern 4. In this way, a multilayer resist pattern composed of the lower layer resist pattern 3 and the polysilsesquioxane film 5 is obtained. The remaining film thickness of the polysilsesquioxane film 5 after this etching process was about 30 nm.
[0026]
Further, the processed multilayer resist pattern had a high aspect ratio and a good shape, and the dimensional conversion difference (upper layer resist dimension−lower layer resist dimension after etching) was 5 nm or less.
[0027]
In this embodiment, since the upper resist pattern 4 is formed before the polysilsesquioxane film 5 is formed, the dimensions thereof are not affected by the film thickness of the polysilsesquioxane film 5, As a result, the dimensions can be controlled with high accuracy.
[0028]
Furthermore, in the case of the present embodiment, the resist pattern is formed by dry etching the upper resist pattern 4 and the lower resist 3 using the polysilsesquioxane film 5 as a mask, so that the lower resist resist resistance sufficient for the upper resist pattern is formed. Therefore, means such as increasing the amount of Si added to the upper resist pattern is not necessary, and there is no problem that the lithography performance of the upper resist represented by resolution is impaired.
[0029]
Next, an embodiment in the case where the present invention and the prior art are out of specification in the dimension inspection, that is, the case where the lithography process needs to be performed again will be described.
[0030]
First, in the present invention, since the polysilsesquioxane film 5 has not yet been formed at the formation stage of the upper layer resist pattern 4, the upper layer resist pattern 4 and the lower layer resist are treated by treatment with a mixed solution of sulfuric acid and hydrogen peroxide. 3 could be easily peeled off. In the wet processing, badge processing (batch processing) can be used, and the time required for stripping the resist on one lot (25 sheets) of the substrate to be processed was 30 minutes.
[0031]
On the other hand, when the multi-layer resist pattern formed by the prior art is peeled off, an SOG film that is insoluble in sulfuric acid and hydrogen peroxide mixed solution exists between the lower layer resist and the upper layer resist. Cannot be used. Therefore, in the single-wafer ashing apparatus, it is necessary to perform stripping step by step using an oxygen-based gas for the upper layer resist, a fluorine-based gas for the SOG film, and an oxygen-based gas for the lower layer resist again. The time required for peeling the resist on one lot (25 sheets) of the substrate to be processed by this method was 100 minutes. That is, it took twice as much time as the present invention.
[0032]
(Second Embodiment)
Next, a method for forming a multilayer resist pattern according to the second embodiment of the present invention will be described.
[0033]
In the first embodiment, the etching process of the polysilsesquioxane film 5 in FIG. 1E is performed by the CDE method. In the present embodiment, the etching process is performed by a wet etching method using an HF-based aqueous solution. The remaining film thickness of the polysilsesquioxane film 5 after the wet etching was about 60 nm as in the case of CDE.
[0034]
It was confirmed that similar effects (reduction in dimensional error and simplification of rework) can be obtained even when such wet etching is used. The steps before and after FIG. 1 (e) are the same as those in the first embodiment.
[0035]
(Third embodiment)
FIG. 2 is a process sectional view showing a multilayer resist pattern forming method according to the third embodiment of the present invention.
[0036]
First, as shown in FIG. 2A, a substrate to be processed in which a silicon oxide film 12 having a thickness of 1 μm is formed on a silicon substrate 11 is prepared. Up to this point, the process is the same as in the first embodiment.
[0037]
Next, as shown in FIG. 2B, a lower resist (polyacenaphthene film) 13 made of a solution of polyacenaphthene (Mw = 1500) having a solid content of 1 wt% in cyclohexanone is formed on the silicon oxide film 12. The film is formed to a thickness of 500 nm.
[0038]
Next, as shown in FIG. 2C, an antireflection film AR5 for DUV (hereinafter simply referred to as an antireflection film) 14 made by Ship1ey is formed on the lower resist 13 by a coating method. At this time, the rotational speed and baking conditions are determined so that the film thickness of the antireflection film 14 is 70 nm.
[0039]
Next, as shown in FIG. 2D, an upper resist pattern 15 of 0.13 μmL / S is formed on the antireflection film 14 by using a chemically amplified positive resist JSRKrFM20G (thickness: 200 nm).
[0040]
The antireflection film 14 used here has an effect of improving the adhesion between the lower layer resist 13 and the upper layer resist pattern 15 as well as an antireflection effect for DUV exposure light.
[0041]
Next, as shown in FIG. 2 (e), a polysilsesquioxide having a thickness of 300 nm and a flat surface is formed on the lower resist 13 and the upper resist pattern 15 so as to have a thickness larger than that for embedding the concave portion of the upper resist pattern 15. A sun film 16 is formed. In the first embodiment, the polysilsesquioxane film 5 is formed by using a spin coating method, but in the second embodiment, the polysilsesquioxane film 16 is formed by a scan-type coating method. By this scan coating method, a uniform coating film having no defects was obtained even on a resist pattern having a step.
[0042]
Next, as shown in FIG. 2 (f), in the same manner as in the first embodiment, polysilyl is used until the surface of the upper resist pattern 4 is exposed using plasma composed of a mixed gas of CF4 / 02 in the CDE apparatus. The sesquioxane film 16 is etched to leave the polysilsesquioxane film 16 only in the recesses of the upper resist pattern 4. Note that this step may be performed using a wet etching method, as in the second embodiment.
[0043]
Finally, as shown in FIG. 2 (g), as in the first embodiment, using a polysilsesquioxane film 16 as a mask, plasma composed of a mixed gas of N 2/02 is used in the RIE apparatus. The upper resist pattern 15, the antireflection film 14, and the lower resist 13 are dry-etched to form the lower resist pattern 13 that is the reverse of the upper resist pattern 15. As a result, a multilayer resist pattern composed of the lower resist pattern 13, the antireflection film 14, and the polysilsesquioxane film 16 is formed.
[0044]
Similar to the first and second embodiments, the processed resist pattern has a high aspect ratio and a good shape, and the dimension conversion difference (upper layer resist dimension−lower layer resist dimension after etching) is extremely small. Met. Further, although the antireflection film 14 exists, the removal thereof is easy, so that the rework in the lithography process becomes simpler than before.
[0045]
The present invention is not limited to the above embodiment. For example, in the above-described embodiment, a substrate in which a silicon oxide film (film to be processed) is formed on a silicon substrate is used as the substrate to be processed, but the film to be processed is a polycrystalline silicon film or metal used for a gate electrode or the like. Other films such as a film may be used. Further, the film to be processed is not limited to a single layer film, and may be a laminated film of a polysilicon film and a W film used for a gate electrode, for example. Further, the substrate to be processed may be a substrate. Examples of the process in which the substrate to be processed becomes a substrate include a process for forming an element isolation groove and a trench capacitor.
[0046]
Further, the semiconductor substrate is not limited to a bulk silicon substrate, and may be, for example, an SOI substrate or a semiconductor substrate other than a silicon substrate.
[0047]
Furthermore, although the case where the KrF excimer laser device is used as the exposure light source has been described in the above embodiment, the present invention may use an ArF, Xe or F2 excimer laser device.
[0048]
In addition, various modifications can be made without departing from the scope of the present invention.
[0049]
【The invention's effect】
As described in detail above, according to the present invention, it is possible to realize a multilayer resist pattern forming method that can reduce the dimensional error of the resist pattern and simplify the rework process.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view showing a multilayer resist pattern forming method according to a first embodiment of the present invention. FIG. 2 is a process cross-sectional view showing a multilayer resist pattern forming method according to a second embodiment of the present invention. FIG. 3 is a process sectional view showing a conventional method for forming a multilayer resist pattern.
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Silicon oxide film 3 ... Underlayer resist (polyarylene film)
4 ... Upper resist pattern 5 ... Polysilsesquioxane film 11 ... Silicon substrate 12 ... Silicon oxide film 13 ... Lower resist (polyacenaphthene film)
14 ... Antireflection film 15 ... Upper resist pattern 16 ... Polysilsesquioxane film

Claims (4)

Forming a lower layer resist as a first film on a substrate to be processed;
Forming an upper layer resist as a second film on the lower layer resist film;
Patterning the upper layer resist to form an upper layer resist pattern;
And a step of forming a third film on the upper resist pattern by a casting method using a solvent containing water as a casting solvent. The method of forming a resist pattern according to claim 1, wherein the third film contains at least one of Si, Al, and Ti. 2. The method for forming a resist pattern according to claim 1, wherein a hydroxyl group and an amino group are contained in the skeleton of the material forming the third film. Etch back or polish the surface of the third film until the surface of the upper resist pattern is exposed using a reactive ion etching method or a chemical mechanical polishing method, so that the first resist pattern is recessed in the upper resist pattern. 3 selectively leaving the film of 3;
The method of forming a resist pattern according to claim 1, further comprising a step of processing the upper layer resist pattern and the lower layer resist by an RIE method using the remaining third film as a mask.

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